From c461e51d55bfc253aafed227c9c05dd7d2e9403d Mon Sep 17 00:00:00 2001 From: Silvano di Ninno Date: Mon, 13 Aug 2018 14:27:01 +0200 Subject: MLK-18502: board:imx8mm_evk enable tzasc Enable TZASC on i.MX 8mm. There is a need on 8MM to enable the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors. Signed-off-by: Silvano di Ninno Reviewed-by: Peng Fan (cherry picked from commit d72b8baecd8495cfba990b999fe390937859ad75) --- arch/arm/cpu/armv8/imx8m/soc.c | 3 +++ arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h | 1 + board/freescale/imx8mm_evk/spl.c | 3 +-- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/imx8m/soc.c b/arch/arm/cpu/armv8/imx8m/soc.c index 9bb9fe37a3..8e506c47fc 100644 --- a/arch/arm/cpu/armv8/imx8m/soc.c +++ b/arch/arm/cpu/armv8/imx8m/soc.c @@ -135,6 +135,9 @@ void enable_tzc380(void) /* Enable TZASC and lock setting */ val = readl(IOMUXC_GPR10); val |= GPR_TZASC_EN; +#ifdef CONFIG_IMX8MM + val |= GPR_TZASC_SWAP_ID; +#endif writel(val, IOMUXC_GPR10); val |= GPR_TZASC_EN_LOCK; writel(val, IOMUXC_GPR10); diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h index b46e1ababa..c1f3a8e64f 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h @@ -125,6 +125,7 @@ #define IOMUXC_GPR22 (IOMUXC_GPR_BASE_ADDR + 0x58) #define GPR_TZASC_EN (1 << 0) +#define GPR_TZASC_SWAP_ID (1 << 1) #define GPR_TZASC_EN_LOCK (1 << 16) #define CNTCR_OFF 0x00 diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index e827484419..657d31a97b 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -190,8 +190,7 @@ int power_init_board(void) void spl_board_init(void) { - /* TODO */ - /* enable_tzc380(); */ + enable_tzc380(); setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); -- cgit v1.2.3