From a4f510740875b9ceed882d6413d475f4f6befe03 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Thu, 29 Apr 2010 17:16:25 +0800 Subject: p1022ds: Fix the DIU issue on RevB1 board DIU doesn't work on P1022DS RevB1 board in u-boot, it is because there are two code bugs in DIU code. 1) We must clear the PMUXCR[eLBC_DIU] bits before we set the eLBC_DIU=2'b01 for DIU mode. The PMUXCR[eLBC_DIU] POR value is 2'b10 in RevB1 board, however the eLBC_DIU is 2'b00 in RevA board due to design issue. 2) We must do dummy read to make sure the write FPGA PIXIS register be completed. Signed-off-by: Dave Liu --- board/freescale/p1022ds/p1022ds_diu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/freescale/p1022ds/p1022ds_diu.c b/board/freescale/p1022ds/p1022ds_diu.c index af0bcb77fe..b2f210a709 100644 --- a/board/freescale/p1022ds/p1022ds_diu.c +++ b/board/freescale/p1022ds/p1022ds_diu.c @@ -91,12 +91,13 @@ void p1022ds_diu_init(void) tmp_val_brdcfg0 = in_8(pixis_base + PIXIS_BRDCFG0); tmp_val_brdcfg0 = (tmp_val_brdcfg0 & 0x3D) | 0x02; out_8(pixis_base + PIXIS_BRDCFG0, tmp_val_brdcfg0); + /* we must do the dummy read from eLBC to sync the write as above */ + in_8(pixis_base + PIXIS_BRDCFG0); /* Setting PMUXCR to switch to DVI from ELBC */ /* Set pmuxcr to allow both i2c1 and i2c2 */ - gur->pmuxcr |= 0x40000000; - tmp = gur->pmuxcr; - + clrsetbits_be32(&gur->pmuxcr, 0xc0000000, 0x40000000); + tmp = in_be32(&gur->pmuxcr); fsl_diu_init(xres, pixel_format, gamma_fix, (unsigned char *)FSL_Logo_BMP); } -- cgit v1.2.3