From 887a2b7504c635da813edd1d07b8122e3608a91f Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 4 May 2015 09:43:44 +0200 Subject: ARM: vf610: support L2 cache for Vybrid Support L2 cache which is available on for the Cortex-A5 core on some Vybrid SoCs (VFx1x series). Vybrid seems to use revision r3p2 of the PL310 cache controller. To enable the cache controller use this two configuration symbols: #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE CA5_L2C_BASE_ADDR Note: U-Boot is currently not able to detect the existence of the L2 cache at runtime. Hence enabling these configurations leads to a crash on SoCs which do not have a L2 cache (e.g. VF500 on Colibri VF50) --- arch/arm/cpu/armv7/vf610/generic.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index f0a6965aa9..be5f7f389d 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #ifdef CONFIG_FSL_ESDHC #include @@ -395,3 +396,39 @@ void enable_caches(void) mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option); } #endif + +#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_SYS_L2_PL310) +#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 +void v7_outer_cache_enable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)CA5_L2C_BASE_ADDR; + unsigned int val; + + /* Must disable the L2 before changing the latency parameters */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x122, &pl310->pl310_tag_latency_ctrl); + writel(0x011, &pl310->pl310_data_latency_ctrl); + + val = readl(&pl310->pl310_prefetch_ctrl); + + /* Turn on the L2 I/D prefetch */ + val |= 0x30000000; + + writel(val, &pl310->pl310_prefetch_ctrl); + + val = readl(&pl310->pl310_power_ctrl); + val |= L2X0_DYNAMIC_CLK_GATING_EN; + val |= L2X0_STNDBY_MODE_EN; + writel(val, &pl310->pl310_power_ctrl); + + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + struct pl310_regs *const pl310 = (struct pl310_regs *)CA5_L2C_BASE_ADDR; + + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} +#endif /* !CONFIG_SYS_L2CACHE_OFF */ -- cgit v1.2.3