From 83d645aff0279effbf279d7441f2d847a7983221 Mon Sep 17 00:00:00 2001 From: Jingchang Lu Date: Tue, 3 Jul 2012 13:26:54 +0800 Subject: Add quad SPI support for Vybrid Signed-off-by: TsiChung Liew --- arch/arm/include/asm/arch-vybrid/quadspi.h | 209 +++++++++++++++++++++++++++++ drivers/spi/Makefile | 1 + drivers/spi/quad_spi.c | 133 ++++++++++++++++++ include/qspi.h | 141 +++++++++++++++++++ 4 files changed, 484 insertions(+) create mode 100644 arch/arm/include/asm/arch-vybrid/quadspi.h create mode 100644 drivers/spi/quad_spi.c create mode 100644 include/qspi.h diff --git a/arch/arm/include/asm/arch-vybrid/quadspi.h b/arch/arm/include/asm/arch-vybrid/quadspi.h new file mode 100644 index 0000000000..c9245b47b0 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/quadspi.h @@ -0,0 +1,209 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __QUADSPI_H__ +#define __QUADSPI_H__ + +#define QUADSPI_MCR (0x000) +#define QUADSPI_IPCR (0x008) +#define QUADSPI_FLSHCR (0x00C) +#define QUADSPI_BUF0CR (0x010) +#define QUADSPI_BUF1CR (0x014) +#define QUADSPI_BUF2CR (0x018) +#define QUADSPI_BUF3CR (0x01C) +#define QUADSPI_BFGENCR (0x020) +#define QUADSPI_SOCCR (0x024) +#define QUADSPI_BUF0IND (0x030) +#define QUADSPI_BUF1IND (0x034) +#define QUADSPI_BUF2IND (0x038) +#define QUADSPI_SFAR (0x100) +#define QUADSPI_SMPR (0x108) +#define QUADSPI_RBSR (0x10C) +#define QUADSPI_RBCT (0x110) +#define QUADSPI_TBSR (0x150) +#define QUADSPI_TBDR (0x154) +#define QUADSPI_SR (0x15C) +#define QUADSPI_FR (0x160) +#define QUADSPI_RSER (0x164) +#define QUADSPI_SPNDST (0x168) +#define QUADSPI_SPTRCLR (0x16C) +#define QUADSPI_SFA1AD (0x180) +#define QUADSPI_SFA2AD (0x184) +#define QUADSPI_SFB1AD (0x188) +#define QUADSPI_SFB2AD (0x18C) +#define QUADSPI_LUTKEY (0x300) +#define QUADSPI_LCKCR (0x304) +#define QUADSPI_LUT0 (0x310) +#define QUADSPI_LUT1 (0x314) +#define QUADSPI_LUT2 (0x318) +#define QUADSPI_LUT3 (0x31C) +#define QUADSPI_LUT4 (0x320) +#define QUADSPI_LUT5 (0x324) +#define QUADSPI_LUT6 (0x328) +#define QUADSPI_LUT7 (0x32C) +#define QUADSPI_LUT8 (0x330) +#define QUADSPI_LUT9 (0x334) +#define QUADSPI_LUT10 (0x338) +#define QUADSPI_LUT11 (0x33C) +#define QUADSPI_LUT12 (0x340) +#define QUADSPI_LUT13 (0x344) +#define QUADSPI_LUT14 (0x348) +#define QUADSPI_LUT15 (0x34C) +#define QUADSPI_LUT16 (0x350) +#define QUADSPI_LUT17 (0x354) +#define QUADSPI_LUT18 (0x358) +#define QUADSPI_LUT19 (0x35C) +#define QUADSPI_LUT20 (0x360) +#define QUADSPI_LUT21 (0x364) +#define QUADSPI_LUT22 (0x368) +#define QUADSPI_LUT23 (0x36C) +#define QUADSPI_LUT24 (0x370) +#define QUADSPI_LUT25 (0x374) +#define QUADSPI_LUT26 (0x378) +#define QUADSPI_LUT27 (0x37C) +#define QUADSPI_LUT28 (0x380) +#define QUADSPI_LUT29 (0x384) +#define QUADSPI_LUT30 (0x388) +#define QUADSPI_LUT31 (0x38C) +#define QUADSPI_LUT32 (0x390) +#define QUADSPI_LUT33 (0x394) +#define QUADSPI_LUT34 (0x398) +#define QUADSPI_LUT35 (0x39C) +#define QUADSPI_LUT36 (0x3A0) +#define QUADSPI_LUT37 (0x3A4) +#define QUADSPI_LUT38 (0x3A8) +#define QUADSPI_LUT39 (0x3AC) +#define QUADSPI_LUT40 (0x3B0) +#define QUADSPI_LUT41 (0x3B4) +#define QUADSPI_LUT42 (0x3B8) +#define QUADSPI_LUT43 (0x3BC) +#define QUADSPI_LUT44 (0x3C0) +#define QUADSPI_LUT45 (0x3C4) +#define QUADSPI_LUT46 (0x3C8) +#define QUADSPI_LUT47 (0x3CC) +#define QUADSPI_LUT48 (0x3D0) +#define QUADSPI_LUT49 (0x3D4) +#define QUADSPI_LUT50 (0x3D8) +#define QUADSPI_LUT51 (0x3DC) +#define QUADSPI_LUT52 (0x3E0) +#define QUADSPI_LUT53 (0x3E4) +#define QUADSPI_LUT54 (0x3E8) +#define QUADSPI_LUT55 (0x3EC) +#define QUADSPI_LUT56 (0x3F0) +#define QUADSPI_LUT57 (0x3F4) +#define QUADSPI_LUT58 (0x3F8) +#define QUADSPI_LUT59 (0x3FC) +#define QUADSPI_LUT60 (0x400) +#define QUADSPI_LUT61 (0x404) +#define QUADSPI_LUT62 (0x408) +#define QUADSPI_LUT63 (0x40C) +#define QUADSPI_RBDR (0x2000) + +#define QUADSPI_MCR_DOZE (1 << 15) +#define QUADSPI_MCR_MDIS (1 << 14) +#define QUADSPI_MCR_CLRTXF (1 << 11) +#define QUADSPI_MCR_CLRRXF (1 << 10) +#define QUADSPI_MCR_DDREN (1 << 7) +#define QUADSPI_MCR_DQSEN (1 << 6) +#define QUADSPI_MCR_SWRSTHD (1 << 1) +#define QUADSPI_MCR_SWRSTSD (1 << 0) + +#define QUADSPI_IPCR_SEQID(x) ((x & 0xF) << 24) +#define QUADSPI_IPCR_PAREN (1 << 16) +#define QUADSPI_IPCR_IDATSZ(x) (x & 0xFFFF) + +#define QUADSPI_FLSHCR_TCSH(x) ((x & 0xF) << 8) +#define QUADSPI_FLSHCR_TCSS(x) (x & 0xF) + +#define QUADSPI_BUF0CR_HPEN (1 << 31) +#define QUADSPI_BUF3CR_ALLMST (1 << 31) +#define QUADSPI_BUFCR_ADATSZ(x) ((x & 0xFF) << 8) +#define QUADSPI_BUFCR_MSTRID(x) (x & 0xF) + +#define QUADSPI_BFGENCR_PAREN (1 << 16) +#define QUADSPI_BFGENCR_SEQID(x) ((x & 0xF) << 12) + +#define QUADSPI_SOCCR_SOCCFG(x) (x & 0xFF) + +#define QUADSPI_BUFIND_TPINDX(x) (x << 3) + +#define QUADSPI_SMPR_DDRSMP(x) ((x & 7) << 16) +#define QUADSPI_SMPR_FSDLY (1 << 6) +#define QUADSPI_SMPR_FSPHS (1 << 5) +#define QUADSPI_SMPR_HSDLY (1 << 2) +#define QUADSPI_SMPR_HSPHS (1 << 1) +#define QUADSPI_SMPR_HSENA (1 << 0) + +#define QUADSPI_RBCT_WMRK(x) (x & 0x1F) +#define QUADSPI_RBCT_RXBRD (1 << 8) + +#define QUADSPI_SR_TXFULL (1 << 27) +#define QUADSPI_SR_TXNE (1 << 24) +#define QUADSPI_SR_RXDMA (1 << 23) +#define QUADSPI_SR_RXFULL (1 << 19) +#define QUADSPI_SR_RXWE (1 << 15) +#define QUADSPI_SR_AHB3FUL (1 << 14) +#define QUADSPI_SR_AHB2FUL (1 << 13) +#define QUADSPI_SR_AHB1FUL (1 << 12) +#define QUADSPI_SR_AHB0FUL (1 << 11) +#define QUADSPI_SR_AHB3NE (1 << 10) +#define QUADSPI_SR_AHB2NE (1 << 9) +#define QUADSPI_SR_AHB1NE (1 << 8) +#define QUADSPI_SR_AHB0NE (1 << 7) +#define QUADSPI_SR_AHBTRN (1 << 6) +#define QUADSPI_SR_AHBGNT (1 << 5) +#define QUADSPI_SR_AHBACC (1 << 2) +#define QUADSPI_SR_IPACC (1 << 1) +#define QUADSPI_SR_BUSY (1 << 0) + +#define QUADSPI_FR_DLPFF (1 << 31) +#define QUADSPI_FR_TBFF (1 << 27) +#define QUADSPI_FR_TBUF (1 << 26) +#define QUADSPI_FR_ILLINE (1 << 23) +#define QUADSPI_FR_RBOF (1 << 17) +#define QUADSPI_FR_RBDF (1 << 16) +#define QUADSPI_FR_ABSEF (1 << 15) +#define QUADSPI_FR_ABOF (1 << 12) +#define QUADSPI_FR_IUEF (1 << 11) +#define QUADSPI_FR_IPAEF (1 << 7) +#define QUADSPI_FR_IPIEF (1 << 6) +#define QUADSPI_FR_IPGEF (1 << 4) +#define QUADSPI_FR_TFF (1 << 0) + +/* QUADSPI_RSER use QUADSPI_FR bit field */ + +#define QUADSPI_SPTRCLR_IPPTRC (1 << 8) +#define QUADSPI_SPTRCLR_BFPTRC (1 << 0) + +#define QUADSPI_SFAnAD(x) (x << 10) + +#define QUADSPI_LCKCR_UNLOCK (1 << 1) +#define QUADSPI_LCKCR_LOCK (1 << 0) + +#define QUADSPI_LUTn_INSTR1(x) ((x & 0x3F) << 26) +#define QUADSPI_LUTn_PAD1(x) ((x & 0x3) << 24) +#define QUADSPI_LUTn_OPRND1(x) ((x & 0xFF) << 16) +#define QUADSPI_LUTn_INSTR0(x) ((x & 0x3F) << 10) +#define QUADSPI_LUTn_PAD0(x) ((x & 0x3) << 8) +#define QUADSPI_LUTn_OPRND0(x) ((x & 0xFF) << 0) + +#endif /* __QUADSPI_H__ */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c967d87834..c3746b035c 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_QUAD_SPI) += quad_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/quad_spi.c b/drivers/spi/quad_spi.c new file mode 100644 index 0000000000..7afeacf72e --- /dev/null +++ b/drivers/spi/quad_spi.c @@ -0,0 +1,133 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +struct quadspi_slave { + struct spi_slave slave; + uint baudrate; + int charbit; +}; + +int quadspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, + void *din, ulong flags); +struct spi_slave *quadspi_setup_slave(struct quadspi_slave *slave, uint mode); +void quadspi_init(void); +void quadspi_tx(u32 ctrl, u16 data); +u16 quadspi_rx(void); + +extern void setup_iomux_quadspi(void); +extern int quadspi_claim_bus(uint bus, uint cs); +extern void quadspi_release_bus(uint bus, uint cs); + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_QUAD_SPI +void quadspi_init(void) +{ + setup_iomux_quadspi(); /* port configuration */ +} + +void quadspi_tx(u32 ctrl, u16 data) +{ +} + +u16 quadspi_rx(void) +{ + return 0; +} + +int quadspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, + void *din, ulong flags) +{ + return 0; +} + +struct spi_slave *quadspi_setup_slave(struct quadspi_slave *slave, uint mode) +{ + return 0; +} +#endif /* CONFIG_QUAD_SPI */ + +#ifdef CONFIG_CMD_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 0; +} + +void spi_init_f(void) +{ +} + +void spi_init_r(void) +{ +} + +void spi_init(void) +{ + quadspi_init(); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct quadspi_slave *slave; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct quadspi_slave)); + if (!slave) + return NULL; + + slave->slave.bus = bus; + slave->slave.cs = cs; + slave->baudrate = max_hz; + + /* specific setup */ + return quadspi_setup_slave(slave, mode); +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return quadspi_claim_bus(slave->bus, slave->cs); +} + +void spi_release_bus(struct spi_slave *slave) +{ + quadspi_release_bus(slave->bus, slave->cs); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + return quadspi_xfer(slave, bitlen, dout, din, flags); +} +#endif /* CONFIG_CMD_SPI */ diff --git a/include/qspi.h b/include/qspi.h new file mode 100644 index 0000000000..badf736739 --- /dev/null +++ b/include/qspi.h @@ -0,0 +1,141 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _QSPI_H_ +#define _QSPI_H_ + +typedef struct { + ulong size; /* total size in bytes */ + ulong sector_cnt; /* number of erase units */ + ulong flash_id; /* flash_id */ + /* virtual sector start addr */ + ulong start[CONFIG_SYS_MAX_QSPI_FLASH_SECT]; + /* sector protection status */ + ulong protect[CONFIG_SYS_MAX_QSPI_FLASH_SECT]; + uchar iowidth; /* witdh of the IO pad */ + ulong erase_blk_tout; /* maximum block erase timeout */ + ulong write_tout; /* maximum write timeout */ + ushort vendor; /* Primary vendor ID */ + ushort manufacturer_id; /* manufacturer ID */ +} qspi_flash_info_t; + +/* Command registers */ +#define QSPI_CMD_WRR 0x01 /* Write */ +#define QSPI_CMD_PP 0x02 /* Page Program */ +#define QSPI_CMD_READ 0x03 /* Read */ +#define QSPI_CMD_WRDI 0x04 /* Write Disable */ +#define QSPI_CMD_RDSR1 0x05 /* Read Status */ +#define QSPI_CMD_WREN 0x06 /* Write Enable */ +#define QSPI_CMD_RDSR2 0x07 /* Read Status 2 */ +#define QSPI_CMD_FAST_RD 0x0B /* Read Fast */ +#define QSPI_CMD_4FAST_RD 0x0C /* Read Fast */ +#define QSPI_CMD_DDRFR 0x0D /* Read DDR Fast */ +#define QSPI_CMD_4DDRFR 0x0E /* Read DDR Fast */ +#define QSPI_CMD_4PP 0x12 /* Page Program */ +#define QSPI_CMD_4READ 0x13 /* Read */ +#define QSPI_CMD_ABRD 0x14 /* AutoBoot Read */ +#define QSPI_CMD_ABWR 0x15 /* AutoBoot Write */ +#define QSPI_CMD_BRRD 0x16 /* Bank Register Read */ +#define QSPI_CMD_BRWR 0x17 /* Bank Register Write */ +#define QSPI_CMD_P4E 0x20 /* 4KB Sector Erase */ +#define QSPI_CMD_4P4E 0x21 /* 4KB Sector Erase */ +#define QSPI_CMD_ASPRD 0x2B /* ASP Read */ +#define QSPI_CMD_ASPP 0x2F /* ASP Program */ +#define QSPI_CMD_CLSR 0x30 /* Clear Status */ +#define QSPI_CMD_QPP 0x32 /* Quad Page Program */ +#define QSPI_CMD_4QPP 0x34 /* Quad Page Program */ +#define QSPI_CMD_RDCR 0x35 /* Read Configuration */ +#define QSPI_CMD_QPPALT 0x38 /* Quad Page Program Alt */ +#define QSPI_CMD_DOR 0x3B /* Read Dual Out */ +#define QSPI_CMD_4DOR 0x3C /* Read Dual Out */ +#define QSPI_CMD_DLPRD 0x41 /* Data Learning Pattern Read*/ +#define QSPI_CMD_PNVDLR 0x43 /* Program NVDLR */ +#define QSPI_CMD_WVDLR 0x4A /* Write VDLR */ +#define QSPI_CMD_BE 0x60 /* Bulk Erase */ +#define QSPI_CMD_QOR 0x6B /* Read Quad Out */ +#define QSPI_CMD_4QOR 0x6C /* Read Quad Out */ +#define QSPI_CMD_ERSP 0x75 /* Erase Suspend */ +#define QSPI_CMD_ERRS 0x7A /* Erase Resume */ +#define QSPI_CMD_RGSP 0x85 /* Program Suspend */ +#define QSPI_CMD_PGRS 0x8A /* Program Resume */ +#define QSPI_CMD_REMS 0x90 /* Read Manufacturer signature */ +#define QSPI_CMD_RDID 0x9F /* Read ID*/ +#define QSPI_CMD_PLBWR 0xA6 /* PPB Lock Write*/ +#define QSPI_CMD_PLBRD 0xA7 /* PPB Lock Read */ +#define QSPI_CMD_RES 0xAB /* Read Elec. Signature */ +#define QSPI_CMD_BRAC 0xB9 /* Bank Register Access */ +#define QSPI_CMD_DIOR 0xBB /* Dual IO Read */ +#define QSPI_CMD_4DIOR 0xBC /* Dual IO Read */ +#define QSPI_CMD_DDRDIOR 0xBD /* DDR Dual IO Read */ +#define QSPI_CMD_4DDRDIOR 0xBE /* DDR Dual IO Read */ +#define QSPI_CMD_BEALT 0xC7 /* Bulk Erase alt */ +#define QSPI_CMD_SE 0xD8 /* Erase 64/256KB */ +#define QSPI_CMD_4SE 0xDC /* Erase 64/256KB */ +#define QSPI_CMD_DYBRD 0xE0 /* DBY Read */ +#define QSPI_CMD_DYBP 0xE1 /* DBY Program */ +#define QSPI_CMD_PPBRD 0xE2 /* PPB Read*/ +#define QSPI_CMD_PASSRD 0xE7 /* Password Read */ +#define QSPI_CMD_PASSSP 0xE8 /* Password Program */ +#define QSPI_CMD_PASSSU 0xE9 /* Password Unlock */ +#define QSPI_CMD_QIOR 0xEB /* Quad IO Read */ +#define QSPI_CMD_4QIOR 0xEC /* Quad IO Read */ +#define QSPI_CMD_DDRQIOR 0xED /* DDR Quad IO Read */ +#define QSPI_CMD_4DDRQIOR 0xEE /* DDR Quad IO Read */ +#define QSPI_CMD_RESET 0xF0 /* SW Reset */ +#define QSPI_CMD_MBR 0xFF /* Mode bit Reset */ + +/* Status Register 1 */ +#define QSPI_SR1_SRWD 0x80 /* Status register wr disable */ +#define QSPI_SR1_P_ERR 0x40 /* Programming Error Occurred */ +#define QSPI_SR1_E_ERR 0x20 /* Erase Error Occurred */ +#define QSPI_SR1_BP2 0x10 /* Block Protection */ +#define QSPI_SR1_BP1 0x08 +#define QSPI_SR1_BP0 0x04 +#define QSPI_SR1_WEL 0x02 /* Write Enable Latch */ +#define QSPI_SR1_WIP 0x01 /* Write in progress */ + +/* Status Register 2 */ +#define QSPI_SR2_ES 0x02 /* Erase suspend */ +#define QSPI_SR2_PS 0x01 /* Program Suspend */ + +/* Configuration register */ +#define QSPI_CR1_LC1 0x80 /* Latency Code */ +#define QSPI_CR1_LC0 0x40 +#define QSPI_CR1_TBPROT 0x20 /* Config. Start of Block Protection */ +#define QSPI_CR1_RFU 0x10 /* RFU */ +#define QSPI_CR1_BPNV 0x08 /* Config. BP2-0 in Status register */ +#define QSPI_CR1_TBPARM 0x04 /* Config. Parameter Sectors Location */ +#define QSPI_CR1_QUAD 0x02 /* Quad I/O Operation */ +#define QSPI_CR1_FREEZE 0x01 /* Lock current state of BP2-0 */ + +/* Bank Address Register */ +#define QSPI_BAR_EXTADD 0x80 /* Extended Address En */ +#define QSPI_BAR_BA24 0x01 /* Bank Address */ + +/* ASP Register */ +#define QSPI_ASPR_PWDMLB 0x04 /* Password protection lock bit */ +#define QSPI_ASPR_PSTMLB 0x02 /* persistent Protection lock bit */ + + + + +#endif /* _QSPI_H_ */ -- cgit v1.2.3