From 7d1febd4af77435dd4051360e5e9aac46efa61e8 Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Mon, 14 Feb 2022 14:52:34 +0100 Subject: ARM: dts: verdin-imx8mm: update IOMUX configuration Update IOMUX configuration as required by the hardware design team. Signed-off-by: Andrejs Cainikovs --- arch/arm/dts/imx8mm-verdin.dts | 214 ++++++++++++++++++++--------------------- 1 file changed, 107 insertions(+), 107 deletions(-) diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index e134a13fb9..057f3e8fa0 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -451,38 +451,38 @@ imx8mm-verdin { pinctrl_can1_int: can1intgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146 >; }; pinctrl_can2_int: can2intgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106 >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6 /* SODIMM 196 */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6 /* SODIMM 200 */ + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6 /* SODIMM 198 */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6 /* SODIMM 202 */ >; }; pinctrl_ecspi3: ecspi3grp { fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146 >; }; pinctrl_fec1: fec1grp { fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f @@ -496,108 +496,108 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ - MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ - MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106 /* SODIMM 66 */ + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106 /* SODIMM 62 */ >; }; /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */ pinctrl_gpio_hpd: gpiohpdgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146 /* SODIMM 17 */ >; }; /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */ pinctrl_gpio1: gpio1grp { fsl,pins = < - MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106 /* SODIMM 206 */ >; }; pinctrl_gpio2: gpio2grp { fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106 /* SODIMM 208 */ >; }; pinctrl_gpio3: gpio3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106 /* SODIMM 210 */ >; }; pinctrl_gpio4: gpio4grp { fsl,pins = < - MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106 /* SODIMM 212 */ >; }; pinctrl_gpio5: gpio5grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106 /* SODIMM 216 */ >; }; pinctrl_gpio6: gpio6grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106 /* SODIMM 218 */ >; }; pinctrl_gpio7: gpio7grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106 /* SODIMM 220 */ >; }; pinctrl_gpio8: gpio8grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106 /* SODIMM 222 */ >; }; /* On Module I2C */ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146 >; }; /* Verdin I2C_4_CSI */ pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146 /* SODIMM 53 */ >; }; /* Verdin I2C_2_DSI */ pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146 /* SODIMM 93 */ >; }; /* Verdin I2C_1 */ pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146 /* SODIMM 12 */ >; }; @@ -610,13 +610,13 @@ pinctrl_pmic: pmicirq { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; pinctrl_reg_eth: regethgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146 >; }; @@ -641,58 +641,58 @@ pinctrl_se050_ena: se050enagrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106 >; }; pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1c4 /* SODIMM 149 */ - MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1c4 /* SODIMM 147 */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x146 /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x146 /* SODIMM 147 */ >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4 /* SODIMM 129 */ - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4 /* SODIMM 131 */ - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146 /* SODIMM 129 */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146 /* SODIMM 131 */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146 /* SODIMM 133 */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146 /* SODIMM 135 */ >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ - MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ - MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ - MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146 /* SODIMM 137 */ + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146 /* SODIMM 139 */ + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146 /* SODIMM 141 */ + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146 /* SODIMM 143 */ >; }; pinctrl_uart4: uart4grp { fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146 /* SODIMM 151 */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146 /* SODIMM 153 */ >; }; pinctrl_reg_usb1_en: regusb1en { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106 /* SODIMM 155 */ >; }; pinctrl_reg_usb2_en: regusb2en { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106 /* SODIMM 185 */ >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 @@ -708,8 +708,8 @@ pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 @@ -725,8 +725,8 @@ pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 @@ -742,102 +742,102 @@ pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6 /* SODIMM 84 */ >; }; pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6 /* SODIMM 76 */ >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SODIMM 78 */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0xd0 /* SODIMM 74 */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xd0 /* SODIMM 80 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xd0 /* SODIMM 82 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xd0 /* SODIMM 70 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xd0 /* SODIMM 72 */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0xd4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xd4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xd4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xd4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xd4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0xd6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xd6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xd6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xd6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xd6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150 >; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154 >; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; pinctrl_wifi_ctrl: wifictrlgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* WIFI_WKUP_WLAN */ - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146 /* WIFI_W_WKUP_HOST */ >; }; pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6 /* PMIC_EN_WIFI */ >; }; -- cgit v1.2.3