From 735d3a6c8eb0ed8891d7d6018297cb24eea1661c Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Thu, 3 Aug 2017 19:05:42 +0200 Subject: colibri-imx6ull: add initial The resulting U-Boot boots at least from serial downloader mode. Signed-off-by: Max Krummenacher Acked-by: Marcel Ziswiler --- arch/arm/cpu/armv7/mx6/Kconfig | 7 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6ull-colibri.dts | 135 +++++++ arch/arm/dts/imx6ull.dtsi | 1 + arch/arm/imx-common/cmd_writebcb_mx7.c | 35 +- board/toradex/colibri-imx6ull/Kconfig | 29 ++ board/toradex/colibri-imx6ull/MAINTAINERS | 10 + board/toradex/colibri-imx6ull/Makefile | 6 + board/toradex/colibri-imx6ull/colibri_imx6ull.c | 465 ++++++++++++++++++++++++ board/toradex/colibri-imx6ull/imximage.cfg | 107 ++++++ configs/colibri-imx6ull_defconfig | 59 +++ include/configs/colibri-imx6ull.h | 256 +++++++++++++ 12 files changed, 1108 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/imx6ull-colibri.dts create mode 100644 board/toradex/colibri-imx6ull/Kconfig create mode 100644 board/toradex/colibri-imx6ull/MAINTAINERS create mode 100644 board/toradex/colibri-imx6ull/Makefile create mode 100644 board/toradex/colibri-imx6ull/colibri_imx6ull.c create mode 100644 board/toradex/colibri-imx6ull/imximage.cfg create mode 100644 configs/colibri-imx6ull_defconfig create mode 100644 include/configs/colibri-imx6ull.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index bbeec37e9f..d5e6c83031 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -79,6 +79,12 @@ config TARGET_COLIBRI_IMX6 select DM_SERIAL select DM_THERMAL +config TARGET_COLIBRI_IMX6ULL + bool "Toradex Colibri iMX6ULL" + select MX6ULL + select DM + select DM_THERMAL + config TARGET_EMBESTMX6BOARDS bool "embestmx6boards" @@ -268,6 +274,7 @@ source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" +source "board/toradex/colibri-imx6ull/Kconfig" source "board/udoo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b698421284..69bee95b82 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -284,6 +284,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ bk4r1.dtb dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ + imx6ull-colibri.dtb \ imx6dl-icore.dtb \ imx6q-icore.dtb diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts new file mode 100644 index 0000000000..28b7ef67ba --- /dev/null +++ b/arch/arm/dts/imx6ull-colibri.dts @@ -0,0 +1,135 @@ +/* + * Copyright 2017 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include +#include "imx6ull.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL"; + compatible = "toradex,imx6ull-colibri", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-gpio"; + regulator-name = "V3.3_1.8_SD"; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1 3300000 0x0>; + }; + + reg_soc_in: regulator-gpio { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1275000>; + regulator-name = "gpio_soc_in"; + regulator-type = "voltage"; + }; + }; + +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; + dc-supply = <®_soc_in>; +}; + +#if TODO +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; +#endif +/* TODO, remove this in U-Boot */ +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; + ad7879@2c { + compatible = "todo"; + reg = <0x2c>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_reg_sd: reg-sd-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 + MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 + MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x79 + MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x79 + >; + }; +}; + +&iomuxc_snvs { +}; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 65950e8019..b3c5f980b9 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include "imx6ull-pinfunc.h" #include "imx6ull-pinfunc-snvs.h" diff --git a/arch/arm/imx-common/cmd_writebcb_mx7.c b/arch/arm/imx-common/cmd_writebcb_mx7.c index 9174a03d14..6dfe7a22e7 100644 --- a/arch/arm/imx-common/cmd_writebcb_mx7.c +++ b/arch/arm/imx-common/cmd_writebcb_mx7.c @@ -24,10 +24,22 @@ #include #include #include + +#ifdef CONFIG_MX7 +/* + * compare with v5_rom_mtd_commit_structures vs. v6_rom_mtd_commit_structures + * in imx-kobs/src/mtd.c + */ +#define USE_RANDOMIZER +#define USE_62_BIT_ECC +#endif + +#ifdef USE_RANDOMIZER #include "rand.h" +#define RAND_16K (16 * 1024) +#endif #define PAGES_PER_STRIDE 64 -#define RAND_16K (16 * 1024) #define BOOT_SEARCH_COUNT 2 /* match with BOOT_CFG_FUSES [6:5] */ @@ -197,6 +209,7 @@ int encode_bch_ecc(void *source_block, size_t source_size, void *target_block, /* gf: FCB_GF */ int m, b0, e0, bn, en, n, gf; +#ifdef USE_62_BIT_ECC /* 62 bit BCH, for i.MX6SX and i.MX7D */ m = 32; b0 = 128; @@ -205,6 +218,16 @@ int encode_bch_ecc(void *source_block, size_t source_size, void *target_block, en = 62; n = 7; gf = 13; +#else + /* 40 bit BCH, for i.MX6UL */ + m = 32; + b0 = 128; + e0 = 40; + bn = 128; + en = 40; + n = 7; + gf = 13; +#endif /* sanity check */ /* nand data block must be large enough for FCB structure */ @@ -365,7 +388,7 @@ static void create_dbbt(struct mtd_info *nand, uint8_t *buf) static int do_write_bcb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int j, k, ret; + int j, ret; uint8_t *buf; size_t rwsize, maxsize; ulong fw1_off, fw2_off; @@ -398,7 +421,10 @@ static int do_write_bcb(cmd_tbl_t *cmdtp, int flag, int argc, rwsize = maxsize = nand->writesize; off = 0; - for(j = 0; j < BOOT_SEARCH_COUNT; j++) { + for (j = 0; j < BOOT_SEARCH_COUNT; j++) { +#ifdef USE_RANDOMIZER + int k; + /* do randomizer */ for (k = 0; k < nand->writesize + nand->oobsize; k++) { *(uint8_t *)(buf + k) ^= RandData[k + ((j * PAGES_PER_STRIDE) % 256) @@ -409,13 +435,16 @@ static int do_write_bcb(cmd_tbl_t *cmdtp, int flag, int argc, #ifdef DEBUG printf("Randomized\n"); dump(buf, 512); #endif +#endif /* USE_RANDOMIZER */ ret = raw_access(nand, (ulong) buf, off, 1, 0); +#ifdef USE_RANDOMIZER /* revert randomizer */ for (k = 0; k < nand->writesize + nand->oobsize; k++) { *(uint8_t *)(buf + k) ^= RandData[k + ((j * PAGES_PER_STRIDE) % 256) / 64 * RAND_16K]; } +#endif /* USE_RANDOMIZER */ printf("FCB %d bytes written to 0x%x: %s\n", rwsize, (unsigned) off, ret ? "ERROR" : "OK"); diff --git a/board/toradex/colibri-imx6ull/Kconfig b/board/toradex/colibri-imx6ull/Kconfig new file mode 100644 index 0000000000..3ce9885c12 --- /dev/null +++ b/board/toradex/colibri-imx6ull/Kconfig @@ -0,0 +1,29 @@ +if TARGET_COLIBRI_IMX6ULL + +config SYS_BOARD + default "colibri-imx6ull" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri-imx6ull" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_NAND + default y + +config TDX_CFG_BLOCK_OFFSET + default "2048" + +config TDX_CFG_BLOCK_OFFSET2 + default "133120" + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS new file mode 100644 index 0000000000..cf5a557948 --- /dev/null +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -0,0 +1,10 @@ +Colibri iMX6ULL +M: Max Krummenacher +M: Toradex ARM Support +W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community +S: Maintained +F: arch/arm/dts/imx6ull-colibri.dts +F: board/toradex/colibri-imx6ull/ +F: configs/colibri-imx6ull_defconfig +F: include/configs/colibri-imx6ull.h diff --git a/board/toradex/colibri-imx6ull/Makefile b/board/toradex/colibri-imx6ull/Makefile new file mode 100644 index 0000000000..36322c59af --- /dev/null +++ b/board/toradex/colibri-imx6ull/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2017 Toradex AG +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_imx6ull.o diff --git a/board/toradex/colibri-imx6ull/colibri_imx6ull.c b/board/toradex/colibri-imx6ull/colibri_imx6ull.c new file mode 100644 index 0000000000..bf8643fcb5 --- /dev/null +++ b/board/toradex/colibri-imx6ull/colibri_imx6ull.c @@ -0,0 +1,465 @@ +/* + * Copyright (C) 2017 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tdx-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_48ohm) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) + +#define USB_CDET_GPIO IMX_GPIO_NR(7, 14) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usb_cdet_pads[] = { + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight On */ + MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Backlight PWM (multiplexed pin) */ + MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define GPIO_BL_ON IMX_GPIO_NR(1, 11) +#define GPIO_PWM_A IMX_GPIO_NR(4, 11) + +static int setup_lcd(void) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + + /* Set BL_ON */ + gpio_request(GPIO_BL_ON, "BL_ON"); + gpio_direction_output(GPIO_BL_ON, 1); + + /* Set PWM to full brightness (assuming inversed polarity) */ + gpio_request(GPIO_PWM_A, "PWM"); + gpio_direction_output(GPIO_PWM_A, 0); + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* USDHC1 is mmc0 */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC2 MXC: %s:failed\n", __func__); + + return ret; +} +/* TODO */ +#define IOMUXC_GPR1_ADDR 0x020E4004 +#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u +#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u + +static int setup_fec(void) +{ + int ret; + /* provide the PHY clock from the i.MX 6 */ + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + /* + * Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK, + * clear gpr1[14], set gpr1[18] + */ + clrsetbits_le32((u32*)IOMUXC_GPR1_ADDR, + IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK, + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); + gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +/* TODO */ +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int reg, ver; + int ret; + + + ret = pmic_get("rn5t567", &dev); + if (ret) + return ret; + ver = pmic_reg_read(dev, RN5T567_LSIVER); + reg = pmic_reg_read(dev, RN5T567_OTPVER); + + printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); + + /* set judge and press timer of N_OE to minimal values */ + pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); + + /* configure sleep slot for 3.3V Ethernet */ + reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT); + reg = (reg & 0xf0) | reg >> 4; + pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg); + + /* disable DCDC2 discharge to avoid backfeeding through VFB2 */ + pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); + + /* configure sleep slot for ARM rail */ + reg = pmic_reg_read(dev, RN5T567_DC2_SLOT); + reg = (reg & 0xf0) | reg >> 4; + pmic_reg_write(dev, RN5T567_DC2_SLOT, reg); + + /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */ + pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); + + return 0; +} + +void reset_cpu(ulong addr) +{ + struct udevice *dev; + + pmic_get("rn5t567", &dev); + + /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ + pmic_reg_write(dev, RN5T567_REPCNT, 0x1); + pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); + + /* + * Re-power factor detection on PMIC side is not instant. 1ms + * proved to be enough time until reset takes effect. + */ + mdelay(1); +} +#endif + +int checkboard(void) +{ + printf("Model: Toradex Colibri iMX6ULL \n"); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_FDT_FIXUP_PARTITIONS) + static struct node_info nodes[] = { + { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + + return ft_common_board_setup(blob, bd); +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +static iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + return -EINVAL; + } + return 0; +} + +int board_usb_phy_mode(int port) +{ + switch (port) { + case 0: + if (gpio_get_value(USB_CDET_GPIO)) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + case 1: + default: + return USB_INIT_HOST; + } +} +#endif + +static struct mxc_serial_platdata mxc_serial_plat = { + .reg = (struct mxc_uart *)UART1_BASE, + .use_dte = 1, +}; + +U_BOOT_DEVICE(mxc_serial) = { + .name = "serial_mxc", + .platdata = &mxc_serial_plat, +}; diff --git a/board/toradex/colibri-imx6ull/imximage.cfg b/board/toradex/colibri-imx6ull/imximage.cfg new file mode 100644 index 0000000000..80bc739c7b --- /dev/null +++ b/board/toradex/colibri-imx6ull/imximage.cfg @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : nand + */ + +BOOT_FROM nand + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000004 +DATA 4 0x021B083C 0x41640158 +DATA 4 0x021B0848 0x40403237 +DATA 4 0x021B0850 0x40403C33 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig new file mode 100644 index 0000000000..13075d6901 --- /dev/null +++ b/configs/colibri-imx6ull_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_COLIBRI_IMX6ULL=y +CONFIG_DM_SERIAL=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,MX6ULL,IMX_NAND" +CONFIG_BOOTDELAY=1 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Colibri iMX6ULL # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_MXC_UART=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Toradex" +CONFIG_G_DNL_VENDOR_NUM=0x1b67 +CONFIG_G_DNL_PRODUCT_NUM=0x4000 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_FDT_FIXUP_PARTITIONS=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h new file mode 100644 index 0000000000..e9e5d2d8d9 --- /dev/null +++ b/include/configs/colibri-imx6ull.h @@ -0,0 +1,256 @@ +/* + * Copyright 2017 Toradex AG + * + * Configuration settings for the Colibri iMX6ULL module. + * + * based on colibri_imx7.h: + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __COLIBRI_IMX6ULL_CONFIG_H +#define __COLIBRI_IMX6ULL_CONFIG_H + +#include "mx6_common.h" +#define CONFIG_IOMUX_LPSR + +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_USE_ARCH_MEMSET + +/* #define CONFIG_DBG_MONITOR*/ +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_CMD_BMODE +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 16352 +#define CONFIG_TFTP_TSIZE + +/* ENET1 */ +#define IMX_FEC_BASE ENET2_BASE_ADDR + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" + +#define SD_BOOTCMD \ + "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \ + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ + "run m4boot && " \ + "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ + "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} " \ + "${setupargs} ${vidargs}; echo Booting from NFS...;" \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ + "ubi.fm_autoconvert=1\0" \ + "ubiboot=run setup; " \ + "setenv bootargs ${defargs} ${ubiargs} " \ + "${setupargs} ${vidargs}; echo Booting from NAND...; " \ + "ubi part ubi && run m4boot && " \ + "ubi read ${kernel_addr_r} kernel && " \ + "ubi read ${fdt_addr_r} dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define CONFIG_BOOTCOMMAND "run ubiboot; " \ + "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;" + +#define BOOTENV_RUN_NET_USB_START "" +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + UBI_BOOTCMD \ + "console=ttymxc0\0" \ + "defargs=\0" \ + "fdt_board=eval-v3\0" \ + "fdt_fixup=;\0" \ + "m4boot=;\0" \ + "ip_dyn=yes\0" \ + "kernel_file=zImage\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "${board}/flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=mmc rescan && setenv interface mmc && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "setup=setenv setupargs " \ + "console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs} consoleblank=0\0" \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + "updlevel=2\0" \ + "vidargs=video=mxsfb:640x480M-16@60" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_NAND_MXS +#define CONFIG_BCH +#define CONFIG_CMD_WRITEBCB_MX7 +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +/* TODO remove nand torture */ +#define CONFIG_CMD_NAND_TORTURE + +/* UBI stuff */ +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */ + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:" \ + "512k(mx6ull-bcb)," \ + "1536k(u-boot1)ro," \ + "1536k(u-boot2)ro," \ + "512k(u-boot-env)," \ + "-(ubi)" + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#define CONFIG_USBD_HS + +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +/* USB Device Firmware Update support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +/* TODO new from mx6ullevk.h */ +#define CONFIG_MXC_GPIO + +#endif -- cgit v1.2.3