From 67ae04a9d961d03e98241de7105f2c5a5f445732 Mon Sep 17 00:00:00 2001 From: "Rajashekhara, Sudhakar" Date: Tue, 10 Jul 2012 13:41:46 +0530 Subject: da850/omapl138: configure pll1_sysclk3 within allowable limits Currently PLL1_SYSCLK3 clock is being configured to 88MHz but the latest OMAP-L138 data sheet (http://www.ti.com/lit/ds/symlink/omap-l138.pdf) restricts this frequency to maximum of 75MHz. This patch modifies the PLL divider and configures PLL1_SYSCLK3 to 66MHz. Signed-off-by: Rajashekhara, Sudhakar --- include/configs/da850evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 947a9509e7..ac25615f74 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -99,7 +99,7 @@ #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 #define CONFIG_SYS_DA850_PLL0_PLLM 24 #define CONFIG_SYS_DA850_PLL1_PLLM 21 -- cgit v1.2.3