From 499cd0008399c3cc9953d7b0d7925cf74bb0e71d Mon Sep 17 00:00:00 2001 From: Santhosh Kumar K Date: Tue, 27 Feb 2024 11:50:52 +0530 Subject: ram: k3-ddrss: Set SDRAM_IDX using device private data, ddr_ram_size The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Set SDRAM_IDX using the device private data, ddr_ram_size for AM64x, AM62x and AM62x SIP. Signed-off-by: Santhosh Kumar K Acked-by: Bryan Brattlof --- drivers/ram/k3-ddrss/k3-ddrss.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 87741d3943..322e8e86de 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -781,9 +781,13 @@ static int k3_ddrss_probe(struct udevice *dev) if (ret) return ret; - if (IS_ENABLED(CONFIG_SOC_K3_AM642)) { + k3_ddrss_ddr_bank_base_size_calc(ddrss); + + if (IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM642)) { + /* AM62x SIP supports only up to 512 MB SDRAM */ /* AM64x supports only up to 2 GB SDRAM */ - writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); + writel((((ilog2(ddrss->ddr_ram_size) - 16) << 5) | 0xF), + ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); } @@ -799,8 +803,6 @@ static int k3_ddrss_probe(struct udevice *dev) k3_lpddr4_start(ddrss); - k3_ddrss_ddr_bank_base_size_calc(ddrss); - if (ddrss->ti_ecc_enabled) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.", -- cgit v1.2.3