From 36ad18a6db0eec546b83e6500ceb7593be53a1ed Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Mon, 27 Aug 2012 19:38:59 -0500 Subject: libfdt: Add support for appending the values to a existing property Some properties may contain multiple values, these values may need to be added to the property respectively. this patch provides this functionality. The main purpose of fdt_append_prop() is to append the values to a existing property, or create a new property if it dose not exist. Signed-off-by: Minghuan Lian Signed-off-by: David Gibson --- include/libfdt.h | 95 +++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/libfdt/fdt_rw.c | 27 +++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/include/libfdt.h b/include/libfdt.h index de82ed5ffd..78798e8f54 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1133,6 +1133,101 @@ static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, #define fdt_setprop_string(fdt, nodeoffset, name, str) \ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_cell - append a single cell value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_cell() appends the given cell value (converting to + * big-endian if necessary) to the value of the named property in the + * given node, or creates a new property with that value if it does + * not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + val = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + /** * fdt_delprop - delete a property * @fdt: pointer to the device tree blob diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c index 5c27a677e3..5ed23d6f19 100644 --- a/lib/libfdt/fdt_rw.c +++ b/lib/libfdt/fdt_rw.c @@ -293,6 +293,33 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, return 0; } +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + struct fdt_property *prop; + int err, oldlen, newlen; + + FDT_RW_CHECK_HEADER(fdt); + + prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); + if (prop) { + newlen = len + oldlen; + err = _fdt_splice_struct(fdt, prop->data, + FDT_TAGALIGN(oldlen), + FDT_TAGALIGN(newlen)); + if (err) + return err; + prop->len = cpu_to_fdt32(newlen); + memcpy(prop->data + oldlen, val, len); + } else { + err = _fdt_add_property(fdt, nodeoffset, name, len, &prop); + if (err) + return err; + memcpy(prop->data, val, len); + } + return 0; +} + int fdt_delprop(void *fdt, int nodeoffset, const char *name) { struct fdt_property *prop; -- cgit v1.2.3 From 24fa0e588e68dfb4b15d1e94c543c9301d226902 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 27 Aug 2012 19:39:00 -0500 Subject: libfdt: Add helpers for 64-bit integer properties In device trees in the world, properties consisting of a single 64-bit integer are not as common as those consisting of a single 32-bit, cell sized integer, but they're common enough that they're worth including convenience functions for. This patch adds helper wrappers of fdt_setprop_inplace(), fdt_setprop() and fdt_appendprop() for handling 64-bit integer quantities in properties. For better consistency with the names of these new *_u64() functions we also add *_u32() functions as alternative names for the existing *_cell() functions handling 32-bit integers. Signed-off-by: David Gibson --- include/libfdt.h | 193 ++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 170 insertions(+), 23 deletions(-) diff --git a/include/libfdt.h b/include/libfdt.h index 78798e8f54..4589c5feb4 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -852,17 +852,17 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, const void *val, int len); /** - * fdt_setprop_inplace_cell - change the value of a single-cell property + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change * @name: name of the property to change - * @val: cell (32-bit integer) value to replace the property with + * @val: 32-bit integer value to replace the property with * - * fdt_setprop_inplace_cell() replaces the value of a given property - * with the 32-bit integer cell value in val, converting val to - * big-endian if necessary. This function cannot change the size of a - * property, and so will only work if the property already exists and - * has length 4. + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. * * This function will alter only the bytes in the blob which contain * the given property value, and will not alter or move any other part @@ -871,7 +871,7 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, * returns: * 0, on success * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 - * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_NOTFOUND, node does not have the named property * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag * -FDT_ERR_BADMAGIC, * -FDT_ERR_BADVERSION, @@ -879,13 +879,59 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, * -FDT_ERR_BADSTRUCTURE, * -FDT_ERR_TRUNCATED, standard meanings */ -static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) { val = cpu_to_fdt32(val); return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); } +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + /** * fdt_nop_property - replace a property with nop tags * @fdt: pointer to the device tree blob @@ -945,11 +991,20 @@ int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); int fdt_finish_reservemap(void *fdt); int fdt_begin_node(void *fdt, const char *name); int fdt_property(void *fdt, const char *name, const void *val, int len); -static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) { val = cpu_to_fdt32(val); return fdt_property(fdt, name, &val, sizeof(val)); } +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_property(fdt, name, &val, sizeof(val)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} #define fdt_property_string(fdt, name, str) \ fdt_property(fdt, name, str, strlen(str)+1) int fdt_end_node(void *fdt); @@ -1068,14 +1123,14 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); /** - * fdt_setprop_cell - set a property to a single cell value + * fdt_setprop_u32 - set a property to a 32-bit integer * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change * @name: name of the property to change * @val: 32-bit integer value for the property (native endian) * - * fdt_setprop_cell() sets the value of the named property in the - * given node to the given cell value (converting to big-endian if + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if * necessary), or creates a new property with that value if it does * not already exist. * @@ -1095,13 +1150,59 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, * -FDT_ERR_BADLAYOUT, * -FDT_ERR_TRUNCATED, standard meanings */ -static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, - uint32_t val) +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) { val = cpu_to_fdt32(val); return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); } +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + /** * fdt_setprop_string - set a property to a string value * @fdt: pointer to the device tree blob @@ -1164,16 +1265,16 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); /** - * fdt_appendprop_cell - append a single cell value to a property + * fdt_appendprop_u32 - append a 32-bit integer value to a property * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node whose property to change * @name: name of the property to change * @val: 32-bit integer value to append to the property (native endian) * - * fdt_appendprop_cell() appends the given cell value (converting to - * big-endian if necessary) to the value of the named property in the - * given node, or creates a new property with that value if it does - * not already exist. + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. * * This function may insert data into the blob, and will therefore * change the offsets of some existing nodes. @@ -1191,13 +1292,59 @@ int fdt_appendprop(void *fdt, int nodeoffset, const char *name, * -FDT_ERR_BADLAYOUT, * -FDT_ERR_TRUNCATED, standard meanings */ -static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) { val = cpu_to_fdt32(val); return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); } +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + val = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + /** * fdt_appendprop_string - append a string to a property * @fdt: pointer to the device tree blob -- cgit v1.2.3 From 367e12597617b2581eb72b3676c6cb86822268b5 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 17 Aug 2012 10:34:35 +0000 Subject: fdt: Check error codes returned from fdtlib when loading ITB Before this patch, error codes returned from fdtlib were ignored and continued access would cause a crash. Now just check if the image is truncated and error if so. Signed-off-by: Joe Hershberger --- common/image.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/common/image.c b/common/image.c index f084d2baed..852a96fab8 100644 --- a/common/image.c +++ b/common/image.c @@ -2820,6 +2820,11 @@ int fit_image_check_hashes(const void *fit, int image_noffset) } } + if (noffset == -FDT_ERR_TRUNCATED || noffset == -FDT_ERR_BADSTRUCTURE) { + err_msg = " error!\nCorrupted or truncated tree"; + goto error; + } + return 1; error: -- cgit v1.2.3 From f0a29d43313c9d0d9091aeae175bd7e8e7ac6124 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 17 Aug 2012 10:34:36 +0000 Subject: fdt: Limit printed hex in fdt print and list commands Prevent printing the entire image in a itb. It is most likely unhelpful to have the hex of the entire image scroll for minutes on your slow serial console. Signed-off-by: Joe Hershberger --- common/cmd_fdt.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index e2225c4d5c..699441b51a 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -35,6 +35,9 @@ #define MAX_LEVEL 32 /* how deeply nested we will go */ #define SCRATCHPAD 1024 /* bytes of scratchpad memory */ +#ifndef CONFIG_CMD_FDT_MAX_DUMP +#define CONFIG_CMD_FDT_MAX_DUMP 64 +#endif /* * Global data (for the gd->bd) @@ -672,19 +675,28 @@ static void print_data(const void *data, int len) } if ((len %4) == 0) { - const u32 *p; - - printf("<"); - for (j = 0, p = data; j < len/4; j ++) - printf("0x%x%s", fdt32_to_cpu(p[j]), j < (len/4 - 1) ? " " : ""); - printf(">"); + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%08x [0x%08x]", (unsigned int)data, len); + else { + const u32 *p; + + printf("<"); + for (j = 0, p = data; j < len/4; j++) + printf("0x%08x%s", fdt32_to_cpu(p[j]), + j < (len/4 - 1) ? " " : ""); + printf(">"); + } } else { /* anything else... hexdump */ - const u8 *s; - - printf("["); - for (j = 0, s = data; j < len; j++) - printf("%02x%s", s[j], j < len - 1 ? " " : ""); - printf("]"); + if (len > CONFIG_CMD_FDT_MAX_DUMP) + printf("* 0x%08x [0x%08x]", (unsigned int)data, len); + else { + const u8 *s; + + printf("["); + for (j = 0, s = data; j < len; j++) + printf("%02x%s", s[j], j < len - 1 ? " " : ""); + printf("]"); + } } } -- cgit v1.2.3 From bc80295b620c5abf9d4fb3b00846ef018e921540 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 17 Aug 2012 10:34:37 +0000 Subject: fdt: Add get commands to fdt Add commands to access data in the fdt. This allows data from a dtb or itb to be accessed from the shell scripts. Signed-off-by: Joe Hershberger --- common/cmd_fdt.c | 144 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 699441b51a..2997452370 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; static int fdt_valid(void); static int fdt_parse_prop(char *const*newval, int count, char *data, int *len); static int fdt_print(const char *pathp, char *prop, int depth); +static int is_printable_string(const void *data, int len); /* * The working_fdt points to our working flattened device tree. @@ -63,6 +64,34 @@ void set_working_fdt_addr(void *addr) setenv("fdtaddr", buf); } +/* + * Get a value from the fdt and format it to be set in the environment + */ +static int fdt_value_setenv(const void *nodep, int len, const char *var) +{ + if (is_printable_string(nodep, len)) + setenv(var, (void *)nodep); + else if (len == 4) { + char buf[11]; + + sprintf(buf, "0x%08X", *(uint32_t *)nodep); + setenv(var, buf); + } else if (len%4 == 0 && len <= 20) { + /* Needed to print things like sha1 hashes. */ + char buf[41]; + int i; + + for (i = 0; i < len; i += sizeof(unsigned int)) + sprintf(buf + (i * 2), "%08x", + *(unsigned int *)(nodep + i)); + setenv(var, buf); + } else { + printf("error: unprintable value\n"); + return 1; + } + return 0; +} + /* * Flattened Device Tree command, see the help for parameter definitions. */ @@ -253,6 +282,117 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 1; } + /******************************************************************** + * Get the value of a property in the working_fdt. + ********************************************************************/ + } else if (argv[1][0] == 'g') { + char *subcmd; /* sub-command */ + char *pathp; /* path */ + char *prop; /* property */ + char *var; /* variable to store result */ + int nodeoffset; /* node offset from libfdt */ + const void *nodep; /* property node pointer */ + int len = 0; /* new length of the property */ + + /* + * Parameters: Node path, property, optional value. + */ + if (argc < 5) + return CMD_RET_USAGE; + + subcmd = argv[2]; + + if (argc < 6 && subcmd[0] != 's') + return CMD_RET_USAGE; + + var = argv[3]; + pathp = argv[4]; + prop = argv[5]; + + nodeoffset = fdt_path_offset(working_fdt, pathp); + if (nodeoffset < 0) { + /* + * Not found or something else bad happened. + */ + printf("libfdt fdt_path_offset() returned %s\n", + fdt_strerror(nodeoffset)); + return 1; + } + + if (subcmd[0] == 'n' || (subcmd[0] == 's' && argc == 5)) { + int reqIndex = -1; + int startDepth = fdt_node_depth( + working_fdt, nodeoffset); + int curDepth = startDepth; + int curIndex = -1; + int nextNodeOffset = fdt_next_node( + working_fdt, nodeoffset, &curDepth); + + if (subcmd[0] == 'n') + reqIndex = simple_strtoul(argv[5], NULL, 16); + + while (curDepth > startDepth) { + if (curDepth == startDepth + 1) + curIndex++; + if (subcmd[0] == 'n' && curIndex == reqIndex) { + const char *nodeName = fdt_get_name( + working_fdt, nextNodeOffset, NULL); + + setenv(var, (char *)nodeName); + return 0; + } + nextNodeOffset = fdt_next_node( + working_fdt, nextNodeOffset, &curDepth); + if (nextNodeOffset < 0) + break; + } + if (subcmd[0] == 's') { + /* get the num nodes at this level */ + char buf[11]; + + sprintf(buf, "%d", curIndex + 1); + setenv(var, buf); + } else { + /* node index not found */ + printf("libfdt node not found\n"); + return 1; + } + } else { + nodep = fdt_getprop( + working_fdt, nodeoffset, prop, &len); + if (len == 0) { + /* no property value */ + setenv(var, ""); + return 0; + } else if (len > 0) { + if (subcmd[0] == 'v') { + int ret; + + ret = fdt_value_setenv(nodep, len, var); + if (ret != 0) + return ret; + } else if (subcmd[0] == 'a') { + /* Get address */ + char buf[11]; + + sprintf(buf, "0x%08X", (uint32_t)nodep); + setenv(var, buf); + } else if (subcmd[0] == 's') { + /* Get size */ + char buf[11]; + + sprintf(buf, "0x%08X", len); + setenv(var, buf); + } else + return CMD_RET_USAGE; + return 0; + } else { + printf("libfdt fdt_getprop(): %s\n", + fdt_strerror(len)); + return 1; + } + } + /* * Print (recursive) / List (single level) */ @@ -836,6 +976,10 @@ U_BOOT_CMD( "fdt resize - Resize fdt to size + padding to 4k addr\n" "fdt print [] - Recursive print starting at \n" "fdt list [] - Print one level starting at \n" + "fdt get value - Get and store in \n" + "fdt get name - Get name of node and store in \n" + "fdt get addr - Get start address of and store in \n" + "fdt get size [] - Get size of [] or num nodes and store in \n" "fdt set [] - Set [to ]\n" "fdt mknode - Create a new node after \n" "fdt rm [] - Delete the node or \n" -- cgit v1.2.3 From 8805beec8f51e861996860db71a831e4c263cf4c Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 17 Aug 2012 10:34:38 +0000 Subject: fdt: Identify scripts in ITBs as printable strings Scripts in the ITB format will have spaces in them and will end in a newline charachter. Make sure that these are considered printable. Signed-off-by: Joe Hershberger --- common/cmd_fdt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 2997452370..a5e2cfcbfa 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -754,12 +754,12 @@ static int is_printable_string(const void *data, int len) if (len == 0) return 0; - /* must terminate with zero */ - if (s[len - 1] != '\0') + /* must terminate with zero or '\n' */ + if (s[len - 1] != '\0' && s[len - 1] != '\n') return 0; /* printable or a null byte (concatenated strings) */ - while (((*s == '\0') || isprint(*s)) && (len > 0)) { + while (((*s == '\0') || isprint(*s) || isspace(*s)) && (len > 0)) { /* * If we see a null, there are three possibilities: * 1) If len == 1, it is the end of the string, printable -- cgit v1.2.3 From 8ac88f2d2818c8efc1558626a4e7fb47dcc18987 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 17 Aug 2012 10:34:39 +0000 Subject: fdt: Check for a token to skip auto-hash validation Allow the itb file to declare to u-boot that its hash should not be checked automatically on bootm or iminfo. This allows an image to either be checked automatically or to include a script which may check it otherwise (such as after part of the itb has been relocated to RAM by the script). Signed-off-by: Joe Hershberger --- common/image.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/image.h | 4 ++++ 2 files changed, 45 insertions(+) diff --git a/common/image.c b/common/image.c index 852a96fab8..750a98b6ba 100644 --- a/common/image.c +++ b/common/image.c @@ -2496,6 +2496,36 @@ int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value, return 0; } +#ifndef USE_HOSTCC +/** + * fit_image_hash_get_ignore - get hash ignore flag + * @fit: pointer to the FIT format image header + * @noffset: hash node offset + * @ignore: pointer to an int, will hold hash ignore flag + * + * fit_image_hash_get_ignore() finds hash ignore property in a given hash node. + * If the property is found and non-zero, the hash algorithm is not verified by + * u-boot automatically. + * + * returns: + * 0, on ignore not found + * value, on ignore found + */ +int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore) +{ + int len; + int *value; + + value = (int *)fdt_getprop(fit, noffset, FIT_IGNORE_PROP, &len); + if (value == NULL || len != sizeof(int)) + *ignore = 0; + else + *ignore = *value; + + return 0; +} +#endif + /** * fit_set_timestamp - set node timestamp property * @fit: pointer to the FIT format image header @@ -2759,6 +2789,9 @@ int fit_image_check_hashes(const void *fit, int image_noffset) char *algo; uint8_t *fit_value; int fit_value_len; +#ifndef USE_HOSTCC + int ignore; +#endif uint8_t value[FIT_MAX_HASH_LEN]; int value_len; int noffset; @@ -2795,6 +2828,14 @@ int fit_image_check_hashes(const void *fit, int image_noffset) } printf("%s", algo); +#ifndef USE_HOSTCC + fit_image_hash_get_ignore(fit, noffset, &ignore); + if (ignore) { + printf("-skipped "); + continue; + } +#endif + if (fit_image_hash_get_value(fit, noffset, &fit_value, &fit_value_len)) { err_msg = " error!\nCan't get hash value " diff --git a/include/image.h b/include/image.h index e5f6649291..4e5863ff7f 100644 --- a/include/image.h +++ b/include/image.h @@ -511,6 +511,7 @@ static inline int image_check_target_arch(const image_header_t *hdr) #define FIT_HASH_NODENAME "hash" #define FIT_ALGO_PROP "algo" #define FIT_VALUE_PROP "value" +#define FIT_IGNORE_PROP "uboot-ignore" /* image node */ #define FIT_DATA_PROP "data" @@ -595,6 +596,9 @@ int fit_image_get_data(const void *fit, int noffset, int fit_image_hash_get_algo(const void *fit, int noffset, char **algo); int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value, int *value_len); +#ifndef USE_HOSTCC +int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore); +#endif int fit_set_timestamp(void *fit, int noffset, time_t timestamp); int fit_set_hashes(void *fit); -- cgit v1.2.3 From c71b64f3617b5a4362c6e4e0aefdd66d6ac6affd Mon Sep 17 00:00:00 2001 From: Gerald Van Baren Date: Mon, 15 Oct 2012 22:24:36 -0400 Subject: libfdt: Add helper function to create a trivial, empty tree The libfdt read/write functions are now usable enough that it's become a moderately common pattern to use them to build and manipulate a device tree from scratch. For example, we do so ourself in our rw_tree1 testcase, and qemu is starting to use this model when building device trees for some targets such as e500. However, the read/write functions require some sort of valid tree to begin with, so this necessitates either having a trivial canned dtb to begin with or, more commonly, creating an empty tree using the serial-write functions first. This patch adds a helper function which uses the serial-write functions to create a trivial, empty but complete and valid tree in a supplied buffer, ready for manipulation with the read/write functions. Signed-off-by: David Gibson From git://git.jdl.com/software/dtc.git patch hash be6026838 with adaptations to include/libfdt.h and lib/libfdt/Makefile for the U-Boot environment. Signed-off-by: Gerald Van Baren --- include/libfdt.h | 1 + lib/libfdt/Makefile | 2 +- lib/libfdt/fdt_empty_tree.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 lib/libfdt/fdt_empty_tree.c diff --git a/include/libfdt.h b/include/libfdt.h index 4589c5feb4..c93ae28833 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1014,6 +1014,7 @@ int fdt_finish(void *fdt); /* Read-write functions */ /**********************************************************************/ +int fdt_create_empty_tree(void *buf, int bufsize); int fdt_open_into(const void *fdt, void *buf, int bufsize); int fdt_pack(void *fdt); diff --git a/lib/libfdt/Makefile b/lib/libfdt/Makefile index c965577dc0..0693d4bf55 100644 --- a/lib/libfdt/Makefile +++ b/lib/libfdt/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)libfdt.o SOBJS = -COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o +COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o fdt_empty_tree.o COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt) COBJS-$(CONFIG_FIT) += $(COBJS-libfdt) diff --git a/lib/libfdt/fdt_empty_tree.c b/lib/libfdt/fdt_empty_tree.c new file mode 100644 index 0000000000..f72d13b1d1 --- /dev/null +++ b/lib/libfdt/fdt_empty_tree.c @@ -0,0 +1,84 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2012 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +int fdt_create_empty_tree(void *buf, int bufsize) +{ + int err; + + err = fdt_create(buf, bufsize); + if (err) + return err; + + err = fdt_finish_reservemap(buf); + if (err) + return err; + + err = fdt_begin_node(buf, ""); + if (err) + return err; + + err = fdt_end_node(buf); + if (err) + return err; + + err = fdt_finish(buf); + if (err) + return err; + + return fdt_open_into(buf, buf, bufsize); +} + -- cgit v1.2.3 From b1af67fe5e019bbfaca9ca4ec7086fbdb69c440a Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:56 +0000 Subject: i2c: sh_i2c.c: support iccl and icch extension R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl and icch. This patch add support for the extentin bits. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 30 ++++++++++++++++++++++-------- include/configs/kzm9g.h | 1 + 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 3147123bba..035069f07b 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -48,7 +48,13 @@ static struct sh_i2c *base; #define SH_IC_WAIT (1 << 1) #define SH_IC_DTE (1 << 0) -static u8 iccl, icch; +#ifdef CONFIG_SH_I2C_8BIT +/* store 8th bit of iccl and icch in ICIC register */ +#define SH_I2C_ICIC_ICCLB8 (1 << 7) +#define SH_I2C_ICIC_ICCHB8 (1 << 6) +#endif + +static u16 iccl, icch; #define IRQ_WAIT 1000 @@ -76,12 +82,20 @@ static void irq_busy(struct sh_i2c *base) static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) { + u8 icic = 0; + writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); - writeb(iccl, &base->iccl); - writeb(icch, &base->icch); - writeb(0, &base->icic); + writeb(iccl & 0xff, &base->iccl); + writeb(icch & 0xff, &base->icch); +#ifdef CONFIG_SH_I2C_8BIT + if (iccl > 0xff) + icic |= SH_I2C_ICIC_ICCLB8; + if (icch > 0xff) + icic |= SH_I2C_ICIC_ICCHB8; +#endif + writeb(icic, &base->icic); writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); @@ -206,18 +220,18 @@ void i2c_init(int speed, int slaveaddr) denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); tmp = num * 10 / denom; if (tmp % 10 >= 5) - iccl = (u8)((num/denom) + 1); + iccl = (u16)((num/denom) + 1); else - iccl = (u8)(num/denom); + iccl = (u16)(num/denom); /* Calculate the value for icch. From the data sheet: icch = (p clock / transfer rate) * (H / (L + H)) */ num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; tmp = num * 10 / denom; if (tmp % 10 >= 5) - icch = (u8)((num/denom) + 1); + icch = (u16)((num/denom) + 1); else - icch = (u8)(num/denom); + icch = (u16)(num/denom); } /* diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 3a882e396b..0132e9d0df 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -154,6 +154,7 @@ /* I2C */ #define CONFIG_CMD_I2C #define CONFIG_SH_I2C 1 +#define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS (2) -- cgit v1.2.3 From 57d7c80472d8c87f7c6d321f89a5aed47c865b5a Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:57 +0000 Subject: i2c: sh_i2c.c: correct BUSY bit define in ICSR Correct BUSY bit define in ICSR from (1<<3) to (1<<4). Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 035069f07b..eced61de0b 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -43,7 +43,7 @@ static struct sh_i2c *base; #define SH_I2C_ICCR_SCP (1 << 0) /* ICSR / ICIC */ -#define SH_IC_BUSY (1 << 3) +#define SH_IC_BUSY (1 << 4) #define SH_IC_TACK (1 << 2) #define SH_IC_WAIT (1 << 1) #define SH_IC_DTE (1 << 0) -- cgit v1.2.3 From 3ce2703d8f11b0b5c28409d8335f36bef258831b Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:58 +0000 Subject: i2c: sh_i2c.c: adjust for SH73A0 Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0. After this patch, "i2c md" and "i2c mw" command on U-Boot work properly on KZM-A9-GT board. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 4 ++++ include/configs/kzm9g.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index eced61de0b..c667a1bdf0 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -135,8 +135,12 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) { u8 ret; +#if defined(CONFIG_SH73A0) + i2c_set_addr(base, id, reg, 0); +#else i2c_set_addr(base, id, reg, 1); udelay(100); +#endif writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 0132e9d0df..75b9257e1d 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -163,7 +163,7 @@ #define CONFIG_SYS_I2C_SLAVE (0x7F) #define CONFIG_SH_I2C_DATA_HIGH (4) #define CONFIG_SH_I2C_DATA_LOW (5) -#define CONFIG_SH_I2C_CLOCK (41666666) +#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE6820000) #define CONFIG_SH_I2C_BASE1 (0xE6822000) -- cgit v1.2.3 From 020ec727a6bda10f47d69926814d476c0085e8a9 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:59 +0000 Subject: i2c: sh_i2c.c: support I2C2, I2C3 and I2C4 sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 15 +++++++++++++++ include/configs/kzm9g.h | 5 ++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index c667a1bdf0..d50c8eca6d 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -184,6 +184,21 @@ int i2c_set_bus_num(unsigned int bus) case 1: base = (void *)CONFIG_SH_I2C_BASE1; break; +#ifdef CONFIG_SH_I2C_BASE2 + case 2: + base = (void *)CONFIG_SH_I2C_BASE2; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE3 + case 3: + base = (void *)CONFIG_SH_I2C_BASE3; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE4 + case 4: + base = (void *)CONFIG_SH_I2C_BASE4; + break; +#endif default: return -1; } diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 75b9257e1d..4898fb60f4 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -157,7 +157,7 @@ #define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (2) +#define CONFIG_SYS_MAX_I2C_BUS (5) #define CONFIG_SYS_I2C_MODULE #define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE (0x7F) @@ -166,5 +166,8 @@ #define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE6820000) #define CONFIG_SH_I2C_BASE1 (0xE6822000) +#define CONFIG_SH_I2C_BASE2 (0xE6824000) +#define CONFIG_SH_I2C_BASE3 (0xE6826000) +#define CONFIG_SH_I2C_BASE4 (0xE6828000) #endif /* __KZM9G_H */ -- cgit v1.2.3 From d042d7121b13d98bd403e7b64438ce55cfefd0d9 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:00 +0000 Subject: i2c: sh_i2c: enable i2c_probe Before this patch i2c_probe() always returned 0 and "i2c probe" command did not work properly. Modify i2c_set_addr() to check TACK when waiting DTE and make i2c_probe() call this function. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index d50c8eca6d..a7204cc1d0 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -69,6 +69,20 @@ static void irq_dte(struct sh_i2c *base) } } +static int irq_dte_with_tack(struct sh_i2c *base) +{ + int i; + + for (i = 0 ; i < IRQ_WAIT ; i++) { + if (SH_IC_DTE & readb(&base->icsr)) + break; + if (SH_IC_TACK & readb(&base->icsr)) + return -1; + udelay(10); + } + return 0; +} + static void irq_busy(struct sh_i2c *base) { int i; @@ -80,9 +94,9 @@ static void irq_busy(struct sh_i2c *base) } } -static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) +static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) { - u8 icic = 0; + u8 icic = SH_IC_TACK; writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); @@ -100,14 +114,18 @@ static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); + writeb(readb(&base->icsr) & ~SH_IC_TACK, &base->icsr); writeb(id << 1, &base->icdr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + return -1; writeb(reg, &base->icdr); if (stop) writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + return -1; + return 0; } static void i2c_finish(struct sh_i2c *base) @@ -305,5 +323,9 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) */ int i2c_probe(u8 chip) { - return 0; + int ret; + + ret = i2c_set_addr(base, chip, 0, 1); + i2c_finish(base); + return ret; } -- cgit v1.2.3 From 0e5fb33cf7fa7352e9ecf88a834dd5e178f0e80f Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:01 +0000 Subject: i2c: sh_i2c.c: check error in i2c_read and i2c_write Before this patch, i2c_{read,write} always returned 0. Check TACK in i2c_raw_{read,write} so that i2c_{read,write} return non-zero when error. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 50 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index a7204cc1d0..afcb503f95 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -134,29 +134,37 @@ static void i2c_finish(struct sh_i2c *base) writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); } -static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) +static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) { - i2c_set_addr(base, id, reg, 0); + int ret = -1; + if (i2c_set_addr(base, id, reg, 0) != 0) + goto exit0; udelay(10); writeb(val, &base->icdr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; irq_busy(base); - + ret = 0; +exit0: i2c_finish(base); + return ret; } -static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) +static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) { - u8 ret; + int ret = -1; #if defined(CONFIG_SH73A0) - i2c_set_addr(base, id, reg, 0); + if (i2c_set_addr(base, id, reg, 0) != 0) + goto exit0; #else - i2c_set_addr(base, id, reg, 1); + if (i2c_set_addr(base, id, reg, 1) != 0) + goto exit0; udelay(100); #endif @@ -164,17 +172,19 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) irq_dte(base); writeb(id << 1 | 0x01, &base->icdr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; - ret = readb(&base->icdr); + ret = readb(&base->icdr) & 0xff; writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); readb(&base->icdr); /* Dummy read */ irq_busy(base); - +exit0: i2c_finish(base); return ret; @@ -286,10 +296,14 @@ void i2c_init(int speed, int slaveaddr) */ int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) { + int ret; int i = 0; - for (i = 0 ; i < len ; i++) - buffer[i] = i2c_raw_read(base, chip, addr + i); - + for (i = 0 ; i < len ; i++) { + ret = i2c_raw_read(base, chip, addr + i); + if (ret < 0) + return -1; + buffer[i] = ret & 0xff; + } return 0; } @@ -310,8 +324,8 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) { int i = 0; for (i = 0; i < len ; i++) - i2c_raw_write(base, chip, addr + i, buffer[i]); - + if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0) + return -1; return 0; } -- cgit v1.2.3 From 937b6862def9f2545f7f804441919b767be105b9 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:03 +0000 Subject: arm: rmobile: kzm9g: enable I2C1 Supply clock to I2C1 and release resetting. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- board/kmc/kzm9g/kzm9g.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 525c97aea6..4bfecb67e6 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SMSTPCR1_CMT0 (1 << 24) #define SMSTPCR1_I2C0 (1 << 16) #define SMSTPCR3_USB (1 << 22) +#define SMSTPCR3_I2C1 (1 << 23) #define PORT32CR (0xE6051020) #define PORT33CR (0xE6051021) @@ -287,8 +288,8 @@ int board_early_init_f(void) clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB); - clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB); + clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); + clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); writel(VCLKCR1_D, &cpg->vclkcr1); /* Setup SCIF4 / workaround */ -- cgit v1.2.3 From 650f95b0c7ee4a43a3dc3e64b1074f02a6b4100e Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:04 +0000 Subject: arm: rmobile: kzm9g: enable I2C2 Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- board/kmc/kzm9g/kzm9g.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 4bfecb67e6..54f25e097c 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -344,6 +344,8 @@ int board_init(void) gpio_direction_output(GPIO_PORT15, 1); /* I2C */ + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); -- cgit v1.2.3 From f539094f4886779432053f5ddf7bfb2f45d182e1 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:05 +0000 Subject: i2c: sh_i2c: use setbits/clrbits macro Use setbits/clrbits macro when read-modify-write register. Signed-off-by: Tetsuyuki Kobayashi Acked-by: Nobuhiro Iwamatsu --- drivers/i2c/sh_i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index afcb503f95..44ba90ef57 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -98,8 +98,8 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) { u8 icic = SH_IC_TACK; - writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); - writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); + clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); + setbits_8(&base->iccr, SH_I2C_ICCR_ICE); writeb(iccl & 0xff, &base->iccl); writeb(icch & 0xff, &base->icch); @@ -114,7 +114,7 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); - writeb(readb(&base->icsr) & ~SH_IC_TACK, &base->icsr); + clrbits_8(&base->icsr, SH_IC_TACK); writeb(id << 1, &base->icdr); if (irq_dte_with_tack(base) != 0) return -1; @@ -131,7 +131,7 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) static void i2c_finish(struct sh_i2c *base) { writeb(0, &base->icsr); - writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); + clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); } static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) -- cgit v1.2.3 From ff5d2dce1e8b24e9f4d85db3906c5d2e25b0cedf Mon Sep 17 00:00:00 2001 From: York Sun Date: Sun, 16 Sep 2012 08:02:30 +0000 Subject: common/i2c: Add i2c write command Add i2c write command to write data from memory to i2c devices. Signed-off-by: York Sun --- common/cmd_i2c.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 795814d88f..b59470e7f6 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -223,6 +223,54 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv return 0; } +static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u_char chip; + uint devaddr, alen, length; + u_char *memaddr; + + if (argc != 5) + return cmd_usage(cmdtp); + + /* + * memaddr is the address where to store things in memory + */ + memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16); + + /* + * I2C chip address + */ + chip = simple_strtoul(argv[2], NULL, 16); + + /* + * I2C data address within the chip. This can be 1 or + * 2 bytes long. Some day it might be 3 bytes long :-). + */ + devaddr = simple_strtoul(argv[3], NULL, 16); + alen = get_alen(argv[3]); + if (alen > 3) + return cmd_usage(cmdtp); + + /* + * Length is the number of objects, not number of bytes. + */ + length = simple_strtoul(argv[4], NULL, 16); + + while (length-- > 0) { + if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) { + puts("Error writing to the chip.\n"); + return 1; + } +/* + * No write delay with FRAM devices. + */ +#if !defined(CONFIG_SYS_I2C_FRAM) + udelay(11000); +#endif + } + return 0; +} + /* * Syntax: * i2c md {i2c_chip} {addr}{.0, .1, .2} {len} @@ -1282,6 +1330,7 @@ static cmd_tbl_t cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""), U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""), U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""), + U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""), U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""), #if defined(CONFIG_CMD_SDRAM) U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""), @@ -1333,6 +1382,7 @@ U_BOOT_CMD( "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" "i2c probe - show devices on the I2C bus\n" "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n" + "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n" "i2c reset - re-init the I2C Controller\n" #if defined(CONFIG_CMD_SDRAM) "i2c sdram chip - print SDRAM configuration information\n" -- cgit v1.2.3 From 54b99e51ab580eb6373f93994fe8f8a8edeefcf8 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 23 Sep 2012 10:12:56 +0000 Subject: i2c_probe: update for use in scripting Allow the use of an I2C address to test and return success if one or more devices is found. This allows device presence to alter the flow of a script. e.g. if i2c probe 0x04 ; then echo found Hannstar touch ; fi Signed-off-by: Eric Nelson --- common/cmd_i2c.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index b59470e7f6..82e63e1322 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -605,18 +605,28 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg /* * Syntax: - * i2c probe {addr}{.0, .1, .2} + * i2c probe {addr} + * + * Returns zero (success) if one or more I2C devices was found */ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int j; + int addr = -1; + int found = 0; #if defined(CONFIG_SYS_I2C_NOPROBES) int k, skip; uchar bus = GET_BUS_NUM; #endif /* NOPROBES */ + if (argc == 2) + addr = simple_strtol(argv[1], 0, 16); + puts ("Valid chip addresses:"); for (j = 0; j < 128; j++) { + if ((0 <= addr) && (j != addr)) + continue; + #if defined(CONFIG_SYS_I2C_NOPROBES) skip = 0; for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { @@ -628,8 +638,10 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv if (skip) continue; #endif - if (i2c_probe(j) == 0) + if (i2c_probe(j) == 0) { printf(" %02X", j); + found++; + } } putc ('\n'); @@ -642,7 +654,7 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv putc ('\n'); #endif - return 0; + return (0 == found); } /* @@ -1380,7 +1392,7 @@ U_BOOT_CMD( "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" - "i2c probe - show devices on the I2C bus\n" + "i2c probe [address] - test for and show device(s) on the I2C bus\n" "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n" "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n" "i2c reset - re-init the I2C Controller\n" -- cgit v1.2.3 From 34cda7a0d89297e450106951d554b56ed4c1fd3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Da=C5=82ek?= Date: Mon, 15 Oct 2012 07:46:54 +0000 Subject: h2200: Add support for iPAQ h2200 palmtop Add basic support for HP iPAQ h2200 palmtop. h2200 palmtop was targeted to general consumers. It has 64 MB of RAM, 32 MB flash. No intergrated Wi-Fi nor Ethernet. Based on Intel PXA255 processor. It was shipped with Windows CE 4.2 operating system. Signed-off-by: Lukasz Dalek --- MAINTAINERS | 4 ++ board/h2200/Makefile | 49 ++++++++++++++ board/h2200/h2200-header.S | 27 ++++++++ board/h2200/h2200.c | 53 +++++++++++++++ boards.cfg | 1 + include/configs/h2200.h | 157 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 291 insertions(+) create mode 100644 board/h2200/Makefile create mode 100644 board/h2200/h2200-header.S create mode 100644 board/h2200/h2200.c create mode 100644 include/configs/h2200.h diff --git a/MAINTAINERS b/MAINTAINERS index 971235bbca..c0fff0e40c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -585,6 +585,10 @@ Stefano Babic twister omap3 vision2 i.MX51 +Lukasz Dalek + + h2200 xscale/pxa + Jason Liu mx53evk i.MX53 diff --git a/board/h2200/Makefile b/board/h2200/Makefile new file mode 100644 index 0000000000..51b1a9ea8d --- /dev/null +++ b/board/h2200/Makefile @@ -0,0 +1,49 @@ +# +# h2200 Support +# +# Copyright (C) 2012 Lukasz Dalek +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := h2200.o + +SRCS := $(COBJS:.o=.c) h2200-header.S +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) $(obj)h2200-header.bin + +$(obj)h2200-header.o: h2200-header.S + $(CC) $(CFLAGS) -c -o $@ $< + +$(obj)h2200-header.bin: $(obj)h2200-header.o + $(OBJCOPY) -O binary $< $@ + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/h2200/h2200-header.S b/board/h2200/h2200-header.S new file mode 100644 index 0000000000..c335bfefcd --- /dev/null +++ b/board/h2200/h2200-header.S @@ -0,0 +1,27 @@ +/* + * iPAQ h2200 header + * + * Copyright (C) 2012 Lukasz Dalek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + .word 0xea0003fe /* b 0x1000 */ + + .org 0x40 + .ascii "ECEC" + + .org 0x1000 - 1 + .byte 0x0 diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c new file mode 100644 index 0000000000..30763061c7 --- /dev/null +++ b/board/h2200/h2200.c @@ -0,0 +1,53 @@ +/* + * iPAQ h2200 board configuration + * + * Copyright (C) 2012 Lukasz Dalek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* We have RAM, disable cache */ + dcache_disable(); + icache_disable(); + + gd->bd->bi_arch_number = MACH_TYPE_H2200; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int dram_init(void) +{ + /* + * Everything except MSC0 was already set up by + * 1st stage bootloader. + * + * This setting enables access to companion chip. + */ + clrsetbits_le32(MSC0, 0xffffffff, CONFIG_SYS_MSC0_VAL); + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/boards.cfg b/boards.cfg index 4b17289722..d467f566c0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -295,6 +295,7 @@ dvlhost arm ixp pdnb3 arm ixp pdnb3 prodrive scpu arm ixp pdnb3 prodrive - pdnb3:SCPU balloon3 arm pxa +h2200 arm pxa lubbock arm pxa palmld arm pxa palmtc arm pxa diff --git a/include/configs/h2200.h b/include/configs/h2200.h new file mode 100644 index 0000000000..ef14dd38c5 --- /dev/null +++ b/include/configs/h2200.h @@ -0,0 +1,157 @@ +/* + * iPAQ h2200 board configuration + * + * Copyright (C) 2012 Lukasz Dalek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define MACH_TYPE_H2200 341 +#define CONFIG_MACH_TYPE MACH_TYPE_H2200 + +#define CONFIG_CPU_PXA25X 1 +#define CONFIG_BOARD_H2200 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE + +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 + +#define CONFIG_ENV_SIZE 0x00040000 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ + +/* + * iPAQ 1st stage bootloader loads 2nd stage bootloader + * at address 0xa0040000 but bootloader requires header + * which is 0x1000 long. + * + * --- Header begin --- + * .word 0xea0003fe ; b 0x1000 + * + * .org 0x40 + * .ascii "ECEC" + * + * .org 0x1000 + * --- Header end --- + */ + +#define CONFIG_SYS_TEXT_BASE 0xa0041000 + +/* + * Static chips + */ + +#define CONFIG_SYS_MSC0_VAL 0x246c7ffc +#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 +#define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 + +/* + * PCMCIA and CF Interfaces + */ + +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00000000 +#define CONFIG_SYS_MCMEM1_VAL 0x00000000 +#define CONFIG_SYS_MCATT0_VAL 0x00000000 +#define CONFIG_SYS_MCATT1_VAL 0x00000000 +#define CONFIG_SYS_MCIO0_VAL 0x00000000 +#define CONFIG_SYS_MCIO1_VAL 0x00000000 + +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00040004 + +#define CONFIG_SYS_MDREFR_VAL 0x0099E018 +#define CONFIG_SYS_MDCNFG_VAL 0x01C801CB +#define CONFIG_SYS_MDMRS_VAL 0x00220022 + +#define CONFIG_SYS_PSSR_VAL 0x00000000 +#define CONFIG_SYS_CKEN 0x00004840 +#define CONFIG_SYS_CCCR 0x00000161 + +/* + * GPIOs + */ + +#define CONFIG_SYS_GPSR0_VAL 0x01000000 +#define CONFIG_SYS_GPSR1_VAL 0x00000000 +#define CONFIG_SYS_GPSR2_VAL 0x00010000 + +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 + +#define CONFIG_SYS_GPDR0_VAL 0xF7E38C00 +#define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83 +#define CONFIG_SYS_GPDR2_VAL 0x000157FF + +#define CONFIG_SYS_GAFR0_L_VAL 0x80401000 +#define CONFIG_SYS_GAFR0_U_VAL 0x00000112 +#define CONFIG_SYS_GAFR1_L_VAL 0x600A9550 +#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA +#define CONFIG_SYS_GAFR2_L_VAL 0x20000000 +#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 + +/* + * Serial port + */ + +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } + +#define CONFIG_CMD_IMPORTENV 1 +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_RUN +#define CONFIG_CMD_IMI + +#define CONFIG_FIT +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "$ " + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8" + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From cb0a6a1ecc8dfe4dbdad6f9376ef78879337b118 Mon Sep 17 00:00:00 2001 From: Zhi-zhou Zhang Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: don't use camel-case style Replace camel-case style with upper-case style globally. Signed-off-by: Zhizhou Zhang --- arch/mips/cpu/mips32/cache.S | 10 ++--- arch/mips/cpu/mips32/cpu.c | 8 ++-- arch/mips/cpu/xburst/cpu.c | 12 +++--- arch/mips/cpu/xburst/start.S | 4 +- arch/mips/include/asm/asm.h | 2 +- arch/mips/include/asm/cacheops.h | 82 ++++++++++++++++++++-------------------- 6 files changed, 59 insertions(+), 59 deletions(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index e683e8be8c..64dfad0263 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -85,17 +85,17 @@ LEAF(mips_init_icache) /* clear tag to invalidate */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_I t0 +1: cache_op INDEX_STORE_TAG_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE -2: cache_op Fill t0 +2: cache_op FILL t0 PTR_ADDU t0, a2 bne t0, t1, 2b /* invalidate again - prudent but not strictly neccessary */ PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_I t0 +1: cache_op INDEX_STORE_TAG_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b 9: jr ra @@ -110,7 +110,7 @@ LEAF(mips_init_dcache) /* clear all tags */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_D t0 +1: cache_op INDEX_STORE_TAG_D t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* load from each line (in cached space) */ @@ -120,7 +120,7 @@ LEAF(mips_init_dcache) bne t0, t1, 2b /* clear all tags */ PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_D t0 +1: cache_op INDEX_STORE_TAG_D t0 PTR_ADDU t0, a2 bne t0, t1, 1b 9: jr ra diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c index 7b49e1b612..50bb248bd0 100644 --- a/arch/mips/cpu/mips32/cpu.c +++ b/arch/mips/cpu/mips32/cpu.c @@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size) return; while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); if (addr == aend) break; addr += lsize; @@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Writeback_Inv_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); if (addr == aend) break; addr += lsize; @@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); while (1) { - cache_op(Hit_Invalidate_D, addr); + cache_op(HIT_INVALIDATE_D, addr); if (addr == aend) break; addr += lsize; diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c index ddcbfaa47c..cc190dfe56 100644 --- a/arch/mips/cpu/xburst/cpu.c +++ b/arch/mips/cpu/xburst/cpu.c @@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size) unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); for (; addr <= aend; addr += lsize) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); } } @@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); for (; addr <= aend; addr += lsize) - cache_op(Hit_Writeback_Inv_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); } void invalidate_dcache_range(ulong start_addr, ulong stop) @@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) unsigned long aend = (stop - 1) & ~(lsize - 1); for (; addr <= aend; addr += lsize) - cache_op(Hit_Invalidate_D, addr); + cache_op(HIT_INVALIDATE_D, addr); } void flush_icache_all(void) @@ -118,7 +118,7 @@ void flush_icache_all(void) for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(Index_Store_Tag_I, addr); + cache_op(INDEX_STORE_TAG_I, addr); } /* invalidate btb */ @@ -139,7 +139,7 @@ void flush_dcache_all(void) for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(Index_Writeback_Inv_D, addr); + cache_op(INDEX_WRITEBACK_INV_D, addr); } __asm__ __volatile__("sync"); diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index d846104d10..3a8280cb0a 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -96,7 +96,7 @@ relocate_code: li t0, KSEG0 addi t1, t0, CONFIG_SYS_DCACHE_SIZE 2: - cache Index_Writeback_Inv_D, 0(t0) + cache INDEX_WRITEBACK_INV_D, 0(t0) bne t0, t1, 2b addi t0, CONFIG_SYS_CACHELINE_SIZE @@ -106,7 +106,7 @@ relocate_code: li t0, KSEG0 addi t1, t0, CONFIG_SYS_ICACHE_SIZE 3: - cache Index_Invalidate_I, 0(t0) + cache INDEX_INVALIDATE_I, 0(t0) bne t0, t1, 3b addi t0, CONFIG_SYS_CACHELINE_SIZE diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 608cfcfbb3..933ccb1b78 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -401,7 +401,7 @@ symbol = value #ifdef CONFIG_SGI_IP28 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ #include -#define R10KCBARRIER(addr) cache Cache_Barrier, addr; +#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr; #else #define R10KCBARRIER(addr) #endif diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 70bcad7694..6464250d84 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -14,54 +14,54 @@ /* * Cache Operations available on all MIPS processors with R4000-style caches */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 +#define INDEX_INVALIDATE_I 0x00 +#define INDEX_WRITEBACK_INV_D 0x01 +#define INDEX_LOAD_TAG_I 0x04 +#define INDEX_LOAD_TAG_D 0x05 +#define INDEX_STORE_TAG_I 0x08 +#define INDEX_STORE_TAG_D 0x09 #if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 +#define HIT_INVALIDATE_I 0x00 #else -#define Hit_Invalidate_I 0x10 +#define HIT_INVALIDATE_I 0x10 #endif -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 +#define HIT_INVALIDATE_D 0x11 +#define HIT_WRITEBACK_INV_D 0x15 /* * R4000-specific cacheops */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define CREATE_DIRTY_EXCL_D 0x0d +#define FILL 0x14 +#define HIT_WRITEBACK_I 0x18 +#define HIT_WRITEBACK_D 0x19 /* * R4000SC and R4400SC-specific cacheops */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define INDEX_INVALIDATE_SI 0x02 +#define INDEX_WRITEBACK_INV_SD 0x03 +#define INDEX_LOAD_TAG_SI 0x06 +#define INDEX_LOAD_TAG_SD 0x07 +#define INDEX_STORE_TAG_SI 0x0A +#define INDEX_STORE_TAG_SD 0x0B +#define CREATE_DIRTY_EXCL_SD 0x0f +#define HIT_INVALIDATE_SI 0x12 +#define HIT_INVALIDATE_SD 0x13 +#define HIT_WRITEBACK_INV_SD 0x17 +#define HIT_WRITEBACK_SD 0x1b +#define HIT_SET_VIRTUAL_SI 0x1e +#define HIT_SET_VIRTUAL_SD 0x1f /* * R5000-specific cacheops */ -#define R5K_Page_Invalidate_S 0x17 +#define R5K_PAGE_INVALIDATE_S 0x17 /* * RM7000-specific cacheops */ -#define Page_Invalidate_T 0x16 +#define PAGE_INVALIDATE_T 0x16 /* * R10000-specific cacheops @@ -69,17 +69,17 @@ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f +#define INDEX_WRITEBACK_INV_S 0x03 +#define INDEX_LOAD_TAG_S 0x07 +#define INDEX_STORE_TAG_S 0x0B +#define HIT_INVALIDATE_S 0x13 +#define CACHE_BARRIER 0x14 +#define HIT_WRITEBACK_INV_S 0x17 +#define INDEX_LOAD_DATA_I 0x18 +#define INDEX_LOAD_DATA_D 0x19 +#define INDEX_LOAD_DATA_S 0x1b +#define INDEX_STORE_DATA_I 0x1c +#define INDEX_STORE_DATA_D 0x1d +#define INDEX_STORE_DATA_S 0x1f #endif /* __ASM_CACHEOPS_H */ -- cgit v1.2.3 From 090854c826276b4d6361b4bdf3091ddcc977544c Mon Sep 17 00:00:00 2001 From: Zhi-zhou Zhang Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: add support for 64 bit addressing Prepare for upcoming mips64 support. This patch add mips64 address support. Signed-off-by: Zhizhou Zhang [daniel.schwierzeck@gmail.com: prefer _MIPS_SZLONG in posix_types.h to fix some warnings] Signed-off-by: Daniel Schwierzeck --- arch/mips/include/asm/addrspace.h | 2 +- arch/mips/include/asm/io.h | 16 ++++++++++++++++ arch/mips/include/asm/posix_types.h | 6 ++++++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3a1e6d615f..b768bb5081 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,7 +136,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) #else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) #endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 025012ae60..80eab75e15 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base) */ extern inline phys_addr_t virt_to_phys(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif } extern inline void * phys_to_virt(unsigned long address) { +#ifndef CONFIG_64BIT return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif } /* @@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address) */ extern inline unsigned long virt_to_bus(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif } extern inline void * bus_to_virt(unsigned long address) { +#ifndef CONFIG_64BIT return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif } /* diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae210b..4deac5207a 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,9 +24,15 @@ typedef int __kernel_pid_t; typedef int __kernel_ipc_pid_t; typedef int __kernel_uid_t; typedef int __kernel_gid_t; +#if _MIPS_SZLONG != 64 typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; +#else +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; -- cgit v1.2.3 From ff9b0cb8b4804ed372c09b8aad2a984b396596b2 Mon Sep 17 00:00:00 2001 From: Zhi-zhou Zhang Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: qemu_mips: move CONFIG_SYS_TEXT_BASE to qemu-mips.h We define CONFIG_SYS_TEXT_BASE in board's specified header file. So config.mk is useless, then remove it. Signed-off-by: Zhizhou Zhang --- board/qemu-mips/config.mk | 10 ---------- include/configs/qemu-mips.h | 1 + 2 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 board/qemu-mips/config.mk diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk deleted file mode 100644 index 27cd34ac36..0000000000 --- a/board/qemu-mips/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# Qemu -M mips system emulator -# See http://fabrice.bellard.free.fr/qemu -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xbfc00000 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80001000 diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index b8b970504f..f45f78b9a2 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -137,6 +137,7 @@ */ /* The following #defines are needed to get flash environment right */ +#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) -- cgit v1.2.3 From 32afad783eb5a372c276fcb9fb30dfb838615909 Mon Sep 17 00:00:00 2001 From: Zhi-zhou Zhang Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: add board qemu-mips64 support Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang Signed-off-by: Daniel Schwierzeck --- arch/mips/cpu/mips64/Makefile | 45 +++++++ arch/mips/cpu/mips64/cache.S | 229 ++++++++++++++++++++++++++++++++++ arch/mips/cpu/mips64/config.mk | 40 ++++++ arch/mips/cpu/mips64/cpu.c | 111 +++++++++++++++++ arch/mips/cpu/mips64/interrupts.c | 34 +++++ arch/mips/cpu/mips64/start.S | 256 ++++++++++++++++++++++++++++++++++++++ arch/mips/cpu/mips64/time.c | 87 +++++++++++++ board/qemu-mips/u-boot.lds | 8 ++ boards.cfg | 2 + examples/standalone/mips64.lds | 59 +++++++++ include/configs/qemu-mips64.h | 175 ++++++++++++++++++++++++++ 11 files changed, 1046 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/cache.S create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c create mode 100644 examples/standalone/mips64.lds create mode 100644 include/configs/qemu-mips64.h diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 0000000000..be38664844 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +START = start.o +COBJS-y = cpu.o interrupts.o time.o cache.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S new file mode 100644 index 0000000000..036f035d96 --- /dev/null +++ b/arch/mips/cpu/mips64/cache.S @@ -0,0 +1,229 @@ +/* + * Cache-handling routined for MIPS CPUs + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RA t9 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE 0x10000 + +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .set push + .set noreorder + .set mips3 + cache \op, 0(\addr) + .set pop + .endm + + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + +/* + * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) + */ +LEAF(mips_init_icache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear tag to invalidate */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op INDEX_STORE_TAG_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* fill once, so data field parity is correct */ + PTR_LI t0, INDEX_BASE +2: cache_op FILL t0 + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* invalidate again - prudent but not strictly neccessary */ + PTR_LI t0, INDEX_BASE +1: cache_op INDEX_STORE_TAG_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_icache) + +/* + * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) + */ +LEAF(mips_init_dcache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear all tags */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op INDEX_STORE_TAG_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* load from each line (in cached space) */ + PTR_LI t0, INDEX_BASE +2: LONG_L zero, 0(t0) + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, INDEX_BASE +1: cache_op INDEX_STORE_TAG_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_dcache) + +/* + * mips_cache_reset - low level initialisation of the primary caches + * + * This routine initialises the primary caches to ensure that they have good + * parity. It must be called by the ROM before any cached locations are used + * to prevent the possibility of data with bad parity being written to memory. + * + * To initialise the instruction cache it is essential that a source of data + * with good parity is available. This routine will initialise an area of + * memory starting at location zero to be used as a source of parity. + * + * RETURNS: N/A + * + */ +NESTED(mips_cache_reset, 0, ra) + move RA, ra + li t2, CONFIG_SYS_ICACHE_SIZE + li t3, CONFIG_SYS_DCACHE_SIZE + li t8, CONFIG_SYS_CACHELINE_SIZE + + li v0, MIPS_MAX_CACHE_SIZE + + /* + * Now clear that much memory starting from zero. + */ + PTR_LI a0, CKSEG1 + PTR_ADDU a1, a0, v0 +2: PTR_ADDIU a0, 64 + f_fill64 a0, -64, zero + bne a0, a1, 2b + + /* + * The caches are probably in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ + + /* + * Assume bottom of RAM will generate good parity for the cache. + */ + + /* + * Initialize the I-cache first, + */ + move a1, t2 + move a2, t8 + PTR_LA v1, mips_init_icache + jalr v1 + + /* + * then initialize D-cache. + */ + move a1, t3 + move a2, t8 + PTR_LA v1, mips_init_dcache + jalr v1 + + jr RA + END(mips_cache_reset) + +/* + * dcache_status - get cache status + * + * RETURNS: 0 - cache disabled; 1 - cache enabled + * + */ +LEAF(dcache_status) + mfc0 t0, CP0_CONFIG + li t1, CONF_CM_UNCACHED + andi t0, t0, CONF_CM_CMASK + move v0, zero + beq t0, t1, 2f + li v0, 1 +2: jr ra + END(dcache_status) + +/* + * dcache_disable - disable cache + * + * RETURNS: N/A + * + */ +LEAF(dcache_disable) + mfc0 t0, CP0_CONFIG + li t1, -8 + and t0, t0, t1 + ori t0, t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + jr ra + END(dcache_disable) + +/* + * dcache_enable - enable cache + * + * RETURNS: N/A + * + */ +LEAF(dcache_enable) + mfc0 t0, CP0_CONFIG + ori t0, CONF_CM_CMASK + xori t0, CONF_CM_CMASK + ori t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + jr ra + END(dcache_enable) diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 0000000000..ebc1ceb83b --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,40 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +ifdef CONFIG_SYS_BIG_ENDIAN +PLATFORM_LDFLAGS += -m elf64btsmip +else +PLATFORM_LDFLAGS += -m elf64ltsmip +endif + +CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c new file mode 100644 index 0000000000..2a38d0c8d0 --- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#define cache_op(op, addr) \ + __asm__ __volatile__( \ + " .set push\n" \ + " .set noreorder\n" \ + " .set mips64\n" \ + " cache %0, %1\n" \ + " .set pop\n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void __attribute__((weak)) _machine_restart(void) +{ + fprintf(stderr, "*** reset failed ***\n"); + + while (1) + /* NOP */; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + _machine_restart(); + + return 0; +} + +void flush_cache(ulong start_addr, ulong size) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + /* aend will be miscalculated when size is zero, so we return here */ + if (size == 0) + return; + + while (1) { + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(HIT_WRITEBACK_INV_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(HIT_INVALIDATE_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) +{ + write_c0_entrylo0(low0); + write_c0_pagemask(pagemask); + write_c0_entrylo1(low1); + write_c0_entryhi(hi); + write_c0_index(index); + tlb_write_indexed(); +} diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c new file mode 100644 index 0000000000..e4e9aae0ca --- /dev/null +++ b/arch/mips/cpu/mips64/interrupts.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void enable_interrupts(void) +{ +} + +int disable_interrupts(void) +{ + return 0; +} diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S new file mode 100644 index 0000000000..4112de7026 --- /dev/null +++ b/arch/mips/cpu/mips64/start.S @@ -0,0 +1,256 @@ +/* + * Startup Code for MIPS64 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any dlater version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .set noreorder + + .globl _start + .text +_start: + .org 0x000 + b reset + nop + .org 0x080 + b romReserved + nop + .org 0x100 + b romReserved + nop + .org 0x180 + b romReserved + nop + .org 0x200 + b romReserved + nop + .org 0x280 + b romReserved + nop + .org 0x300 + b romReserved + nop + .org 0x380 + b romReserved + nop + .org 0x480 + b romReserved + nop + + /* + * We hope there are no more reserved vectors! + * 128 * 8 == 1024 == 0x400 + * so this is address R_VEC+0x400 == 0xbfc00400 + */ + .org 0x500 + .align 4 +reset: + + /* Clear watch registers */ + dmtc0 zero, CP0_WATCHLO + dmtc0 zero, CP0_WATCHHI + + /* WP(Watch Pending), SW0/1 should be cleared */ + mtc0 zero, CP0_CAUSE + + setup_c0_status ST0_KX 0 + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CONFIG0 register */ + dli t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG +#endif + + /* Initialize $gp */ + bal 1f + nop + .dword _gp +1: + ld gp, 0(ra) + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* Initialize any external memory */ + dla t9, lowlevel_init + jalr t9 + nop + + /* Initialize caches... */ + dla t9, mips_cache_reset + jalr t9 + nop + + /* ... and enable them */ + dli t0, CONFIG_SYS_MIPS_CACHE_MODE + mtc0 t0, CP0_CONFIG +#endif + + /* Set up temporary stack */ + dli t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET + dla sp, 0(t0) + + dla t9, board_init_f + jr t9 + nop + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl relocate_code + .ent relocate_code +relocate_code: + move sp, a0 # set new stack pointer + + dli t0, CONFIG_SYS_MONITOR_BASE + dla t3, in_ram + ld t2, -24(t3) # t2 <-- uboot_end_data + move t1, a2 + move s2, a2 # s2 <-- destination address + + /* + * Fix $gp: + * + * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address + */ + move t8, gp + dsub gp, CONFIG_SYS_MONITOR_BASE + dadd gp, a2 # gp now adjusted + dsub s1, gp, t8 # s1 <-- relocation offset + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ + + /* + * Save destination address and size for dlater usage in flush_cache() + */ + move s0, a1 # save gd in s0 + move a0, t1 # a0 <-- destination addr + dsub a1, t2, t0 # a1 <-- size + +1: + lw t3, 0(t0) + sw t3, 0(t1) + daddu t0, 4 + ble t0, t2, 1b + daddu t1, 4 + + /* If caches were enabled, we would have to flush them here. */ + + /* a0 & a1 are already set up for flush_cache(start, size) */ + dla t9, flush_cache + jalr t9 + nop + + /* Jump to where we've relocated ourselves */ + daddi t0, s2, in_ram - _start + jr t0 + nop + + .dword _gp + .dword _GLOBAL_OFFSET_TABLE_ + .dword uboot_end_data + .dword uboot_end + .dword num_got_entries + +in_ram: + /* + * Now we want to update GOT. + * + * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object + * generated by GNU ld. Skip these reserved entries from relocation. + */ + ld t3, -8(t0) # t3 <-- num_got_entries + ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ + ld t9, -40(t0) # t9 <-- _gp + dsub t8, t9 # compute offset + dadd t8, t8, gp # t8 now holds relocated _G_O_T_ + daddi t8, t8, 16 # skipping first two entries + dli t2, 2 +1: + ld t1, 0(t8) + beqz t1, 2f + dadd t1, s1 + sd t1, 0(t8) +2: + daddi t2, 1 + blt t2, t3, 1b + daddi t8, 8 + + /* Clear BSS */ + ld t1, -24(t0) # t1 <-- uboot_end_data + ld t2, -16(t0) # t2 <-- uboot_end + dadd t1, s1 # adjust pointers + dadd t2, s1 + + dsub t1, 8 +1: + daddi t1, 8 + bltl t1, t2, 1b + sd zero, 0(t1) + + move a0, s0 # a0 <-- gd + dla t9, board_init_r + jr t9 + move a1, s2 + + .end relocate_code + + /* Exception handlers */ +romReserved: + b romReserved diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c new file mode 100644 index 0000000000..51542808dd --- /dev/null +++ b/arch/mips/cpu/mips64/time.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static unsigned long timestamp; + +/* how many counter cycles in a jiffy */ +#define CYCLES_PER_JIFFY \ + (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ + +/* + * timer without interrupts + */ + +int timer_init(void) +{ + /* Set up the timer for the first expiration. */ + timestamp = 0; + write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); + + return 0; +} + +ulong get_timer(ulong base) +{ + unsigned int count; + unsigned int expirelo = read_c0_compare(); + + /* Check to see if we have missed any timestamps. */ + count = read_c0_count(); + while ((count - expirelo) < 0x7fffffff) { + expirelo += CYCLES_PER_JIFFY; + timestamp++; + } + write_c0_compare(expirelo); + + return timestamp - base; +} + +void __udelay(unsigned long usec) +{ + unsigned int tmo; + + tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000)); + while ((tmo - read_c0_count()) < 0x7fffffff) + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index 9460b2010c..4d9580f817 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,11 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ +#if defined(CONFIG_64BIT) +OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips") +#else OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") +#endif OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS @@ -63,7 +67,11 @@ SECTIONS } uboot_end_data = .; +#if defined(CONFIG_64BIT) + num_got_entries = (__got_end - __got_start) >> 3; +#else num_got_entries = (__got_end - __got_start) >> 2; +#endif . = ALIGN(4); .sbss : { *(.sbss*) } diff --git a/boards.cfg b/boards.cfg index 4b17289722..cbfba73c33 100644 --- a/boards.cfg +++ b/boards.cfg @@ -404,6 +404,8 @@ M5485HFE m68k mcf547x_8x m548xevb freescale - microblaze-generic microblaze microblaze microblaze-generic xilinx qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN +qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN +qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds new file mode 100644 index 0000000000..9b27ef4769 --- /dev/null +++ b/examples/standalone/mips64.lds @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips") +OUTPUT_ARCH(mips) +SECTIONS +{ + .text : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata*) } + + . = ALIGN(4); + __bss_start = .; + .sbss (NOLOAD) : { *(.sbss*) } + .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } + + _end = .; +} diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h new file mode 100644 index 0000000000..82647e2b1f --- /dev/null +++ b/include/configs/qemu-mips64.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for qemu-mips64 target. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS64 /* MIPS64 CPU core */ +#define CONFIG_QEMU_MIPS +#define CONFIG_MISC_INIT_R + +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addmisc=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate} " \ + "panic=1\0" \ + "bootfile=/tftpboot/vmlinux\0" \ + "load=tftp ffffffff80500000 ${u-boot}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "bootp;bootelf" + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_DHCP + +#define CONFIG_DRIVER_NE2000 +#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8 +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_CMD_IDE +#define CONFIG_DOS_PARTITION + +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000 + +#define CONFIG_SYS_IDE_MAXDEVICE 4 + +#define CONFIG_CMD_RARP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +/* Monitor Command Prompt */ +#if defined(CONFIG_SYS_LITTLE_ENDIAN) +#define CONFIG_SYS_PROMPT "qemu-mips64el # " +#else +#define CONFIG_SYS_PROMPT "qemu-mips64 # " +#endif + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +#define CONFIG_SYS_MALLOC_LEN 128*1024 + +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 + +#define CONFIG_SYS_MHZ 132 + +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_HZ 1000 + +/* Cached addr */ +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 + +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000 +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +/* The following #defines are needed to get flash environment right */ +#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 << 10) + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* We boot from this flash, selected with dip switch */ +#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Primary Environment Sector */ +#define CONFIG_ENV_SIZE 0x8000 + +#define CONFIG_ENV_OVERWRITE 1 + +#define MEM_SIZE 128 + +#define CONFIG_LZMA + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 6b2eba1b7cd661fc6b2b0e0d4d039d1c299e2e07 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Tue, 16 Oct 2012 15:02:08 +0200 Subject: MIPS: qemu_mips.h: cleanup coding style and checkpatch.pl issues Signed-off-by: Daniel Schwierzeck --- include/configs/qemu-mips.h | 54 ++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index f45f78b9a2..5bc7b0d1d5 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -28,14 +28,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ -#define CONFIG_QEMU_MIPS 1 +#define CONFIG_MIPS32 /* MIPS32 CPU core */ +#define CONFIG_QEMU_MIPS #define CONFIG_MISC_INIT_R -/*IP address is default used by Qemu*/ -#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ -#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */ - #define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ #define CONFIG_BAUDRATE 115200 @@ -74,31 +70,31 @@ #define CONFIG_CMD_DHCP #define CONFIG_DRIVER_NE2000 -#define CONFIG_DRIVER_NE2000_BASE (0xb4000300) +#define CONFIG_DRIVER_NE2000_BASE 0xb4000300 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 (0xb40003f8) -#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 0xb40003f8 +#define CONFIG_CONS_INDEX 1 #define CONFIG_CMD_IDE #define CONFIG_DOS_PARTITION #define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0) -#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170) -#define CONFIG_SYS_ATA_DATA_OFFSET (0) -#define CONFIG_SYS_ATA_REG_OFFSET (0) -#define CONFIG_SYS_ATA_BASE_ADDR (0xb4000000) +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 -#define CONFIG_SYS_IDE_MAXDEVICE (4) +#define CONFIG_SYS_IDE_MAXDEVICE 4 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ /* Monitor Command Prompt */ #if defined(CONFIG_SYS_LITTLE_ENDIAN) @@ -111,9 +107,12 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN 128*1024 @@ -125,9 +124,11 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ +/* Cached addr */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_MEMTEST_START 0x80100000 #define CONFIG_SYS_MEMTEST_END 0x80800000 @@ -135,7 +136,6 @@ /*----------------------------------------------------------------------- * FLASH and environment organization */ - /* The following #defines are needed to get flash environment right */ #define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE @@ -147,11 +147,11 @@ #define CONFIG_SYS_FLASH_BASE 0xbfc00000 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) /* Address and size of Primary Environment Sector */ @@ -161,8 +161,6 @@ #define MEM_SIZE 128 -#undef CONFIG_MEMSIZE_IN_BYTES - #define CONFIG_LZMA /*----------------------------------------------------------------------- -- cgit v1.2.3 From ce2f5800177c36451da44345f7ab408df240ff82 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Mon, 15 Oct 2012 15:29:24 +0000 Subject: tools/env: Fix variable delete operation Fix crash introduced by a073d63a36524453a817ab029fad5b188f46127e when attempting to delete a variable. Signed-off-by: Joe Hershberger --- tools/env/fw_env.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index ab8c15d30e..97328bb3a8 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -494,6 +494,8 @@ int fw_setenv(int argc, char *argv[]) char *val = argv[i]; size_t val_len = strlen(val); + if (value) + value[len - 1] = ' '; value = realloc(value, len + val_len + 1); if (!value) { fprintf(stderr, @@ -504,9 +506,8 @@ int fw_setenv(int argc, char *argv[]) memcpy(value + len, val, val_len); len += val_len; - value[len++] = ' '; + value[len++] = '\0'; } - value[len - 1] = '\0'; fw_env_write(name, value); -- cgit v1.2.3 From 74620e1c94565b835c7b6eb34db9b67bfc898bc4 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Mon, 15 Oct 2012 15:29:25 +0000 Subject: tools/env: Improve debug prints Provide more information when using redundant environments Consistently print debug info to stderr Signed-off-by: Joe Hershberger --- tools/env/fw_env.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 97328bb3a8..32e853aa1c 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -739,8 +739,8 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count, return -1; } #ifdef DEBUG - fprintf (stderr, "Read 0x%x bytes at 0x%llx\n", - rc, blockstart + block_seek); + fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n", + rc, blockstart + block_seek, DEVNAME(dev)); #endif processed += readlen; readlen = min (blocklen, count - processed); @@ -819,6 +819,18 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, if (write_total != rc) return -1; +#ifdef DEBUG + fprintf(stderr, "Preserving data "); + if (block_seek != 0) + fprintf(stderr, "0x%x - 0x%lx", 0, block_seek - 1); + if (block_seek + count != write_total) { + if (block_seek != 0) + fprintf(stderr, " and "); + fprintf(stderr, "0x%lx - 0x%x", + block_seek + count, write_total - 1); + } + fprintf(stderr, "\n"); +#endif /* Overwrite the old environment */ memcpy (data + block_seek, buf, count); } else { @@ -877,7 +889,8 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, } #ifdef DEBUG - printf ("Write 0x%x bytes at 0x%llx\n", erasesize, blockstart); + fprintf(stderr, "Write 0x%x bytes at 0x%llx\n", erasesize, + blockstart); #endif if (write (fd, data + processed, erasesize) != erasesize) { fprintf (stderr, "Write error on %s: %s\n", @@ -944,7 +957,7 @@ static int flash_write (int fd_current, int fd_target, int dev_target) } #ifdef DEBUG - printf ("Writing new environment at 0x%lx on %s\n", + fprintf(stderr, "Writing new environment at 0x%lx on %s\n", DEVOFFSET (dev_target), DEVNAME (dev_target)); #endif rc = flash_write_buf(dev_target, fd_target, environment.image, @@ -958,7 +971,8 @@ static int flash_write (int fd_current, int fd_target, int dev_target) off_t offset = DEVOFFSET (dev_current) + offsetof (struct env_image_redundant, flags); #ifdef DEBUG - printf ("Setting obsolete flag in environment at 0x%lx on %s\n", + fprintf(stderr, + "Setting obsolete flag in environment at 0x%lx on %s\n", DEVOFFSET (dev_current), DEVNAME (dev_current)); #endif flash_flag_obsolete (dev_current, fd_current, offset); @@ -1225,6 +1239,9 @@ int fw_env_open(void) /* Other pointers are already set */ free (addr1); } +#ifdef DEBUG + fprintf(stderr, "Selected env in %s\n", DEVNAME(dev_current)); +#endif } return 0; } -- cgit v1.2.3 From b9f4bc34ac0ee40f8d6a952036b4cd62b854aa74 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 8 Oct 2012 04:11:38 +0000 Subject: Remove lh7a40x cpu and serial driver Since commit 957731ed (ARM: remove broken "lpd7a40x" boards), lh7a40x cpu and serial driver have become unused. Remove them. Signed-off-by: Albert ARIBAUD --- arch/arm/cpu/lh7a40x/Makefile | 47 ---- arch/arm/cpu/lh7a40x/config.mk | 33 --- arch/arm/cpu/lh7a40x/cpu.c | 65 ----- arch/arm/cpu/lh7a40x/speed.c | 83 ------- arch/arm/cpu/lh7a40x/start.S | 506 -------------------------------------- arch/arm/cpu/lh7a40x/timer.c | 182 -------------- doc/driver-model/UDM-serial.txt | 32 ++- drivers/serial/Makefile | 1 - drivers/serial/serial_lh7a40x.c | 204 --------------- drivers/usb/gadget/gadget_chips.h | 34 +-- include/lh7a400.h | 75 ------ include/lh7a404.h | 83 ------- include/lh7a40x.h | 279 --------------------- include/lpd7a400_cpld.h | 195 --------------- 14 files changed, 27 insertions(+), 1792 deletions(-) delete mode 100644 arch/arm/cpu/lh7a40x/Makefile delete mode 100644 arch/arm/cpu/lh7a40x/config.mk delete mode 100644 arch/arm/cpu/lh7a40x/cpu.c delete mode 100644 arch/arm/cpu/lh7a40x/speed.c delete mode 100644 arch/arm/cpu/lh7a40x/start.S delete mode 100644 arch/arm/cpu/lh7a40x/timer.c delete mode 100644 drivers/serial/serial_lh7a40x.c delete mode 100644 include/lh7a400.h delete mode 100644 include/lh7a404.h delete mode 100644 include/lh7a40x.h delete mode 100644 include/lpd7a400_cpld.h diff --git a/arch/arm/cpu/lh7a40x/Makefile b/arch/arm/cpu/lh7a40x/Makefile deleted file mode 100644 index 01cf7f5455..0000000000 --- a/arch/arm/cpu/lh7a40x/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).o - -START = start.o -COBJS = cpu.o speed.o timer.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/lh7a40x/config.mk b/arch/arm/cpu/lh7a40x/config.mk deleted file mode 100644 index 1c4aa97eaa..0000000000 --- a/arch/arm/cpu/lh7a40x/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -PLATFORM_CPPFLAGS += -march=armv4 -# ========================================================================= -# -# Supply options according to compiler version -# -# ======================================================================== -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/lh7a40x/cpu.c b/arch/arm/cpu/lh7a40x/cpu.c deleted file mode 100644 index b193189123..0000000000 --- a/arch/arm/cpu/lh7a40x/cpu.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -static void cache_flush(void); - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - /* turn off I/D-cache */ - icache_disable(); - dcache_disable(); - - /* flush I/D-cache */ - cache_flush(); - - return 0; -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); -} diff --git a/arch/arm/cpu/lh7a40x/speed.c b/arch/arm/cpu/lh7a40x/speed.c deleted file mode 100644 index 333ebb504a..0000000000 --- a/arch/arm/cpu/lh7a40x/speed.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. - * - * get_FCLK(), get_HCLK(), get_PCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -ulong get_PLLCLK (void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -/* return FCLK frequency */ -ulong get_FCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - ulong maindiv1, maindiv2, prediv, ps; - - /* - * from userguide 6.1.1.2 - * - * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) / - * ((PREDIV+2) * (2^PS)) - */ - maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; - maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; - prediv = (csc->clkset & CLKSET_PREDIV) >> 2; - ps = (csc->clkset & CLKSET_PS) >> 16; - - return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) / - ((prediv + 2) * (1 << ps))); -} - - -/* return HCLK frequency */ -ulong get_HCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - - return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); -} - -/* return PCLK frequency */ -ulong get_PCLK (void) -{ - lh7a40x_csc_t* csc = LH7A40X_CSC_PTR; - - return (get_HCLK () / - (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); -} diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S deleted file mode 100644 index 33b9269c70..0000000000 --- a/arch/arm/cpu/lh7a40x/start.S +++ /dev/null @@ -1,506 +0,0 @@ -/* - * armboot - Startup Code for ARM920 CPU-core - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - ************************************************************************* - * - * Jump vector table as in table 3.1 in [1] - * - ************************************************************************* - */ - - -.globl _start -_start: b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * relocate armboot to ram - * setup stack - * jump to second stage - * - ************************************************************************* - */ - -.globl _TEXT_BASE -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end__ - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -#define pWDTCTL 0x80001400 /* Watchdog Timer control register */ -#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */ -#define pCLKSET 0x80000420 /* clock divisor register */ - - /* disable watchdog, set watchdog control register to - * all zeros (default reset) - */ - ldr r0, =pWDTCTL - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTENC register (default) - */ - mov r1, #0xffffffff - ldr r0, =pINTENC - str r1, [r0] - - /* FCLK:HCLK:PCLK = 1:2:2 */ - /* default FCLK is 200 MHz, using 14.7456 MHz fin */ - ldr r0, =pCLKSET - ldr r1, =0x0004ee39 -@ ldr r1, =0x0005ee39 @ 1: 2: 4 - str r1, [r0] - - /* - * we do sys-critical inits only at reboot, - * not when booting from ram! - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit -#endif - -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f - -/*------------------------------------------------------------------------------*/ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - */ - .globl relocate_code -relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ - - /* Set up the stack */ -stack_setup: - mov sp, r4 - - adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ - mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs - add r2, r0, r3 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - blo copy_loop - -#ifndef CONFIG_SPL_BUILD - /* - * fix .rel.dyn relocations - */ - ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ - ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ - add r10, r10, r0 /* r10 <- sym table in FLASH */ - ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ - add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ - ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ - add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ -fixloop: - ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ - add r0, r0, r9 /* r0 <- location to fix up in RAM */ - ldr r1, [r2, #4] - and r7, r1, #0xff - cmp r7, #23 /* relative fixup? */ - beq fixrel - cmp r7, #2 /* absolute fixup? */ - beq fixabs - /* ignore unknown type of fixup */ - b fixnext -fixabs: - /* absolute fix: set location to (offset) symbol value */ - mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ - add r1, r10, r1 /* r1 <- address of symbol in table */ - ldr r1, [r1, #4] /* r1 <- symbol value */ - add r1, r1, r9 /* r1 <- relocated sym addr */ - b fixnext -fixrel: - /* relative fix: increase location by offset */ - ldr r1, [r0] - add r1, r1, r9 -fixnext: - str r1, [r0] - add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ - cmp r2, r3 - blo fixloop -#endif - -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start - -_rel_dyn_start_ofs: - .word __rel_dyn_start - _start -_rel_dyn_end_ofs: - .word __rel_dyn_end - _start -_dynsym_start_ofs: - .word __dynsym_start - _start - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ - - -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus - mcr p15, 0, r0, c1, c0, 0 - - - /* - * before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. - */ - mov ip, lr - bl lowlevel_init - mov lr, ip - - mov pc, lr - - -/* - ************************************************************************* - * - * Interrupt handling - * - ************************************************************************* - */ - -@ -@ IRQ stack frame. -@ -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 -#define I_BIT 0x80 - -/* - * use bad_save_user_regs for abort/prefetch/undef/swi ... - * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling - */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr - mov r0, sp - .endm - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 - msr spsr, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - -/* - * exception handlers - */ - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - /* someone ought to write a more effiction fiq_save_user_regs */ - irq_save_user_regs - bl do_fiq - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - - .align 5 -.globl reset_cpu -reset_cpu: - bl disable_interrupts - - /* Disable watchdog */ - ldr r1, =pWDTCTL - mov r3, #0 - str r3, [r1] - - /* reset counter */ - ldr r3, =0x00001984 - str r3, [r1, #4] - - /* Enable the watchdog */ - mov r3, #1 - str r3, [r1] - -_loop_forever: - b _loop_forever diff --git a/arch/arm/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c deleted file mode 100644 index 58b35b15e6..0000000000 --- a/arch/arm/cpu/lh7a40x/timer.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -static ulong timer_load_val = 0; - -/* macro to read the 16 bit timer */ -static inline ulong READ_TIMER(void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - return (timer->value & 0x0000ffff); -} - -static ulong timestamp; -static ulong lastdec; - -int timer_init (void) -{ - lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; - lh7a40x_timer_t* timer = &timers->timer1; - - /* a periodic timer using the 508kHz source */ - timer->control = (TIMER_PER | TIMER_CLK508K); - - if (timer_load_val == 0) { - /* - * 10ms period with 508.469kHz clock = 5084 - */ - timer_load_val = CONFIG_SYS_HZ/100; - } - - /* load value for 10 ms timeout */ - lastdec = timer->load = timer_load_val; - - /* auto load, start timer */ - timer->control = timer->control | TIMER_EN; - timestamp = 0; - - return (0); -} - -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return (get_timer_masked() - base); -} - -void __udelay (unsigned long usec) -{ - ulong tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } - else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER(); - timestamp = 0; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += (lastdec - now); - } else { - /* we have an overflow ... */ - timestamp += ((lastdec + timer_load_val) - now); - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = timer_load_val * 100; - - return tbclk; -} diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index e9c274d451..9feb2e55a3 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -125,67 +125,63 @@ III) Analysis of in-tree drivers ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 17) serial_lh7a40x.c + 17) serial_lpc2292.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 18) serial_lpc2292.c + 18) serial_max3100.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 19) serial_max3100.c - -------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 20) serial_mxc.c + 19) serial_mxc.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 21) serial_netarm.c + 20) serial_netarm.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 22) serial_pl01x.c + 21) serial_pl01x.c ------------------ No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this driver in fact contains two drivers in total. - 23) serial_pxa.c + 22) serial_pxa.c ---------------- This driver is a bit complicated, but due to clean support for CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the conversion process. - 24) serial_s3c24x0.c + 23) serial_s3c24x0.c -------------------- This driver, being quite ad-hoc might need some work to bring back to shape. - 25) serial_s3c44b0.c + 24) serial_s3c44b0.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 26) serial_s5p.c + 25) serial_s5p.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 27) serial_sa1100.c + 26) serial_sa1100.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 28) serial_sh.c + 27) serial_sh.c --------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 29) serial_xuartlite.c + 28) serial_xuartlite.c ---------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 30) usbtty.c + 29) usbtty.c ------------ This driver seems very complicated and entangled with USB framework. The conversion might be complicated here. - 31) arch/powerpc/cpu/mpc512x/serial.c + 30) arch/powerpc/cpu/mpc512x/serial.c ------------------------------------- This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to proper place. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 3c32f97abb..920ce6910e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -45,7 +45,6 @@ COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o -COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MXC_UART) += serial_mxc.o COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c deleted file mode 100644 index 6c9628581b..0000000000 --- a/drivers/serial/serial_lh7a40x.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CONSOLE_UART1) -# define UART_CONSOLE 1 -#elif defined(CONFIG_CONSOLE_UART2) -# define UART_CONSOLE 2 -#elif defined(CONFIG_CONSOLE_UART3) -# define UART_CONSOLE 3 -#else -# error "No console configured ... " -#endif - -static void lh7a40x_serial_setbrg(void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - int i; - unsigned int reg = 0; - - /* - * userguide 15.1.2.4 - * - * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1 - * - * UART_REF_FREQ = external system clock input / 2 (Hz) - * BAUD is desired baudrate (bits/s) - * - * NOTE: we add (divisor/2) to numerator to round for - * more precision - */ - reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1; - uart->brcon = reg; - - for (i = 0; i < 100; i++); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int lh7a40x_serial_init(void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* UART must be enabled before writing to any config registers */ - uart->con |= (UART_EN); - -#ifdef CONFIG_CONSOLE_UART1 - /* infrared disabled */ - uart->con |= UART_SIRD; -#endif - /* loopback disabled */ - uart->con &= ~(UART_LBE); - - /* modem lines and tx/rx polarities */ - uart->con &= ~(UART_MXP | UART_TXP | UART_RXP); - - /* FIFO enable, N81 */ - uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1); - - /* set baudrate */ - serial_setbrg (); - - /* enable rx interrupt */ - uart->inten |= UART_RI; - - return (0); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int lh7a40x_serial_getc(void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - /* wait for character to arrive */ - while (uart->status & UART_RXFE); - - return(uart->data & 0xff); -} - -#ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ -int hwflow_onoff(int on) -{ - switch(on) { - case 0: - default: - break; /* return current */ - case 1: - hwflow = 1; /* turn on */ - break; - case -1: - hwflow = 0; /* turn off */ - break; - } - return hwflow; -} -#endif - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet = 0; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - -/* - * Output a single byte to the serial port. - */ -static void lh7a40x_serial_putc(const char c) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif - - /* wait for room in the tx FIFO */ - while (!(uart->status & UART_TXFE)); - -#ifdef CONFIG_HWFLOW - /* Wait for CTS up */ - while(hwflow && !(uart->status & UART_CTS)); -#endif - - uart->data = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -static int lh7a40x_serial_tstc(void) -{ - lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE); - - return(!(uart->status & UART_RXFE)); -} - -static void lh7a40x_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -static struct serial_device lh7a40x_serial_drv = { - .name = "lh7a40x_serial", - .start = lh7a40x_serial_init, - .stop = NULL, - .setbrg = lh7a40x_serial_setbrg, - .putc = lh7a40x_serial_putc, - .puts = lh7a40x_serial_puts, - .getc = lh7a40x_serial_getc, - .tstc = lh7a40x_serial_tstc, -}; - -void lh7a40x_serial_initialize(void) -{ - serial_register(&lh7a40x_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &lh7a40x_serial_drv; -} diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 5d7b638b38..02cae0fc75 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -58,12 +58,6 @@ #define gadget_is_sa1100(g) 0 #endif -#ifdef CONFIG_USB_GADGET_LH7A40X -#define gadget_is_lh7a40x(g) (!strcmp("lh7a40x_udc", (g)->name)) -#else -#define gadget_is_lh7a40x(g) 0 -#endif - /* handhelds.org tree (?) */ #ifdef CONFIG_USB_GADGET_MQ11XX #define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name)) @@ -195,33 +189,31 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x07; else if (gadget_is_omap(gadget)) return 0x08; - else if (gadget_is_lh7a40x(gadget)) - return 0x09; else if (gadget_is_n9604(gadget)) - return 0x10; + return 0x09; else if (gadget_is_pxa27x(gadget)) - return 0x11; + return 0x10; else if (gadget_is_s3c2410(gadget)) - return 0x12; + return 0x11; else if (gadget_is_at91(gadget)) - return 0x13; + return 0x12; else if (gadget_is_imx(gadget)) - return 0x14; + return 0x13; else if (gadget_is_musbhsfc(gadget)) - return 0x15; + return 0x14; else if (gadget_is_musbhdrc(gadget)) - return 0x16; + return 0x15; else if (gadget_is_mpc8272(gadget)) - return 0x17; + return 0x16; else if (gadget_is_atmel_usba(gadget)) - return 0x18; + return 0x17; else if (gadget_is_fsl_usb2(gadget)) - return 0x19; + return 0x18; else if (gadget_is_amd5536udc(gadget)) - return 0x20; + return 0x19; else if (gadget_is_m66592(gadget)) - return 0x21; + return 0x20; else if (gadget_is_mv(gadget)) - return 0x22; + return 0x21; return -ENOENT; } diff --git a/include/lh7a400.h b/include/lh7a400.h deleted file mode 100644 index d1e70a228b..0000000000 --- a/include/lh7a400.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a400 SoC interface - */ - -#ifndef __LH7A400_H__ -#define __LH7A400_H__ - -#include "lh7a40x.h" - -/* Interrupt Controller (userguide 8.2.1) */ -typedef struct { - volatile u32 intsr; - volatile u32 intrsr; - volatile u32 intens; - volatile u32 intenc; - volatile u32 rsvd1; - volatile u32 rsvd2; - volatile u32 rsvd3; -} /*__attribute__((__packed__))*/ lh7a400_interrupt_t; -#define LH7A400_INTERRUPT_BASE (0x80000500) -#define LH7A400_INTERRUPT_PTR ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE) - -/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ -typedef struct { - lh7a40x_dmachan_t chan[15]; - volatile u32 glblint; - volatile u32 rsvd1; - volatile u32 rsvd2; - volatile u32 rsvd3; -} /*__attribute__((__packed__))*/ lh7a400_dma_t; - -#define LH7A400_DMA_BASE (0x80002800) -#define DMA_USBTX_OFFSET (0x000) -#define DMA_USBRX_OFFSET (0x040) -#define DMA_MMCTX_OFFSET (0x080) -#define DMA_MMCRX_OFFSET (0x0C0) -#define DMA_AC97_BASE (0x80002A00) - -#define LH7A400_DMA_PTR ((lh7a400_dma_t*) LH7A400_DMA_BASE) -#define LH7A400_DMA_USBTX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET)) -#define LH7A400_DMA_USBRX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET)) -#define LH7A400_DMA_MMCTX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET)) -#define LH7A400_DMA_MMCRX \ - ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET)) -#define LH7A400_AC97RX(n) \ - ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ - ((2*n) * sizeof(lh7a400_dmachan_t)))) -#define LH7A400_AC97TX(n) \ - ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \ - (((2*n)+1) * sizeof(lh7a400_dmachan_t)))) - -#endif /* __LH7A400_H__ */ diff --git a/include/lh7a404.h b/include/lh7a404.h deleted file mode 100644 index 4098af34a8..0000000000 --- a/include/lh7a404.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a404 SoC interface - */ - -#ifndef __LH7A404_H__ -#define __LH7A404_H__ - -#include "lh7a40x.h" - -/* Interrupt Controller (userguide 8.2.1) */ -typedef struct { - volatile u32 irqstatus; - volatile u32 fiqstatus; - volatile u32 rawintr; - volatile u32 intsel; - volatile u32 inten; - volatile u32 intenclr; - volatile u32 softint; - volatile u32 softintclr; - volatile u32 protect; - volatile u32 unused1; - volatile u32 unused2; - volatile u32 vectaddr; - volatile u32 nvaddr; - volatile u32 unused3[32]; - volatile u32 vad[16]; - volatile u32 unused4[44]; - volatile u32 vectcntl[16]; - volatile u32 unused5[44]; - volatile u32 itcr; - volatile u32 itip1; - volatile u32 itip2; - volatile u32 itop1; - volatile u32 itop2; - volatile u32 unused6[333]; - volatile u32 periphid[4]; - volatile u32 pcellid[4]; -} /*__attribute__((__packed__))*/ lh7a404_vic_t; -#define LH7A404_VIC_BASE (0x80008000) -#define LH7A400_VIC_PTR(x) ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000))) - - -typedef struct { - lh7a40x_dmachan_t m2p0_tx; - lh7a40x_dmachan_t m2p1_rx; - lh7a40x_dmachan_t m2p2_tx; - lh7a40x_dmachan_t m2p3_rx; - lh7a40x_dmachan_t m2m0; - lh7a40x_dmachan_t m2m1; - lh7a40x_dmachan_t unused1; - lh7a40x_dmachan_t unused2; - lh7a40x_dmachan_t m2p5_rx; - lh7a40x_dmachan_t m2p4_tx; - lh7a40x_dmachan_t m2p7_rx; - lh7a40x_dmachan_t m2p6_tx; - lh7a40x_dmachan_t m2p9_rx; - lh7a40x_dmachan_t m2p8_tx; - volatile u32 chanarb; - volatile u32 glblint; -} /*__attribute__((__packed__))*/ lh7a400_dma_t; - - -#endif /* __LH7A404_H__ */ diff --git a/include/lh7a40x.h b/include/lh7a40x.h deleted file mode 100644 index 09a463c841..0000000000 --- a/include/lh7a40x.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * lh7a40x SoC series common interface - */ - -#ifndef __LH7A40X_H__ -#define __LH7A40X_H__ - -/* (SMC) Static Memory Controller (usersguide 4.2.1) */ -typedef struct { - volatile u32 attib; - volatile u32 com; - volatile u32 io; - volatile u32 rsvd1; -} /*__attribute__((__packed__))*/ lh7a40x_pccard_t; - -typedef struct { - volatile u32 bcr[8]; - lh7a40x_pccard_t pccard[2]; - volatile u32 pcmciacon; -} /*__attribute__((__packed__))*/ lh7a40x_smc_t; -#define LH7A40X_SMC_BASE (0x80002000) -#define LH7A40X_SMC_PTR ((lh7a40x_smc_t*) LH7A40X_SMC_BASE) - -/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */ -typedef struct { - volatile u32 rsvd1; - volatile u32 gblcnfg; - volatile u32 rfshtmr; - volatile u32 bootstat; - volatile u32 sdcsc[4]; -} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t; -#define LH7A40X_SDMC_BASE (0x80002400) -#define LH7A40X_SDMC_PTR ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE) - -/* (CSC) Clock and State Controller (userguide 6.2.1) */ -typedef struct { - volatile u32 pwrsr; - volatile u32 pwrcnt; - volatile u32 halt; - volatile u32 stby; - volatile u32 bleoi; - volatile u32 mceoi; - volatile u32 teoi; - volatile u32 stfclr; - volatile u32 clkset; - volatile u32 scrreg[2]; - volatile u32 rsvd1; - volatile u32 usbreset; -} /*__attribute__((__packed__))*/ lh7a40x_csc_t; -#define LH7A40X_STPWR_BASE (0x80000400) -#define LH7A40X_CSC_PTR ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE) - -#define CLKSET_SMCROM (0x01000000) -#define CLKSET_PS (0x000C0000) -#define CLKSET_PS_0 (0x00000000) -#define CLKSET_PS_1 (0x00040000) -#define CLKSET_PS_2 (0x00080000) -#define CLKSET_PS_3 (0x000C0000) -#define CLKSET_PCLKDIV (0x00030000) -#define CLKSET_PCLKDIV_2 (0x00000000) -#define CLKSET_PCLKDIV_4 (0x00010000) -#define CLKSET_PCLKDIV_8 (0x00020000) -#define CLKSET_MAINDIV2 (0x0000f800) -#define CLKSET_MAINDIV1 (0x00000780) -#define CLKSET_PREDIV (0x0000007C) -#define CLKSET_HCLKDIV (0x00000003) - -/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */ -typedef struct { - volatile u32 maxcnt; - volatile u32 base; - volatile u32 current; - volatile u32 rsvd1; -} lh7a40x_dmabuf_t; - -typedef struct { - volatile u32 control; - volatile u32 interrupt; - volatile u32 rsvd1; - volatile u32 status; - volatile u32 rsvd2; - volatile u32 remain; - volatile u32 rsvd3; - volatile u32 rsvd4; - lh7a40x_dmabuf_t buf[2]; -} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t; - - -/* (WDT) Watchdog Timer (userguide 11.2.1) */ -typedef struct { - volatile u32 ctl; - volatile u32 rst; - volatile u32 status; - volatile u32 count[4]; -} /*__attribute__((__packed__))*/ lh7a40x_wdt_t; -#define LH7A40X_WDT_BASE (0x80001400) -#define LH7A40X_WDT_PTR ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE) - -/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */ -typedef struct { - volatile u32 rtcdr; - volatile u32 rtclr; - volatile u32 rtcmr; - volatile u32 unk1; - volatile u32 rtcstat_eoi; - volatile u32 rtccr; - volatile u32 rsvd1[58]; -} /*__attribute__((__packed__))*/ lh7a40x_rtc_t; -#define LH7A40X_RTC_BASE (0x80000D00) -#define LH7A40X_RTC_PTR ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE) - -/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */ -typedef struct { - volatile u32 load; - volatile u32 value; - volatile u32 control; - volatile u32 tceoi; -} /*__attribute__((__packed__))*/ lh7a40x_timer_t; - -typedef struct { - lh7a40x_timer_t timer1; - volatile u32 rsvd1[4]; - lh7a40x_timer_t timer2; - volatile u32 unk1[4]; - volatile u32 bzcon; - volatile u32 unk2[15]; - lh7a40x_timer_t timer3; - /*volatile u32 rsvd2;*/ -} /*__attribute__((__packed__))*/ lh7a40x_timers_t; -#define LH7A40X_TIMERS_BASE (0x80000C00) -#define LH7A40X_TIMERS_PTR ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE) - -#define TIMER_EN (0x00000080) -#define TIMER_PER (0x00000040) -#define TIMER_FREE (0x00000000) -#define TIMER_CLK508K (0x00000008) -#define TIMER_CLK2K (0x00000000) - -/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */ -typedef struct { - volatile u32 cr0; - volatile u32 cr1; - volatile u32 irr_roeoi; - volatile u32 dr; - volatile u32 cpr; - volatile u32 sr; - /*volatile u32 rsvd1[58];*/ -} /*__attribute__((__packed__))*/ lh7a40x_ssp_t; -#define LH7A40X_SSP_BASE (0x80000B00) -#define LH7A40X_SSP_PTR ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE) - -/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */ -typedef struct { - volatile u32 data; - volatile u32 fcon; - volatile u32 brcon; - volatile u32 con; - volatile u32 status; - volatile u32 rawisr; - volatile u32 inten; - volatile u32 isr; - volatile u32 rsvd1[56]; -} /*__attribute__((__packed__))*/ lh7a40x_uart_t; -#define LH7A40X_UART_BASE (0x80000600) -#define LH7A40X_UART_PTR(n) \ - ((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t)))) - -#define UART_BE (0x00000800) /* the rx error bits */ -#define UART_OE (0x00000400) -#define UART_PE (0x00000200) -#define UART_FE (0x00000100) - -#define UART_WLEN (0x00000060) /* fcon bits */ -#define UART_WLEN_8 (0x00000060) -#define UART_WLEN_7 (0x00000040) -#define UART_WLEN_6 (0x00000020) -#define UART_WLEN_5 (0x00000000) -#define UART_FEN (0x00000010) -#define UART_STP2 (0x00000008) -#define UART_STP2_2 (0x00000008) -#define UART_STP2_1 (0x00000000) -#define UART_EPS (0x00000004) -#define UART_EPS_EVEN (0x00000004) -#define UART_EPS_ODD (0x00000000) -#define UART_PEN (0x00000002) -#define UART_BRK (0x00000001) - -#define UART_BAUDDIV (0x0000ffff) /* brcon bits */ - -#define UART_SIRBD (0x00000080) /* con bits */ -#define UART_LBE (0x00000040) -#define UART_MXP (0x00000020) -#define UART_TXP (0x00000010) -#define UART_RXP (0x00000008) -#define UART_SIRLP (0x00000004) -#define UART_SIRD (0x00000002) -#define UART_EN (0x00000001) - -#define UART_TXFE (0x00000080) /* status bits */ -#define UART_RXFF (0x00000040) -#define UART_TXFF (0x00000020) -#define UART_RXFE (0x00000010) -#define UART_BUSY (0x00000008) -#define UART_DCD (0x00000004) -#define UART_DSR (0x00000002) -#define UART_CTS (0x00000001) - -#define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */ - -#define UART_RTI (0x00000008) /* generic interrupt bits */ -#define UART_MI (0x00000004) -#define UART_TI (0x00000002) -#define UART_RI (0x00000001) - -/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */ -typedef struct { - volatile u32 pad; - volatile u32 pbd; - volatile u32 pcd; - volatile u32 pdd; - volatile u32 padd; - volatile u32 pbdd; - volatile u32 pcdd; - volatile u32 pddd; - volatile u32 ped; - volatile u32 pedd; - volatile u32 kbdctl; - volatile u32 pinmux; - volatile u32 pfd; - volatile u32 pfdd; - volatile u32 pgd; - volatile u32 pgdd; - volatile u32 phd; - volatile u32 phdd; - volatile u32 rsvd1; - volatile u32 inttype1; - volatile u32 inttype2; - volatile u32 gpiofeoi; - volatile u32 gpiointen; - volatile u32 intstatus; - volatile u32 rawintstatus; - volatile u32 gpiodb; - volatile u32 papd; - volatile u32 pbpd; - volatile u32 pcpd; - volatile u32 pdpd; - volatile u32 pepd; - volatile u32 pfpd; - volatile u32 pgpd; - volatile u32 phpd; -} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t; -#define LH7A40X_GPIOINT_BASE (0x80000E00) -#define LH7A40X_GPIOINT_PTR ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE) - -/* Embedded SRAM */ -#define CONFIG_SYS_SRAM_BASE (0xB0000000) -#define CONFIG_SYS_SRAM_SIZE (80*1024) /* 80kB */ - -#endif /* __LH7A40X_H__ */ diff --git a/include/lpd7a400_cpld.h b/include/lpd7a400_cpld.h deleted file mode 100644 index c70af09e67..0000000000 --- a/include/lpd7a400_cpld.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Logic lh7a400-10 Card Engine CPLD interface - */ - -#ifndef __LPD7A400_CPLD_H_ -#define __LPD7A400_CPLD_H_ - - -/* - * IO Controller Address and Register Definitions - * - using LH7A400-10 Card Engine IO Controller Specification - * (logic PN: 70000079) - */ - -/*------------------------------------------------------------------ - * Slow Peripherals (nCS6) - */ -#define LPD7A400_CPLD_CF (0x60200000) -#define LPD7A400_CPLD_ISA (0x60400000) - -/*------------------------------------------------------------------ - * Fast Peripherals (nCS7) - * - * The CPLD directs access to 0x70000000-0x701fffff to the onboard - * ethernet controller - */ -#define LPD7A400_CPLD_WLAN_BASE (0x70000000) - -/* All registers are 8 bit */ -#define LPD7A400_CPLD_CECTL_REG (0x70200000) -#define LPD7A400_CPLD_SPIDATA_REG (0x70600000) -#define LPD7A400_CPLD_SPICTL_REG (0x70800000) -#define LPD7A400_CPLD_EEPSPI_REG (0x70a00000) -#define LPD7A400_CPLD_INTMASK_REG (0x70c00000) -#define LPD7A400_CPLD_MODE_REG (0x70e00000) -#define LPD7A400_CPLD_FLASH_REG (0x71000000) -#define LPD7A400_CPLD_PWRMG_REG (0x71200000) -#define LPD7A400_CPLD_REV_REG (0x71400000) -#define LPD7A400_CPLD_EXTGPIO_REG (0x71600000) -#define LPD7A400_CPLD_GPIODATA_REG (0x71800000) -#define LPD7A400_CPLD_GPIODIR_REG (0x71a00000) - -#define LPD7A400_CPLD_REGPTR (volatile u8*) - -/* Card Engine Control Register (section 3.1.2) */ -#define CECTL_SWINT (0x80) /* Software settable interrupt source - (routed to uP PF3) - 0 = generate interrupt, 1 = do not */ -#define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask - 0 = not masked, 1 = masked */ -#define CECTL_PDRV (0x20) /* PCC_nDRV output - 0 = active, 1 = inactive */ -#define CECTL_USB1C (0x10) /* USB1 connection interrupt - 0 = active, 1 = inactive */ -#define CECTL_USB1P (0x08) /* USB1 Power enable - 0 = enabled, 1 = disabled */ -#define CECTL_AWKP (0x04) /* Auto-Wakeup enable - 0 = enabled, 1 = disabled */ -#define CECTL_LCDV (0x02) /* LCD VEE enable - 0 = disabled, 1 = enabled */ -#define CECTL_WLPE (0x01) /* Wired LAN power enable - 0 = enabled, 1 = disabled */ - -/* SPI Control Register (section 3.1.5) */ -#define SPICTL_SPLD (0x20) /* SPI load (R) - 0 = data reg. has not been loaded, shift - count has not been reset - 1 = data reg. loaded, shift count reset */ -#define SPICTL_SPST (0x10) /* SPI start (RW) - 0 = don't load data reg. and reset shift count - 1 = ready to load data reg and reset shift count */ -#define SPICTL_SPDN (0x08) /* SPI done (R) - 0 = not done - 1 = access done */ -#define SPICTL_SPRW (0x04) /* SPI read/write (RW) - 0 = SPI write access - 1 = SPI read access */ -#define SPICTL_STCS (0x02) /* SPI touch chip select (RW) - 0 = not selected - 1 = selected */ -#define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used} - 0 = not selected - 1 = selected */ - -/* EEPROM SPI Interface Register (section 3.1.6) */ -#define EEPSPI_EECS (0x08) /* EEPROM chip select (RW) - 0 = not selected - 1 = selected */ -#define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */ -#define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */ -#define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */ - -/* Interrupt/Mask Register (section 3.1.7) */ -#define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R) - 0 = interrupt active - 1 = no interrupt */ -#define INTMASK_PIRQ (0x10) /* legacy, no effect */ -#define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW) - 0 = not masked - 1 = masked */ -#define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R) - 0 = interrupt active - 1 = no interrupt */ -#define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R) - 0 = interrupt active - 1 = no interrupt */ - -/* Mode Register (section 3.1.8) */ -#define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R) - 0 = active slot VS1 pin is low - 1 = active slot VS1 pin is high */ -#define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R) - 0 = active slot CD2 is low - 1 = active slot CD2 is high */ -#define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R) - 0 = 16 bit access area - 1 = 8 bit access area */ -#define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R) - 0 = active slot CD1 is low - 1 = active slot CD1 is high */ -#define MODE_upMODE3 (0x08) /* Mode Pin 3 (R) - 0 = off-board boot device - 1 = on-board boot device (flash) */ -#define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only) - 0 = big endian - 1 = little endian */ -#define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */ -#define MODE_upMODE0 (0x01) /* - bus width at boot */ - - -/* Flash Register (section 3.1.9) */ -#define FLASH_FPOP (0x08) /* Flash populated (RW) - 0 = populated, 1 = not */ -#define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip - 0 = busy, 1 = ready */ -#define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip - 0 = busy, 1 = ready */ -#define FLASH_FPEN (0x01) /* Flash program enable (RW) - 0 = flash write protected - 1 = programming enabled */ - -/* Power Management Register (section 3.1.10) - * - when either of these is low an unmaskable interrupt to cpu - * is generated - */ -#define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R) - 0 = low, 1 = high */ -#define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R) - 0 = low, 1 = high */ - - -/* Extended GPIO Register (section 3.1.12) */ -#define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1) - 0 = set pin low, 1 = set pin high */ -#define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2) - 0 = set pin low, 1 = set pin high */ -#define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1) - 0 = set pin low, 1 = set pin high */ - -/* GPIO Data Register (section 3.1.13) */ -#define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2) - 0 = set low (output) / read low (input) - 1 = set high (output) / read high (input) */ - -/* GPIO Direction Register (section 3.1.14) */ -#define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW) - 0 = output, 1 = input */ - -#endif /* __LH7A400_H__ */ -- cgit v1.2.3 From 1db7377a70a8d931c32648e717695133120d5456 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Thu, 13 Sep 2012 22:22:04 +0000 Subject: mmc: at91: add multi block read/write support. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the at91sam9263, the mmc hardware support multi blocks read/write. So this driver enable it. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- drivers/mmc/gen_atmel_mci.c | 11 +++++++++++ include/atmel_mci.h | 7 ++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 4968c5e491..9f06304548 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -87,6 +87,11 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) | MMCI_BF(BLKLEN, blklen) | MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF)), &mci->mr); + /* + * On some new platforms BLKLEN in mci->mr is ignored. + * Should use the BLKLEN in the block register. + */ + writel(MMCI_BF(BLKLEN, blklen), &mci->blkr); initialized = 1; } @@ -183,6 +188,12 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Figure out the transfer arguments */ cmdr = mci_encode_cmd(cmd, data, &error_flags); + /* For multi blocks read/write, set the block register */ + if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) + || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) + writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len), + &mci->blkr); + /* Send the command */ writel(cmd->cmdarg, &mci->argr); writel(cmdr, &mci->cmdr); diff --git a/include/atmel_mci.h b/include/atmel_mci.h index 3dd5d67be9..c711881276 100644 --- a/include/atmel_mci.h +++ b/include/atmel_mci.h @@ -38,7 +38,7 @@ typedef struct atmel_mci { u32 sdcr; /* 0x0c */ u32 argr; /* 0x10 */ u32 cmdr; /* 0x14 */ - u32 _18; /* 0x18 */ + u32 blkr; /* 0x18 */ u32 _1c; /* 0x1c */ u32 rspr; /* 0x20 */ u32 rspr1; /* 0x24 */ @@ -118,6 +118,11 @@ typedef struct atmel_mci { #define MMCI_TRTYP_OFFSET 19 #define MMCI_TRTYP_SIZE 2 +/* Bitfields in BLKR */ +/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */ +#define MMCI_BCNT_OFFSET 0 +#define MMCI_BCNT_SIZE 16 + /* Bitfields in RSPRx */ #define MMCI_RSP_OFFSET 0 #define MMCI_RSP_SIZE 32 -- cgit v1.2.3 From 3a49cd7e1a26af6708b05d4877bb0254a08dded3 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Thu, 13 Sep 2012 22:22:05 +0000 Subject: ARM: at91sam9x5: enable MCI0 support for 9x5ek board. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 15 +++++++++++++++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 10 ++++++++++ include/configs/at91sam9x5ek.h | 10 ++++++++++ 3 files changed, 35 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 6d77219d0d..93485523b5 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -118,6 +118,21 @@ void at91_serial2_hw_init(void) writel(1 << ATMEL_ID_USART2, &pmc->pcer); } +void at91_mci_hw_init(void) +{ + /* Initialize the MCI0 */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ + at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ + + /* Enable clock for MCI0 */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); +} + #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 06028aa01e..edb088680d 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -31,6 +31,7 @@ #include #include #include +#include #ifdef CONFIG_MACB #include #endif @@ -258,6 +259,15 @@ void spi_cs_deactivate(struct spi_slave *slave) } #endif /* CONFIG_ATMEL_SPI */ +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); +} +#endif + int board_early_init_f(void) { at91_seriald_hw_init(); diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index cbdc3e93cb..71f765b494 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -89,6 +89,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NAND #define CONFIG_CMD_SF +#define CONFIG_CMD_MMC /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @@ -138,6 +139,15 @@ #define CONFIG_CMD_UBIFS #endif +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_CMD_FAT +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_DOS_PARTITION +#endif + /* Ethernet */ #define CONFIG_MACB #define CONFIG_RMII -- cgit v1.2.3 From 9924ca6e9b1933b8ea2bb0ca49fe67df9856ccc5 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Thu, 13 Sep 2012 22:22:06 +0000 Subject: mmc: at91: use max timeout value. It will avoid some situation that timeout happened. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- drivers/mmc/gen_atmel_mci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 9f06304548..67b2dbe8d4 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -321,8 +321,8 @@ static int mci_init(struct mmc *mmc) writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */ writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */ - /* Initial Time-outs */ - writel(0x5f, &mci->dtor); + /* This delay can be optimized, but stick with max value */ + writel(0x7f, &mci->dtor); /* Disable Interrupts */ writel(~0UL, &mci->idr); -- cgit v1.2.3 From 6abcf2d53148210111a06fe4d43fb36ea4be85a0 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Apr 2012 16:41:14 +0000 Subject: nds32: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT With almost all the architecture and board BOARD_LATE_INIT does not use. CONFIG_BOARD_LATE_INIT is used instead. This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT. Signed-off-by: Nobuhiro Iwamatsu CC: Macpaul Lin [trini: Fixup for context changes] Signed-off-by: Tom Rini --- arch/nds32/lib/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 89900fea43..875f22013c 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -396,7 +396,7 @@ void board_init_r(gd_t *id, ulong dest_addr) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#ifdef BOARD_LATE_INIT +#ifdef CONFIG_BOARD_LATE_INIT board_late_init(); #endif -- cgit v1.2.3 From bfa5b71408da629493838668e4df0ca9d12107bb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 19 Sep 2012 03:18:53 +0000 Subject: mpc82xx: Remove BMW board port As the board seems to be unmaintained for some time, lets remove the support in mainline completely. Signed-off-by: Stefan Roese Cc: Marek Vasut Cc: James F. Dougherty Cc: Wolfgang Denk Acked-by: Marek Vasut --- arch/powerpc/cpu/mpc824x/cpu_init.c | 4 +- arch/powerpc/cpu/mpc824x/start.S | 9 +- board/bmw/Makefile | 50 -- board/bmw/README | 331 ---------- board/bmw/bmw.c | 159 ----- board/bmw/bmw.h | 86 --- board/bmw/config.mk | 30 - board/bmw/early_init.S | 1170 ----------------------------------- board/bmw/flash.c | 779 ----------------------- board/bmw/m48t59y.c | 324 ---------- board/bmw/m48t59y.h | 57 -- board/bmw/ns16550.c | 57 -- board/bmw/ns16550.h | 79 --- board/bmw/serial.c | 105 ---- boards.cfg | 1 - include/configs/BMW.h | 302 --------- 16 files changed, 4 insertions(+), 3539 deletions(-) delete mode 100644 board/bmw/Makefile delete mode 100644 board/bmw/README delete mode 100644 board/bmw/bmw.c delete mode 100644 board/bmw/bmw.h delete mode 100644 board/bmw/config.mk delete mode 100644 board/bmw/early_init.S delete mode 100644 board/bmw/flash.c delete mode 100644 board/bmw/m48t59y.c delete mode 100644 board/bmw/m48t59y.h delete mode 100644 board/bmw/ns16550.c delete mode 100644 board/bmw/ns16550.h delete mode 100644 board/bmw/serial.c delete mode 100644 include/configs/BMW.h diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c index 395f7767d1..cfc665d95c 100644 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ b/arch/powerpc/cpu/mpc824x/cpu_init.c @@ -63,7 +63,7 @@ void cpu_init_f (void) { /* MOUSSE board is initialized in asm */ -#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW) +#if !defined(CONFIG_MOUSSE) register unsigned long val; CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ @@ -321,7 +321,7 @@ cpu_init_f (void) CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ __asm__ __volatile__("eieio"); -#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */ +#endif /* !CONFIG_MOUSSE */ } diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index 70db73e156..076df70a9f 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -113,9 +113,6 @@ _start: in_flash: -#if defined(CONFIG_BMW) - bl early_init_f /* Must be ASM: no stack yet! */ -#endif /* * Setup BATs - cannot be done in C since we don't have a stack yet */ @@ -126,7 +123,7 @@ in_flash: mfmsr r3 ori r3, r3, (MSR_IR | MSR_DR) mtmsr r3 -#if !defined(CONFIG_BMW) + /* Enable and invalidate data cache. */ mfspr r3, HID0 @@ -158,7 +155,7 @@ in_flash: ori r3, r3, 0x0080 sync mtspr 1011, r3 -#endif /* !CONFIG_BMW */ + /* * Thisk the stack pointer *somewhere* sensible. Doesnt * matter much where as we'll move it when we relocate @@ -498,7 +495,6 @@ relocate_code: bdnz 3b 4: -#if !defined(CONFIG_BMW) /* Unlock the data cache and invalidate locked area */ xor r0, r0, r0 mtspr 1011, r0 @@ -510,7 +506,6 @@ relocate_code: dcbi r0, r4 addi r4, r4, 32 bdnz 41b -#endif /* * Now flush the cache: note that we must start from a cache aligned diff --git a/board/bmw/Makefile b/board/bmw/Makefile deleted file mode 100644 index 4f88efafd4..0000000000 --- a/board/bmw/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o - -SOBJS = early_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/bmw/README b/board/bmw/README deleted file mode 100644 index 1fbef79e64..0000000000 --- a/board/bmw/README +++ /dev/null @@ -1,331 +0,0 @@ -Broadcom 95xx BMW CPCI Platform - -Overview -========= -BMW is an MPC8245 system controller featuring: -* 3U CPCI Form Factor -* BCM5703 Gigabit Ethernet -* M48T59Y NVRAM -* 16MB DOC -* DIP Socket for Socketed DOC up to 1GB -* 64MB SDRAM -* LCD Display -* Configurable Jumper options for 66,85, and 100Mhz memory bus - - -BMW System Address Map -====================== -BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual -(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found -onboard the processor module are listed briefly below: - -0x00000000 - 0x40000000 - 64MB SDRAM SIMM - (Unregistered PC-100 SDRAM DIMM Module) - -0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000 - TSOP 16MB (MD2211-D16-V3) - -0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000 - DIP32 (Socketed 16MB - 1GB ) * - NOTE: this is not populated on all systems. - -0x7c000000 - 0x7c000000 - Reset Register - (Write 0 to reset) - -0x7c000001 - 0x7c000001 - System LED - (Clear Bit 7 to turn on, set to shut off) - -0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3 - (Clear bit 7 to reset, set to assert IRQ3) - -0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register - (Clear bit 7 to make R/W, set to make R/O) - -0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character - 5x7 Dot Matrix Alphanumeric Display - (Each byte sets the appropriate character) - -0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC - NVRAM Memory Region - -0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC - Realtime Clock Registers - -0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom - (AMD AM29F040, ST 29W040B) - -0xFFF00100 - System Reset Vector - - -IO/MMU (BAT) Configuration -====================== -The following Block-Address-Translation (BAT) configuration -is recommended to access all I/O devices. - -#define CONFIG_SYS_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - - -Interrupt Mappings -====================== -BMW uses MPC8245 discrete mode interrupts. With the following -hardwired mappings: - -BCM5701 10/100/1000 Ethernet IRQ1 -CompactPCI Interrupt A IRQ2 -RTC/Watchdog Interrupt IRQ3 -Internal NS16552 UART IRQ4 - - -Jumper Settings -====================== - -BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus. -A jumper (X) is a 0 bit. - -Hence 66= 10110 - 85= 11000 - 100= 10000 - -Jumper Settings for various Speeds -======================= -J1 J2 J3 J4 J5 - X X 66Mhz -======================= -J1 J2 J3 J4 J5 - X X X 85Mhz -======================= -J1 J2 J3 J4 J5 - X X X X 100Mhz -======================= - -Obviously, 100Mhz memory bus is recommended for optimum performance. - - -U-Boot -=============== -Broadcom BMW board is supported under config_BWM option. -Supported features: - -- NVRAM setenv/getenv (used by Linux Kernel for configuration variables) -- BCM570x TFTP file transfer support -- LCD Display Support -- DOC Support - (underway) - - -U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) - -CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) -Built: Aug 6 2002 at 17:44:37 -Local Bus at 66 MHz -DRAM: 64 MB -FLASH: 4095 MB -In: serial -Out: serial -Err: serial -DOC: No DiskOnChip found -Hit any key to stop autoboot: 0 -=>printenv -bootdelay=5 -baudrate=9600 -clocks_in_mhz=1 -hostname=switch-2 -bootcmd=tftp 100000 vmlinux.img;bootm -gateway=10.16.64.1 -ethaddr=00:00:10:18:10:10 -nfsroot=172.16.40.111:/boot/root-fs -filesize=5ec8c -netmask=255.255.240.0 -ipaddr=172.16.40.114 -serverip=172.16.40.111 -root=/dev/nfs -stdin=serial -stdout=serial -stderr=serial - -Environment size: 315/8172 bytes -=>boot - - -DevTools -======== -ELDK - DENX Embedded Linux Development Kit - -ROM Emulator - Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time) - Grammar Engine PL32E 32Pin PLCC Emulation cables - Grammar Engine 3VA8CON (3Volt adapter with Short cables) - Grammar Engine FPNET PromICE Ethernet Adapters - -ICE - WRS/EST VisionICE-II (PPC8240) - - -=>reset - - -U-Boot 1.2.0 (Aug 6 2002 - 17:44:48) - -CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) -Built: Aug 6 2002 at 17:44:37 -Local Bus at 66 MHz -DRAM: 64 MB -FLASH: 4095 MB -In: serial -Out: serial -Err: serial -DOC: No DiskOnChip found -Hit any key to stop autoboot: 0 - -Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000 -BCM570x PCI Memory base address @0x80100000 -eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF -eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010 -eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found -eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON -ARP broadcast 1 -TFTP from server 172.16.40.111; our IP address is 172.16.40.114 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: ################################################################# - ####################################T ############################# - ###################### -done -Bytes transferred = 777199 (bdbef hex) - -eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline. -## Booting image at 00100000 ... - Image Name: vmlinux.bin.gz - Created: 2002-08-06 6:30:13 UTC - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 777135 Bytes = 758 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb -Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002 -CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000 -U-Boot Environment: 0xc01b08f0 -IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10> -cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e -NOTICE: mounting root file system via NFS -IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111 -On node 0 totalpages: 16384 -zone(0): 16384 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111 -root_dev_setup:/dev/nfs or 00:ff -time_init: decrementer frequency = 16.501145 MHz -Calibrating delay loop... 175.71 BogoMIPS -Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem) -Dentry cache hash table entries: 8192 (order: 4, 65536 bytes) -Inode cache hash table entries: 4096 (order: 3, 32768 bytes) -Mount-cache hash table entries: 1024 (order: 1, 8192 bytes) -Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) -Page-cache hash table entries: 16384 (order: 4, 65536 bytes) -POSIX conformance testing by UNIFIX -PCI: Probing PCI hardware -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Initializing RT netlink socket -Starting kswapd -devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au) -devfs: devfs_debug: 0x0 -devfs: boot_options: 0x1 -Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -pty: 256 Unix98 ptys configured -Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled -Testing ttyS0 (0xf7f51500, 0xf7f51500)... -Testing ttyS1 (0xfc004600, 0xfc004600)... -ttyS00 at 0xf7f51500 (irq = 24) is a ST16650 -ttyS01 at 0xfc004600 (irq = 25) is a 16550A -Real Time Clock Driver v1.10e -RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -loop: loaded (max 8 devices) -TFFS 5.1.1 Flash disk driver for DiskOnChip -Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd. -DOC device(s) found: 1 -fl_init: registered device at major: 100 -fl_geninit: registered device at major: 100 -Partition check: - fla: p1 -partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB -partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB -partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB -partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB -Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02) -eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010 -eth0: Broadcom BCM5701 Integrated Copper transceiver found -eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON -bond0 registered without MII link monitoring, in bonding mode. -rtc: unable to get misc minor -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP, IGMP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 4096 bind 4096) -bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex -IP-Config: Gateway not on directly connected network. -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -802.1Q VLAN Support v1.7 Ben Greear -All bugs added by David S. Miller -Looking up port of RPC 100003/2 on 172.16.40.111 -Looking up port of RPC 100005/1 on 172.16.40.111 -VFS: Mounted root (nfs filesystem). -Mounted devfs on /dev -Freeing unused kernel memory: 100k init -INIT: version 2.78 booting -Mounting local filesystems... -not mounted anything -Setting up symlinks in /dev...done. -Setting up extra devices in /dev...done. -Starting devfsd...Started device management daemon for /dev -INIT: Entering runlevel: 2 -Starting internet superserver: inetd. - - -Welcome to Linux/PPC -MPC8245/BMW - - -switch-2 login: root -Password: -PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0) -Last login: Thu Nov 25 11:51:14 1920 on console - - -Welcome to Linux/PPC -MPC8245/BMW - - -login[49]: ROOT LOGIN on `console' - -root@switch-2:~# cat /proc/cpuinfo -cpu : 82xx -revision : 16.20 (pvr 8081 1014) -bogomips : 175.71 -vendor : Broadcom -machine : BMW/MPC8245 -root@switch-2:~# diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c deleted file mode 100644 index 5ba6c09d1c..0000000000 --- a/board/bmw/bmw.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2002 - * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bmw.h" -#include "m48t59y.h" -#include - - -int checkboard(void) -{ - ulong busfreq = get_bus_freq(0); - char buf[32]; - - puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n"); - printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */ - printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); - return 0; -} - -phys_size_t initdram(int board_type) -{ - return 64*1024*1024; -} - - -void -get_tod(void) -{ - int year, month, day, hour, minute, second; - - m48_tod_get(&year, - &month, - &day, - &hour, - &minute, - &second); - - printf(" Current date/time: %d/%d/%d %d:%d:%d \n", - month, day, year, hour, minute, second); - -} - -/* - * EPIC, PCI, and I/O devices. - * Initialize Mousse Platform, probe for PCI devices, - * Query configuration parameters if not set. - */ -int misc_init_f (void) -{ -#if 0 - m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */ - printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n", - TOD_NVRAM_SIZE); - get_tod(); -#endif - - sys_led_msg("BOOT"); - return 0; -} - - -/* - * Initialize PCI Devices, report devices found. - */ -struct pci_controller hose; - -void pci_init_board (void) -{ - pci_mpc824x_init(&hose); - /* pci_dev_init(0); */ -} - -/* - * Write characters to LCD display. - * Note that the bytes for the first character is the last address. - */ -void -sys_led_msg(char* msg) -{ - LED_REG(0) = msg[3]; - LED_REG(1) = msg[2]; - LED_REG(2) = msg[1]; - LED_REG(3) = msg[0]; -} - -#ifdef CONFIG_CMD_DOC -/* - * Map onboard TSOP-16MB DOC FLASH chip. - */ -void doc_init (void) -{ - doc_probe(DOC_BASE_ADDR); -} -#endif - -#define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR) - -/* Read from NVRAM */ -void* -nvram_read(void *dest, const long src, size_t count) -{ - int i; - volatile unsigned char* d = (unsigned char*)dest; - volatile unsigned char* s = (unsigned char*)src; - - for( i = 0; i < count;i++) - d[i] = s[i]; - - return dest; -} - -/* Write to NVRAM */ -void -nvram_write(long dest, const void *src, size_t count) -{ - int i; - volatile unsigned char* d = (unsigned char*)dest; - volatile unsigned char* s = (unsigned char*)src; - - SYS_TOD_UNPROTECT(); - - for( i = 0; i < count;i++) - d[i] = s[i]; - - SYS_TOD_PROTECT(); -} diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h deleted file mode 100644 index dd97569303..0000000000 --- a/board/bmw/bmw.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * BMW/MPC8245 Board definitions. - * For more info, see http://www.vooha.com/ - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * James Dougherty (jfd@broadcom.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __BMW_H -#define __BMW_H - -/* System addresses */ - -#define PCI_SPECIAL_BASE 0xfe000000 -#define PCI_SPECIAL_SIZE 0x01000000 - -#define EUMBBAR_VAL 0x80500000 /* Location of EUMB region */ -#define EUMBSIZE 0x00100000 /* Size of EUMB region */ - -/* Extended ROM space devices */ -#define DOC_BASE_ADDR 0xff000000 /* Onboard DOC TSOP 16MB */ -#define DOC2_BASE_ADDR 0x70000000 /* DIP32 socket -> 1GB */ -#define XROM_BASE_ADDR 0x7c000000 /* RCS2 (PAL / Satellite IO) */ -#define PLD_REG_BASE XROM_BASE_ADDR -#define LED_REG_BASE (XROM_BASE_ADDR | 0x2000) -#define TOD_BASE (XROM_BASE_ADDR | 0x4000) -#define LED_REG(x) (*(volatile unsigned char *) \ - (LED_REG_BASE + (x))) -#define XROM_DEV_SIZE 0x00006000 - -#define ENET_DEV_BASE 0x80000000 - -#define PLD_REG(off) (*(volatile unsigned char *)\ - (PLD_REG_BASE + (off))) - -#define PLD_REVID_B1 0x7f /* Fix me */ -#define PLD_REVID_B2 0x01 /* Fix me */ - -#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ -#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) -#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) -#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) -#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) -#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) -#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) -#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) - -#define TOD_REG_BASE (TOD_BASE | 0x1ff0) -#define TOD_NVRAM_BASE TOD_BASE -#define TOD_NVRAM_SIZE 0x1ff0 -#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) -#define RTC(r) (TOD_BASE + r) - -/* Onboard BCM570x device */ -#define PCI_ENET_IOADDR 0x80000000 -#define PCI_ENET_MEMADDR 0x80000000 - - -#ifndef __ASSEMBLY__ -/* C Function prototypes */ -void sys_led_msg(char* msg); - -#endif /* !__ASSEMBLY__ */ - -#endif /* __BMW_H */ diff --git a/board/bmw/config.mk b/board/bmw/config.mk deleted file mode 100644 index a1a44e5811..0000000000 --- a/board/bmw/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# BMW board -# - -# NOTE: The flags below affect how the BCM570x driver is compiled -PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\ - -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256 diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S deleted file mode 100644 index 63c29d500f..0000000000 --- a/board/bmw/early_init.S +++ /dev/null @@ -1,1170 +0,0 @@ -#include -#include -#include -#include -#include - -#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */ - - -/* - * Initialize the MMU using BAT entries and hardwired TLB - * This obviates the need for any code in cpu_init_f which - * configures the BAT registers. -*/ -#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */ - .global iommu_setup - /* Initialize IO/MMU mappings via BAT method Ch. 7, - * PPC Programming Reference - */ -iommu_setup: - -/* initialize the BAT registers (SPRs 528 - 543 */ -#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */ -#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */ -#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */ -#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */ -#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */ -#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */ -#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */ -#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */ -#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */ -#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */ -#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */ -#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */ -#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */ -#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */ -#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */ -#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */ - - -/* PowerPC processors do not necessarily initialize the BAT - registers on power-up or reset. So they are in an unknown - state. Before programming the BATs for the first time, all - BAT registers MUST have their Vs and Vp bits cleared in the - upper BAT half in order to avoid possibly having 2 BATs - valid and mapping the same memory region. - - The reason for this is that, even with address translation - disabled, multiple BAT hits for an address are treated as - programming errors and can cause unpredictable results. - - It is up to the software to make sure it never has 2 IBAT - mappings or 2 DBAT mappings that are valid for the same - addresses. It is not necessary to perform this code - sequence every time the BATs are programmed, only when - there is a possibility that there may be overlapping BAT - entries. - - When programming the BATs in non-reset scenarios, even if - you are sure that your new mapping will not temporarily - create overlapping regions, it is still a wise idea to - invalidate a BAT entry by setting its upper BAT register to - all 0's before programming it. This will avoid having a - BAT marked valid that is in an unknown or transient state -*/ - - addis r5,0,0x0000 - mtibat0u(r5) - mtibat0l(r5) - mtibat1u(r5) - mtibat1l(r5) - mtibat2u(r5) - mtibat2l(r5) - mtibat3u(r5) - mtibat3l(r5) - mtdbat0u(r5) - mtdbat0l(r5) - mtdbat1u(r5) - mtdbat1l(r5) - mtdbat2u(r5) - mtdbat2l(r5) - mtdbat3u(r5) - mtdbat3l(r5) - isync - -/* - * Set up I/D BAT0 - */ - lis r4, CONFIG_SYS_DBAT0L@h - ori r4, r4, CONFIG_SYS_DBAT0L@l - lis r3, CONFIG_SYS_DBAT0U@h - ori r3, r3, CONFIG_SYS_DBAT0U@l - - mtdbat0l(r4) - isync - mtdbat0u(r3) - isync - sync - - lis r4, CONFIG_SYS_IBAT0L@h - ori r4, r4, CONFIG_SYS_IBAT0L@l - lis r3, CONFIG_SYS_IBAT0U@h - ori r3, r3, CONFIG_SYS_IBAT0U@l - - isync - mtibat0l(r4) - isync - mtibat0u(r3) - isync - -/* - * Set up I/D BAT1 - */ - lis r4, CONFIG_SYS_IBAT1L@h - ori r4, r4, CONFIG_SYS_IBAT1L@l - lis r3, CONFIG_SYS_IBAT1U@h - ori r3, r3, CONFIG_SYS_IBAT1U@l - - isync - mtibat1l(r4) - isync - mtibat1u(r3) - isync - mtdbat1l(r4) - isync - mtdbat1u(r3) - isync - sync - -/* - * Set up I/D BAT2 - */ - lis r4, CONFIG_SYS_IBAT2L@h - ori r4, r4, CONFIG_SYS_IBAT2L@l - lis r3, CONFIG_SYS_IBAT2U@h - ori r3, r3, CONFIG_SYS_IBAT2U@l - - isync - mtibat2l(r4) - isync - mtibat2u(r3) - isync - mtdbat2l(r4) - isync - mtdbat2u(r3) - isync - sync - -/* - * Setup I/D BAT3 - */ - lis r4, CONFIG_SYS_IBAT3L@h - ori r4, r4, CONFIG_SYS_IBAT3L@l - lis r3, CONFIG_SYS_IBAT3U@h - ori r3, r3, CONFIG_SYS_IBAT3U@l - - isync - mtibat3l(r4) - isync - mtibat3u(r3) - isync - mtdbat3l(r4) - isync - mtdbat3u(r3) - isync - sync - - -/* - * Invalidate all 64 TLB's - */ - lis r3, 0 - mtctr r3 - lis r5, 4 - -tlblp: - tlbie r3 - sync - addi r3, r3, 0x1000 - cmplw r3, r5 - blt tlblp - - sync - -/* - * Enable Data Translation - */ - lis r4, MEMORY_MGMT_MSR_BITS@h - ori r4, r4, MEMORY_MGMT_MSR_BITS@l - mfmsr r3 - or r3, r4, r3 - mtmsr r3 - isync - sync - - blr - - -#ifdef USE_V2_INIT -/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */ -/* Macro for hiadjust and lo */ -#define HIADJ(arg) arg@ha -#define HI(arg) arg@h -#define LO(arg) arg@l - -#undef LOADPTR -#define LOADPTR(reg,const32) \ - addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32) - -.globl early_init_f - -early_init_f: -/* MPC8245/BMW CPCI System Init - * Jimmy Blair, Broadcom Corp, 2002. - */ - mflr r11 - /* Zero-out registers */ - - addis r0,r0,0 - mtspr SPRG0,r0 - mtspr SPRG1,r0 - mtspr SPRG2,r0 - mtspr SPRG3,r0 - - /* Set MPU/MSR to a known state. Turn on FP */ - - LOADPTR (r3, MSR_FP) - sync - mtmsr r3 - isync - - /* Init the floating point control/status register */ - - mtfsfi 7,0x0 - mtfsfi 6,0x0 - mtfsfi 5,0x0 - mtfsfi 4,0x0 - mtfsfi 3,0x0 - mtfsfi 2,0x0 - mtfsfi 1,0x0 - mtfsfi 0,0x0 - isync - - /* Set MPU/MSR to a known state. Turn off FP */ - -#if 1 /* Turn off floating point (remove to keep FP on) */ - andi. r3, r3, 0 - sync - mtmsr r3 - isync -#endif - - /* Init the Segment registers */ - - andi. r3, r3, 0 - isync - mtsr 0,r3 - isync - mtsr 1,r3 - isync - mtsr 2,r3 - isync - mtsr 3,r3 - isync - mtsr 4,r3 - isync - mtsr 5,r3 - isync - mtsr 6,r3 - isync - mtsr 7,r3 - isync - mtsr 8,r3 - isync - mtsr 9,r3 - isync - mtsr 10,r3 - isync - mtsr 11,r3 - isync - mtsr 12,r3 - isync - mtsr 13,r3 - isync - mtsr 14,r3 - isync - mtsr 15,r3 - isync - - /* Turn off data and instruction cache control bits */ - - mfspr r3, HID0 - isync - rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */ - sync - isync - mtspr HID0, r4 /* HID0 = r4 */ - isync - - /* Get cpu type */ - - mfspr r28, PVR - rlwinm r28, r28, 16, 16, 31 - - /* invalidate the MPU's data/instruction caches */ - - lis r3, 0x0 - cmpli 0, 0, r28, CPU_TYPE_603 - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_603E - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_603P - beq cpuIs603 - cmpli 0, 0, r28, CPU_TYPE_604R - bne cpuNot604R - -cpuIs604R: - lis r3, 0x0 - mtspr HID0, r3 /* disable the caches */ - isync - ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */ - -cpuNot604R: - ori r3, r3, (HID0_ICFI |HID0_DCI) - -cpuIs603: - ori r3, r3, (HID0_ICE | HID0_DCE) - or r4, r4, r3 /* set bits */ - sync - isync - mtspr HID0, r4 /* HID0 = r4 */ - andc r4, r4, r3 /* clear bits */ - isync - cmpli 0, 0, r28, CPU_TYPE_604 - beq cpuIs604 - cmpli 0, 0, r28, CPU_TYPE_604E - beq cpuIs604 - cmpli 0, 0, r28, CPU_TYPE_604R - beq cpuIs604 - mtspr HID0, r4 - isync - -#ifdef USER_I_CACHE_ENABLE - b instCacheOn603 -#else - b cacheEnableDone -#endif - -cpuIs604: - LOADPTR (r5, 0x1000) /* loop count, 0x1000 */ - mtspr CTR, r5 -loopDelay: - nop - bdnz loopDelay - isync - mtspr HID0, r4 - isync - - /* turn the Instruction cache ON for faster FLASH ROM boots */ - -#ifdef USER_I_CACHE_ENABLE - - ori r4, r4, (HID0_ICE | HID0_ICFI) - isync /* Synchronize for ICE enable */ - b writeReg4 -instCacheOn603: - ori r4, r4, (HID0_ICE | HID0_ICFI) - rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */ - - /* - * The setting of the instruction cache enable (ICE) bit must be - * preceded by an isync instruction to prevent the cache from being - * enabled or disabled while an instruction access is in progress. - */ - isync -writeReg4: - mtspr HID0, r4 /* Enable Instr Cache & Inval cache */ - cmpli 0, 0, r28, CPU_TYPE_604 - beq cacheEnableDone - cmpli 0, 0, r28, CPU_TYPE_604E - beq cacheEnableDone - - mtspr HID0, r3 /* using 2 consec instructions */ - /* PPC603 recommendation */ -#endif -cacheEnableDone: - - /* Detect map A or B */ - - addis r5,r0, HI(CHRP_REG_ADDR) - addis r6,r0, HI(CHRP_REG_DATA) - LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */ - LOADPTR (r8, BMC_BASE) - - stwbrx r8,0,(r5) - lwbrx r3,0,(r6) /* Store read value to r3 */ - cmp 0,0,r3,r7 - beq cr0, X4_KAHLUA_START - - /* It's not an 8240, is it an 8245? */ - - LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */ - cmp 0,0,r3,r7 - beq cr0, X4_KAHLUA_START - - /* Save the PCI controller type in r7 */ - mr r7, r3 - - LOADPTR (r5, PREP_REG_ADDR) - LOADPTR (r6, PREP_REG_DATA) - -X4_KAHLUA_START: - /* MPC8245 changes begin here */ - LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */ - stwbrx r3,0,r5 - li r4, 6 /* Command register value */ - sthbrx r4, 0, r6 - - LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */ - stwbrx r3,0,r5 - li r4, -1 /* Write-to-clear all bits */ - li r3, 2 /* PCI_STATUS is at +2 offset */ - sthbrx r4, r3, r6 - - /*-------PROC_INT1_ADR */ - - LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xff141b98) - stwbrx r4,0,r6 - - /*-------PROC_INT2_ADR */ - - LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */ - stwbrx r3,0,r5 - lis r4, 0x2000 /* Flush PCI config writes */ - stwbrx r4,0,r6 - - LOADPTR (r9, KAHLUA2_ID) - cmpl 0, 0, r7, r9 - bne L1not8245 - - /* MIOCR1 -- turn on bit for DLL delay */ - - LOADPTR (r3, MIOCR1_ADR_X) - stwbrx r3,0,r5 - li r4, 0x04 - stb r4, MIOCR1_SHIFT(r6) - - /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ - /* SDRAM_CLK_DEL (0x77)*/ - - LOADPTR (r3, MIOCR2_ADR_X) - stwbrx r3,0,r5 - li r4, 0x10 - stb r4, MIOCR2_SHIFT(r6) - - /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */ - - LOADPTR (r3, PMCR2_ADR_X) - stwbrx r3,0,r5 - li r4, 0x20 - stb r4, PMCR2_SHIFT(r6) - - /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */ - - LOADPTR (r3, EUMBBAR) - stwbrx r3,0,r5 - LOADPTR (r4, CONFIG_SYS_EUMB_ADDR) - stwbrx r4,0,r6 - -L1not8245: - - /* Toggle the DLL reset bit in AMBOR */ - - LOADPTR (r3, AMBOR) - stwbrx r3,0,r5 - lbz r4, 0(r6) - - andi. r4, r4, 0xdf - stb r4, 0(r6) /* Clear DLL_RESET */ - sync - - ori r4, r4, 0x20 /* Set DLL_RESET */ - stb r4, 0(r6) - sync - - andi. r4, r4, 0xdf - stb r4, 0(r6) /* Clear DLL_RESET */ - - - /* Enable RCS2, use supplied timings */ - LOADPTR (r3, ERCR1) - stwbrx r3,0,r5 - LOADPTR (r4, 0x80408000) - stwbrx r4,0,r6 - - /* Disable RCS3 parameters */ - LOADPTR (r3, ERCR2) - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - /* RCS3 at 0x70000000, 64KBytes */ - LOADPTR (r3, ERCR2) - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000004) - stwbrx r4,0,r6 - - /*-------MCCR1 */ - -#ifdef INCLUDE_ECC -#define MC_ECC 1 -#else /* INCLUDE_ECC */ -#define MC_ECC 0 -#endif /* INCLUDE_ECC */ - -#define MC1_ROMNAL 8 /* 0-15 */ -#define MC1_ROMFAL 11 /* 0-31 */ -#define MC1_DBUS_SIZE 0 /* 0-3, read only */ -#define MC1_BURST 0 /* 0-1 */ -#define MC1_MEMGO 0 /* 0-1 */ -#define MC1_SREN 1 /* 0-1 */ -#define MC1_RAM_TYPE 0 /* 0-1 */ -#define MC1_PCKEN MC_ECC /* 0-1 */ -#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */ - - LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \ - MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \ - MC1_MEMGO << 19 | MC1_SREN << 18 | \ - MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 ) - li r3, MC1_BANKBITS - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne BankBitsAdd - cmpli 0, 0, r3, 0x5555 - beq K2BankBitsHack /* On 8245, 5555 ==> 0 */ -BankBitsAdd: - ori r4, r3, 0 -K2BankBitsHack: - stwbrx r4, 0, r6 - - /*------- MCCR2 */ - -#define MC2_TS_WAIT_TIMER 0 /* 0-7 */ -#define MC2_ASRISE 8 /* 0-15 */ -#define MC2_ASFALL 4 /* 0-15 */ -#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */ -#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */ -#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */ -#define MC2_ECC_EN 0 /* 0-1 */ -#define MC2_EDO 0 /* 0-1 */ -/* -* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM. -* May need to be decreased for 100 MHz -*/ -#define MC2_REFINT 0x3a5 /* 0-0x3fff */ -#define MC2_RSV_PG 0 /* 0-1 */ -#define MC2_RMW_PAR MC_ECC /* 0-1 */ - - LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \ - MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \ - MC2_WRITE_PARITY_CHK_EN << 19 | \ - MC2_INLRD_PARECC_CHK_EN << 18 | \ - MC2_ECC_EN << 17 | MC2_EDO << 16 | \ - MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR) - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne notK2 - /* clear Kahlua2 reserved bits */ - LOADPTR (r3, 0xfffcffff) - and r4, r4, r3 -notK2: - stwbrx r4,0,r6 - - /*------- MCCR3 */ - -#define MC_BSTOPRE 0x079 /* 0-0x7ff */ - -#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf) -#define MC3_REFREC 8 /* 0-15 */ -#define MC3_RDLAT (4+MC_ECC) /* 0-15 */ -#define MC3_CPX 0 /* 0-1 */ -#define MC3_RAS6P 0 /* 0-15 */ -#define MC3_CAS5 0 /* 0-7 */ -#define MC3_CP4 0 /* 0-7 */ -#define MC3_CAS3 0 /* 0-7 */ -#define MC3_RCD2 0 /* 0-7 */ -#define MC3_RP1 0 /* 0-7 */ - - LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \ - MC3_RDLAT << 20 | MC3_CPX << 19 | \ - MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \ - MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1) - cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ - bne notK2b - /* clear Kahlua2 reserved bits */ - LOADPTR (r3, 0xff000000) - and r4, r4, r3 -notK2b: - stwbrx r4,0,r6 - - /*------- MCCR4 */ - -#define MC4_PRETOACT 3 /* 0-15 */ -#define MC4_ACTOPRE 5 /* 0-15 */ -#define MC4_WMODE 0 /* 0-1 */ -#define MC4_INLINE MC_ECC /* 0-1 */ -#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */ -#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3) -#define MC4_REGDIMM 0 /* 0-1 */ -#define MC4_SDMODE_CAS 2 /* 0-7 */ -#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */ -#define MC4_SDMODE_WRAP 0 /* 0-1 */ -#define MC4_SDMODE_BURST 2 /* 0-7 */ -#define MC4_ACTORW 3 /* 0-15 */ -#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf) - - LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */ - stwbrx r3,0,r5 - LOADPTR(r4, \ - MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \ - MC4_WMODE << 23 | MC4_INLINE << 22 | \ - MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \ - MC4_DBUS_RCS1 << 17 | \ - MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \ - MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \ - MC4_ACTORW << 4 | MC4_BSTOPRE_L) - cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */ - bne notK2c - /* Turn on Kahlua2 extended ROM space */ - LOADPTR (r3, 0x00200000) - or r4, r4, r3 -notK2c: - stwbrx r4,0,r6 - -#ifdef INCLUDE_ECC - /*------- MEM_ERREN1 */ - - LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */ - stwbrx r3,0,r5 - lwbrx r4,0,r6 - ori r4,r4,4 /* Set MEM_PERR_EN */ - stwbrx r4,0,r6 -#endif /* INCLUDE_ECC */ - - /*------- MSAR/MEAR */ - - LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xc0804000) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xc0804000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x01010101) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xffbf7f3f) - stwbrx r4,0,r6 - - LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0xffbf7f3f) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x00000000) - stwbrx r4,0,r6 - - LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */ - stwbrx r3,0,r5 - LOADPTR (r4, 0x01010101) - stwbrx r4,0,r6 - - /*-------ODCR */ - - LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */ - stwbrx r3,0,r5 - - li r4, 0x7f - stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */ - - /*-------MBEN */ - - LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */ - stwbrx r3,0,r5 - li r4, 0x01 /* Enable bank 0 */ - stb r4, 0(r6) /* MBEN is at +0 offset */ - -#if 0 /* Jimmy: I think page made is broken */ - /*-------PGMAX */ - - LOADPTR (r3, MPM_ADR_X) - stwbrx r3,0,r5 - li r4, 0x32 - stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */ -#endif - - /* Wait before initializing other registers */ - - lis r4,0x0001 - mtctr r4 - -KahluaX4wait200us: - bdnz KahluaX4wait200us - - /* Set MEMGO bit */ - - LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */ - stwbrx r3,0,r5 - lwbrx r4,0,r6 /* old MCCR1 */ - oris r4,r4,0x0008 /* MEMGO=1 */ - stwbrx r4, 0, r6 - - /* Wait again */ - - addis r4,r0,0x0002 - ori r4,r4,0xffff - - mtctr r4 - -KahluaX4wait8ref: - bdnz KahluaX4wait8ref - - sync - eieio - mtlr r11 - blr - -#else /* USE_V2_INIT */ - - -/* U-Boot works, but memory will not run reliably for all address ranges. - * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not - * initialized correctly. Could work if debugged. - */ -/* PCI Support routines */ - - .globl __pci_config_read_32 -__pci_config_read_32: - lis r4, 0xfec0 - stwbrx r3, r0, r4 - sync - lis r4, 0xfee0 - lwbrx r3, 0, r4 - blr - .globl __pci_config_read_16 -__pci_config_read_16: - lis r4, 0xfec0 - andi. r5, r3, 2 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lhbrx r3, r0, r4 - blr - .globl __pci_config_read_8 -__pci_config_read_8: - lis r4, 0xfec0 - andi. r5, r3, 3 - stwbrx r3, r0, r4 - sync - oris r4, r5, 0xfee0 - lbz r3, 0(4) - blr - .globl __pci_config_write_32 -__pci_config_write_32: - lis r5, 0xfec0 - stwbrx r3, r0, r5 - sync - lis r5, 0xfee0 - stwbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_16 -__pci_config_write_16: - lis r5, 0xfec0 - andi. r6, r3, 2 - stwbrx r3, r0, 5 - sync - oris r5, r6, 0xfee0 - sthbrx r4, r0, r5 - sync - blr - .globl __pci_config_write_8 -__pci_config_write_8: - lis r5, 0xfec0 - andi. r6, r3, 3 - stwbrx r3, r0, r5 - sync - oris r5, r6, 0xfee0 - stb r4, 0(r5) - sync - blr - .globl in_8 -in_8: - oris r3, r3, 0xfe00 - lbz r3,0(r3) - blr - .globl in_16 -in_16: - oris r3, r3, 0xfe00 - lhbrx r3, 0, r3 - blr - .globl in_16_ne -in_16_ne: - oris r3, r3, 0xfe00 - lhzx r3, 0, r3 - blr - .globl in_32 -in_32: - oris r3, r3, 0xfe00 - lwbrx r3, 0, r3 - blr - .globl out_8 -out_8: - oris r3, r3, 0xfe00 - stb r4, 0(r3) - eieio - blr - .globl out_16 -out_16: - oris r3, r3, 0xfe00 - sthbrx r4, 0, r3 - eieio - blr - .globl out_16_ne -out_16_ne: - oris r3, r3, 0xfe00 - sth r4, 0(r3) - eieio - blr - .globl out_32 -out_32: - oris r3, r3, 0xfe00 - stwbrx r4, 0, r3 - eieio - blr - .globl read_8 -read_8: - lbz r3,0(r3) - blr - .globl read_16 -read_16: - lhbrx r3, 0, r3 - blr - .globl read_32 -read_32: - lwbrx r3, 0, r3 - blr - .globl read_32_ne -read_32_ne: - lwz r3, 0(r3) - blr - .globl write_8 -write_8: - stb r4, 0(r3) - eieio - blr - .globl write_16 -write_16: - sthbrx r4, 0, r3 - eieio - blr - .globl write_32 -write_32: - stwbrx r4, 0, r3 - eieio - blr - .globl write_32_ne -write_32_ne: - stw r4, 0(r3) - eieio - blr - - -.globl early_init_f - -early_init_f: - mflr r11 - lis r10, 0x8000 - - /* PCI Latency Timer */ - li r4, 0x0d - ori r3, r10, PLTR@l - bl __pci_config_write_8 - - /* Cache Line Size */ - li r4, 0x08 - ori r3, r10, PCLSR@l - bl __pci_config_write_8 - - /* PCI Cmd */ - li r4, 6 - ori r3, r10, PCICR@l - bl __pci_config_write_16 - -#if 1 - /* PCI Stat */ - ori r3, r10, PCISR@l - bl __pci_config_read_16 - ori r4, r4, 0xffff - ori r3, r10, PCISR@l - bl __pci_config_write_16 -#endif - - /* PICR1 */ - lis r4, 0xff14 - ori r4, r4, 0x1b98 - ori r3, r10, PICR1@l - bl __pci_config_write_32 - - - /* PICR2 */ - lis r4, 0x0404 - ori r4, r4, 0x0004 - ori r3, r10, PICR2@l - bl __pci_config_write_32 - - /* MIOCR1 */ - li r4, 0x04 - ori r3, r10, MIOCR1@l - bl __pci_config_write_8 - - /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ - /* SDRAM_CLK_DEL (0x77)*/ - li r4, 0x10 - ori r3, r10, MIOCR2@l - bl __pci_config_write_8 - - /* EUMBBAR */ - lis r4, 0xfc00 - ori r3, r10, EUMBBAR@l - bl __pci_config_write_32 - - /* AMBOR */ - - /* Even if Address Map B is not being used (though it should), - * the memory DLL needs to be cleared/set/cleared before using memory. - */ - - ori r3, r10, AMBOR@l - bl __pci_config_read_8 /* get Current bits */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - ori r4, r4, 0x0020 - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Set DLL_RESET */ - - andi. r4, r4, 0xffdf - ori r3, r10, AMBOR@l - bl __pci_config_write_16 /* Clear DLL_RESET */ - - /* ERCR1 */ - lis r4, 0x8040 /* Enable RCS2, use supplied timings */ - ori r4, r4, 0x8000 - ori r3, r10, ERCR1@l - bl __pci_config_write_32 - - /* ERCR2 */ - lis r4, 0x0000 /* Disable RCS3 parms */ - ori r4, r4, 0x0000 - ori r3, r10, ERCR2@l - bl __pci_config_write_32 - - /* ERCR3 */ - lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */ - ori r4, r4, 0x0004 - ori r3, r10, ERCR2@l - bl __pci_config_write_32 - - /* Preserve memgo bit */ - /* MCCR1 */ - -/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */ - lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */ -/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */ -/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */ -/* oris r4, r4, 0x0004 / Self-refresh enable */ - -/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */ -/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */ -/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */ - ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */ - - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* MCCR2 */ - - lis r4,0x0000 -/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */ - oris r4,r4,0x1000 /* ASRISE = 8 clocks */ - oris r4,r4,0x0080 /* ASFALL = 8 clocks */ -/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */ -/* oris r4,r4,0x0008 / Write parity check */ -/* oris r4,r4,0x0004 / SDRAM inline reads */ - - -/* Select a refresh rate; it needs to match the bus speed; if too */ -/* slow, data may be lost; if too fast, performance is lost. We */ -/* use the fastest value so we run at all speeds. */ -/* Refresh = (15600ns/busclk) - (213 (see UM)). */ - -/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */ -/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */ -/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */ -/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */ - ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */ -/* ori r4,r4,0x0002 / Reserve a page */ -/* ori r4,r4,0x0001 / RWM parity */ - - ori r3, r10, MCCR2@l - bl __pci_config_write_32 - - - /* MCCR3 */ - lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */ - oris r4,r4,0x0500 /* REFREC = 8 clocks */ - ori r3, r10, MCCR3@l - bl __pci_config_write_32 - - /* MCCR4 */ /* Turn on registered buffer mode */ - lis r4, 0x2000 /* PRETOACT = 3 clocks */ - oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */ -/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */ -/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */ - oris r4,r4,0x0020 /* EXTROM enabled */ - oris r4,r4,0x0010 /* Registered buffers */ -/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */ - oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */ - -/* ori r4,r4,0x8000 / Registered DIMMs */ - ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */ -/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */ -/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */ - ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */ - ori r4,r4,0x0030 /* ACTORW = 3 clocks */ - ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */ - - ori r3, r10, MCCR4@l - bl __pci_config_write_32 - - /* MSAR1 */ - lis r4, 0xc0804000@h - ori r4, r4, 0xc0804000@l - ori r3, r10, MSAR1@l - bl __pci_config_write_32 - - /* MSAR2 */ - lis r4, 0xc0804000@h - ori r4, r4, 0xc0804000@l - ori r3, r10, MSAR2@l - bl __pci_config_write_32 - - /* MESAR1 */ - lis r4, 0x00000000@h - ori r4, r4, 0x00000000@l - ori r3, r10, EMSAR1@l - bl __pci_config_write_32 - - /* MESAR2 */ - lis r4, 0x01010101@h - ori r4, r4, 0x01010101@l - ori r3, r10, EMSAR2@l - bl __pci_config_write_32 - - /* MEAR1 */ - lis r4, 0xffbf7f3f@h - ori r4, r4, 0xffbf7f3f@l - ori r3, r10, MEAR1@l - bl __pci_config_write_32 - - /* MEAR2 */ - lis r4, 0xffbf7f3f@h - ori r4, r4, 0xffbf7f3f@l - ori r3, r10, MEAR2@l - bl __pci_config_write_32 - - /* MEEAR1 */ - lis r4, 0x00000000@h - ori r4, r4, 0x00000000@l - ori r3, r10, EMEAR1@l - bl __pci_config_write_32 - - /* MEEAR2 */ - lis r4, 0x01010101@h - ori r4, r4, 0x01010101@l - ori r3, r10, EMEAR2@l - bl __pci_config_write_32 - - /* ODCR */ - li r4, 0x7f - ori r3, r10, ODCR@l - bl __pci_config_write_8 - - /* MBER */ - li r4, 0x01 - ori r3, r10, MBER@l - bl __pci_config_write_8 - - /* Page CTR aka PGMAX */ - li r4, 0x32 - ori r3, r10, 0x70 - bl __pci_config_write_8 - -#if 0 - /* CLK Drive */ - ori r4, r10, 0xfc01 /* Top bit will be ignored */ - ori r3, r10, 0x74 - bl __pci_config_write_16 -#endif - - /* delay */ - lis r7, 1 - mtctr r7 -label1: bdnz label1 - - /* Set memgo bit */ - /* MCCR1 */ - ori r3, r10, MCCR1@l - bl __pci_config_read_32 - lis r7, 0x0008 - or r4, r3, r7 - ori r3, r10, MCCR1@l - bl __pci_config_write_32 - - /* delay again */ - lis r7, 1 - mtctr r7 -label2: bdnz label2 -#if 0 -/* DEBUG: Infinite loop, write then read */ -loop: - lis r7, 0xffff - mtctr r7 - li r3, 0x5004 - lis r4, 0xa0a0 - ori r4, r4, 0x5050 - bl write_32_ne - li r3, 0x5004 - bl read_32_ne - bdnz loop -#endif - mtlr r11 - blr -#endif diff --git a/board/bmw/flash.c b/board/bmw/flash.c deleted file mode 100644 index 57ffe0890f..0000000000 --- a/board/bmw/flash.c +++ /dev/null @@ -1,779 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define ROM_CS0_START 0xFF800000 -#define ROM_CS1_START 0xFF000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t * info, ulong dest, ulong data); - -#if 0 -static void flash_get_offsets (ulong base, flash_info_t * info); -#endif /* 0 */ - -/*flash command address offsets*/ - -#if 0 -#define ADDR0 (0x555) -#define ADDR1 (0x2AA) -#define ADDR3 (0x001) -#else -#define ADDR0 (0xAAA) -#define ADDR1 (0x555) -#define ADDR3 (0x001) -#endif - -#define FLASH_WORD_SIZE unsigned char - -/*----------------------------------------------------------------------- - */ - -#if 0 -static int byte_parity_odd (unsigned char x) __attribute__ ((const)); -#endif /* 0 */ -static unsigned long flash_id (unsigned char mfct, unsigned char chip) - __attribute__ ((const)); - -typedef struct { - FLASH_WORD_SIZE extval; - unsigned short intval; -} map_entry; - -#if 0 -static int byte_parity_odd (unsigned char x) -{ - x ^= x >> 4; - x ^= x >> 2; - x ^= x >> 1; - return (x & 0x1) != 0; -} -#endif /* 0 */ - - -static unsigned long flash_id (unsigned char mfct, unsigned char chip) -{ - static const map_entry mfct_map[] = { - {(FLASH_WORD_SIZE) AMD_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)}, - {(FLASH_WORD_SIZE) FUJ_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)}, - {(FLASH_WORD_SIZE) STM_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)}, - {(FLASH_WORD_SIZE) MT_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)}, - {(FLASH_WORD_SIZE) INTEL_MANUFACT, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}, - {(FLASH_WORD_SIZE) INTEL_ALT_MANU, - (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)} - }; - - static const map_entry chip_map[] = { - {AMD_ID_F040B, FLASH_AM040}, - {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB} - }; - - const map_entry *p; - unsigned long result = FLASH_UNKNOWN; - - /* find chip id */ - for (p = &chip_map[0]; - p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++) - if (p->extval == chip) { - result = FLASH_VENDMASK | p->intval; - break; - } - - /* find vendor id */ - for (p = &mfct_map[0]; - p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++) - if (p->extval == mfct) { - result &= ~FLASH_VENDMASK; - result |= (unsigned long) p->intval << 16; - break; - } - - return result; -} - - -unsigned long flash_init (void) -{ - unsigned long i; - unsigned char j; - static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - - pflinfo->flash_id = FLASH_UNKNOWN; - pflinfo->size = 0; - pflinfo->sector_count = 0; - } - - for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) { - flash_info_t *const pflinfo = &flash_info[i]; - const unsigned long base_address = flash_banks[i]; - volatile FLASH_WORD_SIZE *const flash = - (FLASH_WORD_SIZE *) base_address; -#if 0 - volatile FLASH_WORD_SIZE *addr2; -#endif -#if 0 - /* write autoselect sequence */ - flash[0x5555] = 0xaa; - flash[0x2aaa] = 0x55; - flash[0x5555] = 0x90; -#else - flash[0xAAA << (3 * i)] = 0xaa; - flash[0x555 << (3 * i)] = 0x55; - flash[0xAAA << (3 * i)] = 0x90; -#endif - __asm__ __volatile__ ("sync"); - -#if 0 - pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]); -#else - pflinfo->flash_id = - flash_id (flash[0x0], flash[0x2 + 14 * i]); -#endif - - switch (pflinfo->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - pflinfo->size = 0x00080000; - pflinfo->sector_count = 8; - for (j = 0; j < 8; j++) { - pflinfo->start[j] = - base_address + 0x00010000 * j; - pflinfo->protect[j] = flash[(j << 16) | 0x2]; - } - break; - case FLASH_STM800AB: - pflinfo->size = 0x00100000; - pflinfo->sector_count = 19; - pflinfo->start[0] = base_address; - pflinfo->start[1] = base_address + 0x4000; - pflinfo->start[2] = base_address + 0x6000; - pflinfo->start[3] = base_address + 0x8000; - for (j = 1; j < 16; j++) { - pflinfo->start[j + 3] = - base_address + 0x00010000 * j; - } -#if 0 - /* check for protected sectors */ - for (j = 0; j < pflinfo->sector_count; j++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE - *) (pflinfo->start[j]); - if (pflinfo->flash_id & FLASH_MAN_SST) - pflinfo->protect[j] = 0; - else - pflinfo->protect[j] = addr2[2] & 1; - } -#endif - break; - } - /* Protect monitor and environment sectors - */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - /* reset device to read mode */ - flash[0x0000] = 0xf0; - __asm__ __volatile__ ("sync"); - } - - return flash_info[0].size + flash_info[1].size; -} - -#if 0 -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if (info->flash_id != FLASH_UNKNOWN) { - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - mfct = "AMD"; - break; - case FLASH_MAN_FUJ: - mfct = "FUJITSU"; - break; - case FLASH_MAN_STM: - mfct = "STM"; - break; - case FLASH_MAN_SST: - mfct = "SST"; - break; - case FLASH_MAN_BM: - mfct = "Bright Microelectonics"; - break; - case FLASH_MAN_INTEL: - mfct = "Intel"; - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - type = "AM29F040B (512K * 8, uniform sector size)"; - break; - case FLASH_AM400B: - type = "AM29LV400B (4 Mbit, bottom boot sect)"; - break; - case FLASH_AM400T: - type = "AM29LV400T (4 Mbit, top boot sector)"; - break; - case FLASH_AM800B: - type = "AM29LV800B (8 Mbit, bottom boot sect)"; - break; - case FLASH_AM800T: - type = "AM29LV800T (8 Mbit, top boot sector)"; - break; - case FLASH_AM160T: - type = "AM29LV160T (16 Mbit, top boot sector)"; - break; - case FLASH_AM320B: - type = "AM29LV320B (32 Mbit, bottom boot sect)"; - break; - case FLASH_AM320T: - type = "AM29LV320T (32 Mbit, top boot sector)"; - break; - case FLASH_STM800AB: - type = "M29W800AB (8 Mbit, bottom boot sect)"; - break; - case FLASH_SST800A: - type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; - break; - case FLASH_SST160A: - type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; - break; - } - } - - printf ("\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, type, info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) { - unsigned long size; - unsigned int erased; - unsigned long *flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for (flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) - && erased; flash++) - erased = *flash == ~0x0UL; - - printf ("%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", info->protect[i] ? "RO" : " "); - } - - puts ("\n"); - return; -} - -#if 0 - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - printf ("flash_get_size: \n"); - /* Write auto select command: read Manufacturer ID */ - eieio (); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90; - value = addr2[0]; - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - printf ("recognised manufacturer"); - - value = addr2[ADDR3]; /* device ID */ - debug ("\ndev_code=%x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id, - info->sector_count, info->size); - /* set up sector start address table */ - if (info->flash_id & FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if (info->flash_id & FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - -#endif - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> - start - [sect] - - - info-> - start - [0]) << - sh8b)); - if (info->flash_id & FLASH_MAN_SST) { - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0 << sh8b] = - (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1 << sh8b] = - (FLASH_WORD_SIZE) 0x00550055; - addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - udelay (30000); /* wait 30 ms */ - } else - addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - - info-> - start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != - (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; - volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int flag; - int i; - unsigned char sh8b; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) - && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c deleted file mode 100644 index 4e83b9076e..0000000000 --- a/board/bmw/m48t59y.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and - * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) - * registers which are used to set/get the internal date/time functions. - * - * This module implements Y2K compliance by taking full year numbers - * and translating back and forth from the TOD 2-digit year. - * - * NOTE: for proper interaction with an operating system, the TOD should - * be used to store Universal Coordinated Time (GMT) and timezone - * conversions should be used. - * - * Here is a diagram of the memory layout: - * - * +---------------------------------------------+ 0xffe0a000 - * | Non-volatile memory | . - * | | . - * | (8176 bytes of Non-volatile memory) | . - * | | . - * +---------------------------------------------+ 0xffe0bff0 - * | Flags | - * +---------------------------------------------+ 0xffe0bff1 - * | Unused | - * +---------------------------------------------+ 0xffe0bff2 - * | Alarm Seconds | - * +---------------------------------------------+ 0xffe0bff3 - * | Alarm Minutes | - * +---------------------------------------------+ 0xffe0bff4 - * | Alarm Date | - * +---------------------------------------------+ 0xffe0bff5 - * | Interrupts | - * +---------------------------------------------+ 0xffe0bff6 - * | WatchDog | - * +---------------------------------------------+ 0xffe0bff7 - * | Calibration | - * +---------------------------------------------+ 0xffe0bff8 - * | Seconds | - * +---------------------------------------------+ 0xffe0bff9 - * | Minutes | - * +---------------------------------------------+ 0xffe0bffa - * | Hours | - * +---------------------------------------------+ 0xffe0bffb - * | Day | - * +---------------------------------------------+ 0xffe0bffc - * | Date | - * +---------------------------------------------+ 0xffe0bffd - * | Month | - * +---------------------------------------------+ 0xffe0bffe - * | Year (2 digits only) | - * +---------------------------------------------+ 0xffe0bfff - */ -#include -#include -#include "bmw.h" - -/* - * Imported from mousse.h: - * - * TOD_REG_BASE Base of m48t59y TOD registers - * SYS_TOD_UNPROTECT() Disable NVRAM write protect - * SYS_TOD_PROTECT() Re-enable NVRAM write protect - */ - -#define YEAR 0xf -#define MONTH 0xe -#define DAY 0xd -#define DAY_OF_WEEK 0xc -#define HOUR 0xb -#define MINUTE 0xa -#define SECOND 0x9 -#define CONTROL 0x8 -#define WATCH 0x7 -#define INTCTL 0x6 -#define WD_DATE 0x5 -#define WD_HOUR 0x4 -#define WD_MIN 0x3 -#define WD_SEC 0x2 -#define _UNUSED 0x1 -#define FLAGS 0x0 - -#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) - -int m48_tod_init(void) -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] = 0; - M48_ADDR[WATCH] = 0; - M48_ADDR[INTCTL] = 0; - - /* - * If the oscillator is currently stopped (as on a new part shipped - * from the factory), start it running. - * - * Here is an example of the TOD bytes on a brand new M48T59Y part: - * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 - */ - - if (M48_ADDR[SECOND] & 0x80) - M48_ADDR[SECOND] = 0; - - /* Is battery low */ - if ( M48_ADDR[FLAGS] & 0x10) { - printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); - } - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * m48_tod_set - */ - -static int to_bcd(int value) -{ - return value / 10 * 16 + value % 10; -} - -static int from_bcd(int value) -{ - return value / 16 * 10 + value % 16; -} - -static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ -{ - static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; - y -= m < 3; - return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_set(int year, /* 1980-2079 */ - int month, /* 01-12 */ - int day, /* 01-31 */ - int hour, /* 00-23 */ - int minute, /* 00-59 */ - int second) /* 00-59 */ - -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ - - M48_ADDR[YEAR] = to_bcd(year % 100); - M48_ADDR[MONTH] = to_bcd(month); - M48_ADDR[DAY] = to_bcd(day); - M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; - M48_ADDR[HOUR] = to_bcd(hour); - M48_ADDR[MINUTE] = to_bcd(minute); - M48_ADDR[SECOND] = to_bcd(second); - - M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_get(int *year, /* 1980-2079 */ - int *month, /* 01-12 */ - int *day, /* 01-31 */ - int *hour, /* 00-23 */ - int *minute, /* 00-59 */ - int *second) /* 00-59 */ -{ - int y; - - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ - - y = from_bcd(M48_ADDR[YEAR]); - *year = y < 80 ? 2000 + y : 1900 + y; - *month = from_bcd(M48_ADDR[MONTH]); - *day = from_bcd(M48_ADDR[DAY]); - /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ - *hour = from_bcd(M48_ADDR[HOUR]); - *minute = from_bcd(M48_ADDR[MINUTE]); - *second = from_bcd(M48_ADDR[SECOND] & 0x7f); - - M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -int m48_tod_get_second(void) -{ - return from_bcd(M48_ADDR[SECOND] & 0x7f); -} - -/* - * Watchdog function - * - * If usec is 0, the watchdog timer is disarmed. - * - * If usec is non-zero, the watchdog timer is armed (or re-armed) for - * approximately usec microseconds (if the exact requested usec is - * not supported by the chip, the next higher available value is used). - * - * Minimum watchdog timeout = 62500 usec - * Maximum watchdog timeout = 124 sec (124000000 usec) - */ - -void m48_watchdog_arm(int usec) -{ - int mpy, res; - - SYS_TOD_UNPROTECT(); - - if (usec == 0) { - res = 0; - mpy = 0; - } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ - res = 0; - mpy = (usec + 62499) / 62500; - } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ - res = 1; - mpy = (usec + 249999) / 250000; - } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ - res = 2; - mpy = (usec + 999999) / 1000000; - } else { /* Resolution: 4s up to 124s */ - res = 3; - mpy = (usec + 3999999) / 4000000; - if (mpy > 31) - mpy = 31; - } - - M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ - mpy << 2 | - res); - - SYS_TOD_PROTECT(); -} - -/* - * U-Boot RTC support. - */ -int -rtc_get( struct rtc_time *tmp ) -{ - m48_tod_get(&tmp->tm_year, - &tmp->tm_mon, - &tmp->tm_mday, - &tmp->tm_hour, - &tmp->tm_min, - &tmp->tm_sec); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - m48_tod_set(tmp->tm_year, /* 1980-2079 */ - tmp->tm_mon, /* 01-12 */ - tmp->tm_mday, /* 01-31 */ - tmp->tm_hour, /* 00-23 */ - tmp->tm_min, /* 00-59 */ - tmp->tm_sec); /* 00-59 */ - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -void -rtc_reset (void) -{ - m48_tod_init(); -} diff --git a/board/bmw/m48t59y.h b/board/bmw/m48t59y.h deleted file mode 100644 index 717300d957..0000000000 --- a/board/bmw/m48t59y.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __M48_T59_Y_H -#define __M48_T59_Y_H - -/* - * M48 T59Y -Timekeeping Battery backed SRAM. - */ - -int m48_tod_init(void); - -int m48_tod_set(int year, - int month, - int day, - int hour, - int minute, - int second); - -int m48_tod_get(int *year, - int *month, - int *day, - int *hour, - int *minute, - int *second); - -int m48_tod_get_second(void); - -void m48_watchdog_arm(int usec); - -#endif /*!__M48_T59_Y_H */ diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c deleted file mode 100644 index be455bbefe..0000000000 --- a/board/bmw/ns16550.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * COM1 NS16550 support - * originally from linux source (arch/powerpc/boot/ns16550.c) - * modified to use CONFIG_SYS_ISA_MEM and new defines - */ - -#include -#include "ns16550.h" - -typedef struct NS16550 *NS16550_t; - -const NS16550_t COM_PORTS[] = - { (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500), -(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) }; - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) -{ - volatile struct NS16550 *com_port; - - com_port = (struct NS16550 *) COM_PORTS[chan]; - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ - return (com_port); -} - -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; /* Access baud rate */ - com_port->dll = baud_divisor & 0xff; /* 9600 baud */ - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ - com_port->mcr = MCR_RTS; /* RTS/DTR */ - com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */ -} - -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) -{ - while ((com_port->lsr & LSR_THRE) == 0); - com_port->thr = c; -} - -unsigned char NS16550_getc (volatile struct NS16550 *com_port) -{ - while ((com_port->lsr & LSR_DR) == 0); - return (com_port->rbr); -} - -int NS16550_tstc (volatile struct NS16550 *com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h deleted file mode 100644 index 2087a4aabd..0000000000 --- a/board/bmw/ns16550.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * NS16550 Serial Port - * originally from linux source (arch/powerpc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CONFIG_SYS_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - * further modified to support the 8245 duart - * modifications (c) Paul Jimenez, Musenki, Inc. 2001. - */ - - -struct NS16550 { - unsigned char rbrthrdlb; /* 0 */ - unsigned char ierdmb; /* 1 */ - unsigned char iirfcrafr; /* 2 */ - unsigned char lcr; /* 3 */ - unsigned char mcr; /* 4 */ - unsigned char lsr; /* 5 */ - unsigned char msr; /* 6 */ - unsigned char scr; /* 7 */ - unsigned char reserved[2]; /* 8 & 9 */ - unsigned char dsr; /* 10 */ - unsigned char dcr; /* 11 */ -}; - - -#define rbr rbrthrdlb -#define thr rbrthrdlb -#define dll rbrthrdlb -#define ier ierdmb -#define dlm ierdmb -#define iir iirfcrafr -#define fcr iirfcrafr -#define afr iirfcrafr - -#define FCR_FIFO_EN 0x01 /*fifo enable */ -#define FCR_RXSR 0x02 /*receiver soft reset */ -#define FCR_TXSR 0x04 /*transmitter soft reset */ -#define FCR_DMS 0x08 /* DMA Mode Select */ - -#define MCR_RTS 0x02 /* Readyu to Send */ -#define MCR_LOOP 0x10 /* Local loopback mode enable */ -/* #define MCR_DTR 0x01 noton 8245 duart */ -/* #define MCR_DMA_EN 0x04 noton 8245 duart */ -/* #define MCR_TX_DFR 0x08 noton 8245 duart */ - -#define LCR_WLS_MSK 0x03 /* character length slect mask */ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble */ -#define LCR_EPS 0x10 /* Even Parity Select */ -#define LCR_STKP 0x20 /* Stick Parity */ -#define LCR_SBRK 0x40 /* Set Break */ -#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -/* useful defaults for LCR*/ -#define LCR_8N1 0x03 - - -volatile struct NS16550 *NS16550_init (int chan, int baud_divisor); -void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c); -unsigned char NS16550_getc (volatile struct NS16550 *com_port); -int NS16550_tstc (volatile struct NS16550 *com_port); -void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor); diff --git a/board/bmw/serial.c b/board/bmw/serial.c deleted file mode 100644 index 08f449c864..0000000000 --- a/board/bmw/serial.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#include "ns16550.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_CONS_INDEX == 1 -static struct NS16550 *console = - (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500); -#elif CONFIG_CONS_INDEX == 2 -static struct NS16550 *console = - (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500); -#else -#error no valid console defined -#endif - -extern ulong get_bus_freq (ulong); - -static int bmw_serial_init(void) -{ - int clock_divisor = gd->bus_clk / 16 / gd->baudrate; - - NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor); - - return (0); -} - -static void bmw_serial_putc(const char c) -{ - if (c == '\n') { - serial_putc ('\r'); - } - NS16550_putc (console, c); -} - -static void bmw_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - - -static int bmw_serial_getc(void) -{ - return NS16550_getc (console); -} - -static int bmw_serial_tstc(void) -{ - return NS16550_tstc (console); -} - -static void bmw_serial_setbrg(void) -{ - int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate; - - NS16550_reinit (console, clock_divisor); -} - -static struct serial_device bmw_serial_drv = { - .name = "bmw_serial", - .start = bmw_serial_init, - .stop = NULL, - .setbrg = bmw_serial_setbrg, - .putc = bmw_serial_putc, - .puts = bmw_serial_puts, - .getc = bmw_serial_getc, - .tstc = bmw_serial_tstc, -}; - -void bmw_serial_initialize(void) -{ - serial_register(&bmw_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &bmw_serial_drv; -} diff --git a/boards.cfg b/boards.cfg index 4b17289722..6c86d42067 100644 --- a/boards.cfg +++ b/boards.cfg @@ -544,7 +544,6 @@ Alaska8220 powerpc mpc8220 alaska sorcery powerpc mpc8220 Yukon8220 powerpc mpc8220 alaska A3000 powerpc mpc824x a3000 -BMW powerpc mpc824x bmw CPC45 powerpc mpc824x cpc45 - - CPC45 CPC45_ROMBOOT powerpc mpc824x cpc45 - - CPC45:BOOT_ROM CU824 powerpc mpc824x cu824 diff --git a/include/configs/BMW.h b/include/configs/BMW.h deleted file mode 100644 index 633e9bd69f..0000000000 --- a/include/configs/BMW.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the CU824 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8245 1 -#define CONFIG_BMW 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */ -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */ -#define DOC_PASSIVE_PROBE 1 -#define CONFIG_SYS_DOC_SUPPORT_2000 1 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1 -#define CONFIG_SYS_DOC_SHORT_TIMEOUT 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - - -#if 0 -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */ -#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM } - -/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the - * reset vector is actually located at FFB00100, but the 8245 - * takes care of us. - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_EUMB_ADDR 0xFC000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ - - /* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */ - - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE -#undef CONFIG_SYS_RAMBOOT -#else -#define CONFIG_SYS_RAMBOOT -#endif - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the MPC8240 user's manual. - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_ETH_DEV_FN 0x7800 -#define CONFIG_SYS_ETH_IOBASE 0x00104000 - - /* Bit-field values for MCCR1. - */ -#define CONFIG_SYS_ROMNAL 0xf -#define CONFIG_SYS_ROMFAL 0x1f -#define CONFIG_SYS_DBUS_SIZE 0x3 - - /* Bit-field values for MCCR2. - */ -#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ -#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ - - /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. - */ -#define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */ - - /* Bit-field values for MCCR3. - */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ - - /* Bit-field values for MCCR4. - */ -#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */ -#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ -#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */ -#define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -#define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ - -#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ - -/* Memory bank settings. - * Only bits 20-29 are actually used from these vales to set the - * start/end addresses. The upper two bits will always be 0, and the lower - * 20 bits will be 0x00000 for a start address, or 0xfffff for an end - * address. Refer to the MPC8240 book. - */ - -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x3ff00000 -#define CONFIG_SYS_BANK1_END 0x3fffffff -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x3ff00000 -#define CONFIG_SYS_BANK2_END 0x3fffffff -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x3ff00000 -#define CONFIG_SYS_BANK3_END 0x3fffffff -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x3ff00000 -#define CONFIG_SYS_BANK4_END 0x3fffffff -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x3ff00000 -#define CONFIG_SYS_BANK5_END 0x3fffffff -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x3ff00000 -#define CONFIG_SYS_BANK6_END 0x3fffffff -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x3ff00000 -#define CONFIG_SYS_BANK7_END 0x3fffffff -#define CONFIG_SYS_BANK7_ENABLE 0 - -#define CONFIG_SYS_ODCR 0xff - -#define CONFIG_PCI 1 /* Include PCI support */ -#undef CONFIG_PCI_PNP - -/* PCI Memory space(s) */ -#define PCI_MEM_SPACE1_START 0x80000000 -#define PCI_MEM_SPACE2_START 0xfd000000 - -/* ROM Spaces */ -#include "../board/bmw/bmw.h" - -/* BAT configuration */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* - * Warining: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_NVRAM 1 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1 -#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */ -#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */ -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From bfb7d7a3d61ff23f9dd265a56e8b5cac5bbfd76e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Oct 2012 14:07:01 +0000 Subject: serial: Implement default_serial_puts() U-Boot contains a lot of duplicit implementations of serial_puts() call which just pipes single characters into the port in loop. Implement function that does this behavior into common code, so others can make easy use of it. This function is called default_serial_puts() and it's sole purpose is to call putc() in loop on the whole string passed to it. Signed-off-by: Marek Vasut Cc: Marek Vasut Cc: Tom Rini --- drivers/serial/serial.c | 7 +++++++ include/serial.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 5bbf3aeb44..d648a73f41 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -273,6 +273,13 @@ void serial_puts(const char *s) get_current()->puts(s); } +void default_serial_puts(const char *s) +{ + struct serial_device *dev = get_current(); + while (*s) + dev->putc(*s++); +} + #if CONFIG_POST & CONFIG_SYS_POST_UART static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; diff --git a/include/serial.h b/include/serial.h index a8d23f519d..14f863ed20 100644 --- a/include/serial.h +++ b/include/serial.h @@ -20,6 +20,8 @@ struct serial_device { struct serial_device *next; }; +void default_serial_puts(const char *s); + extern struct serial_device serial_smc_device; extern struct serial_device serial_scc_device; extern struct serial_device *default_serial_console(void); -- cgit v1.2.3 From ec3fd68952662b1badb02caab9705eb93bdc4f1b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Oct 2012 14:07:02 +0000 Subject: serial: Use default_serial_puts() in drivers Replace the in-place ad-hoc implementation of serial_puts() within the drivers with default_serial_puts() call. This cuts down on the code duplication quite a bit. Signed-off-by: Marek Vasut Cc: Marek Vasut Cc: Tom Rini --- arch/mips/cpu/mips32/au1x00/au1x00_serial.c | 8 +------- arch/mips/cpu/mips32/incaip/asc_serial.c | 10 +--------- arch/mips/cpu/xburst/jz_serial.c | 8 +------- arch/powerpc/cpu/mpc5xx/serial.c | 10 +--------- arch/powerpc/cpu/mpc8220/uart.c | 9 +-------- arch/powerpc/cpu/mpc8260/serial_scc.c | 9 +-------- arch/powerpc/cpu/mpc8260/serial_smc.c | 9 +-------- arch/powerpc/cpu/mpc85xx/serial_scc.c | 9 +-------- arch/sparc/cpu/leon2/serial.c | 9 +-------- arch/sparc/cpu/leon3/serial.c | 9 +-------- board/Marvell/common/serial.c | 9 +-------- board/cogent/serial.c | 8 +------- board/esd/cpci750/serial.c | 10 +--------- board/evb64260/serial.c | 9 +-------- board/pcippc2/fpga_serial.c | 7 ------- board/pcippc2/fpga_serial.h | 1 - board/pcippc2/pcippc2.c | 3 ++- board/prodrive/p3mx/serial.c | 10 +--------- drivers/serial/altera_jtag_uart.c | 8 +------- drivers/serial/altera_uart.c | 9 +-------- drivers/serial/atmel_usart.c | 8 +------- drivers/serial/lpc32xx_hsuart.c | 8 +------- drivers/serial/mcfuart.c | 9 +-------- drivers/serial/ns9750_serial.c | 15 +-------------- drivers/serial/opencores_yanu.c | 10 +--------- drivers/serial/s3c4510b_uart.c | 6 ++---- drivers/serial/s3c64xx.c | 8 +------- drivers/serial/serial_clps7111.c | 9 +-------- drivers/serial/serial_imx.c | 9 +-------- drivers/serial/serial_ixp.c | 9 +-------- drivers/serial/serial_ks8695.c | 9 +-------- drivers/serial/serial_lh7a40x.c | 9 +-------- drivers/serial/serial_lpc2292.c | 9 +-------- drivers/serial/serial_mxc.c | 9 +-------- drivers/serial/serial_netarm.c | 9 +-------- drivers/serial/serial_pl01x.c | 9 +-------- drivers/serial/serial_s3c44b0.c | 9 +-------- drivers/serial/serial_sa1100.c | 9 +-------- drivers/serial/serial_sh.c | 9 +-------- 39 files changed, 39 insertions(+), 297 deletions(-) diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c index 0beac98fde..3e85b90cde 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c @@ -103,12 +103,6 @@ static void au1x00_serial_putc(const char c) *uart_tx = (u32)c; } -static void au1x00_serial_puts(const char *s) -{ - while (*s) - serial_putc(*s++); -} - static int au1x00_serial_getc(void) { volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX); @@ -137,7 +131,7 @@ static struct serial_device au1x00_serial_drv = { .stop = NULL, .setbrg = au1x00_serial_setbrg, .putc = au1x00_serial_putc, - .puts = au1x00_serial_puts, + .puts = default_serial_puts, .getc = au1x00_serial_getc, .tstc = au1x00_serial_tstc, }; diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c index 08949f4fb0..6f0e4f2520 100644 --- a/arch/mips/cpu/mips32/incaip/asc_serial.c +++ b/arch/mips/cpu/mips32/incaip/asc_serial.c @@ -236,14 +236,6 @@ static void asc_serial_putc(const char c) } } -static void asc_serial_puts(const char *s) -{ - while (*s) - { - serial_putc (*s++); - } -} - static int asc_serial_getc(void) { ulong symbol_mask; @@ -292,7 +284,7 @@ static struct serial_device asc_serial_drv = { .stop = NULL, .setbrg = asc_serial_setbrg, .putc = asc_serial_putc, - .puts = asc_serial_puts, + .puts = default_serial_puts, .getc = asc_serial_getc, .tstc = asc_serial_tstc, }; diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c index 3199007757..a147657350 100644 --- a/arch/mips/cpu/xburst/jz_serial.c +++ b/arch/mips/cpu/xburst/jz_serial.c @@ -109,19 +109,13 @@ static int jz_serial_getc(void) return readb(&uart->rbr_thr_dllr); } -static void jz_serial_puts(const char *s) -{ - while (*s) - serial_putc(*s++); -} - static struct serial_device jz_serial_drv = { .name = "jz_serial", .start = jz_serial_init, .stop = NULL, .setbrg = jz_serial_setbrg, .putc = jz_serial_putc, - .puts = jz_serial_puts, + .puts = default_serial_puts, .getc = jz_serial_getc, .tstc = jz_serial_tstc, }; diff --git a/arch/powerpc/cpu/mpc5xx/serial.c b/arch/powerpc/cpu/mpc5xx/serial.c index 6ef8be8fac..732856a5c5 100644 --- a/arch/powerpc/cpu/mpc5xx/serial.c +++ b/arch/powerpc/cpu/mpc5xx/serial.c @@ -161,21 +161,13 @@ static void mpc5xx_serial_setbrg(void) #endif } -static void mpc5xx_serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s); - ++s; - } -} - static struct serial_device mpc5xx_serial_drv = { .name = "mpc5xx_serial", .start = mpc5xx_serial_init, .stop = NULL, .setbrg = mpc5xx_serial_setbrg, .putc = mpc5xx_serial_putc, - .puts = mpc5xx_serial_puts, + .puts = default_serial_puts, .getc = mpc5xx_serial_getc, .tstc = mpc5xx_serial_tstc, }; diff --git a/arch/powerpc/cpu/mpc8220/uart.c b/arch/powerpc/cpu/mpc8220/uart.c index 25d4472ea0..772528f82c 100644 --- a/arch/powerpc/cpu/mpc8220/uart.c +++ b/arch/powerpc/cpu/mpc8220/uart.c @@ -84,13 +84,6 @@ static void mpc8220_serial_putc(const char c) psc->xmitbuf[0] = c; } -static void mpc8220_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static int mpc8220_serial_getc(void) { volatile psc8220_t *psc = (psc8220_t *) PSC_BASE; @@ -132,7 +125,7 @@ static struct serial_device mpc8220_serial_drv = { .stop = NULL, .setbrg = mpc8220_serial_setbrg, .putc = mpc8220_serial_putc, - .puts = mpc8220_serial_puts, + .puts = default_serial_puts, .getc = mpc8220_serial_getc, .tstc = mpc8220_serial_tstc, }; diff --git a/arch/powerpc/cpu/mpc8260/serial_scc.c b/arch/powerpc/cpu/mpc8260/serial_scc.c index ab7755824a..ab2a2b29cb 100644 --- a/arch/powerpc/cpu/mpc8260/serial_scc.c +++ b/arch/powerpc/cpu/mpc8260/serial_scc.c @@ -217,13 +217,6 @@ static void mpc8260_scc_serial_putc(const char c) tbdf->cbd_sc |= BD_SC_READY; } -static void mpc8260_scc_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static int mpc8260_scc_serial_getc(void) { volatile cbd_t *rbdf; @@ -267,7 +260,7 @@ static struct serial_device mpc8260_scc_serial_drv = { .stop = NULL, .setbrg = mpc8260_scc_serial_setbrg, .putc = mpc8260_scc_serial_putc, - .puts = mpc8260_scc_serial_puts, + .puts = default_serial_puts, .getc = mpc8260_scc_serial_getc, .tstc = mpc8260_scc_serial_tstc, }; diff --git a/arch/powerpc/cpu/mpc8260/serial_smc.c b/arch/powerpc/cpu/mpc8260/serial_smc.c index 7edde9a492..feba1f63d2 100644 --- a/arch/powerpc/cpu/mpc8260/serial_smc.c +++ b/arch/powerpc/cpu/mpc8260/serial_smc.c @@ -216,13 +216,6 @@ static void mpc8260_smc_serial_putc(const char c) rtx->txbd.cbd_sc |= BD_SC_READY; } -static void mpc8260_smc_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static int mpc8260_smc_serial_getc(void) { volatile smc_uart_t *up; @@ -270,7 +263,7 @@ static struct serial_device mpc8260_smc_serial_drv = { .stop = NULL, .setbrg = mpc8260_smc_serial_setbrg, .putc = mpc8260_smc_serial_putc, - .puts = mpc8260_smc_serial_puts, + .puts = default_serial_puts, .getc = mpc8260_smc_serial_getc, .tstc = mpc8260_smc_serial_tstc, }; diff --git a/arch/powerpc/cpu/mpc85xx/serial_scc.c b/arch/powerpc/cpu/mpc85xx/serial_scc.c index fe9af55c7a..6345362d88 100644 --- a/arch/powerpc/cpu/mpc85xx/serial_scc.c +++ b/arch/powerpc/cpu/mpc85xx/serial_scc.c @@ -220,13 +220,6 @@ static void mpc85xx_serial_putc(const char c) tbdf->cbd_sc |= BD_SC_READY; } -static void mpc85xx_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static int mpc85xx_serial_getc(void) { volatile cbd_t *rbdf; @@ -268,7 +261,7 @@ static struct serial_device mpc85xx_serial_drv = { .stop = NULL, .setbrg = mpc85xx_serial_setbrg, .putc = mpc85xx_serial_putc, - .puts = mpc85xx_serial_puts, + .puts = default_serial_puts, .getc = mpc85xx_serial_getc, .tstc = mpc85xx_serial_tstc, }; diff --git a/arch/sparc/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c index 16fffb621d..40d5b01d27 100644 --- a/arch/sparc/cpu/leon2/serial.c +++ b/arch/sparc/cpu/leon2/serial.c @@ -105,13 +105,6 @@ static void leon2_serial_putc(const char c) leon2_serial_putc_raw(c); } -static void leon2_serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - static int leon2_serial_getc(void) { LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; @@ -172,7 +165,7 @@ static struct serial_device leon2_serial_drv = { .stop = NULL, .setbrg = leon2_serial_setbrg, .putc = leon2_serial_putc, - .puts = leon2_serial_puts, + .puts = default_serial_puts, .getc = leon2_serial_getc, .tstc = leon2_serial_tstc, }; diff --git a/arch/sparc/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c index c4f3ee83c3..838d4514ee 100644 --- a/arch/sparc/cpu/leon3/serial.c +++ b/arch/sparc/cpu/leon3/serial.c @@ -99,13 +99,6 @@ static void leon3_serial_putc(const char c) leon3_serial_putc_raw(c); } -static void leon3_serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - static int leon3_serial_getc(void) { if (!leon3_apbuart) @@ -146,7 +139,7 @@ static struct serial_device leon3_serial_drv = { .stop = NULL, .setbrg = leon3_serial_setbrg, .putc = leon3_serial_putc, - .puts = leon3_serial_puts, + .puts = default_serial_puts, .getc = leon3_serial_getc, .tstc = leon3_serial_tstc, }; diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 1327c62a75..4a780c3746 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -139,20 +139,13 @@ static void marvell_serial_setbrg(void) #endif /* CONFIG_MPSC */ -static void marvell_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device marvell_serial_drv = { .name = "marvell_serial", .start = marvell_serial_init, .stop = NULL, .setbrg = marvell_serial_setbrg, .putc = marvell_serial_putc, - .puts = marvell_serial_puts, + .puts = default_serial_puts, .getc = marvell_serial_getc, .tstc = marvell_serial_tstc, }; diff --git a/board/cogent/serial.c b/board/cogent/serial.c index cd4a976f89..20631d162d 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -68,12 +68,6 @@ static void cogent_serial_putc(const char c) cma_mb_reg_write (&mbsp->ser_thr, c); } -static void cogent_serial_puts(const char *s) -{ - while (*s != '\0') - serial_putc (*s++); -} - static int cogent_serial_getc(void) { cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE; @@ -96,7 +90,7 @@ static struct serial_device cogent_serial_drv = { .stop = NULL, .setbrg = cogent_serial_setbrg, .putc = cogent_serial_putc, - .puts = cogent_serial_puts, + .puts = default_serial_puts, .getc = cogent_serial_getc, .tstc = cogent_serial_tstc, }; diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c index 25f8950e9a..160e0e0ae0 100644 --- a/board/esd/cpci750/serial.c +++ b/board/esd/cpci750/serial.c @@ -75,21 +75,13 @@ static void cpci750_serial_setbrg(void) galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } - -static void cpci750_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device cpci750_serial_drv = { .name = "cpci750_serial", .start = cpci750_serial_init, .stop = NULL, .setbrg = cpci750_serial_setbrg, .putc = cpci750_serial_putc, - .puts = cpci750_serial_puts, + .puts = default_serial_puts, .getc = cpci750_serial_getc, .tstc = cpci750_serial_tstc, }; diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index 9fd429864a..b9ca1d760c 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -139,20 +139,13 @@ static void evb64260_serial_setbrg(void) #endif /* CONFIG_MPSC */ -static void evb64260_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device evb64260_serial_drv = { .name = "evb64260_serial", .start = evb64260_serial_init, .stop = NULL, .setbrg = evb64260_serial_setbrg, .putc = evb64260_serial_putc, - .puts = evb64260_serial_puts, + .puts = default_serial_puts, .getc = evb64260_serial_getc, .tstc = evb64260_serial_tstc, }; diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c index 5f89d9b125..de61ca0e56 100644 --- a/board/pcippc2/fpga_serial.c +++ b/board/pcippc2/fpga_serial.c @@ -73,13 +73,6 @@ void fpga_serial_putc (char c) } } -void fpga_serial_puts (const char *s) -{ - while (*s) { - fpga_serial_print (*s++); - } -} - int fpga_serial_getc (void) { while ((in8 (UART (LSR)) & 0x01) == 0); diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h index 52750143c4..106fbf7a50 100644 --- a/board/pcippc2/fpga_serial.h +++ b/board/pcippc2/fpga_serial.h @@ -26,7 +26,6 @@ extern void fpga_serial_init (int); extern void fpga_serial_putc (char); -extern void fpga_serial_puts (const char *); extern int fpga_serial_getc (void); extern int fpga_serial_tstc (void); extern void fpga_serial_setbrg (void); diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index 4a91458e8e..5e6fc58cf7 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "hardware.h" #include "pcippc2.h" @@ -129,7 +130,7 @@ int misc_init_r (void) fpga_serial_init (sconsole_get_baudrate ()); sconsole_putc = fpga_serial_putc; - sconsole_puts = fpga_serial_puts; + sconsole_puts = default_serial_puts; sconsole_getc = fpga_serial_getc; sconsole_tstc = fpga_serial_tstc; sconsole_setbrg = fpga_serial_setbrg; diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c index 2f4d294b9d..3536933c00 100644 --- a/board/prodrive/p3mx/serial.c +++ b/board/prodrive/p3mx/serial.c @@ -75,21 +75,13 @@ static void p3mx_serial_setbrg(void) galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); } - -static void p3mx_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device p3mx_serial_drv = { .name = "p3mx_serial", .start = p3mx_serial_init, .stop = NULL, .setbrg = p3mx_serial_setbrg, .putc = p3mx_serial_putc, - .puts = p3mx_serial_puts, + .puts = default_serial_puts, .getc = p3mx_serial_getc, .tstc = p3mx_serial_tstc, }; diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c index 654b5019eb..28319baf18 100644 --- a/drivers/serial/altera_jtag_uart.c +++ b/drivers/serial/altera_jtag_uart.c @@ -59,12 +59,6 @@ static void altera_jtag_serial_putc(char c) writel ((unsigned char)c, &jtag->data); } -static void altera_jtag_serial_puts(const char *s) -{ - while (*s != 0) - serial_putc (*s++); -} - static int altera_jtag_serial_tstc(void) { return ( readl (&jtag->control) & NIOS_JTAG_RRDY); @@ -91,7 +85,7 @@ static struct serial_device altera_jtag_serial_drv = { .stop = NULL, .setbrg = altera_jtag_serial_setbrg, .putc = altera_jtag_serial_putc, - .puts = altera_jtag_serial_puts, + .puts = default_serial_puts, .getc = altera_jtag_serial_getc, .tstc = altera_jtag_serial_tstc, }; diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index 27550ed48d..118cd58ece 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -82,13 +82,6 @@ static void altera_serial_putc(char c) writel ((unsigned char)c, &uart->txdata); } -static void altera_serial_puts(const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - static int altera_serial_tstc(void) { return (readl (&uart->status) & NIOS_UART_RRDY); @@ -107,7 +100,7 @@ static struct serial_device altera_serial_drv = { .stop = NULL, .setbrg = altera_serial_setbrg, .putc = altera_serial_putc, - .puts = altera_serial_puts, + .puts = default_serial_puts, .getc = altera_serial_getc, .tstc = altera_serial_tstc, }; diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 130303129e..c4d7432efc 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -86,12 +86,6 @@ static void atmel_serial_putc(char c) writel(c, &usart->thr); } -static void atmel_serial_puts(const char *s) -{ - while (*s) - serial_putc(*s++); -} - static int atmel_serial_getc(void) { atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; @@ -113,7 +107,7 @@ static struct serial_device atmel_serial_drv = { .stop = NULL, .setbrg = atmel_serial_setbrg, .putc = atmel_serial_putc, - .puts = atmel_serial_puts, + .puts = default_serial_puts, .getc = atmel_serial_getc, .tstc = atmel_serial_tstc, }; diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c index 02429b5541..7559916578 100644 --- a/drivers/serial/lpc32xx_hsuart.c +++ b/drivers/serial/lpc32xx_hsuart.c @@ -77,19 +77,13 @@ static int lpc32xx_serial_init(void) return 0; } -static void lpc32xx_serial_puts(const char *s) -{ - while (*s) - serial_putc(*s++); -} - static struct serial_device lpc32xx_serial_drv = { .name = "lpc32xx_serial", .start = lpc32xx_serial_init, .stop = NULL, .setbrg = lpc32xx_serial_setbrg, .putc = lpc32xx_serial_putc, - .puts = lpc32xx_serial_puts, + .puts = default_serial_puts, .getc = lpc32xx_serial_getc, .tstc = lpc32xx_serial_tstc, }; diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 00a7114691..8ea9af0f61 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -87,13 +87,6 @@ static void mcf_serial_putc(const char c) uart->utb = c; } -static void mcf_serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - static int mcf_serial_getc(void) { volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); @@ -136,7 +129,7 @@ static struct serial_device mcf_serial_drv = { .stop = NULL, .setbrg = mcf_serial_setbrg, .putc = mcf_serial_putc, - .puts = mcf_serial_puts, + .puts = default_serial_puts, .getc = mcf_serial_getc, .tstc = mcf_serial_tstc, }; diff --git a/drivers/serial/ns9750_serial.c b/drivers/serial/ns9750_serial.c index cb545c4065..85fc68a076 100644 --- a/drivers/serial/ns9750_serial.c +++ b/drivers/serial/ns9750_serial.c @@ -99,19 +99,6 @@ static void ns9750_serial_putc(const char c) CONSOLE) = c; } -/*********************************************************************** - * @Function: serial_puts - * @Return: n/a - * @Descr: writes non-zero string to the FIFO. - ***********************************************************************/ - -static void ns9750_serial_puts(const char *s) -{ - while (*s) { - serial_putc( *s++ ); - } -} - /*********************************************************************** * @Function: serial_getc * @Return: the character read @@ -215,7 +202,7 @@ static struct serial_device ns9750_serial_drv = { .stop = NULL, .setbrg = ns9750_serial_setbrg, .putc = ns9750_serial_putc, - .puts = ns9750_serial_puts, + .puts = default_serial_puts, .getc = ns9750_serial_getc, .tstc = ns9750_serial_tstc, }; diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index 49bccf3a6c..4ca6ef0b25 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -161,14 +161,6 @@ static void oc_serial_putc(char c) writel((unsigned char)c, &uart->data); } -static void oc_serial_puts(const char *s) -{ - while (*s != 0) { - serial_putc (*s++); - } -} - - static int oc_serial_tstc(void) { unsigned status ; @@ -195,7 +187,7 @@ static struct serial_device oc_serial_drv = { .stop = NULL, .setbrg = oc_serial_setbrg, .putc = oc_serial_putc, - .puts = oc_serial_puts, + .puts = default_serial_puts, .getc = oc_serial_getc, .tstc = oc_serial_tstc, }; diff --git a/drivers/serial/s3c4510b_uart.c b/drivers/serial/s3c4510b_uart.c index 423d26e678..c460229e05 100644 --- a/drivers/serial/s3c4510b_uart.c +++ b/drivers/serial/s3c4510b_uart.c @@ -199,12 +199,10 @@ static int s3c4510b_serial_getc(void) static void s3c4510b_serial_puts(const char *s) { - while (*s) { - serial_putc (*s++); - } + default_serial_puts(s); /* busy wait for tx complete */ - while ( !uart->m_stat.bf.txComplete); + while (!uart->m_stat.bf.txComplete); /* clear break */ uart->m_ctrl.bf.sendBreak = 0; diff --git a/drivers/serial/s3c64xx.c b/drivers/serial/s3c64xx.c index 9ab8a28d83..ea8d734a9e 100644 --- a/drivers/serial/s3c64xx.c +++ b/drivers/serial/s3c64xx.c @@ -166,19 +166,13 @@ static int s3c64xx_serial_tstc(void) return uart->UTRSTAT & 0x1; } -static void s3c64xx_serial_puts(const char *s) -{ - while (*s) - serial_putc(*s++); -} - static struct serial_device s3c64xx_serial_drv = { .name = "s3c64xx_serial", .start = s3c64xx_serial_init, .stop = NULL, .setbrg = s3c64xx_serial_setbrg, .putc = s3c64xx_serial_putc, - .puts = s3c64xx_serial_puts, + .puts = default_serial_puts, .getc = s3c64xx_serial_getc, .tstc = s3c64xx_serial_tstc, }; diff --git a/drivers/serial/serial_clps7111.c b/drivers/serial/serial_clps7111.c index 65473e8608..c292ed8756 100644 --- a/drivers/serial/serial_clps7111.c +++ b/drivers/serial/serial_clps7111.c @@ -112,20 +112,13 @@ static int clps7111_serial_getc(void) return IO_UARTDR1 & 0xff; } -static void clps7111_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device clps7111_serial_drv = { .name = "clps7111_serial", .start = clps7111_serial_init, .stop = NULL, .setbrg = clps7111_serial_setbrg, .putc = clps7111_serial_putc, - .puts = clps7111_serial_puts, + .puts = default_serial_puts, .getc = clps7111_serial_getc, .tstc = clps7111_serial_tstc, }; diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index 6c075b5b91..9b9be44c52 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -214,20 +214,13 @@ static int imx_serial_tstc(void) return 1; } -static void imx_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device imx_serial_drv = { .name = "imx_serial", .start = imx_serial_init, .stop = NULL, .setbrg = imx_serial_setbrg, .putc = imx_serial_putc, - .puts = imx_serial_puts, + .puts = default_serial_puts, .getc = imx_serial_getc, .tstc = imx_serial_tstc, }; diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c index c8b3658d47..09a3df4016 100644 --- a/drivers/serial/serial_ixp.c +++ b/drivers/serial/serial_ixp.c @@ -121,20 +121,13 @@ static int ixp_serial_getc(void) return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; } -static void ixp_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device ixp_serial_drv = { .name = "ixp_serial", .start = ixp_serial_init, .stop = NULL, .setbrg = ixp_serial_setbrg, .putc = ixp_serial_putc, - .puts = ixp_serial_puts, + .puts = default_serial_puts, .getc = ixp_serial_getc, .tstc = ixp_serial_tstc, }; diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c index 60e8007201..8b1c974de9 100644 --- a/drivers/serial/serial_ks8695.c +++ b/drivers/serial/serial_ks8695.c @@ -102,13 +102,6 @@ static int ks8695_serial_tstc(void) return 0; } -static void ks8695_serial_puts(const char *s) -{ - char c; - while ((c = *s++) != 0) - serial_putc(c); -} - static int ks8695_serial_getc(void) { volatile struct ks8695uart *uartp = KS8695_UART_ADDR; @@ -124,7 +117,7 @@ static struct serial_device ks8695_serial_drv = { .stop = NULL, .setbrg = ks8695_serial_setbrg, .putc = ks8695_serial_putc, - .puts = ks8695_serial_puts, + .puts = default_serial_puts, .getc = ks8695_serial_getc, .tstc = ks8695_serial_tstc, }; diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c index 6c9628581b..68e958ba77 100644 --- a/drivers/serial/serial_lh7a40x.c +++ b/drivers/serial/serial_lh7a40x.c @@ -175,20 +175,13 @@ static int lh7a40x_serial_tstc(void) return(!(uart->status & UART_RXFE)); } -static void lh7a40x_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device lh7a40x_serial_drv = { .name = "lh7a40x_serial", .start = lh7a40x_serial_init, .stop = NULL, .setbrg = lh7a40x_serial_setbrg, .putc = lh7a40x_serial_putc, - .puts = lh7a40x_serial_puts, + .puts = default_serial_puts, .getc = lh7a40x_serial_getc, .tstc = lh7a40x_serial_tstc, }; diff --git a/drivers/serial/serial_lpc2292.c b/drivers/serial/serial_lpc2292.c index fcab20280e..8abc476713 100644 --- a/drivers/serial/serial_lpc2292.c +++ b/drivers/serial/serial_lpc2292.c @@ -89,13 +89,6 @@ static int lpc2292_serial_getc(void) return GET8(U0RBR); } -static void lpc2292_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - /* Test if there is a byte to read */ static int lpc2292_serial_tstc(void) { @@ -108,7 +101,7 @@ static struct serial_device lpc2292_serial_drv = { .stop = NULL, .setbrg = lpc2292_serial_setbrg, .putc = lpc2292_serial_putc, - .puts = lpc2292_serial_puts, + .puts = default_serial_puts, .getc = lpc2292_serial_getc, .tstc = lpc2292_serial_tstc, }; diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index b0612f5aca..9227d64088 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -187,13 +187,6 @@ static int mxc_serial_tstc(void) return 1; } -static void mxc_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - /* * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. @@ -228,7 +221,7 @@ static struct serial_device mxc_serial_drv = { .stop = NULL, .setbrg = mxc_serial_setbrg, .putc = mxc_serial_putc, - .puts = mxc_serial_puts, + .puts = default_serial_puts, .getc = mxc_serial_getc, .tstc = mxc_serial_tstc, }; diff --git a/drivers/serial/serial_netarm.c b/drivers/serial/serial_netarm.c index d30adc3183..44d7c500c7 100644 --- a/drivers/serial/serial_netarm.c +++ b/drivers/serial/serial_netarm.c @@ -182,20 +182,13 @@ static int netarm_serial_getc(void) return ch_uint & 0xff; } -static void netarm_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device netarm_serial_drv = { .name = "netarm_serial", .start = netarm_serial_init, .stop = NULL, .setbrg = netarm_serial_setbrg, .putc = netarm_serial_putc, - .puts = netarm_serial_puts, + .puts = default_serial_puts, .getc = netarm_serial_getc, .tstc = netarm_serial_tstc, }; diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 7db7b65c3f..b331be794b 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -179,13 +179,6 @@ static void pl01x_serial_putc(const char c) pl01x_putc (CONSOLE_PORT, c); } -static void pl01x_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static int pl01x_serial_getc(void) { return pl01x_getc (CONSOLE_PORT); @@ -259,7 +252,7 @@ static struct serial_device pl01x_serial_drv = { .stop = NULL, .setbrg = pl01x_serial_setbrg, .putc = pl01x_serial_putc, - .puts = pl01x_serial_puts, + .puts = default_serial_puts, .getc = pl01x_serial_getc, .tstc = pl01x_serial_tstc, }; diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c index a4428e0f47..9cae843088 100644 --- a/drivers/serial/serial_s3c44b0.c +++ b/drivers/serial/serial_s3c44b0.c @@ -209,20 +209,13 @@ static int s3c44b0_serial_getc(void) } } -static void s3c44b0_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device s3c44b0_serial_drv = { .name = "s3c44b0_serial", .start = s3c44b0_serial_init, .stop = NULL, .setbrg = s3c44b0_serial_setbrg, .putc = s3c44b0_serial_putc, - .puts = s3c44b0_serial_puts, + .puts = default_serial_puts, .getc = s3c44b0_serial_getc, .tstc = s3c44b0_serial_tstc, }; diff --git a/drivers/serial/serial_sa1100.c b/drivers/serial/serial_sa1100.c index c6b34db7c6..3c0f4c59fb 100644 --- a/drivers/serial/serial_sa1100.c +++ b/drivers/serial/serial_sa1100.c @@ -153,20 +153,13 @@ static int sa1100_serial_getc(void) #endif } -static void sa1100_serial_puts(const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - static struct serial_device sa1100_serial_drv = { .name = "sa1100_serial", .start = sa1100_serial_init, .stop = NULL, .setbrg = sa1100_serial_setbrg, .putc = sa1100_serial_putc, - .puts = sa1100_serial_puts, + .puts = default_serial_puts, .getc = sa1100_serial_getc, .tstc = sa1100_serial_tstc, }; diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 1ddfc7d87f..3c931d0212 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -136,13 +136,6 @@ static void sh_serial_putc(const char c) serial_raw_putc(c); } -static void sh_serial_puts(const char *s) -{ - char c; - while ((c = *s++) != 0) - serial_putc(c); -} - static int sh_serial_tstc(void) { return serial_rx_fifo_level() ? 1 : 0; @@ -196,7 +189,7 @@ static struct serial_device sh_serial_drv = { .stop = NULL, .setbrg = sh_serial_setbrg, .putc = sh_serial_putc, - .puts = sh_serial_puts, + .puts = default_serial_puts, .getc = sh_serial_getc, .tstc = sh_serial_tstc, }; -- cgit v1.2.3 From 6d93e25806337d46ee75c6703b3ecc972cb179a5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Oct 2012 14:07:03 +0000 Subject: serial: Reorder serial_assign() Reorder serial_assign() function to get rid of the extra level of indentation. Also, adjust the return value to be -EINVAL instead of positive one to be more consistent. Signed-off-by: Marek Vasut Cc: Marek Vasut Cc: Tom Rini --- drivers/serial/serial.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index d648a73f41..3ab323bcb8 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -205,13 +206,13 @@ int serial_assign(const char *name) struct serial_device *s; for (s = serial_devices; s; s = s->next) { - if (strcmp(s->name, name) == 0) { - serial_current = s; - return 0; - } + if (strcmp(s->name, name)) + continue; + serial_current = s; + return 0; } - return 1; + return -EINVAL; } void serial_reinit_all(void) -- cgit v1.2.3 From dee1941604ca0970f455b8231f695bcdb67045e4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Oct 2012 14:07:04 +0000 Subject: serial: Reorder get_current() Reorder the get_current() function to make it a bit more readable. The code does not grow and there is minor change in the code logic, where dev != NULL is now checked in any case. Signed-off-by: Marek Vasut Cc: Marek Vasut Cc: Tom Rini --- drivers/serial/serial.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 3ab323bcb8..18b9ed4330 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -227,20 +227,23 @@ static struct serial_device *get_current(void) { struct serial_device *dev; - if (!(gd->flags & GD_FLG_RELOC) || !serial_current) { + if (!(gd->flags & GD_FLG_RELOC)) dev = default_serial_console(); + else if (!serial_current) + dev = default_serial_console(); + else + dev = serial_current; - /* We must have a console device */ - if (!dev) { + /* We must have a console device */ + if (!dev) { #ifdef CONFIG_SPL_BUILD - puts("Cannot find console\n"); - hang(); + puts("Cannot find console\n"); + hang(); #else - panic("Cannot find console\n"); + panic("Cannot find console\n"); #endif - } - } else - dev = serial_current; + } + return dev; } -- cgit v1.2.3 From 9cd2b9e47e0ea48f8f5c737044a8cb23528c7318 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Oct 2012 11:36:39 +0000 Subject: kerneldoc: Annotate drivers/serial/serial.c Add kerneldoc annotations into serial core. Signed-off-by: Marek Vasut Cc: Marek Vasut Cc: Tom Rini --- drivers/serial/serial.c | 165 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 18b9ed4330..e0886d562e 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -33,10 +33,28 @@ DECLARE_GLOBAL_DATA_PTR; static struct serial_device *serial_devices; static struct serial_device *serial_current; +/** + * serial_null() - Void registration routine of a serial driver + * + * This routine implements a void registration routine of a serial + * driver. The registration routine of a particular driver is aliased + * to this empty function in case the driver is not compiled into + * U-Boot. + */ static void serial_null(void) { } +/** + * serial_initfunc() - Forward declare of driver registration routine + * @name: Name of the real driver registration routine. + * + * This macro expands onto forward declaration of a driver registration + * routine, which is then used below in serial_initialize() function. + * The declaration is made weak and aliases to serial_null() so in case + * the driver is not compiled in, the function is still declared and can + * be used, but aliases to serial_null() and thus is optimized away. + */ #define serial_initfunc(name) \ void name(void) \ __attribute__((weak, alias("serial_null"))); @@ -95,6 +113,16 @@ serial_initfunc(s3c44b0_serial_initialize); serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); +/** + * serial_register() - Register serial driver with serial driver core + * @dev: Pointer to the serial driver structure + * + * This function registers the serial driver supplied via @dev with + * serial driver core, thus making U-Boot aware of it and making it + * available for U-Boot to use. On platforms that still require manual + * relocation of constant variables, relocation of the supplied structure + * is performed. + */ void serial_register(struct serial_device *dev) { #ifdef CONFIG_NEEDS_MANUAL_RELOC @@ -118,6 +146,15 @@ void serial_register(struct serial_device *dev) serial_devices = dev; } +/** + * serial_initialize() - Register all compiled-in serial port drivers + * + * This function registers all serial port drivers that are compiled + * into the U-Boot binary with the serial core, thus making them + * available to U-Boot to use. Lastly, this function assigns a default + * serial port to the serial core. That serial port is then used as a + * default output. + */ void serial_initialize(void) { mpc8xx_serial_initialize(); @@ -177,6 +214,13 @@ void serial_initialize(void) serial_assign(default_serial_console()->name); } +/** + * serial_stdio_init() - Register serial ports with STDIO core + * + * This function generates a proxy driver for each serial port driver. + * These proxy drivers then register with the STDIO core, making the + * serial drivers available as STDIO devices. + */ void serial_stdio_init(void) { struct stdio_dev dev; @@ -201,6 +245,18 @@ void serial_stdio_init(void) } } +/** + * serial_assign() - Select the serial output device by name + * @name: Name of the serial driver to be used as default output + * + * This function configures the serial output multiplexing by + * selecting which serial device will be used as default. In case + * the STDIO "serial" device is selected as stdin/stdout/stderr, + * the serial device previously configured by this function will be + * used for the particular operation. + * + * Returns 0 on success, negative on error. + */ int serial_assign(const char *name) { struct serial_device *s; @@ -215,6 +271,12 @@ int serial_assign(const char *name) return -EINVAL; } +/** + * serial_reinit_all() - Reinitialize all compiled-in serial ports + * + * This function reinitializes all serial ports that are compiled + * into U-Boot by calling their serial_start() functions. + */ void serial_reinit_all(void) { struct serial_device *s; @@ -223,6 +285,21 @@ void serial_reinit_all(void) s->start(); } +/** + * get_current() - Return pointer to currently selected serial port + * + * This function returns a pointer to currently selected serial port. + * The currently selected serial port is altered by serial_assign() + * function. + * + * In case this function is called before relocation or before any serial + * port is configured, this function calls default_serial_console() to + * determine the serial port. Otherwise, the configured serial port is + * returned. + * + * Returns pointer to the currently selected serial port on success, + * NULL on error. + */ static struct serial_device *get_current(void) { struct serial_device *dev; @@ -247,36 +324,113 @@ static struct serial_device *get_current(void) return dev; } +/** + * serial_init() - Initialize currently selected serial port + * + * This function initializes the currently selected serial port. This + * usually involves setting up the registers of that particular port, + * enabling clock and such. This function uses the get_current() call + * to determine which port is selected. + * + * Returns 0 on success, negative on error. + */ int serial_init(void) { return get_current()->start(); } +/** + * serial_setbrg() - Configure baud-rate of currently selected serial port + * + * This function configures the baud-rate of the currently selected + * serial port. The baud-rate is retrieved from global data within + * the serial port driver. This function uses the get_current() call + * to determine which port is selected. + * + * Returns 0 on success, negative on error. + */ void serial_setbrg(void) { get_current()->setbrg(); } +/** + * serial_getc() - Read character from currently selected serial port + * + * This function retrieves a character from currently selected serial + * port. In case there is no character waiting on the serial port, + * this function will block and wait for the character to appear. This + * function uses the get_current() call to determine which port is + * selected. + * + * Returns the character on success, negative on error. + */ int serial_getc(void) { return get_current()->getc(); } +/** + * serial_tstc() - Test if data is available on currently selected serial port + * + * This function tests if one or more characters are available on + * currently selected serial port. This function never blocks. This + * function uses the get_current() call to determine which port is + * selected. + * + * Returns positive if character is available, zero otherwise. + */ int serial_tstc(void) { return get_current()->tstc(); } +/** + * serial_putc() - Output character via currently selected serial port + * @c: Single character to be output from the serial port. + * + * This function outputs a character via currently selected serial + * port. This character is passed to the serial port driver responsible + * for controlling the hardware. The hardware may still be in process + * of transmitting another character, therefore this function may block + * for a short amount of time. This function uses the get_current() + * call to determine which port is selected. + */ void serial_putc(const char c) { get_current()->putc(c); } +/** + * serial_puts() - Output string via currently selected serial port + * @s: Zero-terminated string to be output from the serial port. + * + * This function outputs a zero-terminated string via currently + * selected serial port. This function behaves as an accelerator + * in case the hardware can queue multiple characters for transfer. + * The whole string that is to be output is available to the function + * implementing the hardware manipulation. Transmitting the whole + * string may take some time, thus this function may block for some + * amount of time. This function uses the get_current() call to + * determine which port is selected. + */ void serial_puts(const char *s) { get_current()->puts(s); } +/** + * default_serial_puts() - Output string by calling serial_putc() in loop + * @s: Zero-terminated string to be output from the serial port. + * + * This function outputs a zero-terminated string by calling serial_putc() + * in a loop. Most drivers do not support queueing more than one byte for + * transfer, thus this function precisely implements their serial_puts(). + * + * To optimize the number of get_current() calls, this function only + * calls get_current() once and then directly accesses the putc() call + * of the &struct serial_device . + */ void default_serial_puts(const char *s) { struct serial_device *dev = get_current(); @@ -287,6 +441,17 @@ void default_serial_puts(const char *s) #if CONFIG_POST & CONFIG_SYS_POST_UART static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; +/** + * uart_post_test() - Test the currently selected serial port using POST + * @flags: POST framework flags + * + * Do a loopback test of the currently selected serial port. This + * function is only useful in the context of the POST testing framwork. + * The serial port is firstly configured into loopback mode and then + * characters are sent through it. + * + * Returns 0 on success, value otherwise. + */ /* Mark weak until post/cpu/.../uart.c migrate over */ __weak int uart_post_test(int flags) -- cgit v1.2.3 From eb1f09e0078668d831bd97eab3557786ea2d956d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 6 Oct 2012 14:07:06 +0000 Subject: kerneldoc: stdio: tmpl: Add stdio template Add STDIO documentation template. Signed-off-by: Marek Vasut Cc: Marek Vasut Cc: Tom Rini [trini: Fix DOCBOOKS line as we don't have linker_lists yet] Signed-off-by: Tom Rini --- doc/DocBook/Makefile | 2 +- doc/DocBook/stdio.tmpl | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 doc/DocBook/stdio.tmpl diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index 2f2ddfc865..7f38444039 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/config.mk -DOCBOOKS := +DOCBOOKS := stdio.xml ### # The build process is as follows (targets): diff --git a/doc/DocBook/stdio.tmpl b/doc/DocBook/stdio.tmpl new file mode 100644 index 0000000000..4783abb0a0 --- /dev/null +++ b/doc/DocBook/stdio.tmpl @@ -0,0 +1,46 @@ + + + + + + The U-Boot STDIO subsystem + + + + This documentation is free software; you can redistribute + it and/or modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later + version. + + + + This program is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU General Public License for more details. + + + + You should have received a copy of the GNU General Public + License along with this program; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, + MA 02111-1307 USA + + + + For more details see the file COPYING in the source + distribution of U-Boot Bootloader. + + + + + + + + U-Boot Serial subsystem +!Idrivers/serial/serial.c + + + -- cgit v1.2.3 From 94fa029a6d1fcf58c4cecc46326f766425bdb918 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Sun, 7 Oct 2012 05:56:05 +0000 Subject: remove CONFIG_SC3 from cmd_ide.c There is no difference in codepath with CONFIG_SC3 enabled, so just remove it Signed-off-by: Pavel Herrmann --- common/cmd_ide.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/common/cmd_ide.c b/common/cmd_ide.c index bae7767310..11e9eacf77 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -400,9 +400,6 @@ void ide_init(void) unsigned char c; int i, bus; -#if defined(CONFIG_SC3) - unsigned int ata_reset_time = ATA_RESET_TIME; -#endif #ifdef CONFIG_IDE_8xx_PCCARD extern int pcmcia_on(void); extern int ide_devices_found; /* Initialized in check_ide_device() */ @@ -502,11 +499,7 @@ void ide_init(void) c = ide_inb(dev, ATA_STATUS); i++; -#if defined(CONFIG_SC3) - if (i > (ata_reset_time * 100)) { -#else if (i > (ATA_RESET_TIME * 100)) { -#endif puts("** Timeout **\n"); /* LED's off */ ide_led((LED_IDE1 | LED_IDE2), 0); -- cgit v1.2.3 From 8d1165e11a7aad00a2bbb05f20bacf021f6d1c12 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Tue, 9 Oct 2012 07:01:56 +0000 Subject: split mpc8xx hooks from cmd_ide.c move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created ide_init_postreset() (invoked after calling ide_reset after ide_preinit), some cleanup to make checkpatch happy, enable IDE init hooks in configs of affected boards. confusingly, these hooks are used by more than just mpc8xx-based boards, and therefore are placed in arch/ppc/lib/ note: checkpatch still emits warnings about using volatile Signed-off-by: Pavel Herrmann --- arch/powerpc/lib/Makefile | 1 + arch/powerpc/lib/ide.c | 201 +++++++++++++++++++++++++++++++++++++++++++ arch/powerpc/lib/ide.h | 31 +++++++ common/cmd_ide.c | 190 ++-------------------------------------- include/configs/CPC45.h | 1 + include/configs/ICU862.h | 1 + include/configs/IVML24.h | 2 + include/configs/IVMS8.h | 2 + include/configs/KUP4K.h | 1 + include/configs/KUP4X.h | 1 + include/configs/MBX.h | 1 + include/configs/NETTA.h | 1 + include/configs/NSCU.h | 1 + include/configs/R360MPI.h | 1 + include/configs/RPXClassic.h | 1 + include/configs/RPXlite.h | 1 + include/configs/RPXlite_DW.h | 1 + include/configs/RRvision.h | 1 + include/configs/SPD823TS.h | 2 + include/configs/TK885D.h | 1 + include/configs/TQM823L.h | 1 + include/configs/TQM823M.h | 1 + include/configs/TQM850L.h | 1 + include/configs/TQM850M.h | 1 + include/configs/TQM855L.h | 1 + include/configs/TQM855M.h | 1 + include/configs/TQM860L.h | 1 + include/configs/TQM860M.h | 1 + include/configs/TQM862L.h | 1 + include/configs/TQM862M.h | 1 + include/configs/TQM866M.h | 1 + include/configs/TQM885D.h | 1 + include/configs/atc.h | 1 + include/configs/c2mon.h | 1 + include/configs/lwmon.h | 1 + include/configs/quantum.h | 1 + include/configs/svm_sc8xx.h | 2 + include/configs/uc100.h | 1 + include/configs/virtlab2.h | 1 + include/ide.h | 8 ++ 40 files changed, 287 insertions(+), 183 deletions(-) create mode 100644 arch/powerpc/lib/ide.c create mode 100644 arch/powerpc/lib/ide.h diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 965f9ea4a5..808021c42e 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -50,6 +50,7 @@ COBJS-y += cache.o COBJS-y += extable.o COBJS-y += interrupts.o COBJS-$(CONFIG_CMD_KGDB) += kgdb.o +COBJS-${CONFIG_CMD_IDE} += ide.o COBJS-y += time.o # Workaround for local bus unaligned access problems diff --git a/arch/powerpc/lib/ide.c b/arch/powerpc/lib/ide.c new file mode 100644 index 0000000000..139a94a5c1 --- /dev/null +++ b/arch/powerpc/lib/ide.c @@ -0,0 +1,201 @@ +/* + * (C) Copyright 2000-2011 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* Code taken from cmd_ide.c */ +#include +#include +#include "ide.h" + +#ifdef CONFIG_IDE_8xx_DIRECT +#include +#include +DECLARE_GLOBAL_DATA_PTR; + +/* Timings for IDE Interface + * + * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk + * 70 165 30 PIO-Mode 0, [ns] + * 4 9 2 [Cycles] + * 50 125 20 PIO-Mode 1, [ns] + * 3 7 2 [Cycles] + * 30 100 15 PIO-Mode 2, [ns] + * 2 6 1 [Cycles] + * 30 80 10 PIO-Mode 3, [ns] + * 2 5 1 [Cycles] + * 25 70 10 PIO-Mode 4, [ns] + * 2 4 1 [Cycles] + */ + +static const pio_config_t pio_config_ns[IDE_MAX_PIO_MODE+1] = { + /* Setup Length Hold */ + { 70, 165, 30 }, /* PIO-Mode 0, [ns] */ + { 50, 125, 20 }, /* PIO-Mode 1, [ns] */ + { 30, 101, 15 }, /* PIO-Mode 2, [ns] */ + { 30, 80, 10 }, /* PIO-Mode 3, [ns] */ + { 25, 70, 10 }, /* PIO-Mode 4, [ns] */ +}; + +static pio_config_t pio_config_clk[IDE_MAX_PIO_MODE+1]; + +#ifndef CONFIG_SYS_PIO_MODE +#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */ +#endif +static int pio_mode = CONFIG_SYS_PIO_MODE; + +/* Make clock cycles and always round up */ + +#define PCMCIA_MK_CLKS(t, T) (((t) * (T) + 999U) / 1000U) + +static void set_pcmcia_timing(int pmode) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); + ulong timings; + + debug("Set timing for PIO Mode %d\n", pmode); + + timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold) + | PCMCIA_SST(pio_config_clk[pmode].t_setup) + | PCMCIA_SL(pio_config_clk[pmode].t_length); + + /* + * IDE 0 + */ + pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0; +#if (CONFIG_SYS_PCMCIA_POR0 != 0) + pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 | timings; +#else + pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0; +#endif + debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0); + + pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1; +#if (CONFIG_SYS_PCMCIA_POR1 != 0) + pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 | timings; +#else + pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1; +#endif + debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1); + + pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2; +#if (CONFIG_SYS_PCMCIA_POR2 != 0) + pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 | timings; +#else + pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2; +#endif + debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2); + + pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3; +#if (CONFIG_SYS_PCMCIA_POR3 != 0) + pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 | timings; +#else + pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3; +#endif + debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3); + + /* + * IDE 1 + */ + pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4; +#if (CONFIG_SYS_PCMCIA_POR4 != 0) + pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 | timings; +#else + pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4; +#endif + debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4); + + pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5; +#if (CONFIG_SYS_PCMCIA_POR5 != 0) + pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 | timings; +#else + pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5; +#endif + debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5); + + pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6; +#if (CONFIG_SYS_PCMCIA_POR6 != 0) + pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 | timings; +#else + pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6; +#endif + debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6); + + pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7; +#if (CONFIG_SYS_PCMCIA_POR7 != 0) + pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 | timings; +#else + pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7; +#endif + debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7); + +} + +int ide_preinit(void) +{ + int i; + /* Initialize PIO timing tables */ + for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) { + pio_config_clk[i].t_setup = + PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk); + pio_config_clk[i].t_length = + PCMCIA_MK_CLKS(pio_config_ns[i].t_length, gd->bus_clk); + pio_config_clk[i].t_hold = + PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk); + debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk" + " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup, + pio_config_clk[i].t_setup, pio_config_ns[i].t_length, + pio_config_clk[i].t_length, pio_config_ns[i].t_hold, + pio_config_clk[i].t_hold); + } + + return 0; +} + +int ide_init_postreset(void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); + + /* PCMCIA / IDE initialization for common mem space */ + pcmp->pcmc_pgcrb = 0; + + /* start in PIO mode 0 - most relaxed timings */ + pio_mode = 0; + set_pcmcia_timing(pio_mode); + return 0; +} +#endif /* CONFIG_IDE_8xx_DIRECT */ + +#ifdef CONFIG_IDE_8xx_PCCARD +int ide_preinit(void) +{ + ide_devices_found = 0; + /* initialize the PCMCIA IDE adapter card */ + pcmcia_on(); + if (!ide_devices_found) + return 1; + udelay(1000000);/* 1 s */ + return 0; +} +#endif diff --git a/arch/powerpc/lib/ide.h b/arch/powerpc/lib/ide.h new file mode 100644 index 0000000000..9e80702916 --- /dev/null +++ b/arch/powerpc/lib/ide.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2012 + * Pavel Herrmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MPC8XX_IDE_H_ +#define _MPC8XX_IDE_H_ 1 + +#ifdef CONFIG_IDE_8xx_PCCARD +int pcmcia_on(void); +extern int ide_devices_found; +#endif +#endif diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 11e9eacf77..9bbdc5debf 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -53,10 +53,6 @@ # include #endif -#ifdef CONFIG_IDE_8xx_DIRECT -DECLARE_GLOBAL_DATA_PTR; -#endif - #ifdef __PPC__ # define EIEIO __asm__ volatile ("eieio") # define SYNC __asm__ volatile ("sync") @@ -65,45 +61,6 @@ DECLARE_GLOBAL_DATA_PTR; # define SYNC /* nothing */ #endif -#ifdef CONFIG_IDE_8xx_DIRECT -/* Timings for IDE Interface - * - * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk - * 70 165 30 PIO-Mode 0, [ns] - * 4 9 2 [Cycles] - * 50 125 20 PIO-Mode 1, [ns] - * 3 7 2 [Cycles] - * 30 100 15 PIO-Mode 2, [ns] - * 2 6 1 [Cycles] - * 30 80 10 PIO-Mode 3, [ns] - * 2 5 1 [Cycles] - * 25 70 10 PIO-Mode 4, [ns] - * 2 4 1 [Cycles] - */ - -const static pio_config_t pio_config_ns [IDE_MAX_PIO_MODE+1] = -{ - /* Setup Length Hold */ - { 70, 165, 30 }, /* PIO-Mode 0, [ns] */ - { 50, 125, 20 }, /* PIO-Mode 1, [ns] */ - { 30, 101, 15 }, /* PIO-Mode 2, [ns] */ - { 30, 80, 10 }, /* PIO-Mode 3, [ns] */ - { 25, 70, 10 }, /* PIO-Mode 4, [ns] */ -}; - -static pio_config_t pio_config_clk [IDE_MAX_PIO_MODE+1]; - -#ifndef CONFIG_SYS_PIO_MODE -#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */ -#endif -static int pio_mode = CONFIG_SYS_PIO_MODE; - -/* Make clock cycles and always round up */ - -#define PCMCIA_MK_CLKS( t, T ) (( (t) * (T) + 999U ) / 1000U ) - -#endif /* CONFIG_IDE_8xx_DIRECT */ - /* ------------------------------------------------------------------------- */ /* Current I/O Device */ @@ -166,10 +123,6 @@ ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer); #endif -#ifdef CONFIG_IDE_8xx_DIRECT -static void set_pcmcia_timing (int pmode); -#endif - /* ------------------------------------------------------------------------- */ int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) @@ -392,22 +345,14 @@ inline int ide_set_piomode(int pio_mode) void ide_init(void) { - -#ifdef CONFIG_IDE_8xx_DIRECT - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); -#endif unsigned char c; int i, bus; #ifdef CONFIG_IDE_8xx_PCCARD - extern int pcmcia_on(void); extern int ide_devices_found; /* Initialized in check_ide_device() */ #endif /* CONFIG_IDE_8xx_PCCARD */ #ifdef CONFIG_IDE_PREINIT - extern int ide_preinit(void); - WATCHDOG_RESET(); if (ide_preinit()) { @@ -416,40 +361,8 @@ void ide_init(void) } #endif /* CONFIG_IDE_PREINIT */ -#ifdef CONFIG_IDE_8xx_PCCARD - extern int pcmcia_on(void); - extern int ide_devices_found; /* Initialized in check_ide_device() */ - WATCHDOG_RESET(); - ide_devices_found = 0; - /* initialize the PCMCIA IDE adapter card */ - pcmcia_on(); - if (!ide_devices_found) - return; - udelay(1000000); /* 1 s */ -#endif /* CONFIG_IDE_8xx_PCCARD */ - - WATCHDOG_RESET(); - -#ifdef CONFIG_IDE_8xx_DIRECT - /* Initialize PIO timing tables */ - for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) { - pio_config_clk[i].t_setup = - PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk); - pio_config_clk[i].t_length = - PCMCIA_MK_CLKS(pio_config_ns[i].t_length, - gd->bus_clk); - pio_config_clk[i].t_hold = - PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk); - debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk" - " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup, - pio_config_clk[i].t_setup, pio_config_ns[i].t_length, - pio_config_clk[i].t_length, pio_config_ns[i].t_hold, - pio_config_clk[i].t_hold); - } -#endif /* CONFIG_IDE_8xx_DIRECT */ - /* * Reset the IDE just to be sure. * Light LED's to show @@ -459,14 +372,14 @@ void ide_init(void) /* ATAPI Drives seems to need a proper IDE Reset */ ide_reset(); -#ifdef CONFIG_IDE_8xx_DIRECT - /* PCMCIA / IDE initialization for common mem space */ - pcmp->pcmc_pgcrb = 0; +#ifdef CONFIG_IDE_INIT_POSTRESET + WATCHDOG_RESET(); - /* start in PIO mode 0 - most relaxed timings */ - pio_mode = 0; - set_pcmcia_timing(pio_mode); -#endif /* CONFIG_IDE_8xx_DIRECT */ + if (ide_init_postreset()) { + puts("ide_preinit_postreset failed\n"); + return; + } +#endif /* CONFIG_IDE_INIT_POSTRESET */ /* * Wait for IDE to get ready. @@ -568,95 +481,6 @@ block_dev_desc_t *ide_get_dev(int dev) } #endif - -#ifdef CONFIG_IDE_8xx_DIRECT - -static void set_pcmcia_timing(int pmode) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia); - ulong timings; - - debug("Set timing for PIO Mode %d\n", pmode); - - timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold) - | PCMCIA_SST(pio_config_clk[pmode].t_setup) - | PCMCIA_SL(pio_config_clk[pmode].t_length); - - /* - * IDE 0 - */ - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0; - pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 -#if (CONFIG_SYS_PCMCIA_POR0 != 0) - | timings -#endif - ; - debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0); - - pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1; - pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 -#if (CONFIG_SYS_PCMCIA_POR1 != 0) - | timings -#endif - ; - debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1); - - pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2; - pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 -#if (CONFIG_SYS_PCMCIA_POR2 != 0) - | timings -#endif - ; - debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2); - - pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3; - pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 -#if (CONFIG_SYS_PCMCIA_POR3 != 0) - | timings -#endif - ; - debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3); - - /* - * IDE 1 - */ - pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4; - pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 -#if (CONFIG_SYS_PCMCIA_POR4 != 0) - | timings -#endif - ; - debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4); - - pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5; - pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 -#if (CONFIG_SYS_PCMCIA_POR5 != 0) - | timings -#endif - ; - debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5); - - pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6; - pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 -#if (CONFIG_SYS_PCMCIA_POR6 != 0) - | timings -#endif - ; - debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6); - - pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7; - pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 -#if (CONFIG_SYS_PCMCIA_POR7 != 0) - | timings -#endif - ; - debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7); - -} - -#endif /* CONFIG_IDE_8xx_DIRECT */ - /* ------------------------------------------------------------------------- */ /* We only need to swap data if we are running on a big endian cpu. */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index fc226f1984..e102c365c4 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -480,6 +480,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index 81f219c9b5..b58b6f638c 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -349,6 +349,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index f98a66bf24..092fcf0641 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -318,6 +318,8 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index d6e9b2381d..38837cab46 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -312,6 +312,8 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index c0035e65de..dae9b8c079 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -353,6 +353,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index 5084cccad8..cceee96742 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -366,6 +366,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h index e8d0cd775b..7145cc4446 100644 --- a/include/configs/MBX.h +++ b/include/configs/MBX.h @@ -276,6 +276,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 604938d8b1..074e01f0fa 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -629,6 +629,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 9f462f4b5e..f4184fcd8f 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -318,6 +318,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index 9befacbaba..868a0b8044 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -329,6 +329,7 @@ */ #if 1 +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index b215c2d642..3595200c45 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -314,6 +314,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 8ffb014fe8..563abea95e 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -249,6 +249,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index f8bcf0fae2..67ab1e962b 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -335,6 +335,7 @@ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 671d52168a..e2b22f0bae 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -329,6 +329,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index cffeb11447..72ea217e54 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -303,6 +303,8 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ #define CONFIG_IDE_LED 1 /* LED for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h index 4176c7fe56..623cb6636b 100644 --- a/include/configs/TK885D.h +++ b/include/configs/TK885D.h @@ -343,6 +343,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index a01b4a6bef..9fac5d15c7 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -335,6 +335,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 1da4acd455..932f158b2c 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -331,6 +331,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 1c054f0bc6..eb08de2814 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -320,6 +320,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 46066dfb4c..bf3a76ca8c 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -322,6 +322,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index dd2da9410c..43dd64356c 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -324,6 +324,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 95bc4d964c..e7fd2db28e 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -359,6 +359,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 487666ce55..81e1b91ee7 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -323,6 +323,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index e8b77ea71a..ed496a1825 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -324,6 +324,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 334b7ecc17..1559336ec1 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -327,6 +327,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 1e2ad40d91..61dcf627d7 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -328,6 +328,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index a13c16aa5a..7d0ae99cb1 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -356,6 +356,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 7df76fbf02..7941631b51 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -341,6 +341,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/atc.h b/include/configs/atc.h index 75f950b94c..538a167528 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -482,6 +482,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index 566c42b6be..41ff00847a 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -302,6 +302,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index ab86053039..df4978161e 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -494,6 +494,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/quantum.h b/include/configs/quantum.h index 4f246510fe..072bd9c7ee 100644 --- a/include/configs/quantum.h +++ b/include/configs/quantum.h @@ -317,6 +317,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 91686d66a7..2b24997f80 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -359,6 +359,8 @@ #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ +#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ #define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h index 8c8fb5ae69..450c98bd3a 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -331,6 +331,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 4bb96cc1ab..c2c0d1d243 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -329,6 +329,7 @@ *----------------------------------------------------------------------- */ +#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/include/ide.h b/include/ide.h index 95dcbdd362..3a08425eeb 100644 --- a/include/ide.h +++ b/include/ide.h @@ -54,6 +54,14 @@ void ide_init(void); ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer); ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer); +#ifdef CONFIG_IDE_PREINIT +int ide_preinit(void); +#endif + +#ifdef CONFIG_IDE_INIT_POSTRESET +int ide_init_postreset(void); +#endif + #if defined(CONFIG_OF_IDE_FIXUP) int ide_device_present(int dev); #endif -- cgit v1.2.3 From e4148c1165d11807e51a9587716e6a513ce1c021 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Sun, 7 Oct 2012 05:56:07 +0000 Subject: split IVM power hooks from cmd_ide.c Move power control code from ide_reset() into IVM-specific IDE reset code. Signed-off-by: Pavel Herrmann --- board/ivm/ivm.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ common/cmd_ide.c | 48 ------------------------------------------------ 2 files changed, 46 insertions(+), 48 deletions(-) diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c index 71d64d434f..ab294794bd 100644 --- a/board/ivm/ivm.c +++ b/board/ivm/ivm.c @@ -333,13 +333,59 @@ void show_boot_progress (int status) void ide_set_reset (int on) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + int i; /* * Configure PC for IDE Reset Pin */ if (on) { /* assert RESET */ immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); + +#ifdef CONFIG_SYS_PB_12V_ENABLE + /* 12V Enable output OFF */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE); + + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE); + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE); + immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE; + + /* wait 500 ms for the voltage to stabilize */ + for (i = 0; i < 500; ++i) + udelay(1000); +#endif /* CONFIG_SYS_PB_12V_ENABLE */ } else { /* release RESET */ +#ifdef CONFIG_SYS_PB_12V_ENABLE + /* 12V Enable output ON */ + immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE; +#endif /* CONFIG_SYS_PB_12V_ENABLE */ + +#ifdef CONFIG_SYS_PB_IDE_MOTOR + /* configure IDE Motor voltage monitor pin as input */ + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR); + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR); + immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR); + +/* wait up to 1 s for the motor voltage to stabilize */ + for (i = 0; i < 1000; ++i) { + if ((immr->im_cpm.cp_pbdat + & CONFIG_SYS_PB_IDE_MOTOR) != 0) + break; + udelay(1000); + } + + if (i == 1000) { /* Timeout */ + printf("\nWarning: 5V for IDE Motor missing\n"); +#ifdef CONFIG_STATUS_LED +#ifdef STATUS_LED_YELLOW + status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON); +#endif +#ifdef STATUS_LED_GREEN + status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF); +#endif +#endif /* CONFIG_STATUS_LED */ + } +#endif /* CONFIG_SYS_PB_IDE_MOTOR */ + immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; } diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 9bbdc5debf..6b4813e4a9 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -1169,9 +1169,6 @@ extern void ide_set_reset(int idereset); static void ide_reset(void) { -#if defined(CONFIG_SYS_PB_12V_ENABLE) || defined(CONFIG_SYS_PB_IDE_MOTOR) - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; -#endif int i; curr_device = -1; @@ -1187,51 +1184,6 @@ static void ide_reset(void) WATCHDOG_RESET(); -#ifdef CONFIG_SYS_PB_12V_ENABLE - /* 12V Enable output OFF */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE); - - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE); - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE); - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE; - - /* wait 500 ms for the voltage to stabilize */ - for (i = 0; i < 500; ++i) - udelay(1000); - - /* 12V Enable output ON */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE; -#endif /* CONFIG_SYS_PB_12V_ENABLE */ - -#ifdef CONFIG_SYS_PB_IDE_MOTOR - /* configure IDE Motor voltage monitor pin as input */ - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR); - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR); - immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR); - - /* wait up to 1 s for the motor voltage to stabilize */ - for (i = 0; i < 1000; ++i) { - if ((immr->im_cpm.cp_pbdat & CONFIG_SYS_PB_IDE_MOTOR) != 0) { - break; - } - udelay(1000); - } - - if (i == 1000) { /* Timeout */ - printf("\nWarning: 5V for IDE Motor missing\n"); -#ifdef CONFIG_STATUS_LED -#ifdef STATUS_LED_YELLOW - status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON); -#endif -#ifdef STATUS_LED_GREEN - status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF); -#endif -#endif /* CONFIG_STATUS_LED */ - } -#endif /* CONFIG_SYS_PB_IDE_MOTOR */ - - WATCHDOG_RESET(); - /* de-assert RESET signal */ ide_set_reset(0); -- cgit v1.2.3 From f5b82c0f9c34ded68e346a0fe7ad13c3ff63f573 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Tue, 9 Oct 2012 07:04:39 +0000 Subject: change all versions of input_data() and output_data() to global weak aliases This changes input_data() and friends from static function to global symbols under weak alias, to enable board specific overrides (and therefore get rid of board-specific code in cmd_ide.c) Also declare ide_bus_offset in the header file, so other files can use ATA_CURR_BASE as well. Signed-off-by: Pavel Herrmann --- board/esd/cpci750/ide.c | 1 - board/linkstation/ide.c | 1 - board/pcs440ep/pcs440ep.c | 1 - common/cmd_ide.c | 57 ++++++++++++++++++++++++++++++----------------- include/ide.h | 11 +++++++++ 5 files changed, 48 insertions(+), 23 deletions(-) diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index aa001df0b8..4ef10e7d72 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -30,7 +30,6 @@ #include #include -extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; int cpci_hd_type; int ata_device(int dev) diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c index f3e3fce824..541c958fca 100644 --- a/board/linkstation/ide.c +++ b/board/linkstation/ide.c @@ -37,7 +37,6 @@ #define IT8212_PCI_IdeBusSkewCONTROL 0x4c #define IT8212_PCI_IdeDrivingCURRENT 0x42 -extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; extern struct pci_controller hose; int ide_preinit (void) diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 746a54c5e3..52da053a2f 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -672,7 +672,6 @@ U_BOOT_CMD( * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) * These values are shifted */ -extern ulong *ide_bus_offset; void inline ide_outb(int dev, int port, unsigned char val) { debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 6b4813e4a9..b9feb8046a 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -109,8 +109,6 @@ static uchar ide_wait (int dev, ulong t); #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */ -static void input_data(int dev, ulong *sect_buf, int words); -static void output_data(int dev, const ulong *sect_buf, int words); static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); #ifndef CONFIG_SYS_ATA_PORT_ADDR @@ -483,12 +481,24 @@ block_dev_desc_t *ide_get_dev(int dev) /* ------------------------------------------------------------------------- */ +void ide_input_swap_data(int dev, ulong *sect_buf, int words) + __attribute__ ((weak, alias("__ide_input_swap_data"))); + +void ide_input_data(int dev, ulong *sect_buf, int words) + __attribute__ ((weak, alias("__ide_input_data"))); + +void ide_output_data(int dev, const ulong *sect_buf, int words) + __attribute__ ((weak, alias("__ide_output_data"))); + /* We only need to swap data if we are running on a big endian cpu. */ /* But Au1x00 cpu:s already swaps data in big endian mode! */ #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SOC_AU1X00) -#define input_swap_data(x,y,z) input_data(x,y,z) +void __ide_input_swap_data(int dev, ulong *sect_buf, int words) +{ + ide_input_data(dev, sect_buf, words); +} #else -static void input_swap_data(int dev, ulong *sect_buf, int words) +void __ide_input_swap_data(int dev, ulong *sect_buf, int words) { #if defined(CONFIG_CPC45) uchar i; @@ -531,7 +541,7 @@ static void input_swap_data(int dev, ulong *sect_buf, int words) #if defined(CONFIG_IDE_SWAP_IO) -static void output_data(int dev, const ulong *sect_buf, int words) +void __ide_output_data(int dev, const ulong *sect_buf, int words) { #if defined(CONFIG_CPC45) uchar *dbuf; @@ -574,7 +584,7 @@ static void output_data(int dev, const ulong *sect_buf, int words) #endif } #else /* ! CONFIG_IDE_SWAP_IO */ -static void output_data(int dev, const ulong *sect_buf, int words) +void __ide_output_data(int dev, const ulong *sect_buf, int words) { #if defined(CONFIG_IDE_AHB) ide_write_data(dev, sect_buf, words); @@ -585,7 +595,7 @@ static void output_data(int dev, const ulong *sect_buf, int words) #endif /* CONFIG_IDE_SWAP_IO */ #if defined(CONFIG_IDE_SWAP_IO) -static void input_data(int dev, ulong *sect_buf, int words) +void __ide_input_data(int dev, ulong *sect_buf, int words) { #if defined(CONFIG_CPC45) uchar *dbuf; @@ -634,7 +644,7 @@ static void input_data(int dev, ulong *sect_buf, int words) #endif } #else /* ! CONFIG_IDE_SWAP_IO */ -static void input_data(int dev, ulong *sect_buf, int words) +void __ide_input_data(int dev, ulong *sect_buf, int words) { #if defined(CONFIG_IDE_AHB) ide_read_data(dev, sect_buf, words); @@ -744,7 +754,7 @@ static void ide_ident(block_dev_desc_t *dev_desc) return; #endif - input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS); + ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS); ident_cpy((unsigned char *) dev_desc->revision, iop.fw_rev, sizeof(dev_desc->revision)); @@ -1006,7 +1016,7 @@ ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer) break; } - input_data(device, buffer, ATA_SECTORWORDS); + ide_input_data(device, buffer, ATA_SECTORWORDS); (void) ide_inb(device, ATA_STATUS); /* clear IRQ */ ++n; @@ -1099,7 +1109,7 @@ ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer) goto WR_OUT; } - output_data(device, buffer, ATA_SECTORWORDS); + ide_output_data(device, buffer, ATA_SECTORWORDS); c = ide_inb(device, ATA_STATUS); /* clear IRQ */ ++n; ++blknr; @@ -1232,10 +1242,17 @@ int ide_device_present(int dev) * ATAPI Support */ +void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) + __attribute__ ((weak, alias("__ide_input_data_shorts"))); + +void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) + __attribute__ ((weak, alias("__ide_output_data_shorts"))); + + #if defined(CONFIG_IDE_SWAP_IO) /* since ATAPI may use commands with not 4 bytes alligned length * we have our own transfer functions, 2 bytes alligned */ -static void output_data_shorts(int dev, ushort *sect_buf, int shorts) +void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) { #if defined(CONFIG_CPC45) uchar *dbuf; @@ -1267,7 +1284,7 @@ static void output_data_shorts(int dev, ushort *sect_buf, int shorts) #endif } -static void input_data_shorts(int dev, ushort *sect_buf, int shorts) +void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) { #if defined(CONFIG_CPC45) uchar *dbuf; @@ -1300,12 +1317,12 @@ static void input_data_shorts(int dev, ushort *sect_buf, int shorts) } #else /* ! CONFIG_IDE_SWAP_IO */ -static void output_data_shorts(int dev, ushort *sect_buf, int shorts) +void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) { outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); } -static void input_data_shorts(int dev, ushort *sect_buf, int shorts) +void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) { insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); } @@ -1384,7 +1401,7 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen, } /* write command block */ - output_data_shorts(device, (unsigned short *) ccb, ccblen / 2); + ide_output_data_shorts(device, (unsigned short *) ccb, ccblen / 2); /* ATAPI Command written wait for completition */ udelay(5000); /* device must set bsy */ @@ -1435,12 +1452,12 @@ unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen, /* ok now decide if it is an in or output */ if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) { debug("Write to device\n"); - output_data_shorts(device, (unsigned short *) buffer, - n); + ide_output_data_shorts(device, + (unsigned short *) buffer, n); } else { debug("Read from device @ %p shorts %d\n", buffer, n); - input_data_shorts(device, (unsigned short *) buffer, - n); + ide_input_data_shorts(device, + (unsigned short *) buffer, n); } } udelay(5000); /* seems that some CD ROMs need this... */ diff --git a/include/ide.h b/include/ide.h index 3a08425eeb..695d08eecc 100644 --- a/include/ide.h +++ b/include/ide.h @@ -27,6 +27,7 @@ #define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS)) #define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) +extern ulong ide_bus_offset[]; #ifdef CONFIG_IDE_LED @@ -72,4 +73,14 @@ void ide_write_register(int dev, unsigned int port, unsigned char val); void ide_read_data(int dev, ulong *sect_buf, int words); void ide_write_data(int dev, ulong *sect_buf, int words); #endif + +/* + * I/O function overrides + */ +void ide_input_swap_data(int dev, ulong *sect_buf, int words); +void ide_input_data(int dev, ulong *sect_buf, int words); +void ide_output_data(int dev, const ulong *sect_buf, int words); +void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts); +void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts); + #endif /* _IDE_H */ -- cgit v1.2.3 From 28920b1fd297cb95ca3e7b6e782929158a8c0aa2 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Sun, 7 Oct 2012 05:56:09 +0000 Subject: split CPC45 board-specific IDE functions from cmd_ide.c Move input_data() and friends to board/cpc45/ide.c, as overrides for weak aliases in cmd_ide.c note: checkpatch emits warnings about using volatile Signed-off-by: Pavel Herrmann --- board/cpc45/Makefile | 2 +- board/cpc45/ide.c | 130 +++++++++++++++++++++++++++++++++++++++++++++++++++ common/cmd_ide.c | 91 ------------------------------------ 3 files changed, 131 insertions(+), 92 deletions(-) create mode 100644 board/cpc45/ide.c diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile index 5c6b78f704..ac1d17440f 100644 --- a/board/cpc45/Makefile +++ b/board/cpc45/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o flash.o plx9030.o pd67290.o +COBJS = $(BOARD).o flash.o plx9030.o pd67290.o ide.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cpc45/ide.c b/board/cpc45/ide.c new file mode 100644 index 0000000000..7b7237b908 --- /dev/null +++ b/board/cpc45/ide.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2000-2011 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define EIEIO __asm__ volatile ("eieio") +#define SYNC __asm__ volatile ("sync") + +void ide_input_swap_data(int dev, ulong *sect_buf, int words) +{ + uchar i; + volatile uchar *pbuf_even = + (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + volatile uchar *pbuf_odd = + (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + ushort *dbuf = (ushort *) sect_buf; + + while (words--) { + for (i = 0; i < 2; i++) { + *(((uchar *) (dbuf)) + 1) = *pbuf_even; + *(uchar *) dbuf = *pbuf_odd; + dbuf += 1; + } + } +} + +void ide_input_data(int dev, ulong *sect_buf, int words) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (words--) { + *dbuf++ = *pbuf_even; + EIEIO; + SYNC; + *dbuf++ = *pbuf_odd; + EIEIO; + SYNC; + *dbuf++ = *pbuf_even; + EIEIO; + SYNC; + *dbuf++ = *pbuf_odd; + EIEIO; + SYNC; + } +} + +void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (shorts--) { + EIEIO; + *dbuf++ = *pbuf_even; + EIEIO; + *dbuf++ = *pbuf_odd; + } +} + +void ide_output_data(int dev, const ulong *sect_buf, int words) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (words--) { + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + } +} + +void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + uchar *dbuf; + volatile uchar *pbuf_even; + volatile uchar *pbuf_odd; + + pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); + pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); + dbuf = (uchar *) sect_buf; + while (shorts--) { + EIEIO; + *pbuf_even = *dbuf++; + EIEIO; + *pbuf_odd = *dbuf++; + } +} diff --git a/common/cmd_ide.c b/common/cmd_ide.c index b9feb8046a..ab790f6753 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -500,22 +500,6 @@ void __ide_input_swap_data(int dev, ulong *sect_buf, int words) #else void __ide_input_swap_data(int dev, ulong *sect_buf, int words) { -#if defined(CONFIG_CPC45) - uchar i; - volatile uchar *pbuf_even = - (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - volatile uchar *pbuf_odd = - (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - ushort *dbuf = (ushort *) sect_buf; - - while (words--) { - for (i = 0; i < 2; i++) { - *(((uchar *) (dbuf)) + 1) = *pbuf_even; - *(uchar *) dbuf = *pbuf_odd; - dbuf += 1; - } - } -#else volatile ushort *pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf = (ushort *) sect_buf; @@ -535,7 +519,6 @@ void __ide_input_swap_data(int dev, ulong *sect_buf, int words) *dbuf++ = ld_le16(pbuf); #endif /* !MIPS */ } -#endif } #endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */ @@ -543,25 +526,6 @@ void __ide_input_swap_data(int dev, ulong *sect_buf, int words) #if defined(CONFIG_IDE_SWAP_IO) void __ide_output_data(int dev, const ulong *sect_buf, int words) { -#if defined(CONFIG_CPC45) - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (words--) { - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - } -#else ushort *dbuf; volatile ushort *pbuf; @@ -581,7 +545,6 @@ void __ide_output_data(int dev, const ulong *sect_buf, int words) *pbuf = *dbuf++; #endif } -#endif } #else /* ! CONFIG_IDE_SWAP_IO */ void __ide_output_data(int dev, const ulong *sect_buf, int words) @@ -597,29 +560,6 @@ void __ide_output_data(int dev, const ulong *sect_buf, int words) #if defined(CONFIG_IDE_SWAP_IO) void __ide_input_data(int dev, ulong *sect_buf, int words) { -#if defined(CONFIG_CPC45) - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - dbuf = (uchar *) sect_buf; - while (words--) { - *dbuf++ = *pbuf_even; - EIEIO; - SYNC; - *dbuf++ = *pbuf_odd; - EIEIO; - SYNC; - *dbuf++ = *pbuf_even; - EIEIO; - SYNC; - *dbuf++ = *pbuf_odd; - EIEIO; - SYNC; - } -#else ushort *dbuf; volatile ushort *pbuf; @@ -641,7 +581,6 @@ void __ide_input_data(int dev, ulong *sect_buf, int words) *dbuf++ = *pbuf; #endif } -#endif } #else /* ! CONFIG_IDE_SWAP_IO */ void __ide_input_data(int dev, ulong *sect_buf, int words) @@ -1254,20 +1193,6 @@ void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) * we have our own transfer functions, 2 bytes alligned */ void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) { -#if defined(CONFIG_CPC45) - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - while (shorts--) { - EIEIO; - *pbuf_even = *dbuf++; - EIEIO; - *pbuf_odd = *dbuf++; - } -#else ushort *dbuf; volatile ushort *pbuf; @@ -1281,25 +1206,10 @@ void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) EIEIO; *pbuf = *dbuf++; } -#endif } void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) { -#if defined(CONFIG_CPC45) - uchar *dbuf; - volatile uchar *pbuf_even; - volatile uchar *pbuf_odd; - - pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN); - pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD); - while (shorts--) { - EIEIO; - *dbuf++ = *pbuf_even; - EIEIO; - *dbuf++ = *pbuf_odd; - } -#else ushort *dbuf; volatile ushort *pbuf; @@ -1313,7 +1223,6 @@ void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) EIEIO; *dbuf++ = *pbuf; } -#endif } #else /* ! CONFIG_IDE_SWAP_IO */ -- cgit v1.2.3 From 19be2ea2ef41300fd720b229caa764d70de48297 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Sun, 7 Oct 2012 05:56:10 +0000 Subject: make ide_led() a weak alias Make ide_led() a weak alias instead of global/local function/empty macro based on CONFIG_IDE_LED value and/or board-specific CONFIGs, to get rid of board-specific code in cmd_ide.c Define dummy values to get rid of compoler errors in case where ide_led() used to be an empty macro Signed-off-by: Pavel Herrmann --- common/cmd_ide.c | 63 ++++++++++++++++++++++++-------------------------------- 1 file changed, 27 insertions(+), 36 deletions(-) diff --git a/common/cmd_ide.c b/common/cmd_ide.c index ab790f6753..7eb19cf2cf 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -81,19 +81,6 @@ static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS]; block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE]; /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_IDE_LED -# if !defined(CONFIG_BMS2003) && \ - !defined(CONFIG_CPC45) && \ - !defined(CONFIG_KUP4K) && \ - !defined(CONFIG_KUP4X) -static void ide_led (uchar led, uchar status); -#else -extern void ide_led (uchar led, uchar status); -#endif -#else -#define ide_led(a,b) /* dummy */ -#endif - #ifdef CONFIG_IDE_RESET static void ide_reset (void); #else @@ -290,6 +277,33 @@ int do_diskboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* ------------------------------------------------------------------------- */ +void __ide_led(uchar led, uchar status) +{ +#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */ + static uchar led_buffer; /* Buffer for current LED status */ + + uchar *led_port = LED_PORT; + + if (status) /* switch LED on */ + led_buffer |= led; + else /* switch LED off */ + led_buffer &= ~led; + + *led_port = led_buffer; +#endif +} + +void ide_led(uchar led, uchar status) + __attribute__ ((weak, alias("__ide_led"))); + +#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */ +# define DEVICE_LED(x) 0 +# define LED_IDE1 1 +# define LED_IDE2 2 +#endif + +/* ------------------------------------------------------------------------- */ + inline void __ide_outb(int dev, int port, unsigned char val) { debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", @@ -442,9 +456,7 @@ void ide_init(void) curr_device = -1; for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) { -#ifdef CONFIG_IDE_LED int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2; -#endif ide_dev_desc[i].type = DEV_TYPE_UNKNOWN; ide_dev_desc[i].if_type = IF_TYPE_IDE; ide_dev_desc[i].dev = i; @@ -1145,27 +1157,6 @@ static void ide_reset(void) /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_IDE_LED) && \ - !defined(CONFIG_CPC45) && \ - !defined(CONFIG_KUP4K) && \ - !defined(CONFIG_KUP4X) - -static uchar led_buffer; /* Buffer for current LED status */ - -static void ide_led(uchar led, uchar status) -{ - uchar *led_port = LED_PORT; - - if (status) /* switch LED on */ - led_buffer |= led; - else /* switch LED off */ - led_buffer &= ~led; - - *led_port = led_buffer; -} - -#endif /* CONFIG_IDE_LED */ - #if defined(CONFIG_OF_IDE_FIXUP) int ide_device_present(int dev) { -- cgit v1.2.3 From 0a4a64c07983be76a2b25242094a19b282b36577 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Tue, 9 Oct 2012 07:06:25 +0000 Subject: move CPC45 ide_led to the same file as other IDE hooks Keep all IDE-related hooks and overrides in a single file, to avoid confusion Signed-off-by: Pavel Herrmann --- board/cpc45/cpc45.c | 15 --------------- board/cpc45/ide.c | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c index 1178822db3..22008066e6 100644 --- a/board/cpc45/cpc45.c +++ b/board/cpc45/cpc45.c @@ -260,21 +260,6 @@ int pcmcia_init(void) #endif -# ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - u_char val; - /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ - val = readb(BCSR_BASE + 0x04); - if (status) { /* led on */ - val |= B_CTRL_LED0; - } else { - val &= ~B_CTRL_LED0; - } - writeb(val, BCSR_BASE + 0x04); -} -# endif - int board_eth_init(bd_t *bis) { return pci_eth_init(bis); diff --git a/board/cpc45/ide.c b/board/cpc45/ide.c index 7b7237b908..03be59f974 100644 --- a/board/cpc45/ide.c +++ b/board/cpc45/ide.c @@ -27,6 +27,7 @@ #include #include #include +#include #define EIEIO __asm__ volatile ("eieio") #define SYNC __asm__ volatile ("sync") @@ -128,3 +129,17 @@ void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) *pbuf_odd = *dbuf++; } } + +void ide_led(uchar led, uchar status) +{ + u_char val; + /* We have one PCMCIA slot and use LED H4 for the IDE Interface */ + val = readb(BCSR_BASE + 0x04); + if (status) /* led on */ + val |= B_CTRL_LED0; + else + val &= ~B_CTRL_LED0; + + writeb(val, BCSR_BASE + 0x04); +} + -- cgit v1.2.3 From 4d1361d86773fce10352bd35729ce74036d5acb0 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Tue, 9 Oct 2012 07:10:08 +0000 Subject: split AU1X00 specific code from cmd_ide.c move special case of ide_swap_read() for AU1X00 SoC into SoC-specific directory. Signed-off-by: Pavel Herrmann --- arch/mips/cpu/mips32/au1x00/Makefile | 2 +- arch/mips/cpu/mips32/au1x00/au1x00_ide.c | 32 ++++++++++++++++++++++++++++++++ common/cmd_ide.c | 5 ++--- 3 files changed, 35 insertions(+), 4 deletions(-) create mode 100644 arch/mips/cpu/mips32/au1x00/au1x00_ide.c diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile index dc58475f68..b9f895df5b 100644 --- a/arch/mips/cpu/mips32/au1x00/Makefile +++ b/arch/mips/cpu/mips32/au1x00/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o +COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_ide.c b/arch/mips/cpu/mips32/au1x00/au1x00_ide.c new file mode 100644 index 0000000000..932cdfb9bb --- /dev/null +++ b/arch/mips/cpu/mips32/au1x00/au1x00_ide.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2000-2011 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include + +/* AU1X00 swaps data in big-endian mode, enforce little-endian function */ +void ide_input_swap_data(int dev, ulong *sect_buf, int words) +{ + ide_input_data(dev, sect_buf, words); +} diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 7eb19cf2cf..5b46e3ca5e 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -503,8 +503,7 @@ void ide_output_data(int dev, const ulong *sect_buf, int words) __attribute__ ((weak, alias("__ide_output_data"))); /* We only need to swap data if we are running on a big endian cpu. */ -/* But Au1x00 cpu:s already swaps data in big endian mode! */ -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SOC_AU1X00) +#if defined(__LITTLE_ENDIAN) void __ide_input_swap_data(int dev, ulong *sect_buf, int words) { ide_input_data(dev, sect_buf, words); @@ -532,7 +531,7 @@ void __ide_input_swap_data(int dev, ulong *sect_buf, int words) #endif /* !MIPS */ } } -#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */ +#endif /* __LITTLE_ENDIAN */ #if defined(CONFIG_IDE_SWAP_IO) -- cgit v1.2.3 From 21d2bf426f15f4f2f184e9f4afcc279feeeba854 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Sun, 7 Oct 2012 05:56:13 +0000 Subject: split PCS440EP specific code from cmd_ide.c Move specific ide_input_data and friends to board-specific file. Signed-off-by: Pavel Herrmann --- board/pcs440ep/pcs440ep.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++ common/cmd_ide.c | 18 --------------- 2 files changed, 56 insertions(+), 18 deletions(-) diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 52da053a2f..f8345ddb46 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -32,6 +32,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -713,3 +714,58 @@ void ide_set_reset (int idereset) udelay (10000); } #endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + + +/* this is motly the same as it should, causing a little code duplication */ +#if defined(CONFIG_CMD_IDE) +#define EIEIO __asm__ volatile ("eieio") + +void ide_input_swap_data(int dev, ulong *sect_buf, int words) +{ + volatile ushort *pbuf = + (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); + ushort *dbuf = (ushort *) sect_buf; + + debug("in input swap data base for read is %lx\n", + (unsigned long) pbuf); + + while (words--) { + *dbuf++ = *pbuf; + *dbuf++ = *pbuf; + } +} + +void ide_output_data(int dev, const ulong *sect_buf, int words) +{ + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); + dbuf = (ushort *) sect_buf; + while (words--) { + EIEIO; + *pbuf = ld_le16(dbuf++); + EIEIO; + *pbuf = ld_le16(dbuf++); + } +} + +void ide_input_data(int dev, ulong *sect_buf, int words) +{ + ushort *dbuf; + volatile ushort *pbuf; + + pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); + dbuf = (ushort *) sect_buf; + + debug("in input data base for read is %lx\n", (unsigned long) pbuf); + + while (words--) { + EIEIO; + *dbuf++ = ld_le16(pbuf); + EIEIO; + *dbuf++ = ld_le16(pbuf); + } +} + +#endif diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 5b46e3ca5e..1c6ad32db1 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -522,9 +522,6 @@ void __ide_input_swap_data(int dev, ulong *sect_buf, int words) #ifdef __MIPS__ *dbuf++ = swab16p((u16 *) pbuf); *dbuf++ = swab16p((u16 *) pbuf); -#elif defined(CONFIG_PCS440EP) - *dbuf++ = *pbuf; - *dbuf++ = *pbuf; #else *dbuf++ = ld_le16(pbuf); *dbuf++ = ld_le16(pbuf); @@ -543,18 +540,10 @@ void __ide_output_data(int dev, const ulong *sect_buf, int words) pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *) sect_buf; while (words--) { -#if defined(CONFIG_PCS440EP) - /* not tested, because CF was write protected */ - EIEIO; - *pbuf = ld_le16(dbuf++); - EIEIO; - *pbuf = ld_le16(dbuf++); -#else EIEIO; *pbuf = *dbuf++; EIEIO; *pbuf = *dbuf++; -#endif } } #else /* ! CONFIG_IDE_SWAP_IO */ @@ -580,17 +569,10 @@ void __ide_input_data(int dev, ulong *sect_buf, int words) debug("in input data base for read is %lx\n", (unsigned long) pbuf); while (words--) { -#if defined(CONFIG_PCS440EP) - EIEIO; - *dbuf++ = ld_le16(pbuf); - EIEIO; - *dbuf++ = ld_le16(pbuf); -#else EIEIO; *dbuf++ = *pbuf; EIEIO; *dbuf++ = *pbuf; -#endif } } #else /* ! CONFIG_IDE_SWAP_IO */ -- cgit v1.2.3 From 8af4472a775e5719127cd109cd5e7f2bde470131 Mon Sep 17 00:00:00 2001 From: Pavel Herrmann Date: Sun, 7 Oct 2012 05:56:14 +0000 Subject: remove unnecessary includes from cmd_ide.c mpc8xx and mpc5xxx specific includes in cmd_ide.c are not required, remove them. Signed-off-by: Pavel Herrmann --- common/cmd_ide.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 1c6ad32db1..d508e9f75b 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -38,14 +38,6 @@ # include #endif -#ifdef CONFIG_8xx -# include -#endif - -#ifdef CONFIG_MPC5xxx -#include -#endif - #include #include -- cgit v1.2.3 From 71bba424adcfa8c44100dee0fd139cc057eace65 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 07:45:54 +0000 Subject: disk: get_device_and_partition() return value fixes When no valid partitions are found, guarantee that we return -1. This most likely already happens, since the most recent get_partition_info() will have returned an error. However, it's best to be explicit. Remove an unnecessary assignment of ret=0 in the success case; this value is over-written with the processed partition ID later. Signed-off-by: Stephen Warren --- disk/part.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disk/part.c b/disk/part.c index 30229692fb..a0c77ddc9d 100644 --- a/disk/part.c +++ b/disk/part.c @@ -624,9 +624,9 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str, */ if (p == MAX_SEARCH_PARTITIONS + 1) *info = tmpinfo; - ret = 0; } else { printf("** No valid partitions found **\n"); + ret = -1; goto cleanup; } } -- cgit v1.2.3 From 38a3021edc5421a2fae90d57112d001d74bba1fa Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:32 +0000 Subject: disk: part_efi: remove indent level from loop Simplify the partition printing loop in print_part_efi() to bail out early when the first invalid partition is found, rather than indenting the whole body of the loop. This simplifies later patches. Signed-off-by: Stephen Warren --- disk/part_efi.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 264ea9c77f..008177ecb0 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -138,15 +138,14 @@ void print_part_efi(block_dev_desc_t * dev_desc) printf("Part\tName\t\t\tStart LBA\tEnd LBA\n"); for (i = 0; i < le32_to_int(gpt_head->num_partition_entries); i++) { + /* Stop at the first non valid PTE */ + if (!is_pte_valid(&gpt_pte[i])) + break; - if (is_pte_valid(&gpt_pte[i])) { - printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1), - print_efiname(&gpt_pte[i]), - le64_to_int(gpt_pte[i].starting_lba), - le64_to_int(gpt_pte[i].ending_lba)); - } else { - break; /* Stop at the first non valid PTE */ - } + printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1), + print_efiname(&gpt_pte[i]), + le64_to_int(gpt_pte[i].starting_lba), + le64_to_int(gpt_pte[i].ending_lba)); } /* Remember to free pte */ -- cgit v1.2.3 From 788a8c1fc9d27aa9f07d85425783bfce6ebe974a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:33 +0000 Subject: disk: part_efi: re-order partition list printf, change case The partition name is a long variable-length string. Move it last on the line to ensure consistent layout and that the entries align with the "header" line. Also, surround it in quotes, so if it's empty, it's obvious that something is still being printed. Also, change the case of the LBA numbers; lower-case looks nicer in my opinion, and will be more consistent with the UUID printing that is added later in this series. Signed-off-by: Stephen Warren --- disk/part_efi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 008177ecb0..b6b2bf505e 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -136,16 +136,16 @@ void print_part_efi(block_dev_desc_t * dev_desc) debug("%s: gpt-entry at %p\n", __func__, gpt_pte); - printf("Part\tName\t\t\tStart LBA\tEnd LBA\n"); + printf("Part\tStart LBA\tEnd LBA\t\tName\n"); for (i = 0; i < le32_to_int(gpt_head->num_partition_entries); i++) { /* Stop at the first non valid PTE */ if (!is_pte_valid(&gpt_pte[i])) break; - printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1), - print_efiname(&gpt_pte[i]), + printf("%3d\t0x%08llx\t0x%08llx\t\"%s\"\n", (i + 1), le64_to_int(gpt_pte[i].starting_lba), - le64_to_int(gpt_pte[i].ending_lba)); + le64_to_int(gpt_pte[i].ending_lba), + print_efiname(&gpt_pte[i])); } /* Remember to free pte */ -- cgit v1.2.3 From f07cd2c4c703cb07ca595fb0b7e3aa3c4ed8b540 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:34 +0000 Subject: disk: part_efi: print partition UUIDs When printing the partition table, print the partition type UUID and the individual partition UUID. Do this unconditionally, since partition UUIDs are useful. Signed-off-by: Stephen Warren --- disk/part_efi.c | 50 ++++++++++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index b6b2bf505e..6b80cd98d4 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -113,6 +113,26 @@ static char *print_efiname(gpt_entry *pte) return name; } +static void uuid_string(unsigned char *uuid, char *str) +{ + static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, + 12, 13, 14, 15}; + int i; + + for (i = 0; i < 16; i++) { + sprintf(str, "%02x", uuid[le[i]]); + str += 2; + switch (i) { + case 3: + case 5: + case 7: + case 9: + *str++ = '-'; + break; + } + } +} + /* * Public Functions (include/part.h) */ @@ -122,6 +142,7 @@ void print_part_efi(block_dev_desc_t * dev_desc) ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1); gpt_entry *gpt_pte = NULL; int i = 0; + char uuid[37]; if (!dev_desc) { printf("%s: Invalid Argument(s)\n", __func__); @@ -137,6 +158,9 @@ void print_part_efi(block_dev_desc_t * dev_desc) debug("%s: gpt-entry at %p\n", __func__, gpt_pte); printf("Part\tStart LBA\tEnd LBA\t\tName\n"); + printf("\tType UUID\n"); + printf("\tPartition UUID\n"); + for (i = 0; i < le32_to_int(gpt_head->num_partition_entries); i++) { /* Stop at the first non valid PTE */ if (!is_pte_valid(&gpt_pte[i])) @@ -146,6 +170,10 @@ void print_part_efi(block_dev_desc_t * dev_desc) le64_to_int(gpt_pte[i].starting_lba), le64_to_int(gpt_pte[i].ending_lba), print_efiname(&gpt_pte[i])); + uuid_string(gpt_pte[i].partition_type_guid.b, uuid); + printf("\ttype:\t%s\n", uuid); + uuid_string(gpt_pte[i].unique_partition_guid.b, uuid); + printf("\tuuid:\t%s\n", uuid); } /* Remember to free pte */ @@ -153,28 +181,6 @@ void print_part_efi(block_dev_desc_t * dev_desc) return; } -#ifdef CONFIG_PARTITION_UUIDS -static void uuid_string(unsigned char *uuid, char *str) -{ - static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, - 12, 13, 14, 15}; - int i; - - for (i = 0; i < 16; i++) { - sprintf(str, "%02x", uuid[le[i]]); - str += 2; - switch (i) { - case 3: - case 5: - case 7: - case 9: - *str++ = '-'; - break; - } - } -} -#endif - int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, disk_partition_t * info) { -- cgit v1.2.3 From 1c8346ab38a981559a25492dcdfda211cb09aab4 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:35 +0000 Subject: disk: part_efi: add new partition attribute definitions Add no_block_io_protocol and legacy_bios_bootable attribute definitions. These are sourced from UEFI Spec 2.3, page 105, table 19. Credits to the libparted source for the specification pointer. Signed-off-by: Stephen Warren --- disk/part_efi.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/disk/part_efi.h b/disk/part_efi.h index 5903e7c812..1d0c67cbe0 100644 --- a/disk/part_efi.h +++ b/disk/part_efi.h @@ -113,7 +113,9 @@ typedef struct _gpt_header { typedef struct _gpt_entry_attributes { unsigned long long required_to_function:1; - unsigned long long reserved:47; + unsigned long long no_block_io_protocol:1; + unsigned long long legacy_bios_bootable:1; + unsigned long long reserved:45; unsigned long long type_guid_specific:16; } __attribute__ ((packed)) gpt_entry_attributes; -- cgit v1.2.3 From 13bf2f55d9ea6620f0bcdc4a9f0b67f6ec81885f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:36 +0000 Subject: disk: part_efi: print raw partition attributes When printing the EFI partition table, print the raw attributes. Convert struct gpt_entry_attributes to a union to allow raw access. Signed-off-by: Stephen Warren --- disk/part_efi.c | 2 ++ disk/part_efi.h | 15 +++++++++------ 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 6b80cd98d4..d563509584 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -158,6 +158,7 @@ void print_part_efi(block_dev_desc_t * dev_desc) debug("%s: gpt-entry at %p\n", __func__, gpt_pte); printf("Part\tStart LBA\tEnd LBA\t\tName\n"); + printf("\tAttributes\n"); printf("\tType UUID\n"); printf("\tPartition UUID\n"); @@ -170,6 +171,7 @@ void print_part_efi(block_dev_desc_t * dev_desc) le64_to_int(gpt_pte[i].starting_lba), le64_to_int(gpt_pte[i].ending_lba), print_efiname(&gpt_pte[i])); + printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw); uuid_string(gpt_pte[i].partition_type_guid.b, uuid); printf("\ttype:\t%s\n", uuid); uuid_string(gpt_pte[i].unique_partition_guid.b, uuid); diff --git a/disk/part_efi.h b/disk/part_efi.h index 1d0c67cbe0..4e28d1dcb6 100644 --- a/disk/part_efi.h +++ b/disk/part_efi.h @@ -111,12 +111,15 @@ typedef struct _gpt_header { unsigned char reserved2[GPT_BLOCK_SIZE - 92]; } __attribute__ ((packed)) gpt_header; -typedef struct _gpt_entry_attributes { - unsigned long long required_to_function:1; - unsigned long long no_block_io_protocol:1; - unsigned long long legacy_bios_bootable:1; - unsigned long long reserved:45; - unsigned long long type_guid_specific:16; +typedef union _gpt_entry_attributes { + struct { + unsigned long long required_to_function:1; + unsigned long long no_block_io_protocol:1; + unsigned long long legacy_bios_bootable:1; + unsigned long long reserved:45; + unsigned long long type_guid_specific:16; + } fields; + unsigned long long raw; } __attribute__ ((packed)) gpt_entry_attributes; #define PARTNAME_SZ (72 / sizeof(efi_char16_t)) -- cgit v1.2.3 From b4414f4a4a8986378a33600046cbe1a917267119 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:37 +0000 Subject: disk: part_efi: set bootable flag in partition objects A partition is considered bootable if it either has the "legacy BIOS bootable" flag set, or if the partition type UUID matches the standard "system" type. Signed-off-by: Stephen Warren --- disk/part_efi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/disk/part_efi.c b/disk/part_efi.c index d563509584..7a39d52f8e 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -133,6 +133,15 @@ static void uuid_string(unsigned char *uuid, char *str) } } +static efi_guid_t system_guid = PARTITION_SYSTEM_GUID; + +static inline int is_bootable(gpt_entry *p) +{ + return p->attributes.fields.legacy_bios_bootable || + !memcmp(&(p->partition_type_guid), &system_guid, + sizeof(efi_guid_t)); +} + /* * Public Functions (include/part.h) */ @@ -219,6 +228,7 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, sprintf((char *)info->name, "%s", print_efiname(&gpt_pte[part - 1])); sprintf((char *)info->type, "U-Boot"); + info->bootable = is_bootable(&gpt_pte[part - 1]); #ifdef CONFIG_PARTITION_UUIDS uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid); #endif -- cgit v1.2.3 From 304b57113041bdbef00ef79b963a569abbc787f9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:38 +0000 Subject: disk: part_dos: checkpatch cleanups Minor cleanups required so later patches don't trigger checkpatch. Signed-off-by: Stephen Warren --- disk/part_dos.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/disk/part_dos.c b/disk/part_dos.c index 5c454e65ab..513a54a094 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -65,7 +65,8 @@ static inline int is_bootable(dos_partition_t *p) return p->boot_ind == 0x80; } -static void print_one_part (dos_partition_t *p, int ext_part_sector, int part_num) +static void print_one_part(dos_partition_t *p, int ext_part_sector, + int part_num) { int lba_start = ext_part_sector + le32_to_int (p->start4); int lba_size = le32_to_int (p->size4); @@ -105,8 +106,9 @@ int test_part_dos (block_dev_desc_t *dev_desc) /* Print a partition that is relative to its Extended partition table */ -static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative, - int part_num) +static void print_partition_extended(block_dev_desc_t *dev_desc, + int ext_part_sector, int relative, + int part_num) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); dos_partition_t *pt; @@ -135,7 +137,7 @@ static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_s if ((pt->sys_ind != 0) && (ext_part_sector == 0 || !is_extended (pt->sys_ind)) ) { - print_one_part (pt, ext_part_sector, part_num); + print_one_part(pt, ext_part_sector, part_num); } /* Reverse engr the fdisk part# assignment rule! */ @@ -151,10 +153,9 @@ static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_s if (is_extended (pt->sys_ind)) { int lba_start = le32_to_int (pt->start4) + relative; - print_partition_extended (dev_desc, lba_start, - ext_part_sector == 0 ? lba_start - : relative, - part_num); + print_partition_extended(dev_desc, lba_start, + ext_part_sector == 0 ? lba_start : relative, + part_num); } } @@ -261,8 +262,8 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part void print_part_dos (block_dev_desc_t *dev_desc) { - printf ("Partition Start Sector Num Sectors Type\n"); - print_partition_extended (dev_desc, 0, 0, 1); + printf("Partition Start Sector Num Sectors Type\n"); + print_partition_extended(dev_desc, 0, 0, 1); } int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition_t * info) -- cgit v1.2.3 From e2e9b37898c4d9f7330ce256d95a37da5064e0cf Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 8 Oct 2012 08:14:40 +0000 Subject: disk: part_dos: print partition UUID in partition list This information may be useful to compare against command "part uuid", or if you want to manually paste the information into the kernel command-line. Signed-off-by: Stephen Warren [trini: print_one_part / print_part_dos output strings didn't quite match before the changes] Signed-off-by: Tom Rini --- disk/part_dos.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/disk/part_dos.c b/disk/part_dos.c index 513a54a094..3fe901ba1b 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -66,13 +66,13 @@ static inline int is_bootable(dos_partition_t *p) } static void print_one_part(dos_partition_t *p, int ext_part_sector, - int part_num) + int part_num, unsigned int disksig) { int lba_start = ext_part_sector + le32_to_int (p->start4); int lba_size = le32_to_int (p->size4); - printf("%5d\t\t%10d\t%10d\t%2x%s%s\n", - part_num, lba_start, lba_size, p->sys_ind, + printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n", + part_num, lba_start, lba_size, disksig, part_num, p->sys_ind, (is_extended(p->sys_ind) ? " Extd" : ""), (is_bootable(p) ? " Boot" : "")); } @@ -108,7 +108,7 @@ int test_part_dos (block_dev_desc_t *dev_desc) */ static void print_partition_extended(block_dev_desc_t *dev_desc, int ext_part_sector, int relative, - int part_num) + int part_num, unsigned int disksig) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); dos_partition_t *pt; @@ -127,6 +127,9 @@ static void print_partition_extended(block_dev_desc_t *dev_desc, return; } + if (!ext_part_sector) + disksig = le32_to_int(&buffer[DOS_PART_DISKSIG_OFFSET]); + /* Print all primary/logical partitions */ pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); for (i = 0; i < 4; i++, pt++) { @@ -137,7 +140,7 @@ static void print_partition_extended(block_dev_desc_t *dev_desc, if ((pt->sys_ind != 0) && (ext_part_sector == 0 || !is_extended (pt->sys_ind)) ) { - print_one_part(pt, ext_part_sector, part_num); + print_one_part(pt, ext_part_sector, part_num, disksig); } /* Reverse engr the fdisk part# assignment rule! */ @@ -155,7 +158,7 @@ static void print_partition_extended(block_dev_desc_t *dev_desc, print_partition_extended(dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, - part_num); + part_num, disksig); } } @@ -262,8 +265,8 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part void print_part_dos (block_dev_desc_t *dev_desc) { - printf("Partition Start Sector Num Sectors Type\n"); - print_partition_extended(dev_desc, 0, 0, 1); + printf("Part\tStart Sector\tNum Sectors\tUUID\t\tType\n"); + print_partition_extended(dev_desc, 0, 0, 1, 0); } int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition_t * info) -- cgit v1.2.3 From ff04f6d1224d8952b566b8671222151495883073 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 9 Oct 2012 07:20:22 +0000 Subject: fs: fat: Fix mkcksum() function parameters The mkcksum() function now takes one parameter, the pointer to 11-byte wide character array, which it then operates on. Currently, the function is wrongly passed (dir_entry)->name, which is only 8-byte wide character array. Though by further inspecting the dir_entry structure, it can be noticed that the name[8] entry is immediatelly followed by ext[3] entry. Thus, name[8] and ext[3] in the dir_entry structure actually work as this 11-byte wide array since they're placed right next to each other by current compiler behavior. Depending on this is obviously wrong, thus fix this by correctly passing both (dir_entry)->name and (dir_entry)->ext to the mkcksum() function and adjust the function appropriately. Signed-off-by: Marek Vasut Cc: Tom Rini --- fs/fat/fat.c | 20 ++++++++++++-------- fs/fat/fat_write.c | 2 +- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 80156c815f..4a60a2503e 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -567,15 +567,16 @@ get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, } /* Calculate short name checksum */ -static __u8 mkcksum(const char *str) +static __u8 mkcksum(const char name[8], const char ext[3]) { int i; __u8 ret = 0; - for (i = 0; i < 11; i++) { - ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + str[i]; - } + for (i = 0; i < sizeof(name); i++) + ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + name[i]; + for (i = 0; i < sizeof(ext); i++) + ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + ext[i]; return ret; } @@ -678,7 +679,8 @@ static dir_entry *get_dentfromdir(fsdata *mydata, int startsect, return NULL; } #ifdef CONFIG_SUPPORT_VFAT - if (dols && mkcksum(dentptr->name) == prevcksum) { + __u8 csum = mkcksum(dentptr->name, dentptr->ext); + if (dols && csum == prevcksum) { prevcksum = 0xffff; dentptr++; continue; @@ -946,13 +948,16 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, for (i = 0; i < DIRENTSPERBLOCK; i++) { char s_name[14], l_name[VFAT_MAXLEN_BYTES]; + __u8 csum; l_name[0] = '\0'; if (dentptr->name[0] == DELETED_FLAG) { dentptr++; continue; } - if ((dentptr->attr & ATTR_VOLUME)) { + + csum = mkcksum(dentptr->name, dentptr->ext); + if (dentptr->attr & ATTR_VOLUME) { #ifdef CONFIG_SUPPORT_VFAT if ((dentptr->attr & ATTR_VFAT) == ATTR_VFAT && (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { @@ -1015,8 +1020,7 @@ do_fat_read_at(const char *filename, unsigned long pos, void *buffer, goto exit; } #ifdef CONFIG_SUPPORT_VFAT - else if (dols == LS_ROOT && - mkcksum(dentptr->name) == prevcksum) { + else if (dols == LS_ROOT && csum == prevcksum) { prevcksum = 0xffff; dentptr++; continue; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 5829adf1a1..4a1bda0a37 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -335,7 +335,7 @@ fill_dir_slot(fsdata *mydata, dir_entry **dentptr, const char *l_name) /* Get short file name and checksum value */ strncpy(s_name, (*dentptr)->name, 16); - checksum = mkcksum(s_name); + checksum = mkcksum((*dentptr)->name, (*dentptr)->ext); do { memset(slotptr, 0x00, sizeof(dir_slot)); -- cgit v1.2.3 From 12c79a957804c13c2ba8e6606990fd6bd1f55e9a Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Wed, 26 Sep 2012 11:43:54 +0000 Subject: powerpc: delete Wind River SBC8560/8540 support The sbc8548/60 (both similar, just variations in UART hardware) support has been removed from the linux kernel as of v3.6-rc1~132 so lets also now remove it from the u-boot tree as well. Signed-off-by: Paul Gortmaker --- MAINTAINERS | 2 - board/sbc8560/Makefile | 50 ----- board/sbc8560/README | 57 ------ board/sbc8560/ddr.c | 43 ----- board/sbc8560/law.c | 60 ------ board/sbc8560/sbc8560.c | 369 ------------------------------------- board/sbc8560/tlb.c | 65 ------- boards.cfg | 6 - include/configs/SBC8540.h | 428 ------------------------------------------ include/configs/sbc8560.h | 459 ---------------------------------------------- 10 files changed, 1539 deletions(-) delete mode 100644 board/sbc8560/Makefile delete mode 100644 board/sbc8560/README delete mode 100644 board/sbc8560/ddr.c delete mode 100644 board/sbc8560/law.c delete mode 100644 board/sbc8560/sbc8560.c delete mode 100644 board/sbc8560/tlb.c delete mode 100644 include/configs/SBC8540.h delete mode 100644 include/configs/sbc8560.h diff --git a/MAINTAINERS b/MAINTAINERS index 971235bbca..ff8e47caac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -214,9 +214,7 @@ Siddarth Gore Paul Gortmaker sbc8349 MPC8349 - sbc8540 MPC8540 sbc8548 MPC8548 - sbc8560 MPC8560 sbc8641d MPC8641D Frank Gottschling diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile deleted file mode 100644 index ce0156040a..0000000000 --- a/board/sbc8560/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2004-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 Wind River Systems Inc . -# Added support for Wind River SBC8560 board -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sbc8560/README b/board/sbc8560/README deleted file mode 100644 index c4b642236e..0000000000 --- a/board/sbc8560/README +++ /dev/null @@ -1,57 +0,0 @@ -The port was tested on Wind River System Sbc8560 board -. U-Boot was installed on the flash memory of the -CPU card (no the SODIMM). - -NOTE: Please configure uboot compile to the proper PCI frequency and -setup the appropriate DIP switch settings. - -SBC8560 board: - -Make sure boards switches are set to their appropriate conditions. -Refer to the Engineering Reference Guide ERG-00300-002. Of particular -importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which -select the on-board FLASH device (Intel 28F128Jx); 2) The settings -for the Clock SW9 (33 MHz or 66 MHz). - - Note: SW9 Settings: 66 MHz - 4:1 ratio CCB clocks:SYSCLK - 3:1 ration e500 Core:CCB - pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on - Note: SW9 Settings: 33 MHz - 8:1 ratio CCB clocks:SYSCLK - 3:1 ration e500 Core:CCB - pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on - - -Flashing the FLASH device with the "Wind River ICE": - -1) Properly connect and configure the Wind River ICE to the target - JTAG port. This includes running the SBC8560 register script. Make - sure target memory can be read and written. - -2) Build the u-boot image: - make distclean - make SBC8560_66_config or SBC8560_33_config - make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all - - Note: reference is made to the ELDK3.0 compiler. Further, it seems - the ppc_8xx compiler is required for the 85xx (no 85xx - designated compiler in ELDK3.0) - -3) Convert the uboot (.elf) file to a uboot.bin file (using - visionClick converter). The bin file should be converted from - fffc0000 to ffffffff - -4) Setup the Flash Utility (tools menu) for: - - Do a "dc clr" [visionClick] to load the default register settings - Determine the clock speed of the PCI bus and set SW9 accordingly - Note: the speed of the PCI bus defaults to the slowest PCI card - PlayBack the "default" register file for the SBC8560 - Select the uboot.bin file with zero bias - Select the initialize Target prior to programming - Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm - Select the erase base address from FFFC0000 to FFFFFFFF - Select the start address from 0 with size of 4000 - -5) Erase and Program diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c deleted file mode 100644 index e9babc6477..0000000000 --- a/board/sbc8560/ddr.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c deleted file mode 100644 index 4e6baed2f4..0000000000 --- a/board/sbc8560/law.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* LAW(Local Access Window) configuration: - * 0000_0000-0800_0000: DDR(512M) -or- larger - * c000_0000-cfff_ffff: PCI(256M) - * d000_0000-dfff_ffff: RapidIO(256M) - * e000_0000-ffff_ffff: localbus(512M) - * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 - * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 - * e800_0000-efff_ffff: LBC 128M, nothing here - * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 - * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 - * f800_0000-fdff_ffff: LBC 64M, nothing here - * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 - * fd00_0000-fdff_ffff: LBC 16M, nothing here - * fe00_0000-feff_ffff: LBC 16M, nothing here - * ff00_0000-ff6f_ffff: LBC 7M, nothing here - * ff70_0000-ff7f_ffff: CCSRBAR 1M - * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 - * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access - * Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c deleted file mode 100644 index 98bc7df4c8..0000000000 --- a/board/sbc8560/sbc8560.c +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -int board_early_init_f (void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xfffffffdf; /* disable master abort */ -#endif - return 0; -} - -void reset_phy (void) -{ -#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR; -#endif - /* reset Giga bit Ethernet port if needed here */ - - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr[0] &= ~0x20; - udelay(2); - bcsr[0] |= 0x20; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr[0] &= ~0x10; - udelay(2); - bcsr[0] |= 0x10; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -} - -int checkboard (void) -{ - sys_info_t sysinfo; - char buf[32]; - - get_sys_info (&sysinfo); - -#ifdef CONFIG_SBC8560 - printf ("Board: Wind River SBC8560 Board\n"); -#else - printf ("Board: Wind River SBC8540 Board\n"); -#endif - printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0])); - printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus)); - printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2)); - if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ - || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) { - printf ("\tLBC: %s MHz\n", - strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f))); - } else { - printf("\tLBC: unknown\n"); - } - printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus)); - printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); - return (0); -} - - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 - - #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - -#if (CONFIG_SYS_SDRAM_SIZE == 512) - ddr->cs0_bnds = 0x0000000f; -#else - ddr->cs0_bnds = 0x00000007; -#endif - ddr->cs1_bnds = 0x0010001f; - ddr->cs2_bnds = 0x00000000; - ddr->cs3_bnds = 0x00000000; - ddr->cs0_config = 0x80000102; - ddr->cs1_config = 0x80000102; - ddr->cs2_config = 0x00000000; - ddr->cs3_config = 0x00000000; - ddr->timing_cfg_1 = 0x37334321; - ddr->timing_cfg_2 = 0x00000800; - ddr->sdram_cfg = 0x42000000; - ddr->sdram_mode = 0x00000022; - ddr->sdram_interval = 0x05200100; - ddr->err_sbe = 0x00ff0000; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - int node; -#ifdef CONFIG_PCI - const char *path; -#endif - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } -} -#endif diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c deleted file mode 100644 index fe0ac763af..0000000000 --- a/board/sbc8560/tlb.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { -/* TLB for CCSRBAR (IMMR) */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -/* TLB for Local Bus stuff, just map the whole 512M */ -/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ - - SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_256M, 1), -#endif - - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_16K, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index a5af63c1ba..df62251253 100644 --- a/boards.cfg +++ b/boards.cfg @@ -682,17 +682,11 @@ suvd3 powerpc mpc83xx km83xx keymile tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,TUGE1 tuxx1 powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,KMSUPX5 -sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 -sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 -sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 sbc8548 powerpc mpc85xx sbc8548 - - sbc8548 sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33 sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66 sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE -sbc8560 powerpc mpc85xx sbc8560 - - sbc8560 -sbc8560_33 powerpc mpc85xx sbc8560 - - sbc8560 -sbc8560_66 powerpc mpc85xx sbc8560 - - sbc8560 socrates powerpc mpc85xx socrates HWW1U1A powerpc mpc85xx hww1u1a exmeritus MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h deleted file mode 100644 index d448bf6650..0000000000 --- a/include/configs/SBC8540.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8540 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * sbc8540 board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_66 -#define CONFIG_PCI_66 -#endif - -#define TSEC_DEBUG - -/* - * High Level Configuration Options - */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - -#define CONFIG_SYS_TEXT_BASE 0xfffc0000 - - -#define CONFIG_CPM2 1 /* has CPM2 */ - -#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ -#define CONFIG_MPC8540 1 - -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ - -/* DDR Setup */ -#define CONFIG_FSL_DDR1 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_SPD - -#if defined(CONFIG_MPC85xx_REV1) -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ -#endif - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CONFIG_SYS_OR2_PRELIM 0x00000000 - -#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1 - -#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CONFIG_SYS_OR5_PRELIM 0xff000ff7 -#else - #define CONFIG_SYS_OR5_PRELIM 0xff0000f0 -#endif - -#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7 -#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#if 0 -#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#else -#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */ -#endif - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#if 0 -#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000) -#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000) -#else -/* SBC8540 uses internal COMM controller */ -#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500) -#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600) -#endif - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - -# define CONFIG_MPC85xx_TSEC1 -# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" -# define CONFIG_MII 1 /* MII PHY management */ -# define TSEC1_PHY_ADDR 25 -# define TSEC1_PHYIDX 0 -/* Options are: TSEC0 */ -# define CONFIG_ETHPRIME "TSEC0" - - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) - #define MDC_DECLARE MDIO_DECLARE - - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) - #define CONFIG_SYS_RAMBOOT -#else - #undef CONFIG_SYS_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CONFIG_SYS_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_ENV_IS_NOWHERE - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) - #define CONFIG_ENV_SIZE 0x2000 - #else - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */ - #endif -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ - #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*Note: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a -# define CONFIG_HAS_ETH1 -# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b -# define CONFIG_HAS_ETH2 -# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c -#endif - -#define CONFIG_SERVERIP YourServerIP -#define CONFIG_IPADDR YourTargetIP -#define CONFIG_GATEWAYIP YourGatewayIP -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH "YourRootPath" -#define CONFIG_BOOTFILE "YourImageName" - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h deleted file mode 100644 index 46d60985d3..0000000000 --- a/include/configs/sbc8560.h +++ /dev/null @@ -1,459 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * (C) Copyright 2004 Wind River Systems Inc . - * Added support for Wind River SBC8560 board - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * sbc8560 board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_66 -#define CONFIG_PCI_66 -#endif - -/* - * High Level Configuration Options - */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ - -#define CONFIG_SYS_TEXT_BASE 0xfffc0000 - - -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ -#define CONFIG_MPC8560 1 - -/* XXX flagging this as something I might want to delete */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_PCI /* pci ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_ENV_OVERWRITE - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you need a flash-boot image(u-boot.bin), if so undef this. - */ -#undef CONFIG_RAM_AS_FLASH - -#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ - #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ -#else - #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." -#endif - -#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ - -/* DDR Setup */ -#define CONFIG_FSL_DDR1 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_SPD - -#if defined(CONFIG_MPC85xx_REV1) -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ -#endif - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ -#else /* Boot from real Flash */ - #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ - #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */ - #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ -#endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* local bus definitions */ -#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */ -#define CONFIG_SYS_OR2_PRELIM 0x00000000 - -#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1 - -#if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ -#else - #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ -#endif -#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1 - -#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ -#if 1 - #define CONFIG_SYS_OR5_PRELIM 0xff000ff7 -#else - #define CONFIG_SYS_OR5_PRELIM 0xff0000f0 -#endif - -#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ -#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7 -#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -/* just hijack the MOT BCSR def for SBC8560 misc devices */ -#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000) -/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */ -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000) -#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#ifdef CONFIG_TSEC_ENET - -#ifndef CONFIG_MII -#define CONFIG_MII 1 /* MII PHY management */ -#endif -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0x19 -#define TSEC2_PHY_ADDR 0x1a -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - - #undef CONFIG_ETHER_NONE /* define if ether on something else */ - #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ - #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - - #if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - - #elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #endif /* CONFIG_ETHER_INDEX */ - - #define CONFIG_MII /* MII PHY management */ - #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - /* - * GPIO pins used for bit-banged MII communications - */ - #define MDIO_PORT 2 /* Port C */ - #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) - #define MDC_DECLARE MDIO_DECLARE - - #define MDIO_ACTIVE (iop->pdir |= 0x00400000) - #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) - #define MDIO_READ ((iop->pdat & 0x00400000) != 0) - - #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - - #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - - #define MIIDELAY udelay(1) - -#endif - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#if 0 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ -#endif -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if 0 -/* XXX This doesn't work and I don't want to fix it */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) - #define CONFIG_SYS_RAMBOOT -#else - #undef CONFIG_SYS_RAMBOOT -#endif -#endif - -/* Environment */ -#if !defined(CONFIG_SYS_RAMBOOT) - #if defined(CONFIG_RAM_AS_FLASH) - #define CONFIG_ENV_IS_NOWHERE - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) - #define CONFIG_ENV_SIZE 0x2000 - #else - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */ - #endif -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600" -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -/* You can compile in a MAC address and your custom net settings by using - * the following syntax. Your board should be marked with the assigned - * MAC addresses directly on it. - * - * #define CONFIG_ETHADDR de:ad:be:ef:00:00 - * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s! - * #define CONFIG_SERVERIP - * #define CONFIG_IPADDR - * #define CONFIG_GATEWAYIP - * #define CONFIG_NETMASK - */ - -#define CONFIG_HOSTNAME SBC8560 -#define CONFIG_ROOTPATH "/home/ppc" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=sbc8560.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From d731282e7c210bb002cc0a2f3859be4efd3120c7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Jul 2012 05:02:21 +0000 Subject: dm: wdt: arm: Move tnetv107x into drivers/watchdog/ Signed-off-by: Marek Vasut Cc: Oliver Brown Cc: Wolfgang Denk Cc: Albert Aribaud Cc: U-Boot DM --- arch/arm/cpu/arm1176/tnetv107x/Makefile | 2 +- arch/arm/cpu/arm1176/tnetv107x/wdt.c | 180 -------------------------------- drivers/watchdog/Makefile | 1 + drivers/watchdog/tnetv107x_wdt.c | 180 ++++++++++++++++++++++++++++++++ include/configs/tnetv107x_evm.h | 1 + 5 files changed, 183 insertions(+), 181 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/wdt.c create mode 100644 drivers/watchdog/tnetv107x_wdt.c diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile index c63dc925ef..c1d4d678c0 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile @@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += aemif.o clock.o init.o mux.o timer.o wdt.o +COBJS += aemif.o clock.o init.o mux.o timer.o SOBJS += lowlevel_init.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/arm1176/tnetv107x/wdt.c b/arch/arm/cpu/arm1176/tnetv107x/wdt.c deleted file mode 100644 index 18aadb0c65..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/wdt.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * TNETV107X: Watchdog timer implementation (for reset) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include - -#define MAX_DIV 0xFFFE0001 - -struct wdt_regs { - u32 kick_lock; -#define KICK_LOCK_1 0x5555 -#define KICK_LOCK_2 0xaaaa - u32 kick; - - u32 change_lock; -#define CHANGE_LOCK_1 0x6666 -#define CHANGE_LOCK_2 0xbbbb - u32 change; - - u32 disable_lock; -#define DISABLE_LOCK_1 0x7777 -#define DISABLE_LOCK_2 0xcccc -#define DISABLE_LOCK_3 0xdddd - u32 disable; - - u32 prescale_lock; -#define PRESCALE_LOCK_1 0x5a5a -#define PRESCALE_LOCK_2 0xa5a5 - u32 prescale; -}; - -static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE; - -#define wdt_reg_read(reg) __raw_readl(®s->reg) -#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg) - -static int write_prescale_reg(unsigned long prescale_value) -{ - wdt_reg_write(prescale_lock, PRESCALE_LOCK_1); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(prescale_lock, PRESCALE_LOCK_2); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(prescale, prescale_value); - - return 0; -} - -static int write_change_reg(unsigned long initial_timer_value) -{ - wdt_reg_write(change_lock, CHANGE_LOCK_1); - if ((wdt_reg_read(change_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(change_lock, CHANGE_LOCK_2); - if ((wdt_reg_read(change_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(change, initial_timer_value); - - return 0; -} - -static int wdt_control(unsigned long disable_value) -{ - wdt_reg_write(disable_lock, DISABLE_LOCK_1); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_2); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x2) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_3); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(disable, disable_value); - return 0; -} - -static int wdt_set_period(unsigned long msec) -{ - unsigned long change_value, count_value; - unsigned long prescale_value = 1; - unsigned long refclk_khz, maxdiv; - int ret; - - refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM); - maxdiv = (MAX_DIV / refclk_khz); - - if ((!msec) || (msec > maxdiv)) - return -1; - - count_value = refclk_khz * msec; - if (count_value > 0xffff) { - change_value = count_value / 0xffff + 1; - prescale_value = count_value / change_value; - } else { - change_value = count_value; - } - - ret = write_prescale_reg(prescale_value - 1); - if (ret) - return ret; - - ret = write_change_reg(change_value); - if (ret) - return ret; - - return 0; -} - -unsigned long last_wdt = -1; - -int wdt_start(unsigned long msecs) -{ - int ret; - ret = wdt_control(0); - if (ret) - return ret; - ret = wdt_set_period(msecs); - if (ret) - return ret; - ret = wdt_control(1); - if (ret) - return ret; - ret = wdt_kick(); - last_wdt = msecs; - return ret; -} - -int wdt_stop(void) -{ - last_wdt = -1; - return wdt_control(0); -} - -int wdt_kick(void) -{ - wdt_reg_write(kick_lock, KICK_LOCK_1); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(kick_lock, KICK_LOCK_2); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(kick, 1); - return 0; -} - -void reset_cpu(ulong addr) -{ - clk_enable(TNETV107X_LPSC_WDT_ARM); - wdt_start(1); - wdt_kick(); -} diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5579bf2f14..923acb9f3a 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o +COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/watchdog/tnetv107x_wdt.c b/drivers/watchdog/tnetv107x_wdt.c new file mode 100644 index 0000000000..18aadb0c65 --- /dev/null +++ b/drivers/watchdog/tnetv107x_wdt.c @@ -0,0 +1,180 @@ +/* + * TNETV107X: Watchdog timer implementation (for reset) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +#define MAX_DIV 0xFFFE0001 + +struct wdt_regs { + u32 kick_lock; +#define KICK_LOCK_1 0x5555 +#define KICK_LOCK_2 0xaaaa + u32 kick; + + u32 change_lock; +#define CHANGE_LOCK_1 0x6666 +#define CHANGE_LOCK_2 0xbbbb + u32 change; + + u32 disable_lock; +#define DISABLE_LOCK_1 0x7777 +#define DISABLE_LOCK_2 0xcccc +#define DISABLE_LOCK_3 0xdddd + u32 disable; + + u32 prescale_lock; +#define PRESCALE_LOCK_1 0x5a5a +#define PRESCALE_LOCK_2 0xa5a5 + u32 prescale; +}; + +static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE; + +#define wdt_reg_read(reg) __raw_readl(®s->reg) +#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg) + +static int write_prescale_reg(unsigned long prescale_value) +{ + wdt_reg_write(prescale_lock, PRESCALE_LOCK_1); + if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1) + return -1; + + wdt_reg_write(prescale_lock, PRESCALE_LOCK_2); + if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3) + return -1; + + wdt_reg_write(prescale, prescale_value); + + return 0; +} + +static int write_change_reg(unsigned long initial_timer_value) +{ + wdt_reg_write(change_lock, CHANGE_LOCK_1); + if ((wdt_reg_read(change_lock) & 0x3) != 0x1) + return -1; + + wdt_reg_write(change_lock, CHANGE_LOCK_2); + if ((wdt_reg_read(change_lock) & 0x3) != 0x3) + return -1; + + wdt_reg_write(change, initial_timer_value); + + return 0; +} + +static int wdt_control(unsigned long disable_value) +{ + wdt_reg_write(disable_lock, DISABLE_LOCK_1); + if ((wdt_reg_read(disable_lock) & 0x3) != 0x1) + return -1; + + wdt_reg_write(disable_lock, DISABLE_LOCK_2); + if ((wdt_reg_read(disable_lock) & 0x3) != 0x2) + return -1; + + wdt_reg_write(disable_lock, DISABLE_LOCK_3); + if ((wdt_reg_read(disable_lock) & 0x3) != 0x3) + return -1; + + wdt_reg_write(disable, disable_value); + return 0; +} + +static int wdt_set_period(unsigned long msec) +{ + unsigned long change_value, count_value; + unsigned long prescale_value = 1; + unsigned long refclk_khz, maxdiv; + int ret; + + refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM); + maxdiv = (MAX_DIV / refclk_khz); + + if ((!msec) || (msec > maxdiv)) + return -1; + + count_value = refclk_khz * msec; + if (count_value > 0xffff) { + change_value = count_value / 0xffff + 1; + prescale_value = count_value / change_value; + } else { + change_value = count_value; + } + + ret = write_prescale_reg(prescale_value - 1); + if (ret) + return ret; + + ret = write_change_reg(change_value); + if (ret) + return ret; + + return 0; +} + +unsigned long last_wdt = -1; + +int wdt_start(unsigned long msecs) +{ + int ret; + ret = wdt_control(0); + if (ret) + return ret; + ret = wdt_set_period(msecs); + if (ret) + return ret; + ret = wdt_control(1); + if (ret) + return ret; + ret = wdt_kick(); + last_wdt = msecs; + return ret; +} + +int wdt_stop(void) +{ + last_wdt = -1; + return wdt_control(0); +} + +int wdt_kick(void) +{ + wdt_reg_write(kick_lock, KICK_LOCK_1); + if ((wdt_reg_read(kick_lock) & 0x3) != 0x1) + return -1; + + wdt_reg_write(kick_lock, KICK_LOCK_2); + if ((wdt_reg_read(kick_lock) & 0x3) != 0x3) + return -1; + + wdt_reg_write(kick, 1); + return 0; +} + +void reset_cpu(ulong addr) +{ + clk_enable(TNETV107X_LPSC_WDT_ARM); + wdt_start(1); + wdt_kick(); +} diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h index 23cab88ded..d6371fce4d 100644 --- a/include/configs/tnetv107x_evm.h +++ b/include/configs/tnetv107x_evm.h @@ -32,6 +32,7 @@ #define CONFIG_ARM1176 #define CONFIG_TNETV107X #define CONFIG_TNETV107X_EVM +#define CONFIG_TNETV107X_WATCHDOG #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_DISABLE_TCM -- cgit v1.2.3 From fb24ffc086043530e1026cc9990955095125ea48 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Jul 2012 05:02:22 +0000 Subject: dm: Move s3c24xx USB driver to a proper place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marek Vasut Cc: David Müller Cc: Minkyu Kang Cc: Wolfgang Denk Cc: Albert Aribaud Cc: U-Boot DM --- arch/arm/cpu/arm920t/s3c24x0/Makefile | 3 - arch/arm/cpu/arm920t/s3c24x0/usb.c | 71 -- arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c | 1757 ------------------------------ arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h | 409 ------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ohci-s3c24xx.c | 1801 +++++++++++++++++++++++++++++++ drivers/usb/host/ohci-s3c24xx.h | 409 +++++++ include/configs/VCMA9.h | 1 + include/configs/smdk2410.h | 1 + 9 files changed, 2213 insertions(+), 2240 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/s3c24x0/usb.c delete mode 100644 arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c delete mode 100644 arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h create mode 100644 drivers/usb/host/ohci-s3c24xx.c create mode 100644 drivers/usb/host/ohci-s3c24xx.h diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile index 0029700e44..808ab8f0f2 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/Makefile +++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile @@ -29,9 +29,6 @@ COBJS-$(CONFIG_USE_IRQ) += interrupts.o COBJS-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o COBJS-y += speed.o COBJS-y += timer.o -COBJS-y += usb.o -COBJS-y += usb_ohci.o - SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c deleted file mode 100644 index 226a3f6c90..0000000000 --- a/arch/arm/cpu/arm920t/s3c24x0/usb.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2006 - * DENX Software Engineering - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if defined(CONFIG_USB_OHCI_NEW) && \ - defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ - defined(CONFIG_S3C24X0) - -#include -#include - -int usb_cpu_init(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); - - /* - * Set the 48 MHz UPLL clocking. Values are taken from - * "PLL value selection guide", 6-23, s3c2400_UM.pdf. - */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); - /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); - - /* - * Enable USB host clock. - */ - writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); - - return 0; -} - -int usb_cpu_stop(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - /* may not want to do this */ - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); - return 0; -} - -int usb_cpu_init_fail(void) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); - return 0; -} - -#endif /* defined(CONFIG_USB_OHCI_NEW) && \ - defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ - defined(CONFIG_S3C24X0) */ diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c deleted file mode 100644 index 944bb32f57..0000000000 --- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c +++ /dev/null @@ -1,1757 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400. - * - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering - * - * Note: Much of this code has been derived from Linux 2.4 - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2002 David Brownell - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -/* - * IMPORTANT NOTES - * 1 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include -/* #include no PCI on the S3C24X0 */ - -#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) - -#include -#include -#include -#include -#include "usb_ohci.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#undef OHCI_VERBOSE_DEBUG /* not always helpful */ - - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#define min_t(type, x, y) \ - ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) - -#undef DEBUG -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#undef SHOW_INFO -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -/* global struct ohci */ -static struct ohci gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -struct urb_priv urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; -/* flag guarding URB transation */ -int urb_finished = 0; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a(struct ohci *hc) -{ - return read_roothub(hc, a, 0xfc0fe000); -} -static inline u32 roothub_b(struct ohci *hc) -{ - return readl(&hc->regs->roothub.b); -} -static inline u32 roothub_status(struct ohci *hc) -{ - return readl(&hc->regs->roothub.status); -} -static u32 roothub_portstatus(struct ohci *hc, int i) -{ - return read_roothub(hc, portstatus[i], 0xffe0fce0); -} - -/* forward declaration */ -static int hc_interrupt(void); -static void td_submit_job(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, - struct devrequest *setup, struct urb_priv *urb, - int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv(struct urb_priv *urb) -{ - int i; - int last; - struct td *td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number(struct usb_device *dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, char *str, - int small) -{ - struct urb_priv *purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number(dev), - usb_pipedevice(pipe), - usb_pipeendpoint(pipe), - usb_pipeout(pipe) ? 'O' : 'I', - usb_pipetype(pipe) < 2 ? - (usb_pipeint(pipe) ? "INTR" : "ISOC") : - (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), - purb->actual_length, transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol(pipe)) { - printf(__FILE__ ": cmd(8):"); - for (i = 0; i < 8; i++) - printf(" %02x", ((__u8 *) setup)[i]); - printf("\n"); - } - if (transfer_len > 0 && buffer) { - printf(__FILE__ ": data(%d/%d):", - purb->actual_length, transfer_len); - len = usb_pipeout(pipe) ? - transfer_len : purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf(" %02x", ((__u8 *) buffer)[i]); - printf("%s\n", i < len ? "..." : ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the - int ed tree inclusive iso eds*/ -void ep_print_int_eds(struct ohci *ohci, char *str) -{ - int i, j; - __u32 *ed_p; - for (i = 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table[i]); - if (*ed_p == 0) - continue; - printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - struct ed *ed = (struct ed *) m32_swap(ed_p); - printf(" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf("\n"); - } -} - -static void ohci_dump_intr_mask(char *label, __u32 mask) -{ - dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : ""); -} - -static void maybe_print_eds(char *label, __u32 value) -{ - struct ed *edp = (struct ed *) value; - - if (value) { - dbg("%s %08x", label, value); - dbg("%08x", edp->hwINFO); - dbg("%08x", edp->hwTailP); - dbg("%08x", edp->hwHeadP); - dbg("%08x", edp->hwNextED); - } -} - -static char *hcfs2string(int state) -{ - switch (state) { - case OHCI_USB_RESET: - return "reset"; - case OHCI_USB_RESUME: - return "resume"; - case OHCI_USB_OPER: - return "operational"; - case OHCI_USB_SUSPEND: - return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status(struct ohci *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl(®s->revision) & 0xff; - if (temp != 0x10) - dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl(®s->control); - dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string(temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR); - - temp = readl(®s->cmdstatus); - dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : ""); - - ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus)); - ohci_dump_intr_mask("intrenable", readl(®s->intrenable)); - - maybe_print_eds("ed_periodcurrent", readl(®s->ed_periodcurrent)); - - maybe_print_eds("ed_controlhead", readl(®s->ed_controlhead)); - maybe_print_eds("ed_controlcurrent", readl(®s->ed_controlcurrent)); - - maybe_print_eds("ed_bulkhead", readl(®s->ed_bulkhead)); - maybe_print_eds("ed_bulkcurrent", readl(®s->ed_bulkcurrent)); - - maybe_print_eds("donehead", readl(®s->donehead)); -} - -static void ohci_dump_roothub(struct ohci *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a(controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", ndp); - temp = roothub_b(controller); - dbg("roothub.b: %08x PPCM=%04x DR=%04x", - temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR) - ); - temp = roothub_status(controller); - dbg("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : ""); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus(controller, i); - dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : ""); - } -} - -static void ohci_dump(struct ohci *controller, int verbose) -{ - dbg("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status(controller); - if (verbose) - ep_print_int_eds(controller, "hcca"); - dbg("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub(controller, 1); -} - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - struct ohci *ohci; - struct ed *ed; - struct urb_priv *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* if we have an unfinished URB from previous transaction let's - * fail and scream as quickly as possible so as not to corrupt - * further communication */ - if (!urb_finished) { - err("sohci_submit_job: URB NOT FINISHED"); - return -1; - } - /* we're about to begin a new transaction here - so mark the URB unfinished */ - urb_finished = 0; - - /* every endpoint has a ed, locate and fill it */ - ed = ep_add_ed(dev, pipe); - if (!ed) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype(pipe)) { - case PIPE_BULK: - /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: - /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc(dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv(purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv(purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link(ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, - interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number(struct usb_device *usb_dev) -{ - struct ohci *ohci = &gohci; - - return m16_swap(ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link(struct ohci *ohci, struct ed *edi) -{ - struct ed *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel((u32)ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel(ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel((u32)ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel(ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink(struct ohci *ohci, struct ed *ed) -{ - struct ed *next; - ed->hwINFO |= m32_swap(OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel(ohci->hc_control, &ohci->regs->control); - } - writel(m32_swap(*((__u32 *) &ed->hwNextED)), - &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED)); - next->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel(ohci->hc_control, &ohci->regs->control); - } - writel(m32_swap(*((__u32 *) &ed->hwNextED)), - &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED)); - next->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration - * command, but the USB stack is a little bit stateless so we do it at every - * transaction. If the state of the ed is ED_NEW then a dummy td is added and - * the state is changed to ED_UNLINK. In all other cases the state is left - * unchanged. The ed info fields are setted anyway even though most of them - * should not change */ - -static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe) -{ - struct td *td; - struct ed *ed_ret; - struct ed *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | - (usb_pipecontrol(pipe) ? 0 : - usb_pipeout(pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc(usb_dev); - ed->hwTailP = (__u32) m32_swap(td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype(pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = m32_swap(usb_pipedevice(pipe) - | usb_pipeendpoint(pipe) << 7 - | (usb_pipeisoc(pipe) ? 0x8000 : 0) - | (usb_pipecontrol(pipe) ? 0 : - (usb_pipeout(pipe) ? 0x800 : 0x1000)) - | usb_pipeslow(pipe) << 13 | - usb_maxpacket(usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len, - struct usb_device *dev, int index, - struct urb_priv *urb_priv) -{ - struct td *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td[index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td[index] = - (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32) data; -#ifdef OHCI_FILL_TRACE - if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x ", i, - ((unsigned char *)td->data)[i]); - printf("\n"); - } -#endif - if (!len) - data = 0; - - td->hwINFO = (__u32) m32_swap(info); - td->hwCBP = (__u32) m32_swap(data); - if (data) - td->hwBE = (__u32) m32_swap(data + len - 1); - else - td->hwBE = 0; - td->hwNextTD = (__u32) m32_swap(td_pt); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ - -static void td_submit_job(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, - struct devrequest *setup, struct urb_priv *urb, - int interval) -{ - struct ohci *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just - use the USB-toggle bits for reseting */ - if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), - 1); - } - urb->td_cnt = 0; - if (data_len) - data = buffer; - else - data = 0; - - switch (usb_pipetype(pipe)) { - case PIPE_BULK: - info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN; - while (data_len > 4096) { - td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, - 4096, dev, cnt, urb); - data += 4096; - data_len -= 4096; - cnt++; - } - info = usb_pipeout(pipe) ? - TD_CC | TD_DP_OUT : - TD_CC | TD_R | TD_DP_IN; - td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, - data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - /* start bulk list */ - writel(OHCI_BLF, &ohci->regs->cmdstatus); - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill(ohci, info, setup, 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout(pipe) ? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : - TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill(ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout(pipe) ? - TD_CC | TD_DP_IN | TD_T_DATA1 : - TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill(ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - /* start Control list */ - writel(OHCI_CLF, &ohci->regs->cmdstatus); - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(struct td *td) -{ - __u32 tdBE, tdCBP; - struct urb_priv *lurb_priv = &urb_priv; - - tdBE = m32_swap(td->hwBE); - tdCBP = m32_swap(td->hwCBP); - - if (!(usb_pipecontrol(lurb_priv->pipe) && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static struct td *dl_reverse_done_list(struct ohci *ohci) -{ - __u32 td_list_hc; - __u32 tmp; - struct td *td_rev = NULL; - struct td *td_list = NULL; - struct urb_priv *lurb_priv = NULL; - - td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (struct td *) td_list_hc; - - if (TD_CC_GET(m32_swap(td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET(m32_swap(td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & m32_swap(0x1)) { - if (lurb_priv && - ((td_list->index+1) < lurb_priv->length)) { - tmp = lurb_priv->length - 1; - td_list->ed->hwHeadP = - (lurb_priv->td[tmp]->hwNextTD & - m32_swap(0xfffffff0)) | - (td_list->ed->hwHeadP & - m32_swap(0x2)); - lurb_priv->td_cnt += lurb_priv->length - - td_list->index - 1; - } else - td_list->ed->hwHeadP &= - m32_swap(0xfffffff2); - } - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; - } - - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list(struct ohci *ohci, struct td *td_list) -{ - struct td *td_list_next = NULL; - struct ed *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - struct urb_priv *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = m32_swap(td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET(tdINFO); - if (cc != 0) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - } - - /* see if this done list makes for all TD's of current URB, - * and mark the URB finished if so */ - if (++(lurb_priv->td_cnt) == lurb_priv->length) { - if ((ed->state & (ED_OPER | ED_UNLINK))) - urb_finished = 1; - else - dbg("dl_done_list: strange.., ED state %x, " - "ed->state\n"); - } else - dbg("dl_done_list: processing TD %x, len %x\n", - lurb_priv->td_cnt, lurb_priv->length); - - if (ed->state != ED_NEW) { - edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; - edTailP = m32_swap(ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink(ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -/* Device descriptor */ -static __u8 root_hub_dev_des[] = { - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x01, /* __u8 iProduct; */ - 0x00, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 root_hub_config_des[] = { - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, - 5 Remote-wakwup, 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -static unsigned char root_hub_str_index0[] = { - 0x04, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 0x09, /* __u8 lang ID */ - 0x04, /* __u8 lang ID */ -}; - -static unsigned char root_hub_str_index1[] = { - 28, /* __u8 bLength; */ - 0x03, /* __u8 bDescriptorType; String-descriptor */ - 'O', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'C', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'I', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'R', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'o', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 't', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - ' ', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'H', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'u', /* __u8 Unicode */ - 0, /* __u8 Unicode */ - 'b', /* __u8 Unicode */ - 0, /* __u8 Unicode */ -}; - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) \ -{ \ - info("WR:status %#8x", (x)); \ - writel((x), &gohci.regs->roothub.status); \ -} -#define WR_RH_PORTSTAT(x) \ -{ \ - info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \ - writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \ -} -#else -#define WR_RH_STAT(x) \ - writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x)\ - writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(struct ohci *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a(controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus(controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, - struct devrequest *cmd) -{ - void *data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - union { - __u32 word[4]; - __u16 hword[8]; - __u8 byte[16]; - } datab; - __u8 *data_buf = datab.byte; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (usb_pipeint(pipe)) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap(cmd->value); - wIndex = m16_swap(cmd->index); - wLength = m16_swap(cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - datab.hword[0] = m16_swap(1); - OK(2); - case RH_GET_STATUS | RH_INTERFACE: - datab.hword[0] = m16_swap(0); - OK(2); - case RH_GET_STATUS | RH_ENDPOINT: - datab.hword[0] = m16_swap(0); - OK(2); - case RH_GET_STATUS | RH_CLASS: - datab.word[0] = - m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK(4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - datab.word[0] = m32_swap(RD_RH_PORTSTAT); - OK(4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): - OK(0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); - OK(0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT(RH_PS_CCS); - OK(0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT(RH_PS_POCI); - OK(0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT(RH_PS_LSDA); - OK(0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT(RH_PS_CSC); - OK(0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT(RH_PS_PESC); - OK(0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT(RH_PS_PSSC); - OK(0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT(RH_PS_OCIC); - OK(0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT(RH_PS_PRSC); - OK(0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT(RH_PS_PSS); - OK(0); - case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT(RH_PS_PRS); - OK(0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT(RH_PS_PPS); - OK(0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT(RH_PS_PES); - OK(0); - } - break; - - case RH_SET_ADDRESS: - gohci.rh.devnum = wValue; - OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_dev_des), wLength)); - data_buf = root_hub_dev_des; - OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; - OK(len); - case (0x03): /* string descriptors */ - if (wValue == 0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if (wValue == 0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof(root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a(&gohci); - - data_buf[0] = 9; /* min length; */ - data_buf[1] = 0x29; - data_buf[2] = temp & RH_A_NDP; - data_buf[3] = 0; - if (temp & RH_A_PSM) - /* per-port power switching? */ - data_buf[3] |= 0x1; - if (temp & RH_A_NOCP) - /* no overcurrent reporting? */ - data_buf[3] |= 0x10; - else if (temp & RH_A_OCPM) - /* per-port overcurrent reporting? */ - data_buf[3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab.word[1] = 0; - data_buf[5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b(&gohci); - data_buf[7] = temp & RH_B_DR; - if (data_buf[2] < 7) { - data_buf[8] = 0xff; - } else { - data_buf[0] += 2; - data_buf[8] = (temp & RH_B_DR) >> 8; - data_buf[10] = data_buf[9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf[0], wLength)); - OK(len); - } - - case RH_GET_CONFIGURATION: - *(__u8 *) data_buf = 0x01; - OK(1); - - case RH_SET_CONFIGURATION: - WR_RH_STAT(0x10000); - OK(0); - - default: - dbg("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub(&gohci, 1); -#else - mdelay(1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy(data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", - 0 /*usb_pipein(pipe) */); -#else - mdelay(1); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < - 0) { - err("sohci_submit_job failed"); - return -1; - } - - mdelay(10); - /* ohci_dump_status(&gohci); */ - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipebulk(pipe)) - timeout = BULK_TO; - else - timeout = 100; - - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - - /* NOTE: since we are not interrupt driven in U-Boot and always - * handle only one URB at a time, we cannot assume the - * transaction finished on the first successful return from - * hc_interrupt().. unless the flag for current URB is set, - * meaning that all TD's to/from device got actually - * transferred and processed. If the current URB is not - * finished we need to re-iterate this loop so as - * hc_interrupt() gets called again as there needs to be some - * more TD's to process still */ - if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { - /* 0xff is returned for an SF-interrupt */ - break; - } - - if (--timeout) { - mdelay(1); - if (!urb_finished) - dbg("\%"); - - } else { - err("CTL:TIMEOUT "); - dbg("submit_common_msg: TO status %x\n", stat); - stat = USB_ST_CRC_ERR; - urb_finished = 1; - break; - } - } - -#if 0 - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub(&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here - in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } -#endif - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - - /* free TDs in urb_priv */ - urb_free_priv(&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", - usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset(struct ohci *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl(&ohci->regs->control) & OHCI_CTRL_IR) { - /* SMM owns the HC - request ownership */ - writel(OHCI_OCR, &ohci->regs->cmdstatus); - info("USB HC TakeOver from SMM"); - while (readl(&ohci->regs->control) & OHCI_CTRL_IR) { - mdelay(10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, readl(&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - writel(0, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel(OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay(1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start(struct ohci *ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel(0, &ohci->regs->ed_controlhead); - writel(0, &ohci->regs->ed_bulkhead); - - /* a reset clears this */ - writel((__u32) ohci->hcca, &ohci->regs->hcca); - - fminterval = 0x2edf; - writel((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel(fminterval, &ohci->regs->fminterval); - writel(0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel(ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel(mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel(mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel(mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel(RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay((roothub_a(ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int hc_interrupt(void) -{ - struct ohci *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && - !(m32_swap(ohci->hcca->done_head) & 0x01)) { - - ints = OHCI_INTR_WDH; - - } else { - ints = readl(®s->intrstatus); - if (ints == ~(u32) 0) { - ohci->disabled++; - err("%s device removed!", ohci->slot_name); - return -1; - } - ints &= readl(®s->intrenable); - if (ints == 0) { - dbg("hc_interrupt: returning..\n"); - return 0xff; - } - } - - /* dbg("Interrupt: %x frame: %x", ints, - le16_to_cpu(ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - stat = 0xff; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump(ohci, 1); -#else - mdelay(1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset(ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - mdelay(1); - - writel(OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci)); - writel(OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel(OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; - mdelay(1); - writel(OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel(OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel(ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci(struct ohci *ohci) -{ - dbg("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset(ohci); -} - -/*-------------------------------------------------------------------------*/ - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(int index, void **controller) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); - - /* - * Set the 48 MHz UPLL clocking. Values are taken from - * "PLL value selection guide", 6-23, s3c2400_UM.pdf. - */ - clk_power->upllcon = ((40 << 12) + (1 << 4) + 2); - gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */ - - /* - * Enable USB host clock. - */ - clk_power->clkcon |= (1 << 4); - - memset(&gohci, 0, sizeof(struct ohci)); - memset(&urb_priv, 0, sizeof(struct urb_priv)); - - /* align the storage */ - if ((__u32) &ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32) &ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1)); - if ((__u32) gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset(phcca, 0, sizeof(struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE; - - gohci.flags = 0; - gohci.slot_name = "s3c2400"; - - if (hc_reset(&gohci) < 0) { - hc_release_ohci(&gohci); - /* Initialization failed */ - clk_power->clkcon &= ~(1 << 4); - return -1; - } - - /* FIXME this is a second HC reset; why?? */ - gohci.hc_control = OHCI_USB_RESET; - writel(gohci.hc_control, &gohci.regs->control); - mdelay(10); - - if (hc_start(&gohci) < 0) { - err("can't start usb-%s", gohci.slot_name); - hc_release_ohci(&gohci); - /* Initialization failed */ - clk_power->clkcon &= ~(1 << 4); - return -1; - } -#ifdef DEBUG - ohci_dump(&gohci, 1); -#else - mdelay(1); -#endif - ohci_inited = 1; - urb_finished = 1; - - return 0; -} - -int usb_lowlevel_stop(int index) -{ - struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset(&gohci); - /* may not want to do this */ - clk_power->clkcon &= ~(1 << 4); - return 0; -} - -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */ diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h deleted file mode 100644 index f272d78859..0000000000 --- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber - * (C) Copyright 2000-2001 David Brownell - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute__ ((aligned(16))); - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f) -#define TD_CC_SET(td_p, cc) \ - {(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)} -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute__ ((aligned(32))); - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute__ ((aligned(256))); - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute__ ((aligned(32))); - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status */ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -struct urb_priv { - struct ed *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs - associated with this request */ -}; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma; */ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */ - struct ed *ed_bulktail; /* last endpoint of bulk list */ - struct ed *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -}; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - struct ed ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(struct ohci *ohci, struct ed *ed); -static int ep_unlink(struct ohci *ohci, struct ed *ed); -static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -struct td gtd[NUM_TD + 1]; - -/* pointers to aligned storage */ -struct td *ptd; - -/* TDs ... */ -static inline struct td *td_alloc(struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) { - if (ptd[i].usb_dev == NULL) { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - - return td; -} - -static inline void ed_free(struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index bcb4662c47..6c94794929 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o +COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o # echi COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c new file mode 100644 index 0000000000..03cd4c3d2a --- /dev/null +++ b/drivers/usb/host/ohci-s3c24xx.c @@ -0,0 +1,1801 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + */ + +#include +/* #include no PCI on the S3C24X0 */ + +#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) + +#include +#include +#include +#include +#include "ohci-s3c24xx.h" + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ + + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define min_t(type, x, y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) + +#undef DEBUG +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#undef SHOW_INFO +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +/* global struct ohci */ +static struct ohci gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +struct urb_priv urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; +/* flag guarding URB transation */ +int urb_finished = 0; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a(struct ohci *hc) +{ + return read_roothub(hc, a, 0xfc0fe000); +} +static inline u32 roothub_b(struct ohci *hc) +{ + return readl(&hc->regs->roothub.b); +} +static inline u32 roothub_status(struct ohci *hc) +{ + return readl(&hc->regs->roothub.status); +} +static u32 roothub_portstatus(struct ohci *hc, int i) +{ + return read_roothub(hc, portstatus[i], 0xffe0fce0); +} + +/* forward declaration */ +static int hc_interrupt(void); +static void td_submit_job(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *setup, struct urb_priv *urb, + int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv(struct urb_priv *urb) +{ + int i; + int last; + struct td *td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number(struct usb_device *dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, char *str, + int small) +{ + struct urb_priv *purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number(dev), + usb_pipedevice(pipe), + usb_pipeendpoint(pipe), + usb_pipeout(pipe) ? 'O' : 'I', + usb_pipetype(pipe) < 2 ? + (usb_pipeint(pipe) ? "INTR" : "ISOC") : + (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), + purb->actual_length, transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol(pipe)) { + printf(__FILE__ ": cmd(8):"); + for (i = 0; i < 8; i++) + printf(" %02x", ((__u8 *) setup)[i]); + printf("\n"); + } + if (transfer_len > 0 && buffer) { + printf(__FILE__ ": data(%d/%d):", + purb->actual_length, transfer_len); + len = usb_pipeout(pipe) ? + transfer_len : purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf(" %02x", ((__u8 *) buffer)[i]); + printf("%s\n", i < len ? "..." : ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the + int ed tree inclusive iso eds*/ +void ep_print_int_eds(struct ohci *ohci, char *str) +{ + int i, j; + __u32 *ed_p; + for (i = 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table[i]); + if (*ed_p == 0) + continue; + printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + struct ed *ed = (struct ed *) m32_swap(ed_p); + printf(" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf("\n"); + } +} + +static void ohci_dump_intr_mask(char *label, __u32 mask) +{ + dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : ""); +} + +static void maybe_print_eds(char *label, __u32 value) +{ + struct ed *edp = (struct ed *) value; + + if (value) { + dbg("%s %08x", label, value); + dbg("%08x", edp->hwINFO); + dbg("%08x", edp->hwTailP); + dbg("%08x", edp->hwHeadP); + dbg("%08x", edp->hwNextED); + } +} + +static char *hcfs2string(int state) +{ + switch (state) { + case OHCI_USB_RESET: + return "reset"; + case OHCI_USB_RESUME: + return "resume"; + case OHCI_USB_OPER: + return "operational"; + case OHCI_USB_SUSPEND: + return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status(struct ohci *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl(®s->revision) & 0xff; + if (temp != 0x10) + dbg("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl(®s->control); + dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string(temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR); + + temp = readl(®s->cmdstatus); + dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : ""); + + ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus)); + ohci_dump_intr_mask("intrenable", readl(®s->intrenable)); + + maybe_print_eds("ed_periodcurrent", readl(®s->ed_periodcurrent)); + + maybe_print_eds("ed_controlhead", readl(®s->ed_controlhead)); + maybe_print_eds("ed_controlcurrent", readl(®s->ed_controlcurrent)); + + maybe_print_eds("ed_bulkhead", readl(®s->ed_bulkhead)); + maybe_print_eds("ed_bulkcurrent", readl(®s->ed_bulkcurrent)); + + maybe_print_eds("donehead", readl(®s->donehead)); +} + +static void ohci_dump_roothub(struct ohci *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a(controller); + ndp = (temp & RH_A_NDP); + + if (verbose) { + dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", ndp); + temp = roothub_b(controller); + dbg("roothub.b: %08x PPCM=%04x DR=%04x", + temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR) + ); + temp = roothub_status(controller); + dbg("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : ""); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus(controller, i); + dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : ""); + } +} + +static void ohci_dump(struct ohci *controller, int verbose) +{ + dbg("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status(controller); + if (verbose) + ep_print_int_eds(controller, "hcca"); + dbg("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub(controller, 1); +} + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + struct ohci *ohci; + struct ed *ed; + struct urb_priv *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* if we have an unfinished URB from previous transaction let's + * fail and scream as quickly as possible so as not to corrupt + * further communication */ + if (!urb_finished) { + err("sohci_submit_job: URB NOT FINISHED"); + return -1; + } + /* we're about to begin a new transaction here + so mark the URB unfinished */ + urb_finished = 0; + + /* every endpoint has a ed, locate and fill it */ + ed = ep_add_ed(dev, pipe); + if (!ed) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype(pipe)) { + case PIPE_BULK: + /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: + /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc(dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv(purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv(purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link(ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, + interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number(struct usb_device *usb_dev) +{ + struct ohci *ohci = &gohci; + + return m16_swap(ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link(struct ohci *ohci, struct ed *edi) +{ + struct ed *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel((u32)ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel((u32)ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink(struct ohci *ohci, struct ed *ed) +{ + struct ed *next; + ed->hwINFO |= m32_swap(OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(m32_swap(*((__u32 *) &ed->hwNextED)), + &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED)); + next->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel(ohci->hc_control, &ohci->regs->control); + } + writel(m32_swap(*((__u32 *) &ed->hwNextED)), + &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED)); + next->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration + * command, but the USB stack is a little bit stateless so we do it at every + * transaction. If the state of the ed is ED_NEW then a dummy td is added and + * the state is changed to ED_UNLINK. In all other cases the state is left + * unchanged. The ed info fields are setted anyway even though most of them + * should not change */ + +static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe) +{ + struct td *td; + struct ed *ed_ret; + struct ed *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) | + (usb_pipecontrol(pipe) ? 0 : + usb_pipeout(pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc(usb_dev); + ed->hwTailP = (__u32) m32_swap(td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype(pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = m32_swap(usb_pipedevice(pipe) + | usb_pipeendpoint(pipe) << 7 + | (usb_pipeisoc(pipe) ? 0x8000 : 0) + | (usb_pipecontrol(pipe) ? 0 : + (usb_pipeout(pipe) ? 0x800 : 0x1000)) + | usb_pipeslow(pipe) << 13 | + usb_maxpacket(usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len, + struct usb_device *dev, int index, + struct urb_priv *urb_priv) +{ + struct td *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td[index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td[index] = + (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32) data; +#ifdef OHCI_FILL_TRACE + if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ", i, + ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = (__u32) m32_swap(info); + td->hwCBP = (__u32) m32_swap(data); + if (data) + td->hwBE = (__u32) m32_swap(data + len - 1); + else + td->hwBE = 0; + td->hwNextTD = (__u32) m32_swap(td_pt); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +static void td_submit_job(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *setup, struct urb_priv *urb, + int interval) +{ + struct ohci *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just + use the USB-toggle bits for reseting */ + if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), + 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype(pipe)) { + case PIPE_BULK: + info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN; + while (data_len > 4096) { + td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, + 4096, dev, cnt, urb); + data += 4096; + data_len -= 4096; + cnt++; + } + info = usb_pipeout(pipe) ? + TD_CC | TD_DP_OUT : + TD_CC | TD_R | TD_DP_IN; + td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data, + data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + /* start bulk list */ + writel(OHCI_BLF, &ohci->regs->cmdstatus); + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill(ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout(pipe) ? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : + TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill(ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout(pipe) ? + TD_CC | TD_DP_IN | TD_T_DATA1 : + TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill(ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + /* start Control list */ + writel(OHCI_CLF, &ohci->regs->cmdstatus); + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(struct td *td) +{ + __u32 tdBE, tdCBP; + struct urb_priv *lurb_priv = &urb_priv; + + tdBE = m32_swap(td->hwBE); + tdCBP = m32_swap(td->hwCBP); + + if (!(usb_pipecontrol(lurb_priv->pipe) && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static struct td *dl_reverse_done_list(struct ohci *ohci) +{ + __u32 td_list_hc; + __u32 tmp; + struct td *td_rev = NULL; + struct td *td_list = NULL; + struct urb_priv *lurb_priv = NULL; + + td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (struct td *) td_list_hc; + + if (TD_CC_GET(m32_swap(td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET(m32_swap(td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & m32_swap(0x1)) { + if (lurb_priv && + ((td_list->index+1) < lurb_priv->length)) { + tmp = lurb_priv->length - 1; + td_list->ed->hwHeadP = + (lurb_priv->td[tmp]->hwNextTD & + m32_swap(0xfffffff0)) | + (td_list->ed->hwHeadP & + m32_swap(0x2)); + lurb_priv->td_cnt += lurb_priv->length - + td_list->index - 1; + } else + td_list->ed->hwHeadP &= + m32_swap(0xfffffff2); + } + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0; + } + + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list(struct ohci *ohci, struct td *td_list) +{ + struct td *td_list_next = NULL; + struct ed *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + struct urb_priv *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = m32_swap(td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET(tdINFO); + if (cc != 0) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + } + + /* see if this done list makes for all TD's of current URB, + * and mark the URB finished if so */ + if (++(lurb_priv->td_cnt) == lurb_priv->length) { + if ((ed->state & (ED_OPER | ED_UNLINK))) + urb_finished = 1; + else + dbg("dl_done_list: strange.., ED state %x, " + "ed->state\n"); + } else + dbg("dl_done_list: processing TD %x, len %x\n", + lurb_priv->td_cnt, lurb_priv->length); + + if (ed->state != ED_NEW) { + edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0; + edTailP = m32_swap(ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink(ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, + 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) \ +{ \ + info("WR:status %#8x", (x)); \ + writel((x), &gohci.regs->roothub.status); \ +} +#define WR_RH_PORTSTAT(x) \ +{ \ + info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \ + writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \ +} +#else +#define WR_RH_STAT(x) \ + writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x)\ + writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(struct ohci *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a(controller); + ndp = (temp & RH_A_NDP); + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus(controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *cmd) +{ + void *data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + union { + __u32 word[4]; + __u16 hword[8]; + __u8 byte[16]; + } datab; + __u8 *data_buf = datab.byte; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", + usb_pipein(pipe)); +#else + mdelay(1); +#endif + if (usb_pipeint(pipe)) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap(cmd->value); + wIndex = m16_swap(cmd->index); + wLength = m16_swap(cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + datab.hword[0] = m16_swap(1); + OK(2); + case RH_GET_STATUS | RH_INTERFACE: + datab.hword[0] = m16_swap(0); + OK(2); + case RH_GET_STATUS | RH_ENDPOINT: + datab.hword[0] = m16_swap(0); + OK(2); + case RH_GET_STATUS | RH_CLASS: + datab.word[0] = + m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK(4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + datab.word[0] = m32_swap(RD_RH_PORTSTAT); + OK(4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): + OK(0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); + OK(0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT(RH_PS_CCS); + OK(0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT(RH_PS_POCI); + OK(0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT(RH_PS_LSDA); + OK(0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT(RH_PS_CSC); + OK(0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT(RH_PS_PESC); + OK(0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT(RH_PS_PSSC); + OK(0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT(RH_PS_OCIC); + OK(0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT(RH_PS_PRSC); + OK(0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT(RH_PS_PSS); + OK(0); + case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PRS); + OK(0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT(RH_PS_PPS); + OK(0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT(RH_PS_PES); + OK(0); + } + break; + + case RH_SET_ADDRESS: + gohci.rh.devnum = wValue; + OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_dev_des), wLength)); + data_buf = root_hub_dev_des; + OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; + OK(len); + case (0x03): /* string descriptors */ + if (wValue == 0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if (wValue == 0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof(root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a(&gohci); + + data_buf[0] = 9; /* min length; */ + data_buf[1] = 0x29; + data_buf[2] = temp & RH_A_NDP; + data_buf[3] = 0; + if (temp & RH_A_PSM) + /* per-port power switching? */ + data_buf[3] |= 0x1; + if (temp & RH_A_NOCP) + /* no overcurrent reporting? */ + data_buf[3] |= 0x10; + else if (temp & RH_A_OCPM) + /* per-port overcurrent reporting? */ + data_buf[3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab.word[1] = 0; + data_buf[5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b(&gohci); + data_buf[7] = temp & RH_B_DR; + if (data_buf[2] < 7) { + data_buf[8] = 0xff; + } else { + data_buf[0] += 2; + data_buf[8] = (temp & RH_B_DR) >> 8; + data_buf[10] = data_buf[9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf[0], wLength)); + OK(len); + } + + case RH_GET_CONFIGURATION: + *(__u8 *) data_buf = 0x01; + OK(1); + + case RH_SET_CONFIGURATION: + WR_RH_STAT(0x10000); + OK(0); + + default: + dbg("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub(&gohci, 1); +#else + mdelay(1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy(data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", + 0 /*usb_pipein(pipe) */); +#else + mdelay(1); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", + usb_pipein(pipe)); +#else + mdelay(1); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < + 0) { + err("sohci_submit_job failed"); + return -1; + } + + mdelay(10); + /* ohci_dump_status(&gohci); */ + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipebulk(pipe)) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + + /* NOTE: since we are not interrupt driven in U-Boot and always + * handle only one URB at a time, we cannot assume the + * transaction finished on the first successful return from + * hc_interrupt().. unless the flag for current URB is set, + * meaning that all TD's to/from device got actually + * transferred and processed. If the current URB is not + * finished we need to re-iterate this loop so as + * hc_interrupt() gets called again as there needs to be some + * more TD's to process still */ + if ((stat >= 0) && (stat != 0xff) && (urb_finished)) { + /* 0xff is returned for an SF-interrupt */ + break; + } + + if (--timeout) { + mdelay(1); + if (!urb_finished) + dbg("\%"); + + } else { + err("CTL:TIMEOUT "); + dbg("submit_common_msg: TO status %x\n", stat); + stat = USB_ST_CRC_ERR; + urb_finished = 1; + break; + } + } + +#if 0 + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub(&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here + in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } +#endif + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", + usb_pipein(pipe)); +#else + mdelay(1); +#endif + + /* free TDs in urb_priv */ + urb_free_priv(&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", + usb_pipein(pipe)); +#else + mdelay(1); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset(struct ohci *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + if (readl(&ohci->regs->control) & OHCI_CTRL_IR) { + /* SMM owns the HC - request ownership */ + writel(OHCI_OCR, &ohci->regs->cmdstatus); + info("USB HC TakeOver from SMM"); + while (readl(&ohci->regs->control) & OHCI_CTRL_IR) { + mdelay(10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel(OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", + ohci->slot_name, readl(&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + writel(0, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel(OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay(1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start(struct ohci *ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel(0, &ohci->regs->ed_controlhead); + writel(0, &ohci->regs->ed_bulkhead); + + /* a reset clears this */ + writel((__u32) ohci->hcca, &ohci->regs->hcca); + + fminterval = 0x2edf; + writel((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel(fminterval, &ohci->regs->fminterval); + writel(0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel(ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel(mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel(mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel(mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel(RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay((roothub_a(ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int hc_interrupt(void) +{ + struct ohci *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && + !(m32_swap(ohci->hcca->done_head) & 0x01)) { + + ints = OHCI_INTR_WDH; + + } else { + ints = readl(®s->intrstatus); + if (ints == ~(u32) 0) { + ohci->disabled++; + err("%s device removed!", ohci->slot_name); + return -1; + } + ints &= readl(®s->intrenable); + if (ints == 0) { + dbg("hc_interrupt: returning..\n"); + return 0xff; + } + } + + /* dbg("Interrupt: %x frame: %x", ints, + le16_to_cpu(ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + stat = 0xff; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump(ohci, 1); +#else + mdelay(1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset(ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + mdelay(1); + + writel(OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci)); + writel(OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel(OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; + mdelay(1); + writel(OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel(OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel(ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci(struct ohci *ohci) +{ + dbg("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset(ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(int index, void **controller) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); + + /* + * Set the 48 MHz UPLL clocking. Values are taken from + * "PLL value selection guide", 6-23, s3c2400_UM.pdf. + */ + clk_power->upllcon = ((40 << 12) + (1 << 4) + 2); + gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */ + + /* + * Enable USB host clock. + */ + clk_power->clkcon |= (1 << 4); + + memset(&gohci, 0, sizeof(struct ohci)); + memset(&urb_priv, 0, sizeof(struct urb_priv)); + + /* align the storage */ + if ((__u32) &ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32) &ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1)); + if ((__u32) gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset(phcca, 0, sizeof(struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE; + + gohci.flags = 0; + gohci.slot_name = "s3c2400"; + + if (hc_reset(&gohci) < 0) { + hc_release_ohci(&gohci); + /* Initialization failed */ + clk_power->clkcon &= ~(1 << 4); + return -1; + } + + /* FIXME this is a second HC reset; why?? */ + gohci.hc_control = OHCI_USB_RESET; + writel(gohci.hc_control, &gohci.regs->control); + mdelay(10); + + if (hc_start(&gohci) < 0) { + err("can't start usb-%s", gohci.slot_name); + hc_release_ohci(&gohci); + /* Initialization failed */ + clk_power->clkcon &= ~(1 << 4); + return -1; + } +#ifdef DEBUG + ohci_dump(&gohci, 1); +#else + mdelay(1); +#endif + ohci_inited = 1; + urb_finished = 1; + + return 0; +} + +int usb_lowlevel_stop(int index) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset(&gohci); + /* may not want to do this */ + clk_power->clkcon &= ~(1 << 4); + return 0; +} + +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */ + +#if defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) + +int usb_cpu_init(void) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); + + /* + * Set the 48 MHz UPLL clocking. Values are taken from + * "PLL value selection guide", 6-23, s3c2400_UM.pdf. + */ + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); + + /* + * Enable USB host clock. + */ + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); + + return 0; +} + +int usb_cpu_stop(void) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + /* may not want to do this */ + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); + return 0; +} + +int usb_cpu_init_fail(void) +{ + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); + return 0; +} + +#endif /* defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) */ diff --git a/drivers/usb/host/ohci-s3c24xx.h b/drivers/usb/host/ohci-s3c24xx.h new file mode 100644 index 0000000000..f272d78859 --- /dev/null +++ b/drivers/usb/host/ohci-s3c24xx.h @@ -0,0 +1,409 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute__ ((aligned(16))); + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f) +#define TD_CC_SET(td_p, cc) \ + {(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)} +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute__ ((aligned(32))); + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute__ ((aligned(256))); + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute__ ((aligned(32))); + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status */ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +struct urb_priv { + struct ed *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs + associated with this request */ +}; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma; */ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */ + struct ed *ed_bulktail; /* last endpoint of bulk list */ + struct ed *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +}; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + struct ed ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(struct ohci *ohci, struct ed *ed); +static int ep_unlink(struct ohci *ohci, struct ed *ed); +static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +struct td gtd[NUM_TD + 1]; + +/* pointers to aligned storage */ +struct td *ptd; + +/* TDs ... */ +static inline struct td *td_alloc(struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) { + if (ptd[i].usb_dev == NULL) { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void ed_free(struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 06adc947b0..fb7d922257 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -124,6 +124,7 @@ /* USB support (currently only works with D-cache off) */ #define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_S3C24XX #define CONFIG_USB_KEYBOARD #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index 1c0978da8a..a8a56fdeb4 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -66,6 +66,7 @@ * USB support (currently only works with D-cache off) ************************************************************/ #define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_S3C24XX #define CONFIG_USB_KEYBOARD #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION -- cgit v1.2.3 From de1f9ac854471ca84c7aa6d236badd3d18ca10f8 Mon Sep 17 00:00:00 2001 From: "402jagan@gmail.com" <402jagan@gmail.com> Date: Sun, 29 Jul 2012 04:26:08 +0000 Subject: versatile: board configs: Use buffered writes on flash This patch provides a support to use buffered writes on flash for versatile and vexpress boards. This will certainly increase the flash writes. Signed-off-by: Jagannadha Sutradharudu Teki <402jagan@gmail.com> --- include/configs/ca9x4_ct_vxp.h | 2 ++ include/configs/versatile.h | 1 + 2 files changed, 3 insertions(+) diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h index 312fd947be..a7cd1d45ad 100644 --- a/include/configs/ca9x4_ct_vxp.h +++ b/include/configs/ca9x4_ct_vxp.h @@ -163,6 +163,8 @@ /* Room required on the stack for the environment data */ #define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ + /* * Amount of flash used for environment: * We don't know which end has the small erase blocks so we use the penultimate diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 38f5302e71..a65c6762b3 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -230,6 +230,7 @@ #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ #endif #endif /* __CONFIG_H */ -- cgit v1.2.3 From 1fb187b3b8e3bb6ed23ab8ec2743ea44bfdadb3c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 17 Oct 2012 10:18:29 +0000 Subject: actux[123]: Update linker script for ELDK 4.2 With ELDK4.2 libserial.o is too large to fit in the area before the environment. Swap in libinput instead which is a little smaller. Cc: Michael Schwingen Signed-off-by: Tom Rini --- board/actux1/u-boot.lds | 2 +- board/actux2/u-boot.lds | 2 +- board/actux3/u-boot.lds | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 9dbaa6faf6..63fd356097 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS net/libnet.o(.text*) board/actux1/libactux1.o(.text*) arch/arm/cpu/ixp/libixp.o(.text*) - drivers/serial/libserial.o(.text*) + drivers/input/libinput.o(.text*) . = env_offset; common/env_embedded.o(.ppcenv) diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 3575ed99fc..9885d06b8e 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS net/libnet.o(.text*) board/actux2/libactux2.o(.text*) arch/arm/cpu/ixp/libixp.o(.text*) - drivers/serial/libserial.o(.text*) + drivers/input/libinput.o(.text*) . = env_offset; common/env_embedded.o(.ppcenv) diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index 35aab29d40..4a1c75aecc 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS net/libnet.o(.text*) board/actux3/libactux3.o(.text*) arch/arm/cpu/ixp/libixp.o(.text*) - drivers/serial/libserial.o(.text*) + drivers/input/libinput.o(.text*) . = env_offset; common/env_embedded.o(.ppcenv) -- cgit v1.2.3 From 2ca7406c642022a211e6a5d5c9c81af531817d4e Mon Sep 17 00:00:00 2001 From: Philippe De Muyter Date: Wed, 3 Oct 2012 13:28:42 +0000 Subject: m68k: Fix relocation errors in start.S When the environment sectors in the flash are big, one get those errors : mcf547x_8x/start.S:173: relocation truncated to fit: R_68K_PC16 against symbol `cpu_init_f' defined in .text section in libmcf547x_8x.a(cpu_init.o) mcf547x_8x/start.S:174: relocation truncated to fit: R_68K_PC16 against symbol `board_init_f' defined in .text section in libm68k.a(board.o) Fix that. Signed-off-by: Philippe De Muyter Cc: "Jin Zhengxiong-R64188" Cc: Jason Jin --- arch/m68k/cpu/mcf547x_8x/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index ec65cae3d8..d99747b7fa 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -164,8 +164,8 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - bsr board_init_f /* run low-level board init code (from flash) */ + jbsr cpu_init_f /* run low-level CPU init code (from flash) */ + jbsr board_init_f /* run low-level board init code (from flash) */ /* board_init_f() does not return */ -- cgit v1.2.3 From 37d6cc3176efc2b643c8e6f8ab95621a757f5174 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 13:28:43 +0000 Subject: m68k: Fix wrong assembler instruction in start.S The jmp _fault generated the following error message, thus change it to bra _fault: start.S: Assembler messages: start.S:310: Error: Conversion of PC relative displacement to absolute Signed-off-by: Marek Vasut Cc: "Jin Zhengxiong-R64188" Cc: Jason Jin --- arch/m68k/cpu/mcf5227x/start.S | 2 +- arch/m68k/cpu/mcf523x/start.S | 2 +- arch/m68k/cpu/mcf52x2/start.S | 2 +- arch/m68k/cpu/mcf532x/start.S | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index c5096a80c2..a683778127 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -485,7 +485,7 @@ clear_bss: /* exception code */ .globl _fault _fault: - jmp _fault + bra _fault .globl _exc_handler _exc_handler: diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index e6a69ab470..05f17231b2 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -247,7 +247,7 @@ clear_bss: /* exception code */ .globl _fault _fault: - jmp _fault + bra _fault .globl _exc_handler _exc_handler: diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index ee17792cb3..f5e55dd965 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -307,7 +307,7 @@ clear_bss: /* exception code */ .globl _fault _fault: - jmp _fault + bra _fault .globl _exc_handler _exc_handler: diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index fe98d76474..583ed1d41a 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -261,7 +261,7 @@ clear_bss: /* exception code */ .globl _fault _fault: - jmp _fault + bra _fault .globl _exc_handler _exc_handler: -- cgit v1.2.3 From 2b05593da61555b091ee1640dc6c4fcb235771e9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 13:28:44 +0000 Subject: m68k: Fix unused variable warning The fbcs variable was unused, producing the following warning: cpu_init.c: In function 'cpu_init_f': cpu_init.c:52:10: warning: unused variable 'fbcs' [-Wunused-variable] Signed-off-by: Marek Vasut Cc: "Jin Zhengxiong-R64188" Cc: Jason Jin --- arch/m68k/cpu/mcf5445x/cpu_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 3f9209ff19..b6ceac32e8 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -31,6 +31,7 @@ #include #include #include +#include #if defined(CONFIG_CMD_NET) #include @@ -49,7 +50,7 @@ void cpu_init_f(void) { scm1_t *scm1 = (scm1_t *) MMAP_SCM1; gpio_t *gpio = (gpio_t *) MMAP_GPIO; - fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; out_be32(&scm1->mpr, 0x77777777); out_be32(&scm1->pacra, 0); -- cgit v1.2.3 From c1568ca5450cc20eb0f15246656724a1df9699c3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 13:28:45 +0000 Subject: m68k: Fix unused variable warning in speed.c The following warning was produced, fix it: speed.c: In function 'get_clocks': speed.c:94:15: warning: variable 'bPci' set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut Cc: "Jin Zhengxiong-R64188" Cc: Jason Jin --- arch/m68k/cpu/mcf5445x/speed.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 073b7efafb..d71b5fe842 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -91,9 +91,12 @@ int get_clocks(void) pll_t *pll = (pll_t *)MMAP_PLL; int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; int pllmult_pci[] = { 12, 6, 16, 8 }; - int vco = 0, bPci, temp, fbtemp, pcrvalue; + int vco = 0, temp, fbtemp, pcrvalue; int *pPllmult = NULL; u16 fbpll_mask; +#ifdef CONFIG_PCI + int bPci; +#endif #ifdef CONFIG_M54455EVB u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3); @@ -105,14 +108,16 @@ int get_clocks(void) ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { pPllmult = &pllmult_pci[0]; fbpll_mask = 3; /* 11b */ +#ifdef CONFIG_PCI bPci = 1; +#endif } else { pPllmult = &pllmult_nopci[0]; fbpll_mask = 7; /* 111b */ #ifdef CONFIG_PCI gd->pci_clk = 0; -#endif bPci = 0; +#endif } #ifdef CONFIG_M54455EVB -- cgit v1.2.3 From c59ac903f2fb515caf712ec19f4bd741659e6a45 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 13:28:46 +0000 Subject: m68k: Fix unused variable in board.c The following warning was produced, fix it: board.c: In function 'board_init_r': board.c:390:8: warning: unused variable 's' [-Wunused-variable] Signed-off-by: Marek Vasut Cc: "Jin Zhengxiong-R64188" Cc: Jason Jin --- arch/m68k/lib/board.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 67c9a1382e..92f935bd01 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -29,6 +29,7 @@ #include #include #include +#include #include @@ -387,7 +388,7 @@ board_init_f (ulong bootflag) */ void board_init_r (gd_t *id, ulong dest_addr) { - char *s; + char *s __maybe_unused; bd_t *bd; #ifndef CONFIG_ENV_IS_NOWHERE -- cgit v1.2.3 From 2b758cad8dfe8a04ed11340024d814612b912c3c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 13:28:47 +0000 Subject: m68k: net: Fix unused variable in mcfmii.c The following warning was produced, fix it: mcfmii.c: In function 'mcffec_miiphy_write': mcfmii.c:318:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut Cc: "Jin Zhengxiong-R64188" Cc: Jason Jin --- drivers/net/mcfmii.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 471c5efea1..5e64dbdd17 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -315,13 +315,11 @@ int mcffec_miiphy_read(const char *devname, unsigned char addr, unsigned char re int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) { - short rdreg; /* register working value */ - #ifdef MII_DEBUG printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); #endif - rdreg = mii_send(mk_mii_write(addr, reg, value)); + mii_send(mk_mii_write(addr, reg, value)); #ifdef MII_DEBUG printf("0x%04x\n", value); -- cgit v1.2.3 From fa862dd7cef9789ddce0c3b7d944e10dbf9761df Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Tue, 16 Oct 2012 16:38:39 +0800 Subject: ColdFire: Fix build error for astro mcf53731 board. Fix the build error by clean up the lds file. Signed-off-by: Jason Jin --- board/astro/mcf5373l/u-boot.lds | 64 +++++++---------------------------------- 1 file changed, 11 insertions(+), 53 deletions(-) diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds index a1d8e0f6dc..19342ac214 100644 --- a/board/astro/mcf5373l/u-boot.lds +++ b/board/astro/mcf5373l/u-boot.lds @@ -22,51 +22,18 @@ */ OUTPUT_ARCH(m68k) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + SECTIONS { /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } .text : { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/m68k/cpu/mcf532x/start.o (.text) - arch/m68k/lib/traps.o (.text) - arch/m68k/lib/interrupts.o (.text) - common/dlmalloc.o (.text) - lib/zlib.o (.text) + arch/m68k/cpu/mcf532x/start.o (.text*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text*) - *(.text) -/* *(.fixup)*/ - *(.got1) + *(.text*) } _etext = .; PROVIDE (etext = .); @@ -74,9 +41,6 @@ SECTIONS { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -86,24 +50,20 @@ SECTIONS .reloc : { __got_start = .; - *(.got) + KEEP(*(.got)) __got_end = .; _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; __fixup_entries = (. - _FIXUP_TABLE_)>>2; .data : { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS + *(.data*) + *(.sdata*) } _edata = .; PROVIDE (edata = .); @@ -113,7 +73,6 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; - . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } @@ -130,9 +89,8 @@ SECTIONS .bss : { _sbss = .; - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) + *(.sbss*) + *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; -- cgit v1.2.3 From 87c9b18687f1d113c49efc2b5eebb03cff868a91 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Tue, 16 Oct 2012 16:40:34 +0800 Subject: ColdFire: Fix the build error for Freescale m5282evb board. Clean up the lds file and fix the environment build error. Signed-off-by: Jason Jin --- board/freescale/m5282evb/u-boot.lds | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index 4ba1964f7e..500fefd445 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -29,6 +29,9 @@ SECTIONS { arch/m68k/cpu/mcf52x2/start.o (.text*) + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text*) + *(.text*) } _etext = .; -- cgit v1.2.3 From 39c7a2635227f5754393e954cb57249328e83cee Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Thu, 18 Oct 2012 16:54:38 +0000 Subject: ColdFire: uart: fix build failure for missing header files The following commit introduces some build failures for ColdFire platform. commit abaef69fbe683197607febeb2cc619490aca2a10 Author: Marek Vasut Date: Thu Sep 13 16:51:38 2012 +0200 Add the missed header files. Sign-off-by: Alison Wang --- drivers/serial/mcfuart.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 8ea9af0f61..7e25797661 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -28,6 +28,8 @@ */ #include +#include +#include #include #include -- cgit v1.2.3 From 39826f09978a0a7070999acc15babf88f03e4051 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 27 Sep 2012 15:41:55 +0000 Subject: arm: fdt: Relocate fdt along with other data Rather than leave the fdt down next to the code/data, we really should relocate it along with everything else. For CONFIG_OF_EMBED this happens automatically, but for CONFIG_OF_SEPARATE it does not. Add code to copy the fdt and point to the new copy after relocation. Signed-off-by: Simon Glass Tested-by: Stephen Warren --- arch/arm/lib/board.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 0b47ab341e..99cb54b8d8 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -274,6 +274,8 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_PRAM ulong reg; #endif + void *new_fdt = NULL; + size_t fdt_size = 0; bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); @@ -409,6 +411,22 @@ void board_init_f(ulong bootflag) debug("Reserving %zu Bytes for Global Data at: %08lx\n", sizeof (gd_t), addr_sp); +#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL) + /* + * If the device tree is sitting immediate above our image then we + * must relocate it. If it is embedded in the data section, then it + * will be relocated with other data. + */ + if (gd->fdt_blob) { + fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); + + addr_sp -= fdt_size; + new_fdt = (void *)addr_sp; + debug("Reserving %zu Bytes for FDT at: %08lx\n", + fdt_size, addr_sp); + } +#endif + /* setup stackpointer for exeptions */ gd->irq_sp = addr_sp; #ifdef CONFIG_USE_IRQ @@ -442,6 +460,10 @@ void board_init_f(ulong bootflag) gd->start_addr_sp = addr_sp; gd->reloc_off = addr - _TEXT_BASE; debug("relocation Offset is: %08lx\n", gd->reloc_off); + if (new_fdt) { + memcpy(new_fdt, gd->fdt_blob, fdt_size); + gd->fdt_blob = new_fdt; + } memcpy(id, (void *)gd, sizeof(gd_t)); relocate_code(addr_sp, id, addr); -- cgit v1.2.3 From 6ab6a650a418f213f51f47c8263cd635130b3c3a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 10 Oct 2012 07:57:51 +0000 Subject: disk: initialize name/part fields when returning a whole disk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When get_device_and_partition() finds a disk without a partition table, under some conditions, it "returns" a disk_partition_t that describes the entire raw disk. Make sure to initialize all fields in the partition descriptor in that case. The value chosen for name is just some arbitrary descriptive string. The value chosen for info matches the check at the end of get_device_and_partition(). However, it's probably not that important; it's not obvious that the value is really used. Reported-by: Benoît Thébaudeau Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau Signed-off-by: Tom Rini --- disk/part.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/disk/part.c b/disk/part.c index a0c77ddc9d..8ba3cdeaa0 100644 --- a/disk/part.c +++ b/disk/part.c @@ -561,6 +561,8 @@ int get_device_and_partition(const char *ifname, const char *dev_part_str, info->size = (*dev_desc)->lba; info->blksz = (*dev_desc)->blksz; info->bootable = 0; + strcpy((char *)info->type, BOOT_PART_TYPE); + strcpy((char *)info->name, "Whole Disk"); #ifdef CONFIG_PARTITION_UUIDS info->uuid[0] = 0; #endif -- cgit v1.2.3 From ddd8418f7f390a39d460e6ab98e8e668f0cf617c Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Fri, 12 Oct 2012 08:48:51 +0000 Subject: env: cosmetic: Consilidate the default env definition There used to be a huge structure duplicated 3 times in the source. Signed-off-by: Joe Hershberger Signed-off-by: Tom Rini --- common/env_common.c | 97 +----------------------------------- common/env_embedded.c | 104 ++------------------------------------ include/env_default.h | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++ tools/env/fw_env.c | 98 +----------------------------------- 4 files changed, 141 insertions(+), 293 deletions(-) create mode 100644 include/env_default.h diff --git a/common/env_common.c b/common/env_common.c index 61c4be54d0..3d3cb70a6d 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -37,102 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; /************************************************************************ * Default settings to be used when no valid environment is found */ - -const uchar default_environment[] = { -#ifdef CONFIG_BOOTARGS - "bootargs=" CONFIG_BOOTARGS "\0" -#endif -#ifdef CONFIG_BOOTCOMMAND - "bootcmd=" CONFIG_BOOTCOMMAND "\0" -#endif -#ifdef CONFIG_RAMBOOTCOMMAND - "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" -#endif -#ifdef CONFIG_NFSBOOTCOMMAND - "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" -#endif -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) - "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" -#endif -#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" -#endif -#ifdef CONFIG_LOADS_ECHO - "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0" -#endif -#ifdef CONFIG_ETHADDR - "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" -#endif -#ifdef CONFIG_ETH1ADDR - "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" -#endif -#ifdef CONFIG_ETH2ADDR - "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" -#endif -#ifdef CONFIG_ETH3ADDR - "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0" -#endif -#ifdef CONFIG_ETH4ADDR - "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0" -#endif -#ifdef CONFIG_ETH5ADDR - "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0" -#endif -#ifdef CONFIG_ETHPRIME - "ethprime=" CONFIG_ETHPRIME "\0" -#endif -#ifdef CONFIG_IPADDR - "ipaddr=" __stringify(CONFIG_IPADDR) "\0" -#endif -#ifdef CONFIG_SERVERIP - "serverip=" __stringify(CONFIG_SERVERIP) "\0" -#endif -#ifdef CONFIG_SYS_AUTOLOAD - "autoload=" CONFIG_SYS_AUTOLOAD "\0" -#endif -#ifdef CONFIG_PREBOOT - "preboot=" CONFIG_PREBOOT "\0" -#endif -#ifdef CONFIG_ROOTPATH - "rootpath=" CONFIG_ROOTPATH "\0" -#endif -#ifdef CONFIG_GATEWAYIP - "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" -#endif -#ifdef CONFIG_NETMASK - "netmask=" __stringify(CONFIG_NETMASK) "\0" -#endif -#ifdef CONFIG_HOSTNAME - "hostname=" __stringify(CONFIG_HOSTNAME) "\0" -#endif -#ifdef CONFIG_BOOTFILE - "bootfile=" CONFIG_BOOTFILE "\0" -#endif -#ifdef CONFIG_LOADADDR - "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" -#endif -#ifdef CONFIG_CLOCKS_IN_MHZ - "clocks_in_mhz=1\0" -#endif -#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) - "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" -#endif -#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG - "arch=" CONFIG_SYS_ARCH "\0" - "cpu=" CONFIG_SYS_CPU "\0" - "board=" CONFIG_SYS_BOARD "\0" -#ifdef CONFIG_SYS_VENDOR - "vendor=" CONFIG_SYS_VENDOR "\0" -#endif -#ifdef CONFIG_SYS_SOC - "soc=" CONFIG_SYS_SOC "\0" -#endif -#endif -#ifdef CONFIG_EXTRA_ENV_SETTINGS - CONFIG_EXTRA_ENV_SETTINGS -#endif - "\0" -}; +#include struct hsearch_data env_htab = { .apply = env_check_apply, diff --git a/common/env_embedded.c b/common/env_embedded.c index 8cc08ae4da..52bc6873dd 100644 --- a/common/env_embedded.c +++ b/common/env_embedded.c @@ -89,107 +89,9 @@ # define ENV_CRC (~0) #endif -env_t environment __PPCENV__ = { - ENV_CRC, /* CRC Sum */ -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT - 1, /* Flags: valid */ -#endif - { -#if defined(CONFIG_BOOTARGS) - "bootargs=" CONFIG_BOOTARGS "\0" -#endif -#if defined(CONFIG_BOOTCOMMAND) - "bootcmd=" CONFIG_BOOTCOMMAND "\0" -#endif -#if defined(CONFIG_RAMBOOTCOMMAND) - "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" -#endif -#if defined(CONFIG_NFSBOOTCOMMAND) - "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" -#endif -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) - "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" -#endif -#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" -#endif -#ifdef CONFIG_LOADS_ECHO - "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0" -#endif -#ifdef CONFIG_ETHADDR - "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" -#endif -#ifdef CONFIG_ETH1ADDR - "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" -#endif -#ifdef CONFIG_ETH2ADDR - "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" -#endif -#ifdef CONFIG_ETH3ADDR - "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0" -#endif -#ifdef CONFIG_ETH4ADDR - "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0" -#endif -#ifdef CONFIG_ETH5ADDR - "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0" -#endif -#ifdef CONFIG_ETHPRIME - "ethprime=" CONFIG_ETHPRIME "\0" -#endif -#ifdef CONFIG_IPADDR - "ipaddr=" __stringify(CONFIG_IPADDR) "\0" -#endif -#ifdef CONFIG_SERVERIP - "serverip=" __stringify(CONFIG_SERVERIP) "\0" -#endif -#ifdef CONFIG_SYS_AUTOLOAD - "autoload=" CONFIG_SYS_AUTOLOAD "\0" -#endif -#ifdef CONFIG_ROOTPATH - "rootpath=" CONFIG_ROOTPATH "\0" -#endif -#ifdef CONFIG_GATEWAYIP - "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" -#endif -#ifdef CONFIG_NETMASK - "netmask=" __stringify(CONFIG_NETMASK) "\0" -#endif -#ifdef CONFIG_HOSTNAME - "hostname=" __stringify(CONFIG_HOSTNAME) "\0" -#endif -#ifdef CONFIG_BOOTFILE - "bootfile=" CONFIG_BOOTFILE "\0" -#endif -#ifdef CONFIG_LOADADDR - "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" -#endif -#ifdef CONFIG_PREBOOT - "preboot=" CONFIG_PREBOOT "\0" -#endif -#ifdef CONFIG_CLOCKS_IN_MHZ - "clocks_in_mhz=" "1" "\0" -#endif -#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) - "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" -#endif -#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG - "arch=" CONFIG_SYS_ARCH "\0" - "cpu=" CONFIG_SYS_CPU "\0" - "board=" CONFIG_SYS_BOARD "\0" -#ifdef CONFIG_SYS_VENDOR - "vendor=" CONFIG_SYS_VENDOR "\0" -#endif -#ifdef CONFIG_SYS_SOC - "soc=" CONFIG_SYS_SOC "\0" -#endif -#endif -#ifdef CONFIG_EXTRA_ENV_SETTINGS - CONFIG_EXTRA_ENV_SETTINGS -#endif - "\0" /* Term. env_t.data with 2 NULs */ - } -}; +#define DEFAULT_ENV_INSTANCE_EMBEDDED +#include + #ifdef CONFIG_ENV_ADDR_REDUND env_t redundand_environment __PPCENV__ = { 0, /* CRC Sum: invalid */ diff --git a/include/env_default.h b/include/env_default.h new file mode 100644 index 0000000000..375e5ca15c --- /dev/null +++ b/include/env_default.h @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED +env_t environment __PPCENV__ = { + ENV_CRC, /* CRC Sum */ +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT + 1, /* Flags: valid */ +#endif + { +#elif defined(DEFAULT_ENV_INSTANCE_STATIC) +static char default_environment[] = { +#else +const uchar default_environment[] = { +#endif +#ifdef CONFIG_BOOTARGS + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#ifdef CONFIG_BOOTCOMMAND + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#ifdef CONFIG_RAMBOOTCOMMAND + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#ifdef CONFIG_NFSBOOTCOMMAND + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHADDR + "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" +#endif +#ifdef CONFIG_ETH1ADDR + "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" +#endif +#ifdef CONFIG_ETH2ADDR + "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" +#endif +#ifdef CONFIG_ETH3ADDR + "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0" +#endif +#ifdef CONFIG_ETH4ADDR + "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0" +#endif +#ifdef CONFIG_ETH5ADDR + "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0" +#endif +#ifdef CONFIG_ETHPRIME + "ethprime=" CONFIG_ETHPRIME "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" __stringify(CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" __stringify(CONFIG_SERVERIP) "\0" +#endif +#ifdef CONFIG_SYS_AUTOLOAD + "autoload=" CONFIG_SYS_AUTOLOAD "\0" +#endif +#ifdef CONFIG_PREBOOT + "preboot=" CONFIG_PREBOOT "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" CONFIG_ROOTPATH "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" __stringify(CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" CONFIG_BOOTFILE "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" +#endif +#ifdef CONFIG_CLOCKS_IN_MHZ + "clocks_in_mhz=1\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" +#endif +#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG + "arch=" CONFIG_SYS_ARCH "\0" + "cpu=" CONFIG_SYS_CPU "\0" + "board=" CONFIG_SYS_BOARD "\0" +#ifdef CONFIG_SYS_VENDOR + "vendor=" CONFIG_SYS_VENDOR "\0" +#endif +#ifdef CONFIG_SYS_SOC + "soc=" CONFIG_SYS_SOC "\0" +#endif +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" +#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED + } +#endif +}; diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 32e853aa1c..9b023e807b 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -119,102 +119,8 @@ static unsigned char active_flag = 1; /* obsolete_flag must be 0 to efficiently set it on NOR flash without erasing */ static unsigned char obsolete_flag = 0; - -static char default_environment[] = { -#if defined(CONFIG_BOOTARGS) - "bootargs=" CONFIG_BOOTARGS "\0" -#endif -#if defined(CONFIG_BOOTCOMMAND) - "bootcmd=" CONFIG_BOOTCOMMAND "\0" -#endif -#if defined(CONFIG_RAMBOOTCOMMAND) - "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" -#endif -#if defined(CONFIG_NFSBOOTCOMMAND) - "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" -#endif -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) - "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" -#endif -#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) - "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" -#endif -#ifdef CONFIG_LOADS_ECHO - "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0" -#endif -#ifdef CONFIG_ETHADDR - "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" -#endif -#ifdef CONFIG_ETH1ADDR - "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" -#endif -#ifdef CONFIG_ETH2ADDR - "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" -#endif -#ifdef CONFIG_ETH3ADDR - "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0" -#endif -#ifdef CONFIG_ETH4ADDR - "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0" -#endif -#ifdef CONFIG_ETH5ADDR - "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0" -#endif -#ifdef CONFIG_ETHPRIME - "ethprime=" CONFIG_ETHPRIME "\0" -#endif -#ifdef CONFIG_IPADDR - "ipaddr=" __stringify(CONFIG_IPADDR) "\0" -#endif -#ifdef CONFIG_SERVERIP - "serverip=" __stringify(CONFIG_SERVERIP) "\0" -#endif -#ifdef CONFIG_SYS_AUTOLOAD - "autoload=" CONFIG_SYS_AUTOLOAD "\0" -#endif -#ifdef CONFIG_ROOTPATH - "rootpath=" CONFIG_ROOTPATH "\0" -#endif -#ifdef CONFIG_GATEWAYIP - "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" -#endif -#ifdef CONFIG_NETMASK - "netmask=" __stringify(CONFIG_NETMASK) "\0" -#endif -#ifdef CONFIG_HOSTNAME - "hostname=" __stringify(CONFIG_HOSTNAME) "\0" -#endif -#ifdef CONFIG_BOOTFILE - "bootfile=" CONFIG_BOOTFILE "\0" -#endif -#ifdef CONFIG_LOADADDR - "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" -#endif -#ifdef CONFIG_PREBOOT - "preboot=" CONFIG_PREBOOT "\0" -#endif -#ifdef CONFIG_CLOCKS_IN_MHZ - "clocks_in_mhz=" "1" "\0" -#endif -#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) - "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY) "\0" -#endif -#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG - "arch=" CONFIG_SYS_ARCH "\0" - "cpu=" CONFIG_SYS_CPU "\0" - "board=" CONFIG_SYS_BOARD "\0" -#ifdef CONFIG_SYS_VENDOR - "vendor=" CONFIG_SYS_VENDOR "\0" -#endif -#ifdef CONFIG_SYS_SOC - "soc=" CONFIG_SYS_SOC "\0" -#endif -#endif -#ifdef CONFIG_EXTRA_ENV_SETTINGS - CONFIG_EXTRA_ENV_SETTINGS -#endif - "\0" /* Termimate struct environment data with 2 NULs */ -}; +#define DEFAULT_ENV_INSTANCE_STATIC +#include static int flash_io (int mode); static char *envmatch (char * s1, char * s2); -- cgit v1.2.3 From ef94f7fa64190876c08b68eb1b067c5e6d3085f5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:02:01 +0000 Subject: input: Use finer grain udelays while waitng for the i8042 keyboard buffer to empty On x86, the i8042 keyboard controller driver frequently waits for the keyboard input buffer to be empty to make sure the controller has had a chance to process the data it was given. The way the delay loop was structured, if the controller hadn't cleared the corresponding status bit immediately, it would wait 1ms before checking again. If the keyboard responded quickly but not instantly, the driver would still wait a full 1ms when perhaps 1us would have been sufficient. Because udelay is a busy wait anyway, this change decreases the delay between checks to 1us. Also, this change gets rid of a hardcoded 250ms delay. On Stumpy, this saves 100-150ms during boot. Signed-off-by: Gabe Black Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- drivers/input/i8042.c | 9 +++------ include/i8042.h | 6 ++++++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index c3bc5360ca..6839c6bac5 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -607,11 +607,10 @@ static void kbd_led_set(void) static int kbd_input_empty(void) { - int kbdTimeout = KBD_TIMEOUT; + int kbdTimeout = KBD_TIMEOUT * 1000; - /* wait for input buf empty */ - while ((in8(I8042_STATUS_REG) & 0x02) && kbdTimeout--) - udelay(1000); + while ((in8(I8042_STATUS_REG) & I8042_STATUS_IN_DATA) && kbdTimeout--) + udelay(1); return kbdTimeout != -1; } @@ -625,8 +624,6 @@ static int kbd_reset(void) out8(I8042_DATA_REG, 0xff); - udelay(250000); - if (kbd_input_empty() == 0) return -1; diff --git a/include/i8042.h b/include/i8042.h index 13952899ba..aeb3f090d0 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -39,6 +39,12 @@ #define I8042_STATUS_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard status read */ #define I8042_COMMAND_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard ctrl write */ +enum { + /* Output register (I8042_DATA_REG) has data for system */ + I8042_STATUS_OUT_DATA = 1 << 0, + I8042_STATUS_IN_DATA = 1 << 1, +}; + #define KBD_US 0 /* default US layout */ #define KBD_GER 1 /* german layout */ -- cgit v1.2.3 From 48edb304d05d5d8b410db74f6e497adcfb132430 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:02:02 +0000 Subject: input: Provide a board specific mechanism to decide whether to skip i8042 init This change adds a board overridable function which can be used to decide whether or not to initialize the i8042 keyboard controller. On systems where it isn't actually connected to anything, this can save a significant amount of boot time. On Stumpy, this saves about 200ms on boot. Signed-off-by: Gabe Black Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- drivers/input/i8042.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 6839c6bac5..3a4c467c59 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -26,6 +26,7 @@ /* includes */ #include +#include #ifdef CONFIG_USE_CPCIDVI extern u8 gt_cpcidvi_in8(u32 offset); @@ -320,6 +321,16 @@ static int kbd_controller_present(void) return in8(I8042_STATUS_REG) != 0xff; } +/* + * Implement a weak default function for boards that optionally + * need to skip the i8042 initialization. + */ +int __weak board_i8042_skip(void) +{ + /* As default, don't skip */ + return 0; +} + /******************************************************************************* * * i8042_kbd_init - reset keyboard and init state flags @@ -329,7 +340,7 @@ int i8042_kbd_init(void) int keymap, try; char *penv; - if (!kbd_controller_present()) + if (!kbd_controller_present() || board_i8042_skip()) return -1; #ifdef CONFIG_USE_CPCIDVI -- cgit v1.2.3 From 45fe668f5f6065f37836d5e941f36418fa3676cd Mon Sep 17 00:00:00 2001 From: Louis Yung-Chieh Lo Date: Thu, 11 Oct 2012 15:15:51 +0000 Subject: input: i8042: Provide feature to disable keyboard before booting kernel The BIOS leaves the keyboard enabled during boot time so that any keystroke would interfere kernel driver initialization. Add a way to disable the keyboard to make sure no scancode will be generated during the boot time. Note that the keyboard will be re-enabled again after the kernel driver is up. This code can be called from the board functions. Signed-off-by: Louis Yung-Chieh Lo Signed-off-by: Louis Yung-Chieh Lo Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- drivers/input/i8042.c | 38 ++++++++++++++++++++++++++++++++++++++ include/i8042.h | 13 +++++++++++++ 2 files changed, 51 insertions(+) diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 3a4c467c59..691aabf402 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -331,6 +331,44 @@ int __weak board_i8042_skip(void) return 0; } +void i8042_flush(void) +{ + int timeout; + + /* + * The delay is to give the keyboard controller some time to fill the + * next byte. + */ + while (1) { + timeout = 100; /* wait for no longer than 100us */ + while (timeout > 0 && !(in8(I8042_STATUS_REG) & 0x01)) { + udelay(1); + timeout--; + } + + /* Try to pull next byte if not timeout. */ + if (in8(I8042_STATUS_REG) & 0x01) + in8(I8042_DATA_REG); + else + break; + } +} + +int i8042_disable(void) +{ + if (kbd_input_empty() == 0) + return -1; + + /* Disable keyboard */ + out8(I8042_COMMAND_REG, 0xad); + + if (kbd_input_empty() == 0) + return -1; + + return 0; +} + + /******************************************************************************* * * i8042_kbd_init - reset keyboard and init state flags diff --git a/include/i8042.h b/include/i8042.h index aeb3f090d0..c48c057374 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -75,6 +75,19 @@ enum { /* exports */ +/** + * Flush all buffer from keyboard controller to host. + */ +void i8042_flush(void); + +/** + * Disables the keyboard so that key strokes no longer generate scancodes to + * the host. + * + * @return 0 if ok, -1 if keyboard input was found while disabling + */ +int i8042_disable(void); + int i8042_kbd_init(void); int i8042_tstc(void); int i8042_getc(void); -- cgit v1.2.3 From 59a1b72ced4f3eff6e7e26e566e6090a5e25d384 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 11 Oct 2012 15:15:52 +0000 Subject: input: Fix i8042 keyboard reset The i8042 keyboard reset was not checking the results of the output buffer after the reset command. This can jam up some KBC/keyboards. Also, remove a write to the wrong register and the CONFIG setting around the incorrect write. Signed-off-by: Marc Jones Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- drivers/input/i8042.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 691aabf402..26958aaa3e 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -666,31 +666,53 @@ static int kbd_input_empty(void) /******************************************************************************/ +static int wait_until_kbd_output_full(void) +{ + int kbdTimeout = KBD_TIMEOUT * 1000; + + while (((in8(I8042_STATUS_REG) & 0x01) == 0) && kbdTimeout--) + udelay(1); + + return kbdTimeout != -1; +} + +/******************************************************************************/ + static int kbd_reset(void) { + /* KB Reset */ if (kbd_input_empty() == 0) return -1; out8(I8042_DATA_REG, 0xff); + if (wait_until_kbd_output_full() == 0) + return -1; + + if (in8(I8042_DATA_REG) != 0xfa) /* ACK */ + return -1; + + if (wait_until_kbd_output_full() == 0) + return -1; + + if (in8(I8042_DATA_REG) != 0xaa) /* Test Pass*/ + return -1; + if (kbd_input_empty() == 0) return -1; -#ifdef CONFIG_USE_CPCIDVI + /* Set KBC mode */ out8(I8042_COMMAND_REG, 0x60); -#else - out8(I8042_DATA_REG, 0x60); -#endif if (kbd_input_empty() == 0) return -1; out8(I8042_DATA_REG, 0x45); - if (kbd_input_empty() == 0) return -1; + /* Enable Keyboard */ out8(I8042_COMMAND_REG, 0xae); if (kbd_input_empty() == 0) -- cgit v1.2.3 From 44abe47debc783396ec48d929844dcf1106b72f3 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Thu, 11 Oct 2012 15:15:53 +0000 Subject: input: Add ANSI 3.64 escape sequence generation. To support Non-ASCII keys (ex, Fn, PgUp/Dn, arrow keys, ...), we need to translate key code into escape sequence. (Updated by sjg@chromium.org to move away from a function to store keycodes, so we can easily record how many were sent. We now need to return this from input_send_keycodes() so we know whether keys were generated.) Signed-off-by: Hung-Te Lin Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- drivers/input/input.c | 102 ++++++++++++++++++++++++++++++++++++++++++-------- include/input.h | 2 + 2 files changed, 89 insertions(+), 15 deletions(-) diff --git a/drivers/input/input.c b/drivers/input/input.c index 5b2b4b0714..98006679b3 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c @@ -93,6 +93,22 @@ static unsigned char kbd_ctrl_xlate[] = { '\r', 0xff, 0xff }; +/* + * Scan key code to ANSI 3.64 escape sequence table. This table is + * incomplete in that it does not include all possible extra keys. + */ +static struct { + int kbd_scan_code; + char *escape; +} kbd_to_ansi364[] = { + { KEY_UP, "\033[A"}, + { KEY_DOWN, "\033[B"}, + { KEY_RIGHT, "\033[C"}, + { KEY_LEFT, "\033[D"}, +}; + +/* Maximum number of output characters that an ANSI sequence expands to */ +#define ANSI_CHAR_MAX 3 int input_queue_ascii(struct input_config *config, int ch) { @@ -289,24 +305,67 @@ static int input_check_keycodes(struct input_config *config, } /** + * Checks and converts a special key code into ANSI 3.64 escape sequence. + * + * @param config Input state + * @param keycode Key code to examine + * @param output_ch Buffer to place output characters into. It should + * be at least ANSI_CHAR_MAX bytes long, to allow for + * an ANSI sequence. + * @param max_chars Maximum number of characters to add to output_ch + * @return number of characters output, if the key was converted, otherwise 0. + * This may be larger than max_chars, in which case the overflow + * characters are not output. + */ +static int input_keycode_to_ansi364(struct input_config *config, + int keycode, char output_ch[], int max_chars) +{ + const char *escape; + int ch_count; + int i; + + for (i = ch_count = 0; i < ARRAY_SIZE(kbd_to_ansi364); i++) { + if (keycode != kbd_to_ansi364[i].kbd_scan_code) + continue; + for (escape = kbd_to_ansi364[i].escape; *escape; escape++) { + if (ch_count < max_chars) + output_ch[ch_count] = *escape; + ch_count++; + } + return ch_count; + } + + return 0; +} + +/** + * Converts and queues a list of key codes in escaped ASCII string form * Convert a list of key codes into ASCII * * You must call input_check_keycodes() before this. It turns the keycode - * list into a list of ASCII characters which are ready to send to the - * input layer. + * list into a list of ASCII characters and sends them to the input layer. * * Characters which were seen last time do not generate fresh ASCII output. + * The output (calls to queue_ascii) may be longer than num_keycodes, if the + * keycode contains special keys that was encoded to longer escaped sequence. * * @param config Input state * @param keycode List of key codes to examine * @param num_keycodes Number of key codes + * @param output_ch Buffer to place output characters into. It should + * be at last ANSI_CHAR_MAX * num_keycodes, to allow for + * ANSI sequences. + * @param max_chars Maximum number of characters to add to output_ch * @param same Number of key codes which are the same + * @return number of characters written into output_ch, or -1 if we would + * exceed max_chars chars. */ static int input_keycodes_to_ascii(struct input_config *config, - int keycode[], int num_keycodes, char output_ch[], int same) + int keycode[], int num_keycodes, char output_ch[], + int max_chars, int same) { struct input_key_xlate *table; - int ch_count; + int ch_count = 0; int i; table = &config->table[0]; @@ -321,19 +380,31 @@ static int input_keycodes_to_ascii(struct input_config *config, } } - /* now find normal keys */ - for (i = ch_count = 0; i < num_keycodes; i++) { + /* Start conversion by looking for the first new keycode (by same). */ + for (i = same; i < num_keycodes; i++) { int key = keycode[i]; + int ch = (key < table->num_entries) ? table->xlate[key] : 0xff; - if (key < table->num_entries && i >= same) { - int ch = table->xlate[key]; - - /* If a normal key with an ASCII value, add it! */ - if (ch != 0xff) - output_ch[ch_count++] = (uchar)ch; + /* + * For a normal key (with an ASCII value), add it; otherwise + * translate special key to escape sequence if possible. + */ + if (ch != 0xff) { + if (ch_count < max_chars) + output_ch[ch_count] = (uchar)ch; + ch_count++; + } else { + ch_count += input_keycode_to_ansi364(config, key, + output_ch, max_chars); } } + if (ch_count > max_chars) { + debug("%s: Output char buffer overflow size=%d, need=%d\n", + __func__, max_chars, ch_count); + return -1; + } + /* ok, so return keys */ return ch_count; } @@ -341,7 +412,7 @@ static int input_keycodes_to_ascii(struct input_config *config, int input_send_keycodes(struct input_config *config, int keycode[], int num_keycodes) { - char ch[num_keycodes]; + char ch[num_keycodes * ANSI_CHAR_MAX]; int count, i, same = 0; int is_repeat = 0; unsigned delay_ms; @@ -363,7 +434,7 @@ int input_send_keycodes(struct input_config *config, } count = input_keycodes_to_ascii(config, keycode, num_keycodes, - ch, is_repeat ? 0 : same); + ch, sizeof(ch), is_repeat ? 0 : same); for (i = 0; i < count; i++) input_queue_ascii(config, ch[i]); delay_ms = is_repeat ? @@ -371,7 +442,8 @@ int input_send_keycodes(struct input_config *config, config->repeat_delay_ms; config->next_repeat_ms = get_timer(0) + delay_ms; - return 0; + + return count; } int input_add_table(struct input_config *config, int left_keycode, diff --git a/include/input.h b/include/input.h index 0f4acb27f8..e90bb0ba9c 100644 --- a/include/input.h +++ b/include/input.h @@ -84,6 +84,8 @@ struct stdio_dev; * @param config Input state * @param keycode List of key codes to examine * @param num_keycodes Number of key codes + * @return number of ascii characters sent, or 0 if none, or -1 for an + * internal error */ int input_send_keycodes(struct input_config *config, int keycode[], int count); -- cgit v1.2.3 From ecd4551f14418abda71607946134fb40253b843b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:08 +0000 Subject: sh: Change bi_baudrate and global data baudrate to int These don't need to be longs, so change them. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/sh/include/asm/global_data.h | 2 +- arch/sh/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h index 6e534ad614..9a2c19376d 100644 --- a/arch/sh/include/asm/global_data.h +++ b/arch/sh/include/asm/global_data.h @@ -31,7 +31,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h index 6c04daf3bc..2c9c4634d8 100644 --- a/arch/sh/include/asm/u-boot.h +++ b/arch/sh/include/asm/u-boot.h @@ -33,7 +33,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned int bi_baudrate; /* Console Baudrate */ unsigned long bi_boot_params; /* where this board expects params */ } bd_t; diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 286c8c8011..698826c1f9 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -405,7 +405,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From 15dc95d48a1c46c0bc738c1857665e61d8ad0b7c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:09 +0000 Subject: avr32: Change bi_baudrate and global data baudrate to int MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These don't need to be longs, so change them. Signed-off-by: Simon Glass Acked-by: Andreas Bießmann Signed-off-by: Tom Rini --- arch/avr32/include/asm/global_data.h | 2 +- arch/avr32/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h index 7878bb185a..bf661e23be 100644 --- a/arch/avr32/include/asm/global_data.h +++ b/arch/avr32/include/asm/global_data.h @@ -33,7 +33,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long stack_end; /* highest stack address */ unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index 1d2959a2ad..97bbbdef6d 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -23,7 +23,7 @@ #define __ASM_U_BOOT_H__ 1 typedef struct bd_info { - unsigned long bi_baudrate; + unsigned int bi_baudrate; unsigned char bi_phy_id[4]; unsigned long bi_board_number; void *bi_boot_params; diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 698826c1f9..138693ea48 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -344,7 +344,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %lu bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From f5a5b3c5eef09785ec3d079e84e9f92725a13cd8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:10 +0000 Subject: m68k: Change bi_baudrate and global data baudrate to int These don't need to be longs, so change them. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/m68k/include/asm/global_data.h | 2 +- arch/m68k/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index cd55b83c52..0cdb11cf99 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -34,7 +34,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; #ifdef CONFIG_PCI diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h index 973c9ee098..8c7c554a46 100644 --- a/arch/m68k/include/asm/u-boot.h +++ b/arch/m68k/include/asm/u-boot.h @@ -58,7 +58,7 @@ typedef struct bd_info { unsigned long bi_vcofreq; /* vco Freq in MHz */ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ #endif - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 138693ea48..d6f14ab533 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -277,7 +277,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %ld bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From 74e8456bc1afef4db29ab64f9bef518cc7b6d8bf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:11 +0000 Subject: microblaze: Change bi_baudrate and global data baudrate to int These don't need to be longs, so change them. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/microblaze/include/asm/global_data.h | 2 +- arch/microblaze/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index de3b8dbe92..2111c7cba2 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -35,7 +35,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER unsigned long precon_buf_idx; /* Pre-Console buffer index */ diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index a0b1dbf9e6..8d00658564 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -40,7 +40,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index d6f14ab533..447c0a2a35 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -198,7 +198,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate); + printf("baudrate = %u bps\n", (ulong)bd->bi_baudrate); return 0; } -- cgit v1.2.3 From 7fffe2fac8a467a9eddf7f2306e1b5f7c3fae186 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:12 +0000 Subject: nios2: Change bi_baudrate and global data baudrate to int These don't need to be longs, so change them. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/nios2/include/asm/global_data.h | 2 +- arch/nios2/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index 3b0d9e6294..413b485b61 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -26,7 +26,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h index 315ef8bedb..e591237634 100644 --- a/arch/nios2/include/asm/u-boot.h +++ b/arch/nios2/include/asm/u-boot.h @@ -39,7 +39,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 447c0a2a35..899a2165e7 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -175,7 +175,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %ld bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From 7a68e330d04548b8fef4c7fcb9a365ae42d6ce35 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:13 +0000 Subject: openrisc: Change bi_baudrate and global data baudrate to int These don't need to be longs, so change them. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/openrisc/include/asm/global_data.h | 2 +- arch/openrisc/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/openrisc/include/asm/global_data.h b/arch/openrisc/include/asm/global_data.h index 6a0c0cc547..96f3f1cdbb 100644 --- a/arch/openrisc/include/asm/global_data.h +++ b/arch/openrisc/include/asm/global_data.h @@ -35,7 +35,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h index 76b813273f..f2f31d3bb4 100644 --- a/arch/openrisc/include/asm/u-boot.h +++ b/arch/openrisc/include/asm/u-boot.h @@ -32,7 +32,7 @@ #define _U_BOOT_H_ typedef struct bd_info { - unsigned long bi_baudrate; /* serial console baudrate */ + unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 899a2165e7..5af60e8aee 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -509,7 +509,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %ld bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From a7e5ee9ebb40e93dbb06c9e3b72f40c99d86e384 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:14 +0000 Subject: powerpc: Change bi_baudrate and global data baudrate to int These don't need to be longs, so change them. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/powerpc/include/asm/global_data.h | 2 +- arch/powerpc/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 5a5877fc2c..374fc6d5ab 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -38,7 +38,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; #if defined(CONFIG_8xx) diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index b2fa2b574b..7229a98eaa 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -81,7 +81,7 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ defined(CONFIG_405CR) || \ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 5af60e8aee..6b2f914c5f 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -148,7 +148,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mhz("ethspeed", bd->bi_ethspeed); #endif printf("IP addr = %s\n", getenv("ipaddr")); - printf("baudrate = %6ld bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", bd->bi_baudrate); print_num("relocaddr", gd->relocaddr); return 0; } -- cgit v1.2.3 From a8f1f1cd97b1efa4c5dfadf99a9646a402b4de38 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:15 +0000 Subject: sparc: Change bi_baudrate and global data baudrate to int These don't need to be longs, so change them. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/sparc/include/asm/global_data.h | 2 +- arch/sparc/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h index 93d3cc02eb..aa63b35cab 100644 --- a/arch/sparc/include/asm/global_data.h +++ b/arch/sparc/include/asm/global_data.h @@ -40,7 +40,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h index 8d011185a0..04c05d4ffe 100644 --- a/arch/sparc/include/asm/u-boot.h +++ b/arch/sparc/include/asm/u-boot.h @@ -54,7 +54,7 @@ typedef struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 6b2f914c5f..ca05985e59 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -231,7 +231,7 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %6ld bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From e46e31a83ab263430d616339bf096af4ca9b9aa2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:16 +0000 Subject: arm: Change global data baudrate to int This does not need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/arm/include/asm/global_data.h | 2 +- arch/arm/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index f8088fe21a..2b9af93806 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -34,7 +34,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER unsigned long precon_buf_idx; /* Pre-Console buffer index */ diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index eac3800729..2ba98bca7d 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -37,7 +37,7 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ + unsigned int bi_baudrate; /* serial console baudrate */ ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ unsigned long bi_arm_freq; /* arm frequency */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index ca05985e59..768699690c 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -369,7 +369,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) print_num("TLB addr", gd->tlb_addr); #endif -- cgit v1.2.3 From 5e84e5a7d445dd4fdcafa88675a99293587e4337 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:17 +0000 Subject: blackfin: Change global data baudrate to int This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/blackfin/include/asm/global_data.h | 2 +- arch/blackfin/include/asm/u-boot.h | 2 +- arch/blackfin/lib/board.c | 2 +- common/cmd_bdinfo.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h index 290a9e7662..d91e5a40d3 100644 --- a/arch/blackfin/include/asm/global_data.h +++ b/arch/blackfin/include/asm/global_data.h @@ -41,7 +41,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long board_type; - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER unsigned long precon_buf_idx; /* Pre-Console buffer index */ diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h index df81183e81..7abd6c2a32 100644 --- a/arch/blackfin/include/asm/u-boot.h +++ b/arch/blackfin/include/asm/u-boot.h @@ -29,7 +29,7 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ + unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ phys_size_t bi_memsize; /* size of DRAM memory in bytes */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index e47b606e87..9fbbea0d9b 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -78,7 +78,7 @@ static void display_global_data(void) printf(" gd: %p\n", gd); printf(" |-flags: %lx\n", gd->flags); printf(" |-board_type: %lx\n", gd->board_type); - printf(" |-baudrate: %lu\n", gd->baudrate); + printf(" |-baudrate: %u\n", gd->baudrate); printf(" |-have_console: %lx\n", gd->have_console); printf(" |-ram_size: %lx\n", gd->ram_size); printf(" |-env_addr: %lx\n", gd->env_addr); diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 768699690c..bc737d0239 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -304,7 +304,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From 8dc22b00ac2a43546e51c15339e07a5094d1e097 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:18 +0000 Subject: mips: Change global data baudrate to int This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/mips/include/asm/global_data.h | 2 +- arch/mips/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 6e2cdc72cf..a735a8a2c7 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -48,7 +48,7 @@ typedef struct global_data { unsigned long tbl; unsigned long lastinc; #endif - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER unsigned long precon_buf_idx; /* Pre-Console buffer index */ diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index 590649aa3e..5fa4a6a730 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -32,7 +32,7 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ + unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index bc737d0239..aca54d1116 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -324,7 +324,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From a25356d77143b3ecf3695b5b71c5abbdca6da079 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:19 +0000 Subject: nds32: Change global data baudrate to int This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/nds32/include/asm/global_data.h | 2 +- arch/nds32/include/asm/u-boot.h | 2 +- common/cmd_bdinfo.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h index 94bd4c2722..b1feb2c0d0 100644 --- a/arch/nds32/include/asm/global_data.h +++ b/arch/nds32/include/asm/global_data.h @@ -44,7 +44,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h index b533fea7c5..7b8d8e48fb 100644 --- a/arch/nds32/include/asm/u-boot.h +++ b/arch/nds32/include/asm/u-boot.h @@ -39,7 +39,7 @@ #include typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ + unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index aca54d1116..656c565535 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -487,7 +487,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From 55f97c1bfb3eb71e623576179fc0b995d0fd18ad Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:20 +0000 Subject: x86: Change global data baudrate to int This doesn't need to be a long, so change it. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/x86/include/asm/global_data.h | 2 +- common/cmd_bdinfo.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 6d29c0b9a3..bce999f41c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -38,7 +38,7 @@ typedef struct global_data { unsigned long gd_addr; /* Location of Global Data */ bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER unsigned long precon_buf_idx; /* Pre-Console buffer index */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 656c565535..48cdd16dd2 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -439,7 +439,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); print_mhz("ethspeed", bd->bi_ethspeed); #endif - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", bd->bi_baudrate); return 0; } -- cgit v1.2.3 From eeaec258b751075d48e081d645516dab3240ab96 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:21:21 +0000 Subject: sandbox: Change global data baudrate to int This doesn't need to be a long, so change it. Signed-off-by: Simon Glass Signed-off-by: Tom Rini --- arch/sandbox/include/asm/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h index 581fd2f2a0..78a751d96f 100644 --- a/arch/sandbox/include/asm/global_data.h +++ b/arch/sandbox/include/asm/global_data.h @@ -36,7 +36,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ -- cgit v1.2.3 From 7f14f30a6d6c80f9fbe3fd8d5b0c294575e3094e Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 15 Oct 2012 09:55:50 +0000 Subject: patman: force git log commands to not use color Colored logs confuse patman when analyzing logs. Add --no-color option in git log commands in case the default config has color. Signed-off-by: Albert ARIBAUD Acked-by: Simon Glass Signed-off-by: Tom Rini --- tools/patman/gitutil.py | 2 +- tools/patman/patchstream.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 59eca99341..72d37a0b04 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -38,7 +38,7 @@ def CountCommitsToBranch(): Return: Number of patches that exist on top of the branch """ - pipe = [['git', 'log', '--oneline', '@{upstream}..'], + pipe = [['git', 'log', '--no-color', '--oneline', '@{upstream}..'], ['wc', '-l']] stdout = command.RunPipe(pipe, capture=True, oneline=True) patch_count = int(stdout) diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index 0503bac42e..ad280cc46c 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -344,7 +344,8 @@ def GetMetaData(start, count): start: Commit to start from: 0=HEAD, 1=next one, etc. count: Number of commits to list """ - pipe = [['git', 'log', '--reverse', 'HEAD~%d' % start, '-n%d' % count]] + pipe = [['git', 'log', '--no-color', '--reverse', 'HEAD~%d' % start, + '-n%d' % count]] stdout = command.RunPipe(pipe, capture=True) series = Series() ps = PatchStream(series, is_log=True) -- cgit v1.2.3 From e81e79ede1aa1052735b9ee9a364f99b93605a08 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:26:07 +0000 Subject: usb: Support the CONFIG_SYS_64BIT_LBA option usb_storage wouldn't compile when the CONFIG_SYS_64BIT_LBA option is turned on because the used fixed size data types in their exported functions when they should have used lbaint_t for the block count parameter. That meant that when the sizes happened to be the same, when using a 28 bit LBA, the driver would build, but when it wasn't, a 48 bit LBA, things broke. This change adjusts the signatures to use the right type and makes small adjustments in the affected functions. Signed-off-by: Gabe Black Signed-off-by: Simon Glass Reviewed-by: Marek Vasut --- common/usb_storage.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/common/usb_storage.c b/common/usb_storage.c index 950451e11f..0c2a4c718f 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -179,9 +179,9 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *us, int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss); unsigned long usb_stor_read(int device, unsigned long blknr, - unsigned long blkcnt, void *buffer); + lbaint_t blkcnt, void *buffer); unsigned long usb_stor_write(int device, unsigned long blknr, - unsigned long blkcnt, const void *buffer); + lbaint_t blkcnt, const void *buffer); struct usb_device * usb_get_dev_index(int index); void uhci_show_temp_int_td(void); @@ -1053,9 +1053,10 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor, #endif /* CONFIG_USB_BIN_FIXUP */ unsigned long usb_stor_read(int device, unsigned long blknr, - unsigned long blkcnt, void *buffer) + lbaint_t blkcnt, void *buffer) { - unsigned long start, blks, buf_addr; + lbaint_t start, blks; + uintptr_t buf_addr; unsigned short smallblks; struct usb_device *dev; struct us_data *ss; @@ -1084,7 +1085,7 @@ unsigned long usb_stor_read(int device, unsigned long blknr, start = blknr; blks = blkcnt; - USB_STOR_PRINTF("\nusb_read: dev %d startblk %lx, blccnt %lx" + USB_STOR_PRINTF("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n", device, start, blks, buf_addr); do { @@ -1114,7 +1115,8 @@ retry_it: } while (blks != 0); ss->flags &= ~USB_READY; - USB_STOR_PRINTF("usb_read: end startblk %lx, blccnt %x buffer %lx\n", + USB_STOR_PRINTF("usb_read: end startblk " LBAF + ", blccnt %x buffer %lx\n", start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ @@ -1124,9 +1126,10 @@ retry_it: } unsigned long usb_stor_write(int device, unsigned long blknr, - unsigned long blkcnt, const void *buffer) + lbaint_t blkcnt, const void *buffer) { - unsigned long start, blks, buf_addr; + lbaint_t start, blks; + uintptr_t buf_addr; unsigned short smallblks; struct usb_device *dev; struct us_data *ss; @@ -1156,7 +1159,7 @@ unsigned long usb_stor_write(int device, unsigned long blknr, start = blknr; blks = blkcnt; - USB_STOR_PRINTF("\nusb_write: dev %d startblk %lx, blccnt %lx" + USB_STOR_PRINTF("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n", device, start, blks, buf_addr); do { @@ -1188,7 +1191,8 @@ retry_it: } while (blks != 0); ss->flags &= ~USB_READY; - USB_STOR_PRINTF("usb_write: end startblk %lx, blccnt %x buffer %lx\n", + USB_STOR_PRINTF("usb_write: end startblk " LBAF + ", blccnt %x buffer %lx\n", start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ -- cgit v1.2.3 From 8b8d779dacc149be0607dfc1b399bbdb62e57108 Mon Sep 17 00:00:00 2001 From: Vincent Palatin Date: Tue, 24 Jul 2012 07:12:02 +0000 Subject: usb: fallback safely when a configuration descriptor is too large When a USB configuration descriptor was larger than our USB buffer (512 bytes), we were skipping the full descriptor reading but then we were still parsing and using it, triggering memory corruptions. Now in that case, it just skips this device enumeration and displays the appropriate message to the user, so he can fix the buffer if he wants. This bug was triggered by some UVC webcams which have very large configuration descriptors (e.g. a couple of kB) describing all their supported video encodings. Signed-off-by: Vincent Palatin Acked-by: Simon Glass --- common/usb.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/common/usb.c b/common/usb.c index 1c9763cb6c..50b81752eb 100644 --- a/common/usb.c +++ b/common/usb.c @@ -508,8 +508,8 @@ int usb_get_configuration_no(struct usb_device *dev, tmp = le16_to_cpu(config->wTotalLength); if (tmp > USB_BUFSIZ) { - USB_PRINTF("usb_get_configuration_no: failed to get " \ - "descriptor - too long: %d\n", tmp); + printf("usb_get_configuration_no: failed to get " \ + "descriptor - too long: %d\n", tmp); return -1; } @@ -946,7 +946,13 @@ int usb_new_device(struct usb_device *dev) le16_to_cpus(&dev->descriptor.idProduct); le16_to_cpus(&dev->descriptor.bcdDevice); /* only support for one config for now */ - usb_get_configuration_no(dev, tmpbuf, 0); + err = usb_get_configuration_no(dev, tmpbuf, 0); + if (err < 0) { + printf("usb_new_device: Cannot read configuration, " \ + "skipping device %04x:%04x\n", + dev->descriptor.idVendor, dev->descriptor.idProduct); + return -1; + } usb_parse_config(dev, tmpbuf, 0); usb_set_maxpacket(dev); /* we set the default configuration here */ -- cgit v1.2.3 From 047cea3655cf34ce1f911c282e82598ded998dd2 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Mon, 22 Oct 2012 13:18:24 +0800 Subject: powerpc/usb: fix bug of CPU hang when missing USB PHY clock when missing USB PHY clock, u-boot will hang during USB initialization when issuing "usb start". We should check USBGP[PHY_CLK_VALID] bit to avoid CPU hanging in this case. Due to controller issue of PHY_CLK_VALID in ULPI mode, we set USB_EN before checking PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work. Signed-off-by: Shengzhou Liu Acked-by: Marek Vasut --- drivers/usb/host/ehci-fsl.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 7b8f033b03..f54b408966 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -30,6 +30,18 @@ #include "ehci.h" +/* Check USB PHY clock valid */ +static int usb_phy_clk_valid(struct usb_ehci *ehci) +{ + if (!((in_be32(&ehci->control) & PHY_CLK_VALID) || + in_be32(&ehci->prictrl))) { + printf("USB PHY clock invalid!\n"); + return 0; + } else { + return 1; + } +} + /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -82,18 +94,16 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) udelay(1000); /* delay required for PHY Clk to appear */ #endif out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); + setbits_be32(&ehci->control, USB_EN); } else { -#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) - clrbits_be32(&ehci->control, UTMI_PHY_EN); setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); + clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN); udelay(1000); /* delay required for PHY Clk to appear */ -#endif + if (!usb_phy_clk_valid(ehci)) + return -EINVAL; out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); } - /* Enable interface. */ - setbits_be32(&ehci->control, USB_EN); - out_be32(&ehci->prictrl, 0x0000000c); out_be32(&ehci->age_cnt_limit, 0x00000040); out_be32(&ehci->sictrl, 0x00000001); -- cgit v1.2.3 From b660df3c9031ba2efded2d083c34f2ea5ff978ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Aug 2012 15:19:06 +0000 Subject: COMMON: Implement common bounce buffer Implement common bounce buffer to be used on a less capable hardware. That includes hardware that can not do DMA from any address or such. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Andy Fleming Signed-off-by: Andy Fleming --- common/Makefile | 1 + common/bouncebuf.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/bouncebuf.h | 87 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 180 insertions(+) create mode 100644 common/bouncebuf.c create mode 100644 include/bouncebuf.h diff --git a/common/Makefile b/common/Makefile index fdfead79c2..2e3b22311d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -204,6 +204,7 @@ COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o endif +COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o COBJS-y += console.o COBJS-y += dlmalloc.o COBJS-y += image.o diff --git a/common/bouncebuf.c b/common/bouncebuf.c new file mode 100644 index 0000000000..4f827f893d --- /dev/null +++ b/common/bouncebuf.c @@ -0,0 +1,92 @@ +/* + * Generic bounce buffer implementation + * + * Copyright (C) 2012 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +static int addr_aligned(void *data, size_t len) +{ + const ulong align_mask = ARCH_DMA_MINALIGN - 1; + + /* Check if start is aligned */ + if ((ulong)data & align_mask) { + debug("Unaligned start address %p\n", data); + return 0; + } + + data += len; + + /* Check if end is aligned */ + if ((ulong)data & align_mask) { + debug("Unaligned end address %p\n", data); + return 0; + } + + /* Aligned */ + return 1; +} + +int bounce_buffer_start(void **data, size_t len, void **backup, uint8_t flags) +{ + void *tmp; + size_t alen; + + if (addr_aligned(*data, len)) { + *backup = NULL; + return 0; + } + + alen = roundup(len, ARCH_DMA_MINALIGN); + tmp = memalign(ARCH_DMA_MINALIGN, alen); + + if (!tmp) + return -ENOMEM; + + if (flags & GEN_BB_READ) + memcpy(tmp, *data, len); + + *backup = *data; + *data = tmp; + + return 0; +} + +int bounce_buffer_stop(void **data, size_t len, void **backup, uint8_t flags) +{ + void *tmp = *data; + + /* The buffer was already aligned, since "backup" is NULL. */ + if (!*backup) + return 0; + + if (flags & GEN_BB_WRITE) + memcpy(*backup, *data, len); + + *data = *backup; + free(tmp); + + return 0; +} diff --git a/include/bouncebuf.h b/include/bouncebuf.h new file mode 100644 index 0000000000..31021c5b85 --- /dev/null +++ b/include/bouncebuf.h @@ -0,0 +1,87 @@ +/* + * Generic bounce buffer implementation + * + * Copyright (C) 2012 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __INCLUDE_BOUNCEBUF_H__ +#define __INCLUDE_BOUNCEBUF_H__ + +/* + * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is lost upon + * stop() call. + */ +#define GEN_BB_READ (1 << 0) +/* + * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware. + * The source buffer starts in an undefined state upon start() call, then the + * operation requiring the aligned transfer happens, then the bounce buffer is + * copied into the destination buffer (if unaligned, otherwise destination + * buffer is used directly) upon stop() call. + */ +#define GEN_BB_WRITE (1 << 1) +/* + * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is copied + * into the destination buffer (if unaligned, otherwise destination buffer is + * used directly) upon stop() call. + */ +#define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE) + +#ifdef CONFIG_BOUNCE_BUFFER +/** + * bounce_buffer_start() -- Start the bounce buffer session + * data: pointer to buffer to be aligned + * len: length of the buffer + * backup: pointer to backup buffer (the original value is stored here if + * needed + * flags: flags describing the transaction, see above. + */ +int bounce_buffer_start(void **data, size_t len, void **backup, uint8_t flags); +/** + * bounce_buffer_stop() -- Finish the bounce buffer session + * data: pointer to buffer that was aligned + * len: length of the buffer + * backup: pointer to backup buffer (the original value is stored here if + * needed + * flags: flags describing the transaction, see above. + */ +int bounce_buffer_stop(void **data, size_t len, void **backup, uint8_t flags); +#else +static inline int bounce_buffer_start(void **data, size_t len, void **backup, + uint8_t flags) +{ + return 0; +} + +static inline int bounce_buffer_stop(void **data, size_t len, void **backup, + uint8_t flags) +{ + return 0; +} +#endif + +#endif -- cgit v1.2.3 From 4e6d81d1a4f042760287b31a6dc121b4ad754b7c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Aug 2012 15:19:07 +0000 Subject: MMC: MXS: Convert MXS MMC driver to generic bounce buffer Implement necessary code to use the generic bounce buffer routines inside this driver. This replaces the MMC bounce buffer, which is to be removed. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Andy Fleming Signed-off-by: Andy Fleming --- drivers/mmc/mxsmmc.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index c80b41b192..109acbf623 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -42,6 +42,7 @@ #include #include #include +#include struct mxsmmc_priv { int id; @@ -95,28 +96,33 @@ static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) { uint32_t data_count = data->blocksize * data->blocks; - uint32_t cache_data_count; + uint32_t cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); int dmach; struct mxs_dma_desc *desc = priv->desc; + void *addr, *backup; + uint8_t flags; memset(desc, 0, sizeof(struct mxs_dma_desc)); desc->address = (dma_addr_t)desc; - if (data_count % ARCH_DMA_MINALIGN) - cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); - else - cache_data_count = data_count; - if (data->flags & MMC_DATA_READ) { priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; - priv->desc->cmd.address = (dma_addr_t)data->dest; + addr = data->dest; + flags = GEN_BB_WRITE; } else { priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; - priv->desc->cmd.address = (dma_addr_t)data->src; + addr = (void *)data->src; + flags = GEN_BB_READ; + } + + bounce_buffer_start(&addr, data_count, &backup, flags); + + priv->desc->cmd.address = (dma_addr_t)addr; + if (data->flags & MMC_DATA_WRITE) { /* Flush data to DRAM so DMA can pick them up */ - flush_dcache_range((uint32_t)priv->desc->cmd.address, - (uint32_t)(priv->desc->cmd.address + cache_data_count)); + flush_dcache_range((uint32_t)addr, + (uint32_t)(addr) + cache_data_count); } /* Invalidate the area, so no writeback into the RAM races with DMA */ @@ -128,15 +134,19 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; mxs_dma_desc_append(dmach, priv->desc); - if (mxs_dma_go(dmach)) + if (mxs_dma_go(dmach)) { + bounce_buffer_stop(&addr, data_count, &backup, flags); return COMM_ERR; + } /* The data arrived into DRAM, invalidate cache over them */ if (data->flags & MMC_DATA_READ) { - invalidate_dcache_range((uint32_t)priv->desc->cmd.address, - (uint32_t)(priv->desc->cmd.address + cache_data_count)); + invalidate_dcache_range((uint32_t)addr, + (uint32_t)(addr) + cache_data_count); } + bounce_buffer_stop(&addr, data_count, &backup, flags); + return 0; } -- cgit v1.2.3 From 6dc71c8d2a3183a37624ef19a0532e7f827d868f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Aug 2012 15:19:08 +0000 Subject: MMC: MXS: Toggle the generic bounce buffer on the boards Flip the boards to use the generic bounce buffer instead of the MMC one. Signed-off-by: Marek Vasut Cc: Andy Fleming Cc: Fabio Estevam Signed-off-by: Andy Fleming --- include/configs/apx4devkit.h | 2 +- include/configs/m28evk.h | 2 +- include/configs/mx28evk.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index af0b714e11..6764b4749c 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -132,7 +132,7 @@ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_MMC_BOUNCE_BUFFER +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MXS_MMC #endif diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index bdbb82065e..b49ec8c7dd 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -135,7 +135,7 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_MMC_BOUNCE_BUFFER +#define CONFIG_BOUNCE_BUFFER #define CONFIG_GENERIC_MMC #define CONFIG_MXS_MMC #endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 7cdbec68de..1443833c83 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -142,7 +142,7 @@ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_MMC_BOUNCE_BUFFER +#define CONFIG_BOUNCE_BUFFER #define CONFIG_MXS_MMC #endif -- cgit v1.2.3 From 49a627f8a1646db883a72c7df3bcc4079138076a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Aug 2012 15:19:09 +0000 Subject: MMC: Remove the MMC bounce buffer Signed-off-by: Marek Vasut Cc: Andy Fleming Cc: Fabio Estevam Signed-off-by: Andy Fleming --- drivers/mmc/mmc.c | 92 ------------------------------------------------------- 1 file changed, 92 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index a60cfe1cb0..5fbf956302 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -47,93 +47,6 @@ int __board_mmc_getcd(struct mmc *mmc) { int board_mmc_getcd(struct mmc *mmc)__attribute__((weak, alias("__board_mmc_getcd"))); -#ifdef CONFIG_MMC_BOUNCE_BUFFER -static int mmc_bounce_need_bounce(struct mmc_data *orig) -{ - ulong addr, len; - - if (orig->flags & MMC_DATA_READ) - addr = (ulong)orig->dest; - else - addr = (ulong)orig->src; - - if (addr % ARCH_DMA_MINALIGN) { - debug("MMC: Unaligned data destination address %08lx!\n", addr); - return 1; - } - - len = (ulong)(orig->blocksize * orig->blocks); - if (len % ARCH_DMA_MINALIGN) { - debug("MMC: Unaligned data destination length %08lx!\n", len); - return 1; - } - - return 0; -} - -static int mmc_bounce_buffer_start(struct mmc_data *backup, - struct mmc_data *orig) -{ - ulong origlen, len; - void *buffer; - - if (!orig) - return 0; - - if (!mmc_bounce_need_bounce(orig)) - return 0; - - memcpy(backup, orig, sizeof(struct mmc_data)); - - origlen = orig->blocksize * orig->blocks; - len = roundup(origlen, ARCH_DMA_MINALIGN); - buffer = memalign(ARCH_DMA_MINALIGN, len); - if (!buffer) { - puts("MMC: Error allocating MMC bounce buffer!\n"); - return 1; - } - - if (orig->flags & MMC_DATA_READ) { - orig->dest = buffer; - } else { - memcpy(buffer, orig->src, origlen); - orig->src = buffer; - } - - return 0; -} - -static void mmc_bounce_buffer_stop(struct mmc_data *backup, - struct mmc_data *orig) -{ - ulong len; - - if (!orig) - return; - - if (!mmc_bounce_need_bounce(backup)) - return; - - if (backup->flags & MMC_DATA_READ) { - len = backup->blocksize * backup->blocks; - memcpy(backup->dest, orig->dest, len); - free(orig->dest); - orig->dest = backup->dest; - } else { - free((void *)orig->src); - orig->src = backup->src; - } - - return; - -} -#else -static inline int mmc_bounce_buffer_start(struct mmc_data *backup, - struct mmc_data *orig) { return 0; } -static inline void mmc_bounce_buffer_stop(struct mmc_data *backup, - struct mmc_data *orig) { } -#endif - int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct mmc_data backup; @@ -141,10 +54,6 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) memset(&backup, 0, sizeof(backup)); - ret = mmc_bounce_buffer_start(&backup, data); - if (ret) - return ret; - #ifdef CONFIG_MMC_TRACE int i; u8 *ptr; @@ -196,7 +105,6 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #else ret = mmc->send_cmd(mmc, cmd, data); #endif - mmc_bounce_buffer_stop(&backup, data); return ret; } -- cgit v1.2.3 From d6b2e5085c8fe3e70f9fffd450e54efae99cbf41 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 11 Sep 2012 08:59:51 +0000 Subject: mmc: Fix mmc_spi error on cmd->flags field The recent removal of the cmd->flags field caused error in the debuging code of mmc_spi. Fix this: mmc_spi.c: In function 'mmc_spi_request': mmc_spi.c:179:2: error: 'struct mmc_cmd' has no member named 'flags' Signed-off-by: Marek Vasut Cc: Andy Fleming Signed-off-by: Andy Fleming --- drivers/mmc/mmc_spi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index de43a85355..11ba532b0c 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -176,8 +176,8 @@ static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd, u8 r1; int i; int ret = 0; - debug("%s:cmd%d %x %x %x\n", __func__, - cmd->cmdidx, cmd->resp_type, cmd->cmdarg, cmd->flags); + debug("%s:cmd%d %x %x\n", __func__, + cmd->cmdidx, cmd->resp_type, cmd->cmdarg); spi_claim_bus(spi); spi_cs_activate(spi); r1 = mmc_spi_sendcmd(mmc, cmd->cmdidx, cmd->cmdarg); -- cgit v1.2.3 From 5d48e4224791611498456908fc23a845cc5b4ed7 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Thu, 20 Sep 2012 20:31:54 +0000 Subject: mmc: sdhci: increase the timeout value for data transfer Timeout value is tunable. When run read/write operation, sometime returned the timeout error. Because the timeout value is too short. So increased the enough timeout value. (This timeout value is used to prevent the infinite loop.) Signed-off-by: Jaehoon Chung Signed-off-by: Kyungmin Park Signed-off-by: Andy Fleming --- drivers/mmc/sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 2e3c408bc5..932987427c 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -83,7 +83,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, { unsigned int stat, rdy, mask, timeout, block = 0; - timeout = 10000; + timeout = 1000000; rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; do { -- cgit v1.2.3 From 804c7f422169212e92530e1ddaf74bf1ca9ebfa1 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Thu, 20 Sep 2012 20:31:55 +0000 Subject: mmc: sdhci: add the DMA select for SDMA In host-control register, DMA select bit field is present. BUt in sdhci.c, didn't select for DMA. if set CONFIG_MMC_SDMA, we need to set SDMA-select bit. Signed-off-by: Jaehoon Chung Signed-off-by: Kyungmin Park Signed-off-by: Andy Fleming --- drivers/mmc/sdhci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 932987427c..15b46868ac 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -82,6 +82,13 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, unsigned int start_addr) { unsigned int stat, rdy, mask, timeout, block = 0; +#ifdef CONFIG_MMC_SDMA + unsigned char ctrl; + ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL); + ctrl &= ~SDHCI_CTRL_DMA_MASK; + ctrl |= SDHCI_CTRL_SDMA; + sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL); +#endif timeout = 1000000; rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; -- cgit v1.2.3 From 13243f2eafc4292917178051fe1bb5aab2774dca Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Thu, 20 Sep 2012 20:31:57 +0000 Subject: mmc: sdhci: Add a quirk to add delay during completion of sdhci_send_cmd MMC host controller requires a delay between every sdhci_send_cmd() execution. In s5p_mmc driver (s5p_sdhci replaces this driver), a delay of 1000us was provided after every mmc_send_cmd() call. Adding a quirk in current sdhci driver to replicate the behaviour. Without this delay, MMC initialization on Origen board fails with following error messages. Timeout for status update! mmc fail to send stop cmd Signed-off-by: Tushar Behera Signed-off-by: Jaehoon Chung Signed-off-by: Andy Fleming --- drivers/mmc/s5p_sdhci.c | 3 ++- drivers/mmc/sdhci.c | 3 +++ include/sdhci.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index b9782367e2..dc49d37f5c 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -83,7 +83,8 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) host->ioaddr = (void *)regbase; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | - SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR; + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | + SDHCI_QUIRK_WAIT_SEND_CMD; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 15b46868ac..7845f873ac 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -240,6 +240,9 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (!ret && data) ret = sdhci_transfer_data(host, data, start_addr); + if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) + udelay(1000); + stat = sdhci_readl(host, SDHCI_INT_STATUS); sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); if (!ret) { diff --git a/include/sdhci.h b/include/sdhci.h index c0345ed86e..c44793d5ec 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -224,6 +224,7 @@ #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) #define SDHCI_QUIRK_NO_CD (1 << 5) +#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) /* to make gcc happy */ struct sdhci_host; -- cgit v1.2.3 From 831f849f79f2c9fcaa6f85f4158296d2dbc3916c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 30 Sep 2012 10:09:49 +0000 Subject: mmc: pxa: Flip over the remaining boards to pxa_mmc_generic Some of the boards still used the old PXA_MMC driver instead of the new generic one. Use the new one instead so the old can be removed and the generic MMC framework can be properly used. Signed-off-by: Marek Vasut Cc: Andy Fleming Signed-off-by: Andy Fleming --- board/lubbock/lubbock.c | 9 +++++++++ board/palmtc/palmtc.c | 9 +++++++++ board/pxa255_idp/pxa_idp.c | 9 +++++++++ board/trizepsiv/conxs.c | 9 +++++++++ include/configs/lubbock.h | 3 ++- include/configs/palmtc.h | 3 ++- include/configs/pxa255_idp.h | 3 ++- include/configs/trizepsiv.h | 3 ++- 8 files changed, 44 insertions(+), 4 deletions(-) diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c index 3527b381df..ef2cc24aae 100644 --- a/board/lubbock/lubbock.c +++ b/board/lubbock/lubbock.c @@ -29,6 +29,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +57,14 @@ int board_init (void) return 0; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + int board_late_init(void) { setenv("stdout", "serial"); diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c index b23eec805e..590ca414aa 100644 --- a/board/palmtc/palmtc.c +++ b/board/palmtc/palmtc.c @@ -24,6 +24,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -51,6 +52,14 @@ int board_init(void) return 0; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + int dram_init(void) { pxa2xx_dram_init(); diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index 877e8d9b2a..9931efdc08 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -77,6 +78,14 @@ int board_init (void) return 0; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + int board_late_init(void) { setenv("stdout", "serial"); diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 871e052b04..c3dee8459e 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -152,3 +153,11 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index ed64960879..5886a155dc 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -130,7 +130,8 @@ #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ #ifdef CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #endif diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 6e8d8e9d57..9c948c5473 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -77,7 +77,8 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 24c53633f0..5a15af6b6a 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -245,7 +245,8 @@ #define RTC 1 /* enable 32KHz osc */ #ifdef CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #endif diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index bc69c1ea2b..c1bfe31e46 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -170,7 +170,8 @@ #define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ #ifdef CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #endif -- cgit v1.2.3 From 48cf9dc63c9353febf8b2c27ff20f0d6dc56d6b6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 30 Sep 2012 10:09:50 +0000 Subject: mmc: pxa: Remove the old non-generic PXA MMC driver This driver is no longer used and it's remaining users were converted to the new generic PXA MMC driver. Thus, remove this driver. Signed-off-by: Marek Vasut Cc: Andy Fleming Signed-off-by: Andy Fleming --- drivers/mmc/Makefile | 1 - drivers/mmc/pxa_mmc.c | 643 -------------------------------------------------- 2 files changed, 644 deletions(-) delete mode 100644 drivers/mmc/pxa_mmc.c diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 565ba6a383..ac3cb0b1e0 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -41,7 +41,6 @@ COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o -COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o COBJS-$(CONFIG_SDHCI) += sdhci.o COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c deleted file mode 100644 index 80c4445034..0000000000 --- a/drivers/mmc/pxa_mmc.c +++ /dev/null @@ -1,643 +0,0 @@ -/* - * (C) Copyright 2003 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pxa_mmc.h" - -extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no); - -static block_dev_desc_t mmc_dev; - -block_dev_desc_t *mmc_get_dev(int dev) -{ - return ((block_dev_desc_t *) & mmc_dev); -} - -/* - * FIXME needs to read cid and csd info to determine block size - * and other parameters - */ -static uchar mmc_buf[MMC_BLOCK_SIZE]; -static uchar spec_ver; -static int mmc_ready = 0; -static int wide = 0; - -static uint32_t * -/****************************************************/ -mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) -/****************************************************/ -{ - static uint32_t resp[4], a, b, c; - uint32_t status; - int i; - - debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl, - cmdat | wide); - writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); - writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK); - while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF)) - ; - writel(cmd, MMC_CMD); - writel(argh, MMC_ARGH); - writel(argl, MMC_ARGL); - writel(cmdat | wide, MMC_CMDAT); - writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK); - writel(MMC_STRPCL_START_CLK, MMC_STRPCL); - while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES)) - ; - - status = readl(MMC_STAT); - debug("MMC status 0x%08x\n", status); - if (status & MMC_STAT_TIME_OUT_RESPONSE) { - return 0; - } - - /* Linux says: - * Did I mention this is Sick. We always need to - * discard the upper 8 bits of the first 16-bit word. - */ - a = (readl(MMC_RES) & 0xffff); - for (i = 0; i < 4; i++) { - b = (readl(MMC_RES) & 0xffff); - c = (readl(MMC_RES) & 0xffff); - resp[i] = (a << 24) | (b << 8) | (c >> 8); - a = c; - debug("MMC resp[%d] = %#08x\n", i, resp[i]); - } - - return resp; -} - -int -/****************************************************/ -mmc_block_read(uchar * dst, uint32_t src, int len) -/****************************************************/ -{ - ushort argh, argl; - ulong status; - - if (len == 0) { - return 0; - } - - debug("mmc_block_rd dst %p src %08x len %d\n", dst, src, len); - - argh = len >> 16; - argl = len & 0xffff; - - /* set block len */ - mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); - - /* send read command */ - argh = src >> 16; - argl = src & 0xffff; - writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); - writel(0xffff, MMC_RDTO); - writel(1, MMC_NOB); - writel(len, MMC_BLKLEN); - mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl, - MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | - MMC_CMDAT_DATA_EN); - - writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK); - while (len) { - if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) { -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - int i; - for (i = min(len, 32); i; i--) { - *dst++ = readb(MMC_RXFIFO); - len--; - } -#else - *dst++ = readb(MMC_RXFIFO); - len--; -#endif - } - status = readl(MMC_STAT); - if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); - return -1; - } - } - writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK); - while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE)) - ; - status = readl(MMC_STAT); - if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); - return -1; - } - return 0; -} - -int -/****************************************************/ -mmc_block_write(ulong dst, uchar * src, int len) -/****************************************************/ -{ - ushort argh, argl; - ulong status; - - if (len == 0) { - return 0; - } - - debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong) src, len); - - argh = len >> 16; - argl = len & 0xffff; - - /* set block len */ - mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); - - /* send write command */ - argh = dst >> 16; - argl = dst & 0xffff; - writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); - writel(1, MMC_NOB); - writel(len, MMC_BLKLEN); - mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl, - MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK | - MMC_CMDAT_DATA_EN); - - writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK); - while (len) { - if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) { - int i, bytes = min(32, len); - - for (i = 0; i < bytes; i++) { - writel(*src++, MMC_TXFIFO); - } - if (bytes < 32) { - writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF); - } - len -= bytes; - } - status = readl(MMC_STAT); - if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); - return -1; - } - } - writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK); - while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE)) - ; - writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK); - while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE)) - ; - status = readl(MMC_STAT); - if (status & MMC_STAT_ERRORS) { - printf("MMC_STAT error %lx\n", status); - return -1; - } - return 0; -} - -int -/****************************************************/ -pxa_mmc_read(long src, uchar * dst, int size) -/****************************************************/ -{ - ulong end, part_start, part_end, part_len, aligned_start, aligned_end; - ulong mmc_block_size, mmc_block_address; - - if (size == 0) { - return 0; - } - - if (!mmc_ready) { - printf("Please initial the MMC first\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - src -= CONFIG_SYS_MMC_BASE; - end = src + size; - part_start = ~mmc_block_address & src; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & src; - aligned_end = mmc_block_address & end; - - /* all block aligned accesses */ - debug - ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong) dst, end, part_start, part_end, aligned_start, - aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; - debug - ("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong) dst, end, part_start, part_end, aligned_start, - aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < - 0) { - return -1; - } - memcpy(dst, mmc_buf + part_start, part_len); - dst += part_len; - src += part_len; - } - debug - ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong) dst, end, part_start, part_end, aligned_start, - aligned_end); - for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug - ("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong) dst, end, part_start, part_end, aligned_start, - aligned_end); - if ((mmc_block_read((uchar *) (dst), src, mmc_block_size)) < 0) { - return -1; - } - } - debug - ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong) dst, end, part_start, part_end, aligned_start, - aligned_end); - if (part_end && src < end) { - debug - ("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, (ulong) dst, end, part_start, part_end, aligned_start, - aligned_end); - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { - return -1; - } - memcpy(dst, mmc_buf, part_end); - } - return 0; -} - -int -/****************************************************/ -pxa_mmc_write(uchar * src, uint32_t dst, int size) -/****************************************************/ -{ - ulong end, part_start, part_end, part_len, aligned_start, aligned_end; - ulong mmc_block_size, mmc_block_address; - - if (size == 0) { - return 0; - } - - if (!mmc_ready) { - printf("Please initial the MMC first\n"); - return -1; - } - - mmc_block_size = MMC_BLOCK_SIZE; - mmc_block_address = ~(mmc_block_size - 1); - - dst -= CONFIG_SYS_MMC_BASE; - end = dst + size; - part_start = ~mmc_block_address & dst; - part_end = ~mmc_block_address & end; - aligned_start = mmc_block_address & dst; - aligned_end = mmc_block_address & end; - - /* all block aligned accesses */ - debug - ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, dst, end, part_start, part_end, aligned_start, - aligned_end); - if (part_start) { - part_len = mmc_block_size - part_start; - debug - ("ps src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, dst, end, part_start, part_end, aligned_start, - aligned_end); - if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < - 0) { - return -1; - } - memcpy(mmc_buf + part_start, src, part_len); - if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < - 0) { - return -1; - } - dst += part_len; - src += part_len; - } - debug - ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, dst, end, part_start, part_end, aligned_start, - aligned_end); - for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { - debug - ("al src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, dst, end, part_start, part_end, aligned_start, - aligned_end); - if ((mmc_block_write(dst, (uchar *) src, mmc_block_size)) < 0) { - return -1; - } - } - debug - ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, dst, end, part_start, part_end, aligned_start, - aligned_end); - if (part_end && dst < end) { - debug - ("pe src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n", - src, dst, end, part_start, part_end, aligned_start, - aligned_end); - if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) { - return -1; - } - memcpy(mmc_buf, src, part_end); - if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) { - return -1; - } - } - return 0; -} - -static ulong -/****************************************************/ -mmc_bread(int dev_num, ulong blknr, lbaint_t blkcnt, void *dst) -/****************************************************/ -{ - int mmc_block_size = MMC_BLOCK_SIZE; - ulong src = blknr * mmc_block_size + CONFIG_SYS_MMC_BASE; - - pxa_mmc_read(src, (uchar *) dst, blkcnt * mmc_block_size); - return blkcnt; -} - -#ifdef __GNUC__ -#define likely(x) __builtin_expect(!!(x), 1) -#define unlikely(x) __builtin_expect(!!(x), 0) -#else -#define likely(x) (x) -#define unlikely(x) (x) -#endif - -#define UNSTUFF_BITS(resp,start,size) \ - ({ \ - const int __size = size; \ - const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \ - const int32_t __off = 3 - ((start) / 32); \ - const int32_t __shft = (start) & 31; \ - uint32_t __res; \ - \ - __res = resp[__off] >> __shft; \ - if (__size + __shft > 32) \ - __res |= resp[__off-1] << ((32 - __shft) % 32); \ - __res & __mask; \ - }) - -/* - * Given the decoded CSD structure, decode the raw CID to our CID structure. - */ -static void mmc_decode_cid(uint32_t * resp) -{ - if (IF_TYPE_SD == mmc_dev.if_type) { - /* - * SD doesn't currently have a version field so we will - * have to assume we can parse this. - */ - sprintf((char *)mmc_dev.vendor, - "Man %02x OEM %c%c \"%c%c%c%c%c\" Date %02u/%04u", - UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, 112, 8), - UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, 96, 8), - UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, 80, 8), - UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, 64, 8), - UNSTUFF_BITS(resp, 8, 4), UNSTUFF_BITS(resp, 12, - 8) + 2000); - sprintf((char *)mmc_dev.revision, "%d.%d", - UNSTUFF_BITS(resp, 60, 4), UNSTUFF_BITS(resp, 56, 4)); - sprintf((char *)mmc_dev.product, "%u", - UNSTUFF_BITS(resp, 24, 32)); - } else { - /* - * The selection of the format here is based upon published - * specs from sandisk and from what people have reported. - */ - switch (spec_ver) { - case 0: /* MMC v1.0 - v1.2 */ - case 1: /* MMC v1.4 */ - sprintf((char *)mmc_dev.vendor, - "Man %02x%02x%02x \"%c%c%c%c%c%c%c\" Date %02u/%04u", - UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, - 112, - 8), - UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, - 96, 8), - UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, - 80, 8), - UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, - 64, 8), - UNSTUFF_BITS(resp, 56, 8), UNSTUFF_BITS(resp, - 48, 8), - UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8, - 4) + - 1997); - sprintf((char *)mmc_dev.revision, "%d.%d", - UNSTUFF_BITS(resp, 44, 4), UNSTUFF_BITS(resp, - 40, 4)); - sprintf((char *)mmc_dev.product, "%u", - UNSTUFF_BITS(resp, 16, 24)); - break; - - case 2: /* MMC v2.0 - v2.2 */ - case 3: /* MMC v3.1 - v3.3 */ - case 4: /* MMC v4 */ - sprintf((char *)mmc_dev.vendor, - "Man %02x OEM %04x \"%c%c%c%c%c%c\" Date %02u/%04u", - UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, - 104, - 16), - UNSTUFF_BITS(resp, 96, 8), UNSTUFF_BITS(resp, - 88, 8), - UNSTUFF_BITS(resp, 80, 8), UNSTUFF_BITS(resp, - 72, 8), - UNSTUFF_BITS(resp, 64, 8), UNSTUFF_BITS(resp, - 56, 8), - UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8, - 4) + - 1997); - sprintf((char *)mmc_dev.product, "%u", - UNSTUFF_BITS(resp, 16, 32)); - sprintf((char *)mmc_dev.revision, "N/A"); - break; - - default: - printf("MMC card has unknown MMCA version %d\n", - spec_ver); - break; - } - } - printf("%s card.\nVendor: %s\nProduct: %s\nRevision: %s\n", - (IF_TYPE_SD == mmc_dev.if_type) ? "SD" : "MMC", mmc_dev.vendor, - mmc_dev.product, mmc_dev.revision); -} - -/* - * Given a 128-bit response, decode to our card CSD structure. - */ -static void mmc_decode_csd(uint32_t * resp) -{ - unsigned int mult, csd_struct; - - if (IF_TYPE_SD == mmc_dev.if_type) { - csd_struct = UNSTUFF_BITS(resp, 126, 2); - if (csd_struct != 0) { - printf("SD: unrecognised CSD structure version %d\n", - csd_struct); - return; - } - } else { - /* - * We only understand CSD structure v1.1 and v1.2. - * v1.2 has extra information in bits 15, 11 and 10. - */ - csd_struct = UNSTUFF_BITS(resp, 126, 2); - if (csd_struct != 1 && csd_struct != 2) { - printf("MMC: unrecognised CSD structure version %d\n", - csd_struct); - return; - } - - spec_ver = UNSTUFF_BITS(resp, 122, 4); - mmc_dev.if_type = IF_TYPE_MMC; - } - - mult = 1 << (UNSTUFF_BITS(resp, 47, 3) + 2); - mmc_dev.lba = (1 + UNSTUFF_BITS(resp, 62, 12)) * mult; - mmc_dev.blksz = 1 << UNSTUFF_BITS(resp, 80, 4); - - /* FIXME: The following just makes assumes that's the partition type -- should really read it */ - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = DEV_TYPE_HARDDISK; - mmc_dev.removable = 0; - mmc_dev.block_read = mmc_bread; - - printf("Detected: %lu blocks of %lu bytes (%luMB) ", - mmc_dev.lba, - mmc_dev.blksz, - mmc_dev.lba * mmc_dev.blksz / (1024 * 1024)); -} - -int -/****************************************************/ -mmc_legacy_init(int verbose) -/****************************************************/ -{ - int retries, rc = -ENODEV; - uint32_t cid_resp[4]; - uint32_t *resp; - uint16_t rca = 0; - - /* Reset device interface type */ - mmc_dev.if_type = IF_TYPE_UNKNOWN; - -#ifdef CONFIG_CPU_MONAHANS /* pxa3xx */ - writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA); -#else /* pxa2xx */ - writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */ -#endif - writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT); - writel(MMC_RES_TO_MAX, MMC_RESTO); - writel(MMC_SPI_DISABLE, MMC_SPI); - - /* reset */ - mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); - udelay(200000); - retries = 3; - while (retries--) { - resp = mmc_cmd(MMC_CMD_APP_CMD, 0, 0, MMC_CMDAT_R1); - if (!(resp[0] & 0x00000020)) { /* Card does not support APP_CMD */ - debug("Card does not support APP_CMD\n"); - break; - } - - /* Select 3.2-3.3V and 3.3-3.4V */ - resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0030, 0x0000, - MMC_CMDAT_R3 | (retries < 2 ? 0 - : MMC_CMDAT_INIT)); - if (resp[0] & 0x80000000) { - mmc_dev.if_type = IF_TYPE_SD; - debug("Detected SD card\n"); - break; - } - udelay(200000); - } - - if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) { - debug("Failed to detect SD Card, trying MMC\n"); - resp = - mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, MMC_CMDAT_R3); - - retries = 10; - while (retries-- && resp && !(resp[0] & 0x80000000)) { - udelay(200000); - resp = - mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, - MMC_CMDAT_R3); - } - } - - /* try to get card id */ - resp = - mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, 0, MMC_CMDAT_R2 | MMC_CMDAT_BUSY); - if (resp) { - memcpy(cid_resp, resp, sizeof(cid_resp)); - - /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1); - if (IF_TYPE_SD == mmc_dev.if_type) - rca = ((resp[0] & 0xffff0000) >> 16); - resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2); - if (resp) { - mmc_decode_csd(resp); - rc = 0; - mmc_ready = 1; - } - - mmc_decode_cid(cid_resp); - } - - writel(0, MMC_CLKRT); /* 20 MHz */ - resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); - -#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS) - if (IF_TYPE_SD == mmc_dev.if_type) { - resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1); - resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1); - wide = MMC_CMDAT_SD_4DAT; - } -#endif - - fat_register_device(&mmc_dev, 1); /* partitions start counting with 1 */ - - return rc; -} -- cgit v1.2.3 From 757bff49ba3159d71ccacabdb68f8309b1eb6613 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 15 Oct 2012 19:10:29 +0000 Subject: mmc: dw-mmc: support DesignWare MMC Controller Support the DesginWare MMC Controller. Signed-off-by: Jaehoon Chung Signed-off-by: Kyungmin Park Signed-off-by: Rajeshawari Shinde Signed-off-by: Andy Fleming --- drivers/mmc/Makefile | 1 + drivers/mmc/dw_mmc.c | 385 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/dwmmc.h | 191 +++++++++++++++++++++++++ 3 files changed, 577 insertions(+) create mode 100644 drivers/mmc/dw_mmc.c create mode 100644 include/dwmmc.h diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index ac3cb0b1e0..a1dd7302bf 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_SDHCI) += sdhci.o COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o +COBJS-$(CONFIG_DWMMC) += dw_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c new file mode 100644 index 0000000000..4070d4ea53 --- /dev/null +++ b/drivers/mmc/dw_mmc.c @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + * Rajeshawari Shinde + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +#define PAGE_SIZE 4096 + +static int dwmci_wait_reset(struct dwmci_host *host, u32 value) +{ + unsigned long timeout = 1000; + u32 ctrl; + + dwmci_writel(host, DWMCI_CTRL, value); + + while (timeout--) { + ctrl = dwmci_readl(host, DWMCI_CTRL); + if (!(ctrl & DWMCI_RESET_ALL)) + return 1; + } + return 0; +} + +static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, + u32 desc0, u32 desc1, u32 desc2) +{ + struct dwmci_idmac *desc = idmac; + + desc->flags = desc0; + desc->cnt = desc1; + desc->addr = desc2; + desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac); +} + +static void dwmci_prepare_data(struct dwmci_host *host, + struct mmc_data *data) +{ + unsigned long ctrl; + unsigned int i = 0, flags, cnt, blk_cnt; + ulong data_start, data_end, start_addr; + ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks); + + + blk_cnt = data->blocks; + + dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); + + data_start = (ulong)cur_idmac; + dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); + + if (data->flags == MMC_DATA_READ) + start_addr = (unsigned int)data->dest; + else + start_addr = (unsigned int)data->src; + + do { + flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; + flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; + if (blk_cnt <= 8) { + flags |= DWMCI_IDMAC_LD; + cnt = data->blocksize * blk_cnt; + } else + cnt = data->blocksize * 8; + + dwmci_set_idma_desc(cur_idmac, flags, cnt, + start_addr + (i * PAGE_SIZE)); + + if(blk_cnt < 8) + break; + blk_cnt -= 8; + cur_idmac++; + i++; + } while(1); + + data_end = (ulong)cur_idmac; + flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); + + ctrl = dwmci_readl(host, DWMCI_CTRL); + ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; + dwmci_writel(host, DWMCI_CTRL, ctrl); + + ctrl = dwmci_readl(host, DWMCI_BMOD); + ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; + dwmci_writel(host, DWMCI_BMOD, ctrl); + + dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); + dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); +} + +static int dwmci_set_transfer_mode(struct dwmci_host *host, + struct mmc_data *data) +{ + unsigned long mode; + + mode = DWMCI_CMD_DATA_EXP; + if (data->flags & MMC_DATA_WRITE) + mode |= DWMCI_CMD_RW; + + return mode; +} + +static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + int flags = 0, i; + unsigned int timeout = 100000; + u32 retry = 10000; + u32 mask, ctrl; + + while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { + if (timeout == 0) { + printf("Timeout on data busy\n"); + return TIMEOUT; + } + timeout--; + } + + dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); + + if (data) + dwmci_prepare_data(host, data); + + + dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); + + if (data) + flags = dwmci_set_transfer_mode(host, data); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -1; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + flags |= DWMCI_CMD_ABORT_STOP; + else + flags |= DWMCI_CMD_PRV_DAT_WAIT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + flags |= DWMCI_CMD_RESP_EXP; + if (cmd->resp_type & MMC_RSP_136) + flags |= DWMCI_CMD_RESP_LENGTH; + } + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= DWMCI_CMD_CHECK_CRC; + + flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); + + debug("Sending CMD%d\n",cmd->cmdidx); + + dwmci_writel(host, DWMCI_CMD, flags); + + for (i = 0; i < retry; i++) { + mask = dwmci_readl(host, DWMCI_RINTSTS); + if (mask & DWMCI_INTMSK_CDONE) { + if (!data) + dwmci_writel(host, DWMCI_RINTSTS, mask); + break; + } + } + + if (i == retry) + return TIMEOUT; + + if (mask & DWMCI_INTMSK_RTO) { + debug("Response Timeout..\n"); + return TIMEOUT; + } else if (mask & DWMCI_INTMSK_RE) { + debug("Response Error..\n"); + return -1; + } + + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); + cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); + cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); + cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); + } else { + cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); + } + } + + if (data) { + do { + mask = dwmci_readl(host, DWMCI_RINTSTS); + if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { + debug("DATA ERROR!\n"); + return -1; + } + } while (!(mask & DWMCI_INTMSK_DTO)); + + dwmci_writel(host, DWMCI_RINTSTS, mask); + + ctrl = dwmci_readl(host, DWMCI_CTRL); + ctrl &= ~(DWMCI_DMA_EN); + dwmci_writel(host, DWMCI_CTRL, ctrl); + } + + udelay(100); + + return 0; +} + +static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) +{ + u32 div, status; + int timeout = 10000; + unsigned long sclk; + + if (freq == host->clock) + return 0; + + /* + * If host->mmc_clk didn't define, + * then assume that host->bus_hz is source clock value. + * host->bus_hz should be set from user. + */ + if (host->mmc_clk) + sclk = host->mmc_clk(host->dev_index); + else if (host->bus_hz) + sclk = host->bus_hz; + else { + printf("Didn't get source clock value..\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP(sclk, 2 * freq); + + dwmci_writel(host, DWMCI_CLKENA, 0); + dwmci_writel(host, DWMCI_CLKSRC, 0); + + dwmci_writel(host, DWMCI_CLKDIV, div); + dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | + DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); + + do { + status = dwmci_readl(host, DWMCI_CMD); + if (timeout-- < 0) { + printf("TIMEOUT error!!\n"); + return -ETIMEDOUT; + } + } while (status & DWMCI_CMD_START); + + dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | + DWMCI_CLKEN_LOW_PWR); + + dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | + DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); + + timeout = 10000; + do { + status = dwmci_readl(host, DWMCI_CMD); + if (timeout-- < 0) { + printf("TIMEOUT error!!\n"); + return -ETIMEDOUT; + } + } while (status & DWMCI_CMD_START); + + host->clock = freq; + + return 0; +} + +static void dwmci_set_ios(struct mmc *mmc) +{ + struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + u32 ctype; + + debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); + + dwmci_setup_bus(host, mmc->clock); + switch (mmc->bus_width) { + case 8: + ctype = DWMCI_CTYPE_8BIT; + break; + case 4: + ctype = DWMCI_CTYPE_4BIT; + break; + default: + ctype = DWMCI_CTYPE_1BIT; + break; + } + + dwmci_writel(host, DWMCI_CTYPE, ctype); + + if (host->clksel) + host->clksel(host); +} + +static int dwmci_init(struct mmc *mmc) +{ + struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + u32 fifo_size, fifoth_val; + + dwmci_writel(host, DWMCI_PWREN, 1); + + if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { + debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); + return -1; + } + + dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); + dwmci_writel(host, DWMCI_INTMASK, 0); + + dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); + + dwmci_writel(host, DWMCI_IDINTEN, 0); + dwmci_writel(host, DWMCI_BMOD, 1); + + fifo_size = dwmci_readl(host, DWMCI_FIFOTH); + if (host->fifoth_val) + fifoth_val = host->fifoth_val; + else + fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) | + TX_WMARK(fifo_size/2); + dwmci_writel(host, DWMCI_FIFOTH, fifoth_val); + + dwmci_writel(host, DWMCI_CLKENA, 0); + dwmci_writel(host, DWMCI_CLKSRC, 0); + + return 0; +} + +int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) +{ + struct mmc *mmc; + int err = 0; + + mmc = malloc(sizeof(struct mmc)); + if (!mmc) { + printf("mmc malloc fail!\n"); + return -1; + } + + mmc->priv = host; + host->mmc = mmc; + + sprintf(mmc->name, "%s", host->name); + mmc->send_cmd = dwmci_send_cmd; + mmc->set_ios = dwmci_set_ios; + mmc->init = dwmci_init; + mmc->f_min = min_clk; + mmc->f_max = max_clk; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + + mmc->host_caps = host->caps; + + if (host->buswidth == 8) { + mmc->host_caps |= MMC_MODE_8BIT; + mmc->host_caps &= ~MMC_MODE_4BIT; + } else { + mmc->host_caps |= MMC_MODE_4BIT; + mmc->host_caps &= ~MMC_MODE_8BIT; + } + mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; + + err = mmc_register(mmc); + + return err; +} diff --git a/include/dwmmc.h b/include/dwmmc.h new file mode 100644 index 0000000000..c8b1d408e2 --- /dev/null +++ b/include/dwmmc.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __DWMMC_HW_H +#define __DWMMC_HW_H + +#include +#include + +#define DWMCI_CTRL 0x000 +#define DWMCI_PWREN 0x004 +#define DWMCI_CLKDIV 0x008 +#define DWMCI_CLKSRC 0x00C +#define DWMCI_CLKENA 0x010 +#define DWMCI_TMOUT 0x014 +#define DWMCI_CTYPE 0x018 +#define DWMCI_BLKSIZ 0x01C +#define DWMCI_BYTCNT 0x020 +#define DWMCI_INTMASK 0x024 +#define DWMCI_CMDARG 0x028 +#define DWMCI_CMD 0x02C +#define DWMCI_RESP0 0x030 +#define DWMCI_RESP1 0x034 +#define DWMCI_RESP2 0x038 +#define DWMCI_RESP3 0x03C +#define DWMCI_MINTSTS 0x040 +#define DWMCI_RINTSTS 0x044 +#define DWMCI_STATUS 0x048 +#define DWMCI_FIFOTH 0x04C +#define DWMCI_CDETECT 0x050 +#define DWMCI_WRTPRT 0x054 +#define DWMCI_GPIO 0x058 +#define DWMCI_TCMCNT 0x05C +#define DWMCI_TBBCNT 0x060 +#define DWMCI_DEBNCE 0x064 +#define DWMCI_USRID 0x068 +#define DWMCI_VERID 0x06C +#define DWMCI_HCON 0x070 +#define DWMCI_UHS_REG 0x074 +#define DWMCI_BMOD 0x080 +#define DWMCI_PLDMND 0x084 +#define DWMCI_DBADDR 0x088 +#define DWMCI_IDSTS 0x08C +#define DWMCI_IDINTEN 0x090 +#define DWMCI_DSCADDR 0x094 +#define DWMCI_BUFADDR 0x098 +#define DWMCI_DATA 0x200 + +/* Interrupt Mask register */ +#define DWMCI_INTMSK_ALL 0xffffffff +#define DWMCI_INTMSK_RE (1 << 1) +#define DWMCI_INTMSK_CDONE (1 << 2) +#define DWMCI_INTMSK_DTO (1 << 3) +#define DWMCI_INTMSK_TXDR (1 << 4) +#define DWMCI_INTMSK_RXDR (1 << 5) +#define DWMCI_INTMSK_DCRC (1 << 7) +#define DWMCI_INTMSK_RTO (1 << 8) +#define DWMCI_INTMSK_DRTO (1 << 9) +#define DWMCI_INTMSK_HTO (1 << 10) +#define DWMCI_INTMSK_FRUN (1 << 11) +#define DWMCI_INTMSK_HLE (1 << 12) +#define DWMCI_INTMSK_SBE (1 << 13) +#define DWMCI_INTMSK_ACD (1 << 14) +#define DWMCI_INTMSK_EBE (1 << 15) + +/* Raw interrupt Regsiter */ +#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ + DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) +#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) +/* CTRL register */ +#define DWMCI_CTRL_RESET (1 << 0) +#define DWMCI_CTRL_FIFO_RESET (1 << 1) +#define DWMCI_CTRL_DMA_RESET (1 << 2) +#define DWMCI_DMA_EN (1 << 5) +#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) +#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ + DWMCI_CTRL_DMA_RESET) + +/* CMD register */ +#define DWMCI_CMD_RESP_EXP (1 << 6) +#define DWMCI_CMD_RESP_LENGTH (1 << 7) +#define DWMCI_CMD_CHECK_CRC (1 << 8) +#define DWMCI_CMD_DATA_EXP (1 << 9) +#define DWMCI_CMD_RW (1 << 10) +#define DWMCI_CMD_SEND_STOP (1 << 12) +#define DWMCI_CMD_ABORT_STOP (1 << 14) +#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) +#define DWMCI_CMD_UPD_CLK (1 << 21) +#define DWMCI_CMD_USE_HOLD_REG (1 << 29) +#define DWMCI_CMD_START (1 << 31) + +/* CLKENA register */ +#define DWMCI_CLKEN_ENABLE (1 << 0) +#define DWMCI_CLKEN_LOW_PWR (1 << 16) + +/* Card-type registe */ +#define DWMCI_CTYPE_1BIT 0 +#define DWMCI_CTYPE_4BIT (1 << 0) +#define DWMCI_CTYPE_8BIT (1 << 16) + +/* Status Register */ +#define DWMCI_BUSY (1 << 9) + +/* FIFOTH Register */ +#define MSIZE(x) ((x) << 28) +#define RX_WMARK(x) ((x) << 16) +#define TX_WMARK(x) (x) + +#define DWMCI_IDMAC_OWN (1 << 31) +#define DWMCI_IDMAC_CH (1 << 4) +#define DWMCI_IDMAC_FS (1 << 3) +#define DWMCI_IDMAC_LD (1 << 2) + +/* Bus Mode Register */ +#define DWMCI_BMOD_IDMAC_RESET (1 << 0) +#define DWMCI_BMOD_IDMAC_FB (1 << 1) +#define DWMCI_BMOD_IDMAC_EN (1 << 7) + +struct dwmci_host { + char *name; + void *ioaddr; + unsigned int quirks; + unsigned int caps; + unsigned int version; + unsigned int clock; + unsigned int bus_hz; + int dev_index; + int buswidth; + u32 fifoth_val; + struct mmc *mmc; + + void (*clksel)(struct dwmci_host *host); + unsigned int (*mmc_clk)(int dev_index); +}; + +struct dwmci_idmac { + u32 flags; + u32 cnt; + u32 addr; + u32 next_addr; +}; + +static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) +{ + writel(val, host->ioaddr + reg); +} + +static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val) +{ + writew(val, host->ioaddr + reg); +} + +static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) +{ + writeb(val, host->ioaddr + reg); +} +static inline u32 dwmci_readl(struct dwmci_host *host, int reg) +{ + return readl(host->ioaddr + reg); +} + +static inline u16 dwmci_readw(struct dwmci_host *host, int reg) +{ + return readw(host->ioaddr + reg); +} + +static inline u8 dwmci_readb(struct dwmci_host *host, int reg) +{ + return readb(host->ioaddr + reg); +} + +int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); +#endif /* __DWMMC_HW_H */ -- cgit v1.2.3 From 505f3e6f2e0e90b78dec065e64ad57c5d8741b04 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Tue, 21 Aug 2012 23:35:42 +0000 Subject: fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian Signed-off-by: Andy Fleming --- drivers/pci/fsl_pci_init.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 0d46c96312..20dabf36f0 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -499,13 +499,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) } #ifndef CONFIG_PCI_NOSCAN - pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); - - /* Programming Interface (PCI_CLASS_PROG) - * 0 == pci host or pcie root-complex, - * 1 == pci agent or pcie end-point - */ - if (!temp8) { + if (!fsl_is_pci_agent(hose)) { debug(" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); @@ -543,12 +537,22 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int fsl_is_pci_agent(struct pci_controller *hose) { - u8 prog_if; + u8 pcie_cap; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + if (pcie_cap == PCI_CAP_ID_EXP) { + u8 header_type; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, + &header_type); + return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; + } else { + u8 prog_if; - return (prog_if == FSL_PROG_IF_AGENT); + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + return (prog_if == FSL_PROG_IF_AGENT); + } } int fsl_pci_init_port(struct fsl_pci_info *pci_info, @@ -618,12 +622,10 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, void fsl_pci_config_unlock(struct pci_controller *hose) { pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); - u8 agent; u8 pcie_cap; u16 pbfr; - pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); - if (!agent) + if (!fsl_is_pci_agent(hose)) return; pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); -- cgit v1.2.3 From 168e5bc4095177764edaff306c9d4674a6f7f5e6 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 6 Sep 2012 17:28:35 +0000 Subject: mpc85xx: make gpio_direction_output respect value Users of familiar with the Linux gpiolib API expect that value parameter to gpio_direction_output reflects the initial state of the output pin. gpio_direction_output was always driving the output low, now it drives it high or low according to the value provided. Signed-off-by: Chris Packham Cc: Kyle Moffett Cc: Andy Fleming Cc: Peter Tyser Cc: Kumar Gala Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/mpc85xx_gpio.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index 5a608a5d0f..2aed5148ef 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -98,7 +98,10 @@ static inline int gpio_direction_input(unsigned gpio) static inline int gpio_direction_output(unsigned gpio, int value) { - mpc85xx_gpio_set_low(1U << gpio); + if (value) + mpc85xx_gpio_set_high(1U << gpio); + else + mpc85xx_gpio_set_low(1U << gpio); return 0; } -- cgit v1.2.3 From 320d53da605d67b9d95622c5c6bfd5ac2c17ed58 Mon Sep 17 00:00:00 2001 From: Mark Marshall Date: Sun, 9 Sep 2012 23:06:03 +0000 Subject: powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset. We should only write TSR_WIS to the SPRN_TSR register in reset_85xx_watchdog. The old code would cause the timer interrupt to be acknowledged when the watchdog was reset, and we would then get no more timer interrupts. This bug would affect all mpc85xx boards that have the watchdog enabled. Signed-off-by: Mark Marshall Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 5ddb29435c..a5048a1306 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -270,10 +270,7 @@ reset_85xx_watchdog(void) /* * Clear TSR(WIS) bit by writing 1 */ - unsigned long val; - val = mfspr(SPRN_TSR); - val |= TSR_WIS; - mtspr(SPRN_TSR, val); + mtspr(SPRN_TSR, TSR_WIS); } #endif /* CONFIG_WATCHDOG */ -- cgit v1.2.3 From 9f26fd7947a92a30f4eb68d4d0f60c1a73ab4280 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 17 Sep 2012 17:30:31 +0000 Subject: board/freescale/common:QIXIS:Fix magic number usage QIXIS FPGA layout defines the address of registers but The actual register bit implementation is board-specific, So avoid use of magic numbers as it may vary across different boards's QIXIS FPGA implementation. Also, Avoid board specific defines in common/qixis.h Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming --- board/freescale/common/qixis.c | 13 +++++++------ board/freescale/common/qixis.h | 6 ------ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 6cd7e5108a..e336b32806 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -32,22 +32,22 @@ void qixis_write(unsigned int reg, u8 value) void qixis_reset(void) { - QIXIS_WRITE(rst_ctl, 0x83); + QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); } void qixis_bank_reset(void) { - QIXIS_WRITE(rcfg_ctl, 0x20); - QIXIS_WRITE(rcfg_ctl, 0x21); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); } -/* Set the boot bank to the power-on default bank0 */ +/* Set the boot bank to the power-on default bank */ void clear_altbank(void) { u8 reg; reg = QIXIS_READ(brdcfg[0]); - reg = reg & ~QIXIS_LBMAP_MASK; + reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK; QIXIS_WRITE(brdcfg[0], reg); } @@ -115,7 +115,8 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) for (i = 0; i < ARRAY_SIZE(period); i++) { if (strcmp(argv[2], period[i]) == 0) { /* disable watchdog */ - QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08); + QIXIS_WRITE(rcfg_ctl, + rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); QIXIS_WRITE(watch, ((i<<2) - 1)); QIXIS_WRITE(rcfg_ctl, rcfg); return 0; diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 7a0268a02c..83a3b693f6 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -86,12 +86,6 @@ struct qixis { u8 res15[16]; }; -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 7 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_ALTBANK 0x04 - u8 qixis_read(unsigned int reg); void qixis_write(unsigned int reg, u8 value); -- cgit v1.2.3 From 4e0be34a85b6bc9b8ae36feaf14440a347a2b22c Mon Sep 17 00:00:00 2001 From: Zang Roy-R61911 Date: Tue, 18 Sep 2012 09:50:08 +0000 Subject: P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the workaround conditional. In formal release document, the errata number should be ESDHC13 instead of ESDHC136. Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 +++-- arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 ++++++---- arch/powerpc/include/asm/config_mpc85xx.h | 2 +- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index e8989bdf45..7e4cc03640 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -79,8 +79,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) puts("Work-around for Erratum ESDHC135 enabled\n"); #endif -#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136) - puts("Work-around for Erratum ESDHC136 enabled\n"); +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13) + if (SVR_MAJ(svr) < 3) + puts("Work-around for Erratum ESDHC13 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) puts("Work-around for Erratum ESDHC-A001 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index afb56719da..ba558dedd7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -497,11 +497,13 @@ skip_l2: setup_mp(); #endif -#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136 +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 { - void *p; - p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; - setbits_be32(p, 1 << (31 - 14)); + if (SVR_MAJ(svr) < 3) { + void *p; + p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + setbits_be32(p, 1 << (31 - 14)); + } } #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index aa27741a92..39a3cdede0 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -389,7 +389,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC13 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 -- cgit v1.2.3 From 97b24d3d51a92cb8c0c1e1a74abf22fe1a1807a3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 19 Oct 2012 05:00:10 +0000 Subject: common: Add symbol handling for generic lists into Makefile This patch adds essential components for generation of the contents of the linker section that is used by the linker-generated array. All of the contents is held in a separate file, u-boot.lst, which is generated at runtime just before U-Boot is linked. The purpose of this code is to especially generate the appropriate boundary symbols around each subsection in the section carrying the linker-generated arrays. Obviously, the interim linker code for actual placement of the variables into the section is generated too. The generated file, u-boot.lst, is included into u-boot.lds via the linker INCLUDE directive in u-boot.lds . Adjustments are made in the Makefile and spl/Makefile so that the u-boot.lds and u-boot-spl.lds depend on their respective .lst files. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger Acked-by: Joe Hershberger Tested-by: Joe Hershberger --- .gitignore | 1 + Makefile | 20 ++++++-- config.mk | 2 + helper.mk | 64 ++++++++++++++++++++++++++ nand_spl/board/freescale/mpc8536ds/Makefile | 9 +++- nand_spl/board/freescale/mpc8569mds/Makefile | 9 +++- nand_spl/board/freescale/mpc8572ds/Makefile | 9 +++- nand_spl/board/freescale/mx31pdk/Makefile | 9 +++- nand_spl/board/freescale/p1010rdb/Makefile | 9 +++- nand_spl/board/freescale/p1023rds/Makefile | 9 +++- nand_spl/board/freescale/p1_p2_rdb/Makefile | 9 +++- nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 9 +++- nand_spl/board/karo/tx25/Makefile | 9 +++- spl/.gitignore | 1 + spl/Makefile | 8 +++- 15 files changed, 152 insertions(+), 25 deletions(-) create mode 100644 helper.mk diff --git a/.gitignore b/.gitignore index d91e91b1e6..1ac43f2825 100644 --- a/.gitignore +++ b/.gitignore @@ -38,6 +38,7 @@ /u-boot.sha1 /u-boot.dis /u-boot.lds +/u-boot.lst /u-boot.ubl /u-boot.ais /u-boot.dtb diff --git a/Makefile b/Makefile index 08eecbbbcd..c4afc9f507 100644 --- a/Makefile +++ b/Makefile @@ -535,7 +535,10 @@ else GEN_UBOOT = \ UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ - cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \ + UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ + sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\ + cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ + $$UNDEF_SYM $$UNDEF_LST $(__OBJS) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -Map u-boot.map -o u-boot endif @@ -568,8 +571,12 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot $(LDSCRIPT): depend $(MAKE) -C $(dir $@) $(notdir $@) -$(obj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates u-boot.lst, +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS))) +$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@ nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(MAKE) -C nand_spl/board/$(BOARDDIR) all @@ -808,6 +815,7 @@ clean: $(obj)board/matrix_vision/*/bootscript.img \ $(obj)board/voiceblue/eeprom \ $(obj)u-boot.lds \ + $(obj)include/u-boot.lst \ $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \ $(obj)arch/blackfin/cpu/init.{lds,elf} @rm -f $(obj)include/bmp_logo.h @@ -841,8 +849,10 @@ clobber: tidy @rm -f $(obj)u-boot.dtb @rm -f $(obj)u-boot.sb @rm -f $(obj)u-boot.spr - @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map} - @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map} + @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map} + @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} + @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} + @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst} @rm -f $(obj)MLO @rm -f $(obj)tools/xway-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c diff --git a/config.mk b/config.mk index bb5c69a15d..b7cd4814fe 100644 --- a/config.mk +++ b/config.mk @@ -23,6 +23,8 @@ ######################################################################### +include $(TOPDIR)/helper.mk + ifeq ($(CURDIR),$(SRCTREE)) dir := else diff --git a/helper.mk b/helper.mk new file mode 100644 index 0000000000..79a1da01e3 --- /dev/null +++ b/helper.mk @@ -0,0 +1,64 @@ +# +# Copyright (C) 2012 Marek Vasut +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +######################################################################### + +## +# make_u_boot_list - Generate contents of u_boot_list section +# 1: The name of the resulting file (usually u-boot.lst) +# 2: Files to analyze for possible u_boot_list entries +# +# This function generates the contents of the u_boot_list section, +# including all the border symbols for it's subsections. The operation +# of this function is as follows, numbering goes per lines: +# +# 1) Dump the ELF header sections from all files supplied via $(2) +# 2) Filter out all other stuff that does not belong into .u_boot_list +# section. +# 3) Fix up the lines so that the resulting output is is in format +# ".u_boot_list.*". +# 4) Remove the last .something$, since that only contains the name +# of the variable to be put into a subsection. This name is irelevant +# for generation of border symbols, thus of no interest, remove it. +# 5) Take each line and for every dot "." in that line, print the whole +# line until that dot "." . This is important so that we have all +# parent border symbols generated as well. +# 6) Load every line and firstly append "\a" at the end and print the +# line. Next, append "@" at the end and print the line. Finally, +# append "~" at the end of line. This will make sense in conjunction +# with 6) and 7). +# 7) Sort the lines. It is imperative to use LC_COLLATE=C here because +# with this, the "\a" symbol is first and "~" symbol is last. Any +# other symbols fall inbetween. Symbols like "@", which marks the +# end of current line (representing current section) and ".", which +# means the line continues and thus represents subsection. +# 8) With such ordering, all lines ending with "\a" will float at the +# begining of all lines with the same prefix. Thus it is easy to +# replace "\a" with __start and make it the __start border symbol. +# Very similarly for "~", which will be always at the bottom and so +# can be replaced by "__end" and made into the __end border symbol. +# Finally, every line ending with "@" symbol will be transformed +# into " *(SORT(${line}*)); " format, which in the linker parlance +# will allow it to trap all symbols relevant to the subsection. +# +define make_u_boot_list +$(1): $(2) + $(OBJDUMP) -h $(2) | \ + sed -n -e '/.*\.u_boot_list[^ ]\+/ ! {d;n}' \ + -e 's/.*\(\.u_boot_list[^ ]\+\).*$$$$/\1/' \ + -e 's/\.[^\.]\+$$$$//' \ + -e ':s /^.\+$$$$/ { p;s/^\(.*\)\.[^\.]*$$$$/\1/;b s }' | \ + sed -n -e 'h;s/$$$$/\a/p;g;s/$$$$/@/p;g;s/$$$$/~/p;' | \ + LC_COLLATE=C sort -u | \ + sed -n -e '/\a$$$$/ { s/\./_/g;s/\a$$$$/__start = .;/p; }'\ + -e '/~$$$$/ { s/\./_/g;s/~$$$$/__end = .;/p; }'\ + -e '/@$$$$/ { s/\(.*\)@$$$$/*(SORT(\1.*));/p }' > $(1) +endef diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index 43da3df157..e5388d89c8 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -61,8 +62,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index 43da3df157..e5388d89c8 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -61,8 +62,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index 43da3df157..e5388d89c8 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -61,8 +62,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile index 87784d2937..43e72c42d4 100644 --- a/nand_spl/board/freescale/mx31pdk/Makefile +++ b/nand_spl/board/freescale/mx31pdk/Makefile @@ -6,6 +6,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL @@ -36,8 +37,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map \ -o $@ -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ ######################################################################### diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile index cdbd49292c..f270faae02 100644 --- a/nand_spl/board/freescale/p1010rdb/Makefile +++ b/nand_spl/board/freescale/p1010rdb/Makefile @@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \ $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -62,8 +63,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index da435213fc..b2882844b3 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -27,6 +27,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -57,8 +58,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index 43da3df157..e5388d89c8 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -61,8 +62,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile index 46cf7099b6..7146d16a27 100644 --- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile @@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_NAND_SPL @@ -62,8 +63,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl -$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile index 0336346660..becf7fa99e 100644 --- a/nand_spl/board/karo/tx25/Makefile +++ b/nand_spl/board/karo/tx25/Makefile @@ -27,6 +27,7 @@ include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL @@ -57,8 +58,12 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map \ -o $@ -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ +# The following line expands into whole rule which generates $(LSTSCRIPT), +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS))) +$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@ ######################################################################### diff --git a/spl/.gitignore b/spl/.gitignore index 7c8814709f..8cf487e5c8 100644 --- a/spl/.gitignore +++ b/spl/.gitignore @@ -2,3 +2,4 @@ u-boot-spl u-boot-spl.bin u-boot-spl.lds u-boot-spl.map +u-boot.lst diff --git a/spl/Makefile b/spl/Makefile index 92267d6dea..20a943c14d 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -154,8 +154,12 @@ $(START): depend $(LIBS): depend $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) -$(obj)u-boot-spl.lds: $(LDSCRIPT) depend - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - < $< > $@ +# The following line expands into whole rule which generates u-boot.lst, +# the file containing u-boots LG-array linker section. This is included into +# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file. +$(eval $(call make_u_boot_list, $(obj)u-boot.lst, $(LIBS))) +$(obj)u-boot-spl.lds: $(LDSCRIPT) $(obj)u-boot.lst depend + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ depend: $(obj).depend .PHONY: depend -- cgit v1.2.3 From 42ebaae3a33b8393a37e7176234e71b5eada58d4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Oct 2012 10:27:02 +0000 Subject: common: Implement support for linker-generated arrays This patch adds support for linker-generated array. These arrays are a generalization of the U-Boot command declaration approach. Basically, the idea is to generate an array, where elements of the array are statically initialized at compile time and each element is declared separatelly at different place. Such array is assembled together into continuous piece of memory by linker and a pointer to it's first entry can then be retrieved via accessor. The actual implementation relies on placing any variable that is to represent an element of LG-array into particular subsection of the .u_boot_list linker section . The subsection is determined by user options. Once compiled, it is possible to dump all symbols placed in .u_boot_list section and the subsections in which they should be and generate appropriate bounds for each requested subsection of the .u_boot_list section. Each such subsection thus contains __start and __end entries at the begining and end respecitively. This allows for simple run-time traversing of the array, since the symbols are properly defined. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger --- include/linker_lists.h | 148 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 include/linker_lists.h diff --git a/include/linker_lists.h b/include/linker_lists.h new file mode 100644 index 0000000000..0b405d78ea --- /dev/null +++ b/include/linker_lists.h @@ -0,0 +1,148 @@ +/* + * include/linker_lists.h + * + * Implementation of linker-generated arrays + * + * Copyright (C) 2012 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +#ifndef __LINKER_LISTS_H__ +#define __LINKER_LISTS_H__ + +/** + * ll_entry_declare() - Declare linker-generated array entry + * @_type: Data type of the entry + * @_name: Name of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots, for name concatenation) + * @_section_d: Subsection of u_boot_list in which this entry is placed + * (with dots, for section concatenation) + * + * This macro declares a variable that is placed into a linker-generated + * array. This is a basic building block for more advanced use of linker- + * generated arrays. The user is expected to build their own macro wrapper + * around this one. + * + * A variable declared using this macro must be compile-time initialized + * and is as such placed into subsection of special section, .u_boot_list. + * The subsection is specified by the _section_[u,d] parameter, see below. + * The base name of the variable is _name, yet the actual variable is + * declared as concatenation of + * + * %_u_boot_list_ + @_section_u + _ + @_name + * + * which ensures name uniqueness. This variable shall never be refered + * directly though. + * + * Special precaution must be made when using this macro: + * 1) The _type must not contain the "static" keyword, otherwise the entry + * is not generated. + * + * 2) The @_section_u and @_section_d variables must match, the only difference + * is that in @_section_u is every dot "." character present in @_section_d + * replaced by a single underscore "_" character in @_section_u. The actual + * purpose of these parameters is to select proper subsection in the global + * .u_boot_list section. + * + * 3) In case a section is declared that contains some array elements AND a + * subsection of this section is declared and contains some elements, it is + * imperative that the elements are of the same type. + * + * 4) In case an outer section is declared that contains some array elements + * AND am inner subsection of this section is declared and contains some + * elements, then when traversing the outer section, even the elements of + * the inner sections are present in the array. + * + * Example: + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * .x = 3, + * .y = 4, + * }; + */ +#define ll_entry_declare(_type, _name, _section_u, _section_d) \ + _type _u_boot_list_##_section_u##_##_name __attribute__(( \ + unused, aligned(4), \ + section(".u_boot_list."#_section_d"."#_name))) + +/** + * ll_entry_start() - Point to first entry of linker-generated array + * @_type: Data type of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots) + * + * This function returns (_type *) pointer to the very first entry of a + * linker-generated array placed into subsection of .u_boot_list section + * specified by _section_u argument. + * + * Example: + * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub); + */ +#define ll_entry_start(_type, _section_u) \ + ({ \ + extern _type _u_boot_list_##_section_u##__start; \ + _type *_ll_result = &_u_boot_list_##_section_u##__start;\ + _ll_result; \ + }) + +/** + * ll_entry_count() - Return the number of elements in linker-generated array + * @_type: Data type of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots) + * + * This function returns the number of elements of a linker-generated array + * placed into subsection of .u_boot_list section specified by _section_u + * argument. The result is of an unsigned int type. + * + * Example: + * int i; + * const unsigned int count = ll_entry_count(struct my_sub_cmd, cmd_sub); + * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub); + * for (i = 0; i < count; i++, msc++) + * printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y); + */ +#define ll_entry_count(_type, _section_u) \ + ({ \ + extern _type _u_boot_list_##_section_u##__start; \ + extern _type _u_boot_list_##_section_u##__end; \ + unsigned int _ll_result = \ + &_u_boot_list_##_section_u##__end - \ + &_u_boot_list_##_section_u##__start; \ + _ll_result; \ + }) + + +/** + * ll_entry_get() - Retrieve entry from linker-generated array by name + * @_type: Data type of the entry + * @_name: Name of the entry + * @_section_u: Subsection of u_boot_list in which this entry is placed + * (with underscores instead of dots) + * + * This function returns a pointer to a particular entry in LG-array + * identified by the subsection of u_boot_list where the entry resides + * and it's name. + * + * Example: + * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * .x = 3, + * .y = 4, + * }; + * ... + * struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub); + */ +#define ll_entry_get(_type, _name, _section_u) \ + ({ \ + extern _type _u_boot_list_##_section_u##_##_name; \ + _type *_ll_result = &_u_boot_list_##_section_u##_##_name;\ + _ll_result; \ + }) + +#endif /* __LINKER_LISTS_H__ */ -- cgit v1.2.3 From 556751427b9b79266918e87f7399e1a6eea60096 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Oct 2012 10:27:03 +0000 Subject: common: Add .u_boot_list into all linker files Add section for the linker-generated lists into all possible linker files, so that everyone can easily use these lists. This is mostly a mechanical adjustment. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger --- arch/arm/cpu/arm920t/ep93xx/u-boot.lds | 5 +++++ arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 4 ++++ arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 4 ++++ arch/arm/cpu/armv7/omap-common/u-boot-spl.lds | 5 +++++ arch/arm/cpu/ixp/u-boot.lds | 5 +++++ arch/arm/cpu/u-boot.lds | 5 +++++ arch/avr32/cpu/u-boot.lds | 5 +++++ arch/blackfin/cpu/u-boot.lds | 4 ++++ arch/microblaze/cpu/u-boot.lds | 5 +++++ arch/nds32/cpu/n1213/u-boot.lds | 5 +++++ arch/nios2/cpu/u-boot.lds | 5 +++++ arch/powerpc/cpu/74xx_7xx/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc512x/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc5xx/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds | 3 +++ arch/powerpc/cpu/mpc5xxx/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc8220/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc824x/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc8260/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc83xx/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 4 ++++ arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 4 ++++ arch/powerpc/cpu/mpc85xx/u-boot.lds | 5 +++++ arch/powerpc/cpu/mpc86xx/u-boot.lds | 5 +++++ arch/powerpc/cpu/ppc4xx/u-boot.lds | 5 +++++ arch/sandbox/cpu/u-boot.lds | 5 +++++ arch/sh/cpu/sh2/u-boot.lds | 4 ++++ arch/sh/cpu/sh3/u-boot.lds | 4 ++++ arch/sh/cpu/sh4/u-boot.lds | 4 ++++ arch/x86/cpu/u-boot.lds | 5 +++++ board/BuS/eb_cpu5282/u-boot.lds | 5 +++++ board/LEOX/elpt860/u-boot.lds | 5 +++++ board/RPXClassic/u-boot.lds | 5 +++++ board/RPXClassic/u-boot.lds.debug | 5 +++++ board/RPXlite/u-boot.lds | 5 +++++ board/RPXlite/u-boot.lds.debug | 5 +++++ board/RPXlite_dw/u-boot.lds | 5 +++++ board/RPXlite_dw/u-boot.lds.debug | 5 +++++ board/RRvision/u-boot.lds | 5 +++++ board/actux1/u-boot.lds | 5 +++++ board/actux2/u-boot.lds | 5 +++++ board/actux3/u-boot.lds | 5 +++++ board/adder/u-boot.lds | 5 +++++ board/ait/cam_enc_4xx/u-boot-spl.lds | 4 ++++ board/altera/nios2-generic/u-boot.lds | 5 +++++ board/amcc/acadia/u-boot-nand.lds | 3 +++ board/amcc/bamboo/u-boot-nand.lds | 3 +++ board/amcc/canyonlands/u-boot-nand.lds | 3 +++ board/amcc/kilauea/u-boot-nand.lds | 3 +++ board/amcc/sequoia/u-boot-nand.lds | 3 +++ board/amcc/sequoia/u-boot-ram.lds | 3 +++ board/astro/mcf5373l/u-boot.lds | 5 +++++ board/c2mon/u-boot.lds | 5 +++++ board/c2mon/u-boot.lds.debug | 5 +++++ board/cobra5272/u-boot.lds | 5 +++++ board/cogent/u-boot.lds | 5 +++++ board/cogent/u-boot.lds.debug | 5 +++++ board/cray/L1/u-boot.lds.debug | 5 +++++ board/dave/PPChameleonEVB/u-boot.lds | 5 +++++ board/davinci/da8xxevm/u-boot-spl-da850evm.lds | 6 ++++++ board/davinci/da8xxevm/u-boot-spl-hawk.lds | 5 +++++ board/dbau1x00/u-boot.lds | 5 +++++ board/dvlhost/u-boot.lds | 5 +++++ board/eltec/mhpc/u-boot.lds | 5 +++++ board/eltec/mhpc/u-boot.lds.debug | 5 +++++ board/emk/top860/u-boot.lds | 5 +++++ board/ep88x/u-boot.lds | 5 +++++ board/esd/dasa_sim/u-boot.lds | 5 +++++ board/esd/pmc440/u-boot-nand.lds | 3 +++ board/esd/tasreg/u-boot.lds | 5 +++++ board/esteem192e/u-boot.lds | 5 +++++ board/etx094/u-boot.lds | 5 +++++ board/evb64260/u-boot.lds | 5 +++++ board/fads/u-boot.lds | 5 +++++ board/flagadm/u-boot.lds | 5 +++++ board/flagadm/u-boot.lds.debug | 5 +++++ board/freescale/m5208evbe/u-boot.lds | 5 +++++ board/freescale/m52277evb/u-boot.lds | 5 +++++ board/freescale/m5235evb/u-boot.lds | 5 +++++ board/freescale/m5249evb/u-boot.lds | 5 +++++ board/freescale/m5253demo/u-boot.lds | 5 +++++ board/freescale/m5253evbe/u-boot.lds | 5 +++++ board/freescale/m5271evb/u-boot.lds | 5 +++++ board/freescale/m5272c3/u-boot.lds | 5 +++++ board/freescale/m5275evb/u-boot.lds | 5 +++++ board/freescale/m5282evb/u-boot.lds | 5 +++++ board/freescale/m53017evb/u-boot.lds | 5 +++++ board/freescale/m5329evb/u-boot.lds | 5 +++++ board/freescale/m5373evb/u-boot.lds | 5 +++++ board/freescale/m54451evb/u-boot.lds | 5 +++++ board/freescale/m54455evb/u-boot.lds | 5 +++++ board/freescale/m547xevb/u-boot.lds | 5 +++++ board/freescale/m548xevb/u-boot.lds | 5 +++++ board/freescale/mx31ads/u-boot.lds | 5 +++++ board/gaisler/gr_cpci_ax2000/u-boot.lds | 5 +++++ board/gaisler/gr_ep2s60/u-boot.lds | 5 +++++ board/gaisler/gr_xc3s_1500/u-boot.lds | 5 +++++ board/gaisler/grsim/u-boot.lds | 5 +++++ board/gaisler/grsim_leon2/u-boot.lds | 5 +++++ board/gen860t/u-boot-flashenv.lds | 4 ++++ board/gen860t/u-boot.lds | 5 +++++ board/genietv/u-boot.lds | 5 +++++ board/genietv/u-boot.lds.debug | 5 +++++ board/hermes/u-boot.lds | 5 +++++ board/hermes/u-boot.lds.debug | 5 +++++ board/hymod/u-boot.lds | 5 +++++ board/hymod/u-boot.lds.debug | 5 +++++ board/icu862/u-boot.lds | 5 +++++ board/icu862/u-boot.lds.debug | 5 +++++ board/idmr/u-boot.lds | 5 +++++ board/incaip/u-boot.lds | 5 +++++ board/ip860/u-boot.lds | 5 +++++ board/ip860/u-boot.lds.debug | 5 +++++ board/ivm/u-boot.lds | 5 +++++ board/ivm/u-boot.lds.debug | 5 +++++ board/korat/u-boot-F7FC.lds | 3 +++ board/kup/kup4k/u-boot.lds | 5 +++++ board/kup/kup4k/u-boot.lds.debug | 5 +++++ board/kup/kup4x/u-boot.lds | 5 +++++ board/kup/kup4x/u-boot.lds.debug | 5 +++++ board/lantec/u-boot.lds | 5 +++++ board/lantec/u-boot.lds.debug | 5 +++++ board/lwmon/u-boot.lds | 5 +++++ board/lwmon/u-boot.lds.debug | 5 +++++ board/manroland/uc100/u-boot.lds | 5 +++++ board/matrix_vision/mvsmr/u-boot.lds | 5 +++++ board/mbx8xx/u-boot.lds | 5 +++++ board/mbx8xx/u-boot.lds.debug | 5 +++++ board/micronas/vct/u-boot.lds | 5 +++++ board/mousse/u-boot.lds | 5 +++++ board/mpl/pip405/u-boot.lds.debug | 5 +++++ board/mvblue/u-boot.lds | 5 +++++ board/netphone/u-boot.lds | 5 +++++ board/netphone/u-boot.lds.debug | 5 +++++ board/netta/u-boot.lds | 5 +++++ board/netta/u-boot.lds.debug | 5 +++++ board/netta2/u-boot.lds | 5 +++++ board/netta2/u-boot.lds.debug | 5 +++++ board/netvia/u-boot.lds | 5 +++++ board/netvia/u-boot.lds.debug | 5 +++++ board/nx823/u-boot.lds | 5 +++++ board/nx823/u-boot.lds.debug | 5 +++++ board/openrisc/openrisc-generic/u-boot.lds | 5 +++++ board/pb1x00/u-boot.lds | 5 +++++ board/qemu-mips/u-boot.lds | 5 +++++ board/qi/qi_lb60/u-boot.lds | 5 +++++ board/quantum/u-boot.lds | 5 +++++ board/r360mpi/u-boot.lds | 5 +++++ board/rbc823/u-boot.lds | 5 +++++ board/renesas/sh7757lcr/u-boot.lds | 4 ++++ board/rsdproto/u-boot.lds | 5 +++++ board/samsung/smdk5250/smdk5250-uboot-spl.lds | 5 +++++ board/samsung/smdk6400/u-boot-nand.lds | 7 ++++++- board/sandburst/karef/u-boot.lds.debug | 5 +++++ board/sandburst/metrobox/u-boot.lds.debug | 5 +++++ board/sandpoint/u-boot.lds | 5 +++++ board/siemens/IAD210/u-boot.lds | 5 +++++ board/sixnet/u-boot.lds | 5 +++++ board/snmc/qs850/u-boot.lds | 5 +++++ board/snmc/qs860t/u-boot.lds | 5 +++++ board/spc1920/u-boot.lds | 5 +++++ board/spd8xx/u-boot.lds | 5 +++++ board/spd8xx/u-boot.lds.debug | 5 +++++ board/stx/stxxtc/u-boot.lds | 5 +++++ board/stx/stxxtc/u-boot.lds.debug | 5 +++++ board/svm_sc8xx/u-boot.lds | 5 +++++ board/tqc/tqm8xx/u-boot.lds | 5 +++++ board/v37/u-boot.lds | 5 +++++ board/vpac270/u-boot-spl.lds | 4 ++++ board/w7o/u-boot.lds.debug | 5 +++++ board/westel/amx860/u-boot.lds | 5 +++++ board/westel/amx860/u-boot.lds.debug | 5 +++++ board/xes/xpedite1000/u-boot.lds.debug | 5 +++++ examples/standalone/sparc.lds | 1 + nand_spl/board/freescale/mx31pdk/u-boot.lds | 5 +++++ nand_spl/board/karo/tx25/u-boot.lds | 5 +++++ nand_spl/board/samsung/smdk6400/u-boot.lds | 5 +++++ 177 files changed, 853 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index dc6ba34082..8c6a407c43 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -52,6 +52,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); __bss_start = .; .bss : { *(.bss) } diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index f8ea38c03d..2940a6f2c1 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -54,6 +54,10 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index afd3381e16..ae9538ee40 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -54,6 +54,10 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 1d8efb213b..9979c30853 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -47,6 +47,11 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + .u_boot_list : { + #include + } + . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index 7199de4af1..a7ffab3cca 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -50,6 +50,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index e49ca0c552..85f4eecf27 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -53,6 +53,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); __image_copy_end = .; diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds index 0e532f234e..2accee6597 100644 --- a/arch/avr32/cpu/u-boot.lds +++ b/arch/avr32/cpu/u-boot.lds @@ -53,6 +53,11 @@ SECTIONS } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); _got = .; .got : { diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds index 2b8d285e1f..cbc79de0ab 100644 --- a/arch/blackfin/cpu/u-boot.lds +++ b/arch/blackfin/cpu/u-boot.lds @@ -119,6 +119,10 @@ SECTIONS ___u_boot_cmd_end = .; } >ram_data + .u_boot_list : { + #include + } >ram_data + .text_l1 : { . = ALIGN(4); diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index d033a2835b..06a2855221 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -58,6 +58,11 @@ SECTIONS __u_boot_cmd_end = .; } + . = ALIGN(4); + .u_boot_list : { + #include + } + .bss ALIGN(0x4): { __bss_start = .; diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds index 190342062a..62e357a27b 100644 --- a/arch/nds32/cpu/n1213/u-boot.lds +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -56,6 +56,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); _end = .; diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds index 4856bd368d..e24b769b5e 100644 --- a/arch/nios2/cpu/u-boot.lds +++ b/arch/nios2/cpu/u-boot.lds @@ -53,6 +53,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + /* INIT DATA sections - "Small" data (see the gcc -G option) * is always gp-relative. Here we make all init data sections * adjacent to simplify the startup code -- and provide diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds index 24823cd20f..04484a5ad7 100644 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds @@ -66,6 +66,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index 7a4d9270df..656a0620fc 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -61,6 +61,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index e02b213d28..e04528daa6 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -69,6 +69,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds index 0c6c54e10a..acddf5f1b2 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds @@ -70,6 +70,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index 5dcaec1820..998221e003 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -64,6 +64,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds index 39bb42e1c9..45d5e19f52 100644 --- a/arch/powerpc/cpu/mpc8220/u-boot.lds +++ b/arch/powerpc/cpu/mpc8220/u-boot.lds @@ -63,6 +63,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds index b30ce76e02..a80d91eb5f 100644 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ b/arch/powerpc/cpu/mpc824x/u-boot.lds @@ -64,6 +64,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index 60b71ecd70..f33f64874c 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -63,6 +63,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 2f4b9ad557..45a9cf8395 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -62,6 +62,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 8ba9399169..29aabde4c3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -74,6 +74,10 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 668158f702..46dbaed1e0 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -53,6 +53,10 @@ SECTIONS } _edata = .; + .u_boot_list : { + #include + } + . = ALIGN(8); __init_begin = .; __init_end = .; diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index efe34b774d..49fe44d4eb 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -81,6 +81,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 121e529876..17371acebf 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -68,6 +68,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 2466b79594..6df673ebf7 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -82,6 +82,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index 99601387cb..b7f25ab88a 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -28,6 +28,11 @@ SECTIONS _u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __u_boot_sandbox_option_start = .; _u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) } __u_boot_sandbox_option_end = .; diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds index b86a82297f..3cd28f7b35 100644 --- a/arch/sh/cpu/sh2/u-boot.lds +++ b/arch/sh/cpu/sh2/u-boot.lds @@ -80,6 +80,10 @@ SECTIONS } PROVIDE (__u_boot_cmd_end = .); + .u_boot_list : { + #include + } + PROVIDE (reloc_dst_end = .); PROVIDE (bss_start = .); diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds index 9bf8503640..f0bad518f2 100644 --- a/arch/sh/cpu/sh3/u-boot.lds +++ b/arch/sh/cpu/sh3/u-boot.lds @@ -86,6 +86,10 @@ SECTIONS } PROVIDE (__u_boot_cmd_end = .); + .u_boot_list : { + #include + } + PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds index d9c70bce09..d204304cf4 100644 --- a/arch/sh/cpu/sh4/u-boot.lds +++ b/arch/sh/cpu/sh4/u-boot.lds @@ -83,6 +83,10 @@ SECTIONS } PROVIDE (__u_boot_cmd_end = .); + .u_boot_list : { + #include + } + PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index fe28030d84..4bb2a2f5a1 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -38,6 +38,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds index 4ba1964f7e..a708d0607b 100644 --- a/board/BuS/eb_cpu5282/u-boot.lds +++ b/board/BuS/eb_cpu5282/u-boot.lds @@ -69,6 +69,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index 5aaf6b309d..b04e56c08b 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -90,6 +90,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index 99c48f28d4..46f2f8f7b9 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index 99c48f28d4..46f2f8f7b9 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index 4491edd944..1b042f8e99 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 838537375b..46134325d2 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -75,6 +75,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 63fd356097..e3a44227c6 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -60,6 +60,11 @@ SECTIONS } __u_boot_cmd_end =.; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN (4); .rel.dyn : { __rel_dyn_start = .; diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 9885d06b8e..e39b0ce675 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -60,6 +60,11 @@ SECTIONS } __u_boot_cmd_end =.; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN (4); .rel.dyn : { __rel_dyn_start = .; diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index 4a1c75aecc..d38f341515 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -60,6 +60,11 @@ SECTIONS } __u_boot_cmd_end =.; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN (4); .rel.dyn : { __rel_dyn_start = .; diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index a7627699e7..05d6323d26 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -66,6 +66,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index 52c986e8a9..656b2fbf89 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -48,6 +48,10 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); + .u_boot_list : { + #include + } >.sram + . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds index 88ced629ec..f0877330ae 100644 --- a/board/altera/nios2-generic/u-boot.lds +++ b/board/altera/nios2-generic/u-boot.lds @@ -54,6 +54,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + /* INIT DATA sections - "Small" data (see the gcc -G option) * is always gp-relative. Here we make all init data sections * adjacent to simplify the startup code -- and provide diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index ab67de2f76..9609338cd8 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -76,6 +76,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index 3ad87095a1..4f4194e0a7 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -77,6 +77,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 76f89f188d..1876baeb15 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -77,6 +77,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index ab67de2f76..9609338cd8 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -76,6 +76,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index 07ae8b1291..a0b98f42a6 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -77,6 +77,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index 423400ac66..32a7661704 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -68,6 +68,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds index 19342ac214..5d2c6552b8 100644 --- a/board/astro/mcf5373l/u-boot.lds +++ b/board/astro/mcf5373l/u-boot.lds @@ -73,6 +73,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds index b9b8e3c727..0b92ef639c 100644 --- a/board/c2mon/u-boot.lds +++ b/board/c2mon/u-boot.lds @@ -78,6 +78,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug index c7711028ad..c28e2b94c3 100644 --- a/board/c2mon/u-boot.lds.debug +++ b/board/c2mon/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index c4039edf43..77b8e806c2 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 2393d8d8af..f7137bda87 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -74,6 +74,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index 99c48f28d4..46f2f8f7b9 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index fcf8ebbf8e..15cccee718 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 3b10114354..184c6fc3ee 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -78,6 +78,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 6f6e065a9f..c5fd93c0f7 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -47,6 +47,12 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .u_boot_list : { + #include + } >.sram + . = ALIGN(4); .rel.dyn : { __rel_dyn_start = .; diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index b3a41afc42..86dc172ee2 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -57,6 +57,11 @@ SECTIONS *(.data.rel.ro) } + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); __rel_dyn_start = .; __rel_dyn_end = .; diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 4a59cea80f..6992c0f571 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -60,6 +60,11 @@ SECTIONS __u_boot_cmd_end = .; } + . = ALIGN(4); + .u_boot_list : { + #include + } + uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 01ec39008d..51716304a5 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -60,6 +60,11 @@ SECTIONS } __u_boot_cmd_end =.; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN (4); .rel.dyn : { __rel_dyn_start = .; diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index fd4e8a50d5..25b8839540 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index c7711028ad..c28e2b94c3 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index fb06648663..485c68d656 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -71,6 +71,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 332b35a57d..067fd5ffda 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -66,6 +66,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index b15948d34c..607e601c8c 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -77,6 +77,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index 71f0fd2c3e..38f5cc6ba3 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -106,6 +106,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index f697ccd515..158828c150 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -69,6 +69,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 163b83d819..3eaaad8bcd 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -79,6 +79,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds index 8465937d10..df9b44a344 100644 --- a/board/etx094/u-boot.lds +++ b/board/etx094/u-boot.lds @@ -79,6 +79,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index 2d031efc4e..05461ca8b9 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -74,6 +74,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index 9ea0674b88..4a41db8e36 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index fd4e8a50d5..25b8839540 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index c7711028ad..c28e2b94c3 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds index 6e39be169a..b1d2d016d4 100644 --- a/board/freescale/m5208evbe/u-boot.lds +++ b/board/freescale/m5208evbe/u-boot.lds @@ -73,6 +73,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index 3e9f4c3460..0a7ca55a53 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds index d39e7348b3..a4a62acefb 100644 --- a/board/freescale/m5235evb/u-boot.lds +++ b/board/freescale/m5235evb/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index c4039edf43..77b8e806c2 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index cbd28312a0..1dd5539ca9 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -73,6 +73,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index c4039edf43..77b8e806c2 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index 4717036d50..ecad6671c2 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index c4039edf43..77b8e806c2 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index 6c2dfe8ec4..60c0501d8b 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index 500fefd445..28386f967a 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index 80935f28bf..81da237bdb 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -75,6 +75,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index 40af8bc23c..c575522f27 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -73,6 +73,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index 19342ac214..5d2c6552b8 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -73,6 +73,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds index 45924b7514..76ead53b7e 100644 --- a/board/freescale/m54451evb/u-boot.lds +++ b/board/freescale/m54451evb/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds index f341449346..0d2cb02da7 100644 --- a/board/freescale/m54455evb/u-boot.lds +++ b/board/freescale/m54455evb/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index 5472689b5b..11fa8bcd34 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index cf3f38c0f3..0c8ffd41c6 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 79eb7aca38..e59fd18414 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -61,6 +61,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index 87cb8e32ba..ec72718beb 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -90,6 +90,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + .data : { *(.data) diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index 2fb44aa832..5a387967ff 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -90,6 +90,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + .data : { *(.data) diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 8719e97ee4..3da021c497 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -90,6 +90,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + .data : { *(.data) diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index 33890b504d..eba1015af9 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -89,6 +89,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + .data : { *(.data) diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index cf6e5020ba..4f90a46cf4 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -89,6 +89,11 @@ SECTIONS . = ALIGN(4); __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + .data : { *(.data) diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index 5bb6c62d71..8e04b11019 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -75,6 +75,10 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index be99b51208..c8602be5ad 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -75,6 +75,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 1d66a9b2bd..961222b1e2 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -84,6 +84,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index cfa4ef3f87..a3479ba290 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index ca9711575d..9fe2f58ef3 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -76,6 +76,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 8a197deef7..6a53d8a39f 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 1309f209de..50e4788030 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -114,6 +114,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index 99c48f28d4..46f2f8f7b9 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index 93c79a64b4..f476967e39 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 91d3e67e82..87ec870160 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index f697ccd515..158828c150 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -69,6 +69,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 4a59cea80f..6992c0f571 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -60,6 +60,11 @@ SECTIONS __u_boot_cmd_end = .; } + . = ALIGN(4); + .u_boot_list : { + #include + } + uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index 2f61b11d81..79e4f2d804 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index 1e843eb24e..7e63cd70a1 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index 732a46f272..ff4581f4a7 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index 6a017e305c..f91310a078 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -112,6 +112,9 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + .u_boot_list : { + #include + } . = .; __start___ex_table = .; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index 4491edd944..1b042f8e99 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index 4491edd944..1b042f8e99 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds index de0b355a62..e57a7948e6 100644 --- a/board/lantec/u-boot.lds +++ b/board/lantec/u-boot.lds @@ -79,6 +79,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug index 856a99b6f9..29148eedda 100644 --- a/board/lantec/u-boot.lds.debug +++ b/board/lantec/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index 8bf7324f37..78445b3068 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 241223481b..8fcdb90919 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index 731cec9af7..aa289cd52c 100644 --- a/board/manroland/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds @@ -73,6 +73,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 57c37deb89..5222ebd7eb 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -78,6 +78,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index a95c47feac..722a405929 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds index 3a05ef9049..114ce10d90 100644 --- a/board/micronas/vct/u-boot.lds +++ b/board/micronas/vct/u-boot.lds @@ -59,6 +59,11 @@ SECTIONS __u_boot_cmd_end = .; } + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index dae2cfc7da..aff426938f 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -64,6 +64,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index fcf8ebbf8e..15cccee718 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds index 11624d21f5..dc5747c846 100644 --- a/board/mvblue/u-boot.lds +++ b/board/mvblue/u-boot.lds @@ -74,6 +74,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index a949e4f592..ae48cba28a 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index a001f3fd87..ffebab52fe 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index a949e4f592..ae48cba28a 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index a001f3fd87..ffebab52fe 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index a949e4f592..ae48cba28a 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index a001f3fd87..ffebab52fe 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index a949e4f592..ae48cba28a 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 6c7d698c95..b37ea7b49f 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index fd4e8a50d5..25b8839540 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index c7711028ad..c28e2b94c3 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds index 1aed197bb9..599546487e 100644 --- a/board/openrisc/openrisc-generic/u-boot.lds +++ b/board/openrisc/openrisc-generic/u-boot.lds @@ -30,6 +30,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } > ram __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + .rodata : { *(.rodata); *(.rodata.*) diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index bd0dee1efb..41b001c3b1 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -60,6 +60,11 @@ SECTIONS __u_boot_cmd_end = .; } + . = ALIGN(4); + .u_boot_list : { + #include + } + uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index 4d9580f817..c5826a29d7 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -66,6 +66,11 @@ SECTIONS __u_boot_cmd_end = .; } + . = ALIGN(4); + .u_boot_list : { + #include + } + uboot_end_data = .; #if defined(CONFIG_64BIT) num_got_entries = (__got_end - __got_start) >> 3; diff --git a/board/qi/qi_lb60/u-boot.lds b/board/qi/qi_lb60/u-boot.lds index 7317652569..4a373ec138 100644 --- a/board/qi/qi_lb60/u-boot.lds +++ b/board/qi/qi_lb60/u-boot.lds @@ -51,6 +51,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 2fa085a3d9..3138154f7e 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index d943fb6de7..5e3d78fe94 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -81,6 +81,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds index 38ebe88507..b2cf39233b 100644 --- a/board/renesas/sh7757lcr/u-boot.lds +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -85,6 +85,10 @@ SECTIONS } PROVIDE (__u_boot_cmd_end = .); + .u_boot_list : { + #include + } + PROVIDE (reloc_dst_end = .); /* _reloc_dst_end = .; */ diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index a729c52626..d43663c716 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -101,6 +101,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds index d78dd77efd..951d8cec1d 100644 --- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -48,6 +48,11 @@ SECTIONS .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram . = ALIGN(4); + .u_boot_list : { + #include + } >.sram + . = ALIGN(4); + /* Align .machine_param on 256 byte boundary for easier searching */ .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram . = ALIGN(4); diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index f1628152d3..50924fcf1e 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -51,7 +51,12 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; - . = ALIGN(4); + . = align(4); + .u_boot_list : { + #include + } + + . = align(4); .mmudata : { *(.mmudata) } . = ALIGN(4); diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 31746e3adc..c3a72cb7b6 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -119,6 +119,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 4922bd241e..bb73307eff 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -119,6 +119,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds index e382fd1a1e..a9c06ad098 100644 --- a/board/sandpoint/u-boot.lds +++ b/board/sandpoint/u-boot.lds @@ -72,6 +72,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds index 0e78e4fd47..4214acef55 100644 --- a/board/siemens/IAD210/u-boot.lds +++ b/board/siemens/IAD210/u-boot.lds @@ -79,6 +79,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index 02d198001f..0a717073da 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 9ab248a4e9..eca88e57d2 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -73,6 +73,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index d0b60cf7c1..9133469f0c 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index a84e7fd35b..a233817757 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -79,6 +79,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index a95c47feac..722a405929 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index a949e4f592..ae48cba28a 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index a001f3fd87..ffebab52fe 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index c65f0228c3..4cdad4b1d3 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -87,6 +87,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index e905c26c6f..ea2fc44ae7 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -85,6 +85,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index e62d53db54..c82b1b31b7 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -70,6 +70,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 1958c2fb90..20161a46a6 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -57,6 +57,10 @@ SECTIONS *(.data) } + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index 1c67b301fb..4d640887a1 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -110,6 +110,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds index 3470b437e8..607473632d 100644 --- a/board/westel/amx860/u-boot.lds +++ b/board/westel/amx860/u-boot.lds @@ -79,6 +79,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = .; __start___ex_table = .; diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug index 91d3e67e82..87ec870160 100644 --- a/board/westel/amx860/u-boot.lds.debug +++ b/board/westel/amx860/u-boot.lds.debug @@ -111,6 +111,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index e2e66aec99..5296165aed 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -115,6 +115,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/examples/standalone/sparc.lds b/examples/standalone/sparc.lds index 9733daa86b..646b80f2d3 100644 --- a/examples/standalone/sparc.lds +++ b/examples/standalone/sparc.lds @@ -46,6 +46,7 @@ SECTIONS { *(.data) } + . = ALIGN(4); __data_end = .; diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds index d2b08f60c5..b2a0f7c854 100644 --- a/nand_spl/board/freescale/mx31pdk/u-boot.lds +++ b/nand_spl/board/freescale/mx31pdk/u-boot.lds @@ -50,6 +50,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds index d2b08f60c5..24a3c0c845 100644 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ b/nand_spl/board/karo/tx25/u-boot.lds @@ -50,6 +50,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { diff --git a/nand_spl/board/samsung/smdk6400/u-boot.lds b/nand_spl/board/samsung/smdk6400/u-boot.lds index 567f63516f..84810624cb 100644 --- a/nand_spl/board/samsung/smdk6400/u-boot.lds +++ b/nand_spl/board/samsung/smdk6400/u-boot.lds @@ -54,6 +54,11 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include + } + . = ALIGN(4); .rel.dyn : { -- cgit v1.2.3 From 6c7c946cadfafdea80eb930e3181085b907a0362 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Oct 2012 10:27:04 +0000 Subject: common: Convert the U-Boot commands to LG-arrays This patch converts the old method of creating a list of command onto the new LG-arrays code. The old u_boot_cmd section is converted to new u_boot_list_cmd subsection and LG-array macros used as needed. Minor adjustments had to be made to the common code to work with the LG-array macros, mostly the fixup_cmdtable() calls are now passed the ll_entry_start and ll_entry_count instead of linker-generated symbols. The command.c had to be adjusted as well so it would use the newly introduced LG-array API instead of directly using linker-generated symbols. Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger --- arch/arm/imx-common/cmd_bmode.c | 11 +++++++---- arch/avr32/lib/board.c | 4 ++-- arch/m68k/lib/board.c | 4 ++-- arch/mips/lib/board.c | 4 ++-- arch/nds32/lib/board.c | 4 ++-- arch/sparc/lib/board.c | 4 ++-- common/cmd_help.c | 8 ++++---- common/command.c | 17 ++++++++++------- doc/README.commands | 10 +++++----- include/command.h | 26 ++++++++++++++------------ 10 files changed, 50 insertions(+), 42 deletions(-) diff --git a/arch/arm/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c index 02fe72ed7f..ddc14b099e 100644 --- a/arch/arm/imx-common/cmd_bmode.c +++ b/arch/arm/imx-common/cmd_bmode.c @@ -24,6 +24,7 @@ #include #include #include +#include static const struct boot_mode *modes[2]; @@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p) int size; char *dest; - if (__u_boot_cmd_bmode.usage) { - free(__u_boot_cmd_bmode.usage); - __u_boot_cmd_bmode.usage = NULL; + cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd); + + if (entry->usage) { + free(entry->usage); + entry->usage = NULL; } modes[0] = p; @@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p) dest = malloc(size); if (dest) { create_usage(dest); - __u_boot_cmd_bmode.usage = dest; + entry->usage = dest; } } diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 9d3b76e15a..e3287c486b 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -272,8 +272,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) /* * We have to relocate the command table manually */ - fixup_cmdtable(&__u_boot_cmd_start, - (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); + fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), + ll_entry_count(cmd_tbl_t, cmd)); #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ /* there are some other pointer constants we must deal with */ diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 92f935bd01..02d73fda61 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -416,8 +416,8 @@ void board_init_r (gd_t *id, ulong dest_addr) /* * We have to relocate the command table manually */ - fixup_cmdtable(&__u_boot_cmd_start, - (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); + fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), + ll_entry_count(cmd_tbl_t, cmd)); #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ /* there are some other pointer constants we must deal with */ diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index b14b33efcd..7ddd77832c 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -266,8 +266,8 @@ void board_init_r(gd_t *id, ulong dest_addr) /* * We have to relocate the command table manually */ - fixup_cmdtable(&__u_boot_cmd_start, - (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); + fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), + ll_entry_count(cmd_tbl_t, cmd)); #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ /* there are some other pointer constants we must deal with */ diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 875f22013c..91395cabf3 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -320,8 +320,8 @@ void board_init_r(gd_t *id, ulong dest_addr) /* * We have to relocate the command table manually */ - fixup_cmdtable(&__u_boot_cmd_start, - (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); + fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), + ll_entry_count(cmd_tbl_t, cmd)); #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ serial_initialize(); diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index ff0e0f2fd0..32d025a342 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -246,8 +246,8 @@ void board_init_f(ulong bootflag) /* * We have to relocate the command table manually */ - fixup_cmdtable(&__u_boot_cmd_start, - (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); + fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), + ll_entry_count(cmd_tbl_t, cmd)); #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ #if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP) diff --git a/common/cmd_help.c b/common/cmd_help.c index 8c8178e41d..3178a1aa42 100644 --- a/common/cmd_help.c +++ b/common/cmd_help.c @@ -26,9 +26,9 @@ int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - return _do_help(&__u_boot_cmd_start, - &__u_boot_cmd_end - &__u_boot_cmd_start, - cmdtp, flag, argc, argv); + cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd); + const int len = ll_entry_count(cmd_tbl_t, cmd); + return _do_help(start, len, cmdtp, flag, argc, argv); } U_BOOT_CMD( @@ -41,7 +41,7 @@ U_BOOT_CMD( ); /* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */ -cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = { +ll_entry_declare(cmd_tbl_t, question_mark, cmd, cmd) = { "?", CONFIG_SYS_MAXARGS, 1, do_help, "alias for 'help'", #ifdef CONFIG_SYS_LONGHELP diff --git a/common/command.c b/common/command.c index aa0fb0a3d3..50c84292c1 100644 --- a/common/command.c +++ b/common/command.c @@ -137,8 +137,9 @@ cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len) cmd_tbl_t *find_cmd (const char *cmd) { - int len = &__u_boot_cmd_end - &__u_boot_cmd_start; - return find_cmd_tbl(cmd, &__u_boot_cmd_start, len); + cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd); + const int len = ll_entry_count(cmd_tbl_t, cmd); + return find_cmd_tbl(cmd, start, len); } int cmd_usage(const cmd_tbl_t *cmdtp) @@ -181,7 +182,9 @@ int var_complete(int argc, char * const argv[], char last_char, int maxv, char * static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]) { - cmd_tbl_t *cmdtp; + cmd_tbl_t *cmdtp = ll_entry_start(cmd_tbl_t, cmd); + const int count = ll_entry_count(cmd_tbl_t, cmd); + const cmd_tbl_t *cmdend = cmdtp + count; const char *p; int len, clen; int n_found = 0; @@ -195,12 +198,12 @@ static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv if (argc == 0) { /* output full list of commands */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + for (; cmdtp != cmdend; cmdtp++) { if (n_found >= maxv - 2) { - cmdv[n_found++] = "..."; + cmdv[n_found] = "..."; break; } - cmdv[n_found++] = cmdtp->name; + cmdv[n_found] = cmdtp->name; } cmdv[n_found] = NULL; return n_found; @@ -228,7 +231,7 @@ static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv len = p - cmd; /* return the partial matches */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { + for (; cmdtp != cmdend; cmdtp++) { clen = strlen(cmdtp->name); if (clen < len) diff --git a/doc/README.commands b/doc/README.commands index 125f077c08..923418b1a4 100644 --- a/doc/README.commands +++ b/doc/README.commands @@ -15,12 +15,12 @@ help: Long description. This is a string **** Behind the scene ****** -The structure created is named with a special prefix (__u_boot_cmd_) +The structure created is named with a special prefix (__u_boot_list_cmd_) and placed by the linker in a special section. This makes it possible for the final link to extract all commands compiled into any object code and construct a static array so the -command can be found in an array starting at __u_boot_cmd_start. +command can be found in an array starting at _u_boot_list_cmd__start. To ensure that the linker does not discard these symbols when linking full U-Boot we generate a list of all the commands we have built (based @@ -33,6 +33,6 @@ If a new board is defined do not forget to define the command section by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these 3 lines: - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_list : { + #include "u-boot.lst"; + } diff --git a/include/command.h b/include/command.h index 1f06aa1819..24864d5cc7 100644 --- a/include/command.h +++ b/include/command.h @@ -28,6 +28,7 @@ #define __COMMAND_H #include +#include #ifndef NULL #define NULL 0 @@ -153,9 +154,6 @@ int cmd_process(int flag, int argc, char * const argv[], #define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ #define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ -#define Struct_Section __attribute__((unused, section(".u_boot_cmd"), \ - aligned(4))) - #ifdef CONFIG_AUTO_COMPLETE # define _CMD_COMPLETE(x) x, #else @@ -167,18 +165,22 @@ int cmd_process(int flag, int argc, char * const argv[], # define _CMD_HELP(x) #endif -#define U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \ - {#name, maxargs, rep, cmd, usage, _CMD_HELP(help) _CMD_COMPLETE(comp)} +#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, _comp) \ + { #_name, _maxargs, _rep, _cmd, _usage, \ + _CMD_HELP(_help) _CMD_COMPLETE(_comp) } -#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \ - U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL) +#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help) \ + U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, NULL) -#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \ - cmd_tbl_t __u_boot_cmd_##name Struct_Section = \ - U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) +#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \ + ll_entry_declare(cmd_tbl_t, _name, cmd, cmd) = \ + U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ + _usage, _help, _comp); -#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ - U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL) +#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help) \ + U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL) #if defined(CONFIG_NEEDS_MANUAL_RELOC) void fixup_cmdtable(cmd_tbl_t *cmdtp, int size); -- cgit v1.2.3 From 8b493a52367623f36e628e4ab2cf8ee082b655e0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 17 Oct 2012 00:45:46 +0000 Subject: common: Discard the __u_boot_cmd section The command declaration now uses the new LG-array method to generate list of commands. Thus the __u_boot_cmd section is now superseded and redundant and therefore can be removed. Also, remove externed symbols associated with this section from include/command.h . Signed-off-by: Marek Vasut Cc: Joe Hershberger Cc: Mike Frysinger --- Makefile | 4 +--- arch/arm/cpu/arm920t/ep93xx/u-boot.lds | 3 --- arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 3 --- arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 3 --- arch/arm/cpu/ixp/u-boot.lds | 3 --- arch/arm/cpu/u-boot.lds | 3 --- arch/avr32/cpu/u-boot.lds | 5 ----- arch/blackfin/cpu/u-boot.lds | 6 ------ arch/microblaze/cpu/u-boot.lds | 8 -------- arch/nds32/cpu/n1213/u-boot.lds | 3 --- arch/nios2/cpu/u-boot.lds | 7 ------- arch/powerpc/cpu/74xx_7xx/u-boot.lds | 3 --- arch/powerpc/cpu/mpc512x/u-boot.lds | 3 --- arch/powerpc/cpu/mpc5xx/u-boot.lds | 3 --- arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds | 3 --- arch/powerpc/cpu/mpc5xxx/u-boot.lds | 3 --- arch/powerpc/cpu/mpc8220/u-boot.lds | 3 --- arch/powerpc/cpu/mpc824x/u-boot.lds | 3 --- arch/powerpc/cpu/mpc8260/u-boot.lds | 3 --- arch/powerpc/cpu/mpc83xx/u-boot.lds | 3 --- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 3 --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 3 --- arch/powerpc/cpu/mpc86xx/u-boot.lds | 3 --- arch/powerpc/cpu/ppc4xx/u-boot.lds | 3 --- arch/sandbox/cpu/u-boot.lds | 3 --- arch/sh/cpu/sh2/u-boot.lds | 7 ------- arch/sh/cpu/sh3/u-boot.lds | 7 ------- arch/sh/cpu/sh4/u-boot.lds | 7 ------- arch/x86/cpu/u-boot.lds | 4 ---- board/BuS/eb_cpu5282/u-boot.lds | 3 --- board/LEOX/elpt860/u-boot.lds | 3 --- board/RPXClassic/u-boot.lds | 3 --- board/RPXClassic/u-boot.lds.debug | 3 --- board/RPXlite/u-boot.lds | 3 --- board/RPXlite/u-boot.lds.debug | 3 --- board/RPXlite_dw/u-boot.lds | 3 --- board/RPXlite_dw/u-boot.lds.debug | 3 --- board/RRvision/u-boot.lds | 3 --- board/actux1/u-boot.lds | 5 ----- board/actux2/u-boot.lds | 5 ----- board/actux3/u-boot.lds | 5 ----- board/adder/u-boot.lds | 3 --- board/altera/nios2-generic/u-boot.lds | 7 ------- board/amcc/acadia/u-boot-nand.lds | 3 --- board/amcc/bamboo/u-boot-nand.lds | 3 --- board/amcc/canyonlands/u-boot-nand.lds | 3 --- board/amcc/kilauea/u-boot-nand.lds | 3 --- board/amcc/sequoia/u-boot-nand.lds | 3 --- board/amcc/sequoia/u-boot-ram.lds | 3 --- board/astro/mcf5373l/u-boot.lds | 3 --- board/c2mon/u-boot.lds | 3 --- board/c2mon/u-boot.lds.debug | 3 --- board/cobra5272/u-boot.lds | 3 --- board/cogent/u-boot.lds | 3 --- board/cogent/u-boot.lds.debug | 3 --- board/cray/L1/u-boot.lds.debug | 3 --- board/dave/PPChameleonEVB/u-boot.lds | 3 --- board/dbau1x00/u-boot.lds | 6 ------ board/dvlhost/u-boot.lds | 5 ----- board/eltec/mhpc/u-boot.lds | 3 --- board/eltec/mhpc/u-boot.lds.debug | 3 --- board/emk/top860/u-boot.lds | 3 --- board/ep88x/u-boot.lds | 3 --- board/esd/dasa_sim/u-boot.lds | 3 --- board/esd/pmc440/u-boot-nand.lds | 3 --- board/esd/tasreg/u-boot.lds | 3 --- board/esteem192e/u-boot.lds | 3 --- board/etx094/u-boot.lds | 3 --- board/evb64260/u-boot.lds | 3 --- board/fads/u-boot.lds | 3 --- board/flagadm/u-boot.lds | 3 --- board/flagadm/u-boot.lds.debug | 3 --- board/freescale/m5208evbe/u-boot.lds | 3 --- board/freescale/m52277evb/u-boot.lds | 3 --- board/freescale/m5235evb/u-boot.lds | 3 --- board/freescale/m5249evb/u-boot.lds | 3 --- board/freescale/m5253demo/u-boot.lds | 3 --- board/freescale/m5253evbe/u-boot.lds | 3 --- board/freescale/m5271evb/u-boot.lds | 3 --- board/freescale/m5272c3/u-boot.lds | 3 --- board/freescale/m5275evb/u-boot.lds | 3 --- board/freescale/m5282evb/u-boot.lds | 3 --- board/freescale/m53017evb/u-boot.lds | 3 --- board/freescale/m5329evb/u-boot.lds | 3 --- board/freescale/m5373evb/u-boot.lds | 3 --- board/freescale/m54451evb/u-boot.lds | 3 --- board/freescale/m54455evb/u-boot.lds | 3 --- board/freescale/m547xevb/u-boot.lds | 3 --- board/freescale/m548xevb/u-boot.lds | 3 --- board/freescale/mx31ads/u-boot.lds | 3 --- board/gaisler/gr_cpci_ax2000/u-boot.lds | 4 ---- board/gaisler/gr_ep2s60/u-boot.lds | 4 ---- board/gaisler/gr_xc3s_1500/u-boot.lds | 4 ---- board/gaisler/grsim/u-boot.lds | 4 ---- board/gaisler/grsim_leon2/u-boot.lds | 4 ---- board/gen860t/u-boot-flashenv.lds | 3 --- board/gen860t/u-boot.lds | 3 --- board/genietv/u-boot.lds | 3 --- board/genietv/u-boot.lds.debug | 3 --- board/hermes/u-boot.lds | 3 --- board/hermes/u-boot.lds.debug | 3 --- board/hymod/u-boot.lds | 3 --- board/hymod/u-boot.lds.debug | 3 --- board/icu862/u-boot.lds | 3 --- board/icu862/u-boot.lds.debug | 3 --- board/idmr/u-boot.lds | 3 --- board/incaip/u-boot.lds | 6 ------ board/ip860/u-boot.lds | 3 --- board/ip860/u-boot.lds.debug | 3 --- board/ivm/u-boot.lds | 3 --- board/ivm/u-boot.lds.debug | 3 --- board/korat/u-boot-F7FC.lds | 3 --- board/kup/kup4k/u-boot.lds | 3 --- board/kup/kup4k/u-boot.lds.debug | 3 --- board/kup/kup4x/u-boot.lds | 3 --- board/kup/kup4x/u-boot.lds.debug | 3 --- board/lantec/u-boot.lds | 3 --- board/lantec/u-boot.lds.debug | 3 --- board/lwmon/u-boot.lds | 3 --- board/lwmon/u-boot.lds.debug | 3 --- board/manroland/uc100/u-boot.lds | 3 --- board/matrix_vision/mvsmr/u-boot.lds | 3 --- board/mbx8xx/u-boot.lds | 3 --- board/mbx8xx/u-boot.lds.debug | 3 --- board/micronas/vct/u-boot.lds | 7 ------- board/mousse/u-boot.lds | 3 --- board/mousse/u-boot.lds.ram | 3 --- board/mousse/u-boot.lds.rom | 3 --- board/mpl/pip405/u-boot.lds.debug | 3 --- board/mvblue/u-boot.lds | 3 --- board/netphone/u-boot.lds | 3 --- board/netphone/u-boot.lds.debug | 3 --- board/netta/u-boot.lds | 3 --- board/netta/u-boot.lds.debug | 3 --- board/netta2/u-boot.lds | 3 --- board/netta2/u-boot.lds.debug | 3 --- board/netvia/u-boot.lds | 3 --- board/netvia/u-boot.lds.debug | 3 --- board/nx823/u-boot.lds | 3 --- board/nx823/u-boot.lds.debug | 3 --- board/openrisc/openrisc-generic/u-boot.lds | 3 --- board/pb1x00/u-boot.lds | 6 ------ board/qemu-mips/u-boot.lds | 7 ------- board/qi/qi_lb60/u-boot.lds | 3 --- board/quantum/u-boot.lds | 3 --- board/r360mpi/u-boot.lds | 3 --- board/rbc823/u-boot.lds | 3 --- board/renesas/sh7757lcr/u-boot.lds | 7 ------- board/rsdproto/u-boot.lds | 3 --- board/samsung/smdk6400/u-boot-nand.lds | 3 --- board/sandburst/karef/u-boot.lds.debug | 3 --- board/sandburst/metrobox/u-boot.lds.debug | 3 --- board/sandpoint/u-boot.lds | 3 --- board/siemens/IAD210/u-boot.lds | 3 --- board/sixnet/u-boot.lds | 3 --- board/snmc/qs850/u-boot.lds | 3 --- board/snmc/qs860t/u-boot.lds | 3 --- board/spc1920/u-boot.lds | 3 --- board/spd8xx/u-boot.lds | 3 --- board/spd8xx/u-boot.lds.debug | 3 --- board/stx/stxxtc/u-boot.lds | 3 --- board/stx/stxxtc/u-boot.lds.debug | 3 --- board/svm_sc8xx/u-boot.lds | 3 --- board/tqc/tqm8xx/u-boot.lds | 3 --- board/v37/u-boot.lds | 3 --- board/w7o/u-boot.lds.debug | 3 --- board/westel/amx860/u-boot.lds | 3 --- board/westel/amx860/u-boot.lds.debug | 3 --- board/xes/xpedite1000/u-boot.lds.debug | 3 --- include/command.h | 2 -- nand_spl/board/freescale/mx31pdk/u-boot.lds | 3 --- nand_spl/board/karo/tx25/u-boot.lds | 3 --- nand_spl/board/samsung/smdk6400/u-boot.lds | 3 --- 173 files changed, 1 insertion(+), 583 deletions(-) diff --git a/Makefile b/Makefile index c4afc9f507..feb0fd6666 100644 --- a/Makefile +++ b/Makefile @@ -533,12 +533,10 @@ GEN_UBOOT = \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot else GEN_UBOOT = \ - UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ - sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\ cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ - $$UNDEF_SYM $$UNDEF_LST $(__OBJS) \ + $$UNDEF_LST $(__OBJS) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -Map u-boot.map -o u-boot endif diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 8c6a407c43..008ae891ca 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -48,9 +48,6 @@ SECTIONS .got : { *(.got) } . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 2940a6f2c1..6dc681a313 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -50,9 +50,6 @@ SECTIONS } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index ae9538ee40..f3bd5e7367 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -50,9 +50,6 @@ SECTIONS } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index a7ffab3cca..81d954f2de 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -46,9 +46,6 @@ SECTIONS . = ALIGN(4); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 85f4eecf27..227aaff1e6 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -49,9 +49,6 @@ SECTIONS . = ALIGN(4); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds index 2accee6597..0b16d2a883 100644 --- a/arch/avr32/cpu/u-boot.lds +++ b/arch/avr32/cpu/u-boot.lds @@ -47,11 +47,6 @@ SECTIONS } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { - KEEP(*(.u_boot_cmd)) - } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds index cbc79de0ab..58db838fb0 100644 --- a/arch/blackfin/cpu/u-boot.lds +++ b/arch/blackfin/cpu/u-boot.lds @@ -112,12 +112,6 @@ SECTIONS CONSTRUCTORS } >ram_data - .u_boot_cmd : - { - ___u_boot_cmd_start = .; - *(.u_boot_cmd) - ___u_boot_cmd_end = .; - } >ram_data .u_boot_list : { #include diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 06a2855221..4297b93443 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -50,14 +50,6 @@ SECTIONS __data_end = .; } - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - . = ALIGN(4); .u_boot_list : { #include diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds index 62e357a27b..cef19c51ee 100644 --- a/arch/nds32/cpu/n1213/u-boot.lds +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -52,9 +52,6 @@ SECTIONS } . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds index e24b769b5e..d0eb80de0e 100644 --- a/arch/nios2/cpu/u-boot.lds +++ b/arch/nios2/cpu/u-boot.lds @@ -45,13 +45,6 @@ SECTIONS * the initialization code relocates the command table as * well -- admittedly, this is just pure laziness ;-) */ - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds index 04484a5ad7..ecee439579 100644 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds @@ -62,9 +62,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index 656a0620fc..7faefba555 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -57,9 +57,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index e04528daa6..c91e146d26 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -65,9 +65,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds index acddf5f1b2..ac7844dcf4 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index 998221e003..1f46eadb5d 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -60,9 +60,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds index 45d5e19f52..c1479544f9 100644 --- a/arch/powerpc/cpu/mpc8220/u-boot.lds +++ b/arch/powerpc/cpu/mpc8220/u-boot.lds @@ -59,9 +59,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds index a80d91eb5f..a7130125c7 100644 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ b/arch/powerpc/cpu/mpc824x/u-boot.lds @@ -60,9 +60,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index f33f64874c..42385fcc19 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -59,9 +59,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 45a9cf8395..d699def9dd 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -58,9 +58,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 29aabde4c3..f7c4a22d29 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -70,9 +70,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 49fe44d4eb..4a40a1f51b 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -77,9 +77,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 17371acebf..8bfadf28dc 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -64,9 +64,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 6df673ebf7..a96ddd5577 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -78,9 +78,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index b7f25ab88a..1b781ebf6a 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -24,9 +24,6 @@ SECTIONS { - __u_boot_cmd_start = .; - _u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds index 3cd28f7b35..17f8091ea4 100644 --- a/arch/sh/cpu/sh2/u-boot.lds +++ b/arch/sh/cpu/sh2/u-boot.lds @@ -72,13 +72,6 @@ SECTIONS } PROVIDE (_egot = .); - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); .u_boot_list : { #include diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds index f0bad518f2..c8319610c2 100644 --- a/arch/sh/cpu/sh3/u-boot.lds +++ b/arch/sh/cpu/sh3/u-boot.lds @@ -78,13 +78,6 @@ SECTIONS } PROVIDE (_egot = .); - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); .u_boot_list : { #include diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds index d204304cf4..0ecafcf5d9 100644 --- a/arch/sh/cpu/sh4/u-boot.lds +++ b/arch/sh/cpu/sh4/u-boot.lds @@ -75,13 +75,6 @@ SECTIONS } PROVIDE (_egot = .); - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); .u_boot_list : { #include diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index 4bb2a2f5a1..a1ecefafc6 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -33,10 +33,6 @@ SECTIONS .text : { *(.text*); } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds index a708d0607b..0c92d31f61 100644 --- a/board/BuS/eb_cpu5282/u-boot.lds +++ b/board/BuS/eb_cpu5282/u-boot.lds @@ -65,9 +65,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index b04e56c08b..2bb876d689 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -86,9 +86,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index 46f2f8f7b9..dc8c4e958f 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index 46f2f8f7b9..dc8c4e958f 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index 1b042f8e99..b43a1e4281 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 46134325d2..748e5113ef 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -71,9 +71,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index e3a44227c6..c41eed0e6f 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -54,11 +54,6 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) - } - __u_boot_cmd_end =.; . = ALIGN(4); .u_boot_list : { diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index e39b0ce675..84099840b5 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -54,11 +54,6 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) - } - __u_boot_cmd_end =.; . = ALIGN(4); .u_boot_list : { diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index d38f341515..a3bd02b0d2 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -54,11 +54,6 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) - } - __u_boot_cmd_end =.; . = ALIGN(4); .u_boot_list : { diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 05d6323d26..73e2f3f9cf 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -62,9 +62,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds index f0877330ae..289386b35c 100644 --- a/board/altera/nios2-generic/u-boot.lds +++ b/board/altera/nios2-generic/u-boot.lds @@ -46,13 +46,6 @@ SECTIONS * the initialization code relocates the command table as * well -- admittedly, this is just pure laziness ;-) */ - __u_boot_cmd_start = .; - .u_boot_cmd : - { - *(.u_boot_cmd) - } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index 9609338cd8..beba978f83 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -72,9 +72,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index 4f4194e0a7..2dd00d7f42 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -73,9 +73,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 1876baeb15..8ac5116296 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -73,9 +73,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index 9609338cd8..beba978f83 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -72,9 +72,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index a0b98f42a6..18266efd09 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -73,9 +73,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index 32a7661704..6b02784926 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -64,9 +64,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds index 5d2c6552b8..bc40fd649d 100644 --- a/board/astro/mcf5373l/u-boot.lds +++ b/board/astro/mcf5373l/u-boot.lds @@ -69,9 +69,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds index 0b92ef639c..b854c180c4 100644 --- a/board/c2mon/u-boot.lds +++ b/board/c2mon/u-boot.lds @@ -74,9 +74,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug index c28e2b94c3..92796e6744 100644 --- a/board/c2mon/u-boot.lds.debug +++ b/board/c2mon/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index 77b8e806c2..d054f20bce 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index f7137bda87..2a6027f814 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -70,9 +70,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index 46f2f8f7b9..dc8c4e958f 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index 15cccee718..d7a2e56008 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 184c6fc3ee..8a306d6076 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -74,9 +74,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 6992c0f571..8a871cff49 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -54,12 +54,6 @@ SECTIONS .sdata : { *(.sdata*) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - . = ALIGN(4); .u_boot_list : { #include diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 51716304a5..1bd1700aa2 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -54,11 +54,6 @@ SECTIONS *(.got) } . =.; - __u_boot_cmd_start =.; - .u_boot_cmd : { - *(.u_boot_cmd) - } - __u_boot_cmd_end =.; . = ALIGN(4); .u_boot_list : { diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index 25b8839540..c8d38942c9 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index c28e2b94c3..92796e6744 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index 485c68d656..22626d392a 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -67,9 +67,6 @@ SECTIONS . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 067fd5ffda..1dcc22a191 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -62,9 +62,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index 607e601c8c..7eca18390b 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -73,9 +73,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index 38f5cc6ba3..ca7df4592e 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -102,9 +102,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index 158828c150..0d6a0f3a3b 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -65,9 +65,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 3eaaad8bcd..69f15000db 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -75,9 +75,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds index df9b44a344..56c3470bde 100644 --- a/board/etx094/u-boot.lds +++ b/board/etx094/u-boot.lds @@ -75,9 +75,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index 05461ca8b9..eac9c070e3 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -70,9 +70,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index 4a41db8e36..6022dbce72 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index 25b8839540..c8d38942c9 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index c28e2b94c3..92796e6744 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds index b1d2d016d4..2c151f20f5 100644 --- a/board/freescale/m5208evbe/u-boot.lds +++ b/board/freescale/m5208evbe/u-boot.lds @@ -69,9 +69,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index 0a7ca55a53..dbd6f6ab20 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds index a4a62acefb..00932ae68d 100644 --- a/board/freescale/m5235evb/u-boot.lds +++ b/board/freescale/m5235evb/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index 77b8e806c2..d054f20bce 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index 1dd5539ca9..f8116f601e 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -69,9 +69,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index 77b8e806c2..d054f20bce 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index ecad6671c2..133ec01036 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index 77b8e806c2..d054f20bce 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index 60c0501d8b..fc68de1ba1 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index 28386f967a..ad49874c5a 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index 81da237bdb..d25a36f651 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -71,9 +71,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index c575522f27..6616594e7b 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -69,9 +69,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index 5d2c6552b8..bc40fd649d 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -69,9 +69,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds index 76ead53b7e..91328a4af6 100644 --- a/board/freescale/m54451evb/u-boot.lds +++ b/board/freescale/m54451evb/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds index 0d2cb02da7..36a4c264b9 100644 --- a/board/freescale/m54455evb/u-boot.lds +++ b/board/freescale/m54455evb/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index 11fa8bcd34..de4d0eb907 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index 0c8ffd41c6..fbbe0c5dc5 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index e59fd18414..29ad0e6e79 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -57,9 +57,6 @@ SECTIONS } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index ec72718beb..774c494f03 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -85,10 +85,6 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index 5a387967ff..f6d13014f3 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -85,10 +85,6 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 3da021c497..7df6e83392 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -85,10 +85,6 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index eba1015af9..b241cbc1d0 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -84,10 +84,6 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index 4f90a46cf4..63c15b9117 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -84,10 +84,6 @@ SECTIONS /* CMD Table */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - . = ALIGN(4); - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index 8e04b11019..1cbe7e32ba 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -71,9 +71,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index c8602be5ad..dd89c70f56 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -71,9 +71,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 961222b1e2..124b183516 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -80,9 +80,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index a3479ba290..e1cf249650 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index 9fe2f58ef3..f02eb1c2aa 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -72,9 +72,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 6a53d8a39f..e84cc7991e 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 50e4788030..7afae0a625 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -110,9 +110,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index 46f2f8f7b9..dc8c4e958f 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index f476967e39..6778eb13ad 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 87ec870160..3e075a85bd 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index 158828c150..0d6a0f3a3b 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -65,9 +65,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 6992c0f571..8a871cff49 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -54,12 +54,6 @@ SECTIONS .sdata : { *(.sdata*) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - . = ALIGN(4); .u_boot_list : { #include diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index 79e4f2d804..e47aff0fa7 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index 7e63cd70a1..4cca652748 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index ff4581f4a7..53a19b2947 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index f91310a078..033cff42d9 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -108,9 +108,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; .u_boot_list : { #include diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index 1b042f8e99..b43a1e4281 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index 1b042f8e99..b43a1e4281 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds index e57a7948e6..94118024bd 100644 --- a/board/lantec/u-boot.lds +++ b/board/lantec/u-boot.lds @@ -75,9 +75,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug index 29148eedda..e788f5c170 100644 --- a/board/lantec/u-boot.lds.debug +++ b/board/lantec/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index 78445b3068..bc71b0d2c1 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 8fcdb90919..0a3e6466a9 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index aa289cd52c..e32ae37ea4 100644 --- a/board/manroland/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds @@ -69,9 +69,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 5222ebd7eb..5a3a9eabbf 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -74,9 +74,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index 722a405929..4155b604fb 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds index 114ce10d90..2ce8d0e158 100644 --- a/board/micronas/vct/u-boot.lds +++ b/board/micronas/vct/u-boot.lds @@ -52,13 +52,6 @@ SECTIONS . = ALIGN(4); .sdata : { *(.sdata*) } - . = ALIGN(4); - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - . = ALIGN(4); .u_boot_list : { #include diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index aff426938f..43f91f1a3c 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -60,9 +60,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram index b3364be48c..5255651347 100644 --- a/board/mousse/u-boot.lds.ram +++ b/board/mousse/u-boot.lds.ram @@ -85,9 +85,6 @@ SECTIONS } > ram */ - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; __start___ex_table = .; __ex_table : { *(__ex_table) } > ram diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom index b4b9e02e52..29a34fb9c5 100644 --- a/board/mousse/u-boot.lds.rom +++ b/board/mousse/u-boot.lds.rom @@ -102,9 +102,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; __start___ex_table = .; __ex_table : { *(__ex_table) } diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index 15cccee718..d7a2e56008 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds index dc5747c846..c378564f6d 100644 --- a/board/mvblue/u-boot.lds +++ b/board/mvblue/u-boot.lds @@ -70,9 +70,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index ae48cba28a..cdc1fdac2c 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index ffebab52fe..900da64859 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index ae48cba28a..cdc1fdac2c 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index ffebab52fe..900da64859 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index ae48cba28a..cdc1fdac2c 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index ffebab52fe..900da64859 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index ae48cba28a..cdc1fdac2c 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index b37ea7b49f..6cbf4dc66e 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index 25b8839540..c8d38942c9 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index c28e2b94c3..92796e6744 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds index 599546487e..4cffacbd46 100644 --- a/board/openrisc/openrisc-generic/u-boot.lds +++ b/board/openrisc/openrisc-generic/u-boot.lds @@ -26,9 +26,6 @@ SECTIONS _endtext = .; } > ram - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } > ram - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 41b001c3b1..07ddd364a0 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -54,12 +54,6 @@ SECTIONS .sdata : { *(.sdata*) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - . = ALIGN(4); .u_boot_list : { #include diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index c5826a29d7..cb2356f731 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -59,13 +59,6 @@ SECTIONS . = ALIGN(4); .sdata : { *(.sdata*) } - . = .; - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - . = ALIGN(4); .u_boot_list : { #include diff --git a/board/qi/qi_lb60/u-boot.lds b/board/qi/qi_lb60/u-boot.lds index 4a373ec138..b3cb869748 100644 --- a/board/qi/qi_lb60/u-boot.lds +++ b/board/qi/qi_lb60/u-boot.lds @@ -47,9 +47,6 @@ SECTIONS .sdata : { *(.sdata*) } - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 3138154f7e..3ef0d9e0b7 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index 5e3d78fe94..a86b568f6e 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -77,9 +77,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds index b2cf39233b..cf406ce966 100644 --- a/board/renesas/sh7757lcr/u-boot.lds +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -77,13 +77,6 @@ SECTIONS } PROVIDE (_egot = .); - PROVIDE (__u_boot_cmd_start = .); - .u_boot_cmd : - { - *(.u_boot_cmd) - . = ALIGN(4); - } - PROVIDE (__u_boot_cmd_end = .); .u_boot_list : { #include diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index d43663c716..ff950294f3 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -97,9 +97,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index 50924fcf1e..fbb442a02b 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -47,9 +47,6 @@ SECTIONS . = ALIGN(4); .got : { *(.got) } - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = align(4); .u_boot_list : { diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index c3a72cb7b6..7a0757f146 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -115,9 +115,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index bb73307eff..07bd6fe19f 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -115,9 +115,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds index a9c06ad098..ae3afa1130 100644 --- a/board/sandpoint/u-boot.lds +++ b/board/sandpoint/u-boot.lds @@ -68,9 +68,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds index 4214acef55..c0f107319e 100644 --- a/board/siemens/IAD210/u-boot.lds +++ b/board/siemens/IAD210/u-boot.lds @@ -75,9 +75,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index 0a717073da..6cf7a01738 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index eca88e57d2..f57f8a0258 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -69,9 +69,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index 9133469f0c..18f962cfa5 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index a233817757..f69e39d583 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -75,9 +75,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index 722a405929..4155b604fb 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index ae48cba28a..cdc1fdac2c 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index ffebab52fe..900da64859 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 4cdad4b1d3..163587512b 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -83,9 +83,6 @@ SECTIONS . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index ea2fc44ae7..7cc41cd521 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -81,9 +81,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index c82b1b31b7..fd2d72e8ae 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -66,9 +66,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index 4d640887a1..2ce5a9a71c 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -106,9 +106,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds index 607473632d..9b69d3d1e6 100644 --- a/board/westel/amx860/u-boot.lds +++ b/board/westel/amx860/u-boot.lds @@ -75,9 +75,6 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug index 87ec870160..3e075a85bd 100644 --- a/board/westel/amx860/u-boot.lds.debug +++ b/board/westel/amx860/u-boot.lds.debug @@ -107,9 +107,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index 5296165aed..c4e5706543 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -111,9 +111,6 @@ SECTIONS _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/include/command.h b/include/command.h index 24864d5cc7..10bc2606c7 100644 --- a/include/command.h +++ b/include/command.h @@ -62,8 +62,6 @@ struct cmd_tbl_s { typedef struct cmd_tbl_s cmd_tbl_t; -extern cmd_tbl_t __u_boot_cmd_start; -extern cmd_tbl_t __u_boot_cmd_end; #if defined(CONFIG_CMD_RUN) extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds index b2a0f7c854..da49c100c5 100644 --- a/nand_spl/board/freescale/mx31pdk/u-boot.lds +++ b/nand_spl/board/freescale/mx31pdk/u-boot.lds @@ -46,9 +46,6 @@ SECTIONS } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds index 24a3c0c845..ee361314fd 100644 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ b/nand_spl/board/karo/tx25/u-boot.lds @@ -46,9 +46,6 @@ SECTIONS } . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { diff --git a/nand_spl/board/samsung/smdk6400/u-boot.lds b/nand_spl/board/samsung/smdk6400/u-boot.lds index 84810624cb..2ed646630c 100644 --- a/nand_spl/board/samsung/smdk6400/u-boot.lds +++ b/nand_spl/board/samsung/smdk6400/u-boot.lds @@ -50,9 +50,6 @@ SECTIONS . = ALIGN(4); .got : { *(.got) } - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; . = ALIGN(4); .u_boot_list : { -- cgit v1.2.3 From 47444a27d2d8fb5c9f2799345278f935d453ab5d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Oct 2012 10:27:06 +0000 Subject: kerneldoc: tmpl: Implement template for LG-arrays Implement kerneldoc template for linker-generated arrays. This is the first template in U-Boot that is used to generate kerneldoc style documentation. This template is very basic. Signed-off-by: Marek Vasut --- doc/DocBook/Makefile | 2 +- doc/DocBook/linker_lists.tmpl | 46 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 doc/DocBook/linker_lists.tmpl diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index 7f38444039..da88b32419 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/config.mk -DOCBOOKS := stdio.xml +DOCBOOKS := linker_lists.xml stdio.xml ### # The build process is as follows (targets): diff --git a/doc/DocBook/linker_lists.tmpl b/doc/DocBook/linker_lists.tmpl new file mode 100644 index 0000000000..f1975165d6 --- /dev/null +++ b/doc/DocBook/linker_lists.tmpl @@ -0,0 +1,46 @@ + + + + + + The U-Boot Linker-Generated Arrays + + + + This documentation is free software; you can redistribute + it and/or modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later + version. + + + + This program is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU General Public License for more details. + + + + You should have received a copy of the GNU General Public + License along with this program; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, + MA 02111-1307 USA + + + + For more details see the file COPYING in the source + distribution of U-Boot Bootloader. + + + + + + + + Linker-Generated Arrays +!Iinclude/linker_lists.h + + + -- cgit v1.2.3 From 24a3fdd64d449c1acd4ccc3636f8bf02e903b6f8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:26:06 +0000 Subject: ide: Add printf format string for CONFIG_SYS_64BIT_LBA option The size of an LBA type changes depending on this option. We need to use a different printf() string in each case, so create a define for this. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- include/ide.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/ide.h b/include/ide.h index 695d08eecc..158e1beaf9 100644 --- a/include/ide.h +++ b/include/ide.h @@ -43,8 +43,10 @@ extern ulong ide_bus_offset[]; #ifdef CONFIG_SYS_64BIT_LBA typedef uint64_t lbaint_t; +#define LBAF "%llx" #else typedef ulong lbaint_t; +#define LBAF "%lx" #endif /* -- cgit v1.2.3 From 0c9c8fb5ec9c2ec20670dce0c5ff0752371893da Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:26:08 +0000 Subject: disk: Make the disk partition code work with no specific partition types Currently, if the disk partition code is compiled with all of the parition types compiled out, it hits an #error which stops the build. This change adjusts that file so that those functions will fall through to their defaults in those cases instead of breaking the build. These functions are needed because other code calls them, and that code is needed because other config options are overly broad and bring in support we don't need along with support we do. Also reduce repetition of the 6-term #ifdef throughout the file. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- disk/part.c | 50 +++++++++++++++++--------------------------------- 1 file changed, 17 insertions(+), 33 deletions(-) diff --git a/disk/part.c b/disk/part.c index 8ba3cdeaa0..4646f682d2 100644 --- a/disk/part.c +++ b/disk/part.c @@ -35,12 +35,15 @@ #define PRINTF(fmt,args...) #endif +/* Rather than repeat this expression each time, add a define for it */ #if (defined(CONFIG_CMD_IDE) || \ defined(CONFIG_CMD_SATA) || \ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) +#define HAVE_BLOCK_DEVICE +#endif struct block_drvr { char *name; @@ -71,6 +74,7 @@ static const struct block_drvr block_drvr[] = { DECLARE_GLOBAL_DATA_PTR; +#ifdef HAVE_BLOCK_DEVICE block_dev_desc_t *get_dev(const char *ifname, int dev) { const struct block_drvr *drvr = block_drvr; @@ -104,12 +108,7 @@ block_dev_desc_t *get_dev(const char *ifname, int dev) } #endif -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) ) +#ifdef HAVE_BLOCK_DEVICE /* ------------------------------------------------------------------------- */ /* @@ -239,18 +238,7 @@ void dev_print (block_dev_desc_t *dev_desc) } #endif -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) ) - -#if defined(CONFIG_MAC_PARTITION) || \ - defined(CONFIG_DOS_PARTITION) || \ - defined(CONFIG_ISO_PARTITION) || \ - defined(CONFIG_AMIGA_PARTITION) || \ - defined(CONFIG_EFI_PARTITION) +#ifdef HAVE_BLOCK_DEVICE void init_part (block_dev_desc_t * dev_desc) { @@ -293,6 +281,12 @@ void init_part (block_dev_desc_t * dev_desc) } +#if defined(CONFIG_MAC_PARTITION) || \ + defined(CONFIG_DOS_PARTITION) || \ + defined(CONFIG_ISO_PARTITION) || \ + defined(CONFIG_AMIGA_PARTITION) || \ + defined(CONFIG_EFI_PARTITION) + static void print_part_header (const char *type, block_dev_desc_t * dev_desc) { puts ("\nPartition Map for "); @@ -326,6 +320,8 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc) dev_desc->dev, type); } +#endif /* any CONFIG_..._PARTITION */ + void print_part (block_dev_desc_t * dev_desc) { @@ -372,24 +368,12 @@ void print_part (block_dev_desc_t * dev_desc) puts ("## Unknown partition table\n"); } - -#else /* neither MAC nor DOS nor ISO nor AMIGA nor EFI partition configured */ -# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION -# error nor CONFIG_ISO_PARTITION nor CONFIG_AMIGA_PARTITION -# error nor CONFIG_EFI_PARTITION configured! -#endif - -#endif +#endif /* HAVE_BLOCK_DEVICE */ int get_partition_info(block_dev_desc_t *dev_desc, int part , disk_partition_t *info) { -#if defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) +#ifdef HAVE_BLOCK_DEVICE #ifdef CONFIG_PARTITION_UUIDS /* The common case is no UUID support */ @@ -444,7 +428,7 @@ int get_partition_info(block_dev_desc_t *dev_desc, int part default: break; } -#endif +#endif /* HAVE_BLOCK_DEVICE */ return -1; } -- cgit v1.2.3 From 9936be31fb11a702f6f2f867a2e65dc423ed7d36 Mon Sep 17 00:00:00 2001 From: Taylor Hutt Date: Fri, 12 Oct 2012 14:26:09 +0000 Subject: disk: Address cast and format errors This change addresses a few printf-formatting errors, and a typecast error. Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- disk/part_efi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/disk/part_efi.c b/disk/part_efi.c index 7a39d52f8e..a3873cebb3 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -422,7 +422,7 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, count = le32_to_int(pgpt_head->num_partition_entries) * le32_to_int(pgpt_head->sizeof_partition_entry); - debug("%s: count = %lu * %lu = %u\n", __func__, + debug("%s: count = %lu * %lu = %zu\n", __func__, le32_to_int(pgpt_head->num_partition_entries), le32_to_int(pgpt_head->sizeof_partition_entry), count); @@ -432,7 +432,8 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc, } if (count == 0 || pte == NULL) { - printf("%s: ERROR: Can't allocate 0x%X bytes for GPT Entries\n", + printf("%s: ERROR: Can't allocate 0x%zX " + "bytes for GPT Entries\n", __func__, count); return NULL; } @@ -474,7 +475,7 @@ static int is_pte_valid(gpt_entry * pte) sizeof(unused_guid.b)) == 0) { debug("%s: Found an unused PTE GUID at 0x%08X\n", __func__, - (unsigned int)pte); + (unsigned int)(uintptr_t)pte); return 0; } else { -- cgit v1.2.3 From 84cd93272e384bf26e8346f2153a0b46dfb7b434 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2012 14:26:11 +0000 Subject: fs: Add a Coreboot Filesystem (CBFS) driver and commands This change adds CBFS support and some commands to use it to u-boot. These commands are: cbfsinit - Initialize CBFS support and pull all metadata into RAM. The end of the ROM is an optional parameter which defaults to the standard 0xffffffff and can be used to support multiple CBFSes in a system. The last one set up with cbfsinit is the one that will be used. cbfsinfo - Print information from the CBFS header. cbfsls - Print out the size, type, and name of all the files in the current CBFS. Recognized types are translated into symbolic names. cbfsload - Load a file from CBFS into memory. Like the similar command for fat filesystems, you can optionally provide a maximum size. Support for CBFS is compiled in when the CONFIG_CMD_CBFS option is specified. The CBFS driver can also be used programmatically from within u-boot. If u-boot needs something out of CBFS very early before the heap is configured, it won't be able to use the normal CBFS support which caches some information in memory it allocates from the heap. The cbfs_file_find_uncached function searches a CBFS instance without touching the heap. Signed-off-by: Gabe Black Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- Makefile | 3 +- README | 7 ++ common/Makefile | 1 + common/cmd_cbfs.c | 214 ++++++++++++++++++++++++++++++++++ fs/Makefile | 1 + fs/cbfs/Makefile | 43 +++++++ fs/cbfs/cbfs.c | 339 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/cbfs.h | 181 +++++++++++++++++++++++++++++ 8 files changed, 788 insertions(+), 1 deletion(-) create mode 100644 common/cmd_cbfs.c create mode 100644 fs/cbfs/Makefile create mode 100644 fs/cbfs/cbfs.c create mode 100644 include/cbfs.h diff --git a/Makefile b/Makefile index feb0fd6666..328347d177 100644 --- a/Makefile +++ b/Makefile @@ -260,7 +260,8 @@ LIBS-y += drivers/net/npe/libnpe.o endif LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o -LIBS-y += fs/cramfs/libcramfs.o \ +LIBS-y += fs/cbfs/libcbfs.o \ + fs/cramfs/libcramfs.o \ fs/ext4/libext4fs.o \ fs/fat/libfat.o \ fs/fdos/libfdos.o \ diff --git a/README b/README index df4aed14e4..10017c53d5 100644 --- a/README +++ b/README @@ -1316,6 +1316,13 @@ The following options need to be configured: This will also enable the command "fatwrite" enabling the user to write files to FAT. +CBFS (Coreboot Filesystem) support + CONFIG_CMD_CBFS + + Define this to enable support for reading from a Coreboot + filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls + and cbfsload. + - Keyboard Support: CONFIG_ISA_KEYBOARD diff --git a/common/Makefile b/common/Makefile index fdfead79c2..281f4f1e16 100644 --- a/common/Makefile +++ b/common/Makefile @@ -70,6 +70,7 @@ COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o +COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff --git a/common/cmd_cbfs.c b/common/cmd_cbfs.c new file mode 100644 index 0000000000..3b6cfd879b --- /dev/null +++ b/common/cmd_cbfs.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CBFS commands + */ +#include +#include +#include + +int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + uintptr_t end_of_rom = 0xffffffff; + char *ep; + + if (argc > 2) { + printf("usage: cbfsls [end of rom]>\n"); + return 0; + } + if (argc == 2) { + end_of_rom = (int)simple_strtoul(argv[1], &ep, 16); + if (*ep) { + puts("\n** Invalid end of ROM **\n"); + return 1; + } + } + file_cbfs_init(end_of_rom); + if (file_cbfs_result != CBFS_SUCCESS) { + printf("%s.\n", file_cbfs_error()); + return 1; + } + return 0; +} + +U_BOOT_CMD( + cbfsinit, 2, 0, do_cbfs_init, + "initialize the cbfs driver", + "[end of rom]\n" + " - Initialize the cbfs driver. The optional 'end of rom'\n" + " parameter specifies where the end of the ROM is that the\n" + " CBFS is in. It defaults to 0xFFFFFFFF\n" +); + +int do_cbfs_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct cbfs_cachenode *file; + unsigned long offset; + unsigned long count; + char buf[12]; + long size; + + if (argc < 3) { + printf("usage: cbfsload [bytes]\n"); + return 1; + } + + /* parse offset and count */ + offset = simple_strtoul(argv[1], NULL, 16); + if (argc == 4) + count = simple_strtoul(argv[3], NULL, 16); + else + count = 0; + + file = file_cbfs_find(argv[2]); + if (!file) { + if (file_cbfs_result == CBFS_FILE_NOT_FOUND) + printf("%s: %s\n", file_cbfs_error(), argv[2]); + else + printf("%s.\n", file_cbfs_error()); + return 1; + } + + printf("reading %s\n", file_cbfs_name(file)); + + size = file_cbfs_read(file, (void *)offset, count); + + printf("\n%ld bytes read\n", size); + + sprintf(buf, "%lX", size); + setenv("filesize", buf); + + return 0; +} + +U_BOOT_CMD( + cbfsload, 4, 0, do_cbfs_fsload, + "load binary file from a cbfs filesystem", + " [bytes]\n" + " - load binary file 'filename' from the cbfs to address 'addr'\n" +); + +int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct cbfs_cachenode *file = file_cbfs_get_first(); + int files = 0; + + if (!file) { + printf("%s.\n", file_cbfs_error()); + return 1; + } + + printf(" size type name\n"); + printf("------------------------------------------\n"); + while (file) { + u32 type = file_cbfs_type(file); + char *type_name = NULL; + const char *filename = file_cbfs_name(file); + + printf(" %8d", file_cbfs_size(file)); + + switch (type) { + case CBFS_TYPE_STAGE: + type_name = "stage"; + break; + case CBFS_TYPE_PAYLOAD: + type_name = "payload"; + break; + case CBFS_TYPE_OPTIONROM: + type_name = "option rom"; + break; + case CBFS_TYPE_BOOTSPLASH: + type_name = "boot splash"; + break; + case CBFS_TYPE_RAW: + type_name = "raw"; + break; + case CBFS_TYPE_VSA: + type_name = "vsa"; + break; + case CBFS_TYPE_MBI: + type_name = "mbi"; + break; + case CBFS_TYPE_MICROCODE: + type_name = "microcode"; + break; + case CBFS_COMPONENT_CMOS_DEFAULT: + type_name = "cmos default"; + break; + case CBFS_COMPONENT_CMOS_LAYOUT: + type_name = "cmos layout"; + break; + case -1UL: + type_name = "null"; + break; + } + if (type_name) + printf(" %16s", type_name); + else + printf(" %16d", type); + + if (filename[0]) + printf(" %s\n", filename); + else + printf(" %s\n", "(empty)"); + file_cbfs_get_next(&file); + files++; + } + + printf("\n%d file(s)\n\n", files); + return 0; +} + +U_BOOT_CMD( + cbfsls, 1, 1, do_cbfs_ls, + "list files", + " - list the files in the cbfs\n" +); + +int do_cbfs_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct cbfs_header *header = file_cbfs_get_header(); + + if (!header) { + printf("%s.\n", file_cbfs_error()); + return 1; + } + + printf("\n"); + printf("CBFS version: %#x\n", header->version); + printf("ROM size: %#x\n", header->rom_size); + printf("Boot block size: %#x\n", header->boot_block_size); + printf("CBFS size: %#x\n", + header->rom_size - header->boot_block_size - header->offset); + printf("Alignment: %d\n", header->align); + printf("Offset: %#x\n", header->offset); + printf("\n"); + + return 0; +} + +U_BOOT_CMD( + cbfsinfo, 1, 1, do_cbfs_fsinfo, + "print information about filesystem", + " - print information about the cbfs filesystem\n" +); diff --git a/fs/Makefile b/fs/Makefile index 901e1894b6..b4db606236 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -22,6 +22,7 @@ # # +subdirs-$(CONFIG_CMD_CBFS) += cbfs subdirs-$(CONFIG_CMD_CRAMFS) := cramfs subdirs-$(CONFIG_CMD_EXT4) += ext4 ifndef CONFIG_CMD_EXT4 diff --git a/fs/cbfs/Makefile b/fs/cbfs/Makefile new file mode 100644 index 0000000000..2be8a6880b --- /dev/null +++ b/fs/cbfs/Makefile @@ -0,0 +1,43 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)libcbfs.o + +COBJS-$(CONFIG_CMD_CBFS) := cbfs.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c new file mode 100644 index 0000000000..cae6d56db7 --- /dev/null +++ b/fs/cbfs/cbfs.c @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +enum cbfs_result file_cbfs_result; + +const char *file_cbfs_error(void) +{ + switch (file_cbfs_result) { + case CBFS_SUCCESS: + return "Success"; + case CBFS_NOT_INITIALIZED: + return "CBFS not initialized"; + case CBFS_BAD_HEADER: + return "Bad CBFS header"; + case CBFS_BAD_FILE: + return "Bad CBFS file"; + case CBFS_FILE_NOT_FOUND: + return "File not found"; + default: + return "Unknown"; + } +} + + +static const u32 good_magic = 0x4f524243; +static const u8 good_file_magic[] = "LARCHIVE"; + + +static int initialized; +static struct cbfs_header cbfs_header; +static struct cbfs_cachenode *file_cache; + +/* Do endian conversion on the CBFS header structure. */ +static void swap_header(struct cbfs_header *dest, struct cbfs_header *src) +{ + dest->magic = be32_to_cpu(src->magic); + dest->version = be32_to_cpu(src->version); + dest->rom_size = be32_to_cpu(src->rom_size); + dest->boot_block_size = be32_to_cpu(src->boot_block_size); + dest->align = be32_to_cpu(src->align); + dest->offset = be32_to_cpu(src->offset); +} + +/* Do endian conversion on a CBFS file header. */ +static void swap_file_header(struct cbfs_fileheader *dest, + const struct cbfs_fileheader *src) +{ + memcpy(&dest->magic, &src->magic, sizeof(dest->magic)); + dest->len = be32_to_cpu(src->len); + dest->type = be32_to_cpu(src->type); + dest->checksum = be32_to_cpu(src->checksum); + dest->offset = be32_to_cpu(src->offset); +} + +/* + * Given a starting position in memory, scan forward, bounded by a size, and + * find the next valid CBFS file. No memory is allocated by this function. The + * caller is responsible for allocating space for the new file structure. + * + * @param start The location in memory to start from. + * @param size The size of the memory region to search. + * @param align The alignment boundaries to check on. + * @param newNode A pointer to the file structure to load. + * @param used A pointer to the count of of bytes scanned through, + * including the file if one is found. + * + * @return 1 if a file is found, 0 if one isn't. + */ +static int file_cbfs_next_file(u8 *start, u32 size, u32 align, + struct cbfs_cachenode *newNode, u32 *used) +{ + struct cbfs_fileheader header; + + *used = 0; + + while (size >= align) { + const struct cbfs_fileheader *fileHeader = + (const struct cbfs_fileheader *)start; + u32 name_len; + u32 step; + + /* Check if there's a file here. */ + if (memcmp(good_file_magic, &(fileHeader->magic), + sizeof(fileHeader->magic))) { + *used += align; + size -= align; + start += align; + continue; + } + + swap_file_header(&header, fileHeader); + if (header.offset < sizeof(const struct cbfs_cachenode *) || + header.offset > header.len) { + file_cbfs_result = CBFS_BAD_FILE; + return -1; + } + newNode->next = NULL; + newNode->type = header.type; + newNode->data = start + header.offset; + newNode->data_length = header.len; + name_len = header.offset - sizeof(struct cbfs_cachenode *); + newNode->name = (char *)fileHeader + + sizeof(struct cbfs_cachenode *); + newNode->name_length = name_len; + newNode->checksum = header.checksum; + + step = header.len; + if (step % align) + step = step + align - step % align; + + *used += step; + return 1; + } + return 0; +} + +/* Look through a CBFS instance and copy file metadata into regular memory. */ +static void file_cbfs_fill_cache(u8 *start, u32 size, u32 align) +{ + struct cbfs_cachenode *cache_node; + struct cbfs_cachenode *newNode; + struct cbfs_cachenode **cache_tail = &file_cache; + + /* Clear out old information. */ + cache_node = file_cache; + while (cache_node) { + struct cbfs_cachenode *oldNode = cache_node; + cache_node = cache_node->next; + free(oldNode); + } + file_cache = NULL; + + while (size >= align) { + int result; + u32 used; + + newNode = (struct cbfs_cachenode *) + malloc(sizeof(struct cbfs_cachenode)); + result = file_cbfs_next_file(start, size, align, + newNode, &used); + + if (result < 0) { + free(newNode); + return; + } else if (result == 0) { + free(newNode); + break; + } + *cache_tail = newNode; + cache_tail = &newNode->next; + + size -= used; + start += used; + } + file_cbfs_result = CBFS_SUCCESS; +} + +/* Get the CBFS header out of the ROM and do endian conversion. */ +static int file_cbfs_load_header(uintptr_t end_of_rom, + struct cbfs_header *header) +{ + struct cbfs_header *header_in_rom; + + header_in_rom = (struct cbfs_header *)(uintptr_t) + *(u32 *)(end_of_rom - 3); + swap_header(header, header_in_rom); + + if (header->magic != good_magic || header->offset > + header->rom_size - header->boot_block_size) { + file_cbfs_result = CBFS_BAD_HEADER; + return 1; + } + return 0; +} + +void file_cbfs_init(uintptr_t end_of_rom) +{ + u8 *start_of_rom; + initialized = 0; + + if (file_cbfs_load_header(end_of_rom, &cbfs_header)) + return; + + start_of_rom = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size); + + file_cbfs_fill_cache(start_of_rom + cbfs_header.offset, + cbfs_header.rom_size, cbfs_header.align); + if (file_cbfs_result == CBFS_SUCCESS) + initialized = 1; +} + +const struct cbfs_header *file_cbfs_get_header(void) +{ + if (initialized) { + file_cbfs_result = CBFS_SUCCESS; + return &cbfs_header; + } else { + file_cbfs_result = CBFS_NOT_INITIALIZED; + return NULL; + } +} + +const struct cbfs_cachenode *file_cbfs_get_first(void) +{ + if (!initialized) { + file_cbfs_result = CBFS_NOT_INITIALIZED; + return NULL; + } else { + file_cbfs_result = CBFS_SUCCESS; + return file_cache; + } +} + +void file_cbfs_get_next(const struct cbfs_cachenode **file) +{ + if (!initialized) { + file_cbfs_result = CBFS_NOT_INITIALIZED; + file = NULL; + return; + } + + if (*file) + *file = (*file)->next; + file_cbfs_result = CBFS_SUCCESS; +} + +const struct cbfs_cachenode *file_cbfs_find(const char *name) +{ + struct cbfs_cachenode *cache_node = file_cache; + + if (!initialized) { + file_cbfs_result = CBFS_NOT_INITIALIZED; + return NULL; + } + + while (cache_node) { + if (!strcmp(name, cache_node->name)) + break; + cache_node = cache_node->next; + } + if (!cache_node) + file_cbfs_result = CBFS_FILE_NOT_FOUND; + else + file_cbfs_result = CBFS_SUCCESS; + + return cache_node; +} + +const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom, + const char *name) +{ + u8 *start; + u32 size; + u32 align; + static struct cbfs_cachenode node; + + if (file_cbfs_load_header(end_of_rom, &cbfs_header)) + return NULL; + + start = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size); + size = cbfs_header.rom_size; + align = cbfs_header.align; + + while (size >= align) { + int result; + u32 used; + + result = file_cbfs_next_file(start, size, align, &node, &used); + + if (result < 0) + return NULL; + else if (result == 0) + break; + + if (!strcmp(name, node.name)) + return &node; + + size -= used; + start += used; + } + file_cbfs_result = CBFS_FILE_NOT_FOUND; + return NULL; +} + +const char *file_cbfs_name(const struct cbfs_cachenode *file) +{ + file_cbfs_result = CBFS_SUCCESS; + return file->name; +} + +u32 file_cbfs_size(const struct cbfs_cachenode *file) +{ + file_cbfs_result = CBFS_SUCCESS; + return file->data_length; +} + +u32 file_cbfs_type(const struct cbfs_cachenode *file) +{ + file_cbfs_result = CBFS_SUCCESS; + return file->type; +} + +long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer, + unsigned long maxsize) +{ + u32 size; + + size = file->data_length; + if (maxsize && size > maxsize) + size = maxsize; + + memcpy(buffer, file->data, size); + + file_cbfs_result = CBFS_SUCCESS; + return size; +} diff --git a/include/cbfs.h b/include/cbfs.h new file mode 100644 index 0000000000..6ea3f35119 --- /dev/null +++ b/include/cbfs.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CBFS_H +#define __CBFS_H + +#include +#include + +enum cbfs_result { + CBFS_SUCCESS = 0, + CBFS_NOT_INITIALIZED, + CBFS_BAD_HEADER, + CBFS_BAD_FILE, + CBFS_FILE_NOT_FOUND +}; + +enum cbfs_filetype { + CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_PAYLOAD = 0x20, + CBFS_TYPE_OPTIONROM = 0x30, + CBFS_TYPE_BOOTSPLASH = 0x40, + CBFS_TYPE_RAW = 0x50, + CBFS_TYPE_VSA = 0x51, + CBFS_TYPE_MBI = 0x52, + CBFS_TYPE_MICROCODE = 0x53, + CBFS_COMPONENT_CMOS_DEFAULT = 0xaa, + CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa +}; + +struct cbfs_header { + u32 magic; + u32 version; + u32 rom_size; + u32 boot_block_size; + u32 align; + u32 offset; + u32 pad[2]; +} __packed; + +struct cbfs_fileheader { + u8 magic[8]; + u32 len; + u32 type; + u32 checksum; + u32 offset; +} __packed; + +struct cbfs_cachenode { + struct cbfs_cachenode *next; + u32 type; + void *data; + u32 data_length; + char *name; + u32 name_length; + u32 checksum; +} __packed; + +extern enum cbfs_result file_cbfs_result; + +/* + * Return a string describing the most recent error condition. + * + * @return A pointer to the constant string. + */ +const char *file_cbfs_error(void); + +/* + * Initialize the CBFS driver and load metadata into RAM. + * + * @param end_of_rom Points to the end of the ROM the CBFS should be read + * from. + */ +void file_cbfs_init(uintptr_t end_of_rom); + +/* + * Get the header structure for the current CBFS. + * + * @return A pointer to the constant structure, or NULL if there is none. + */ +const struct cbfs_header *file_cbfs_get_header(void); + +/* + * Get a handle for the first file in CBFS. + * + * @return A handle for the first file in CBFS, NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_get_first(void); + +/* + * Get a handle to the file after this one in CBFS. + * + * @param file A pointer to the handle to advance. + */ +void file_cbfs_get_next(const struct cbfs_cachenode **file); + +/* + * Find a file with a particular name in CBFS. + * + * @param name The name to search for. + * + * @return A handle to the file, or NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_find(const char *name); + + +/***************************************************************************/ +/* All of the functions below can be used without first initializing CBFS. */ +/***************************************************************************/ + +/* + * Find a file with a particular name in CBFS without using the heap. + * + * @param end_of_rom Points to the end of the ROM the CBFS should be read + * from. + * @param name The name to search for. + * + * @return A handle to the file, or NULL on error. + */ +const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom, + const char *name); + +/* + * Get the name of a file in CBFS. + * + * @param file The handle to the file. + * + * @return The name of the file, NULL on error. + */ +const char *file_cbfs_name(const struct cbfs_cachenode *file); + +/* + * Get the size of a file in CBFS. + * + * @param file The handle to the file. + * + * @return The size of the file, zero on error. + */ +u32 file_cbfs_size(const struct cbfs_cachenode *file); + +/* + * Get the type of a file in CBFS. + * + * @param file The handle to the file. + * + * @return The type of the file, zero on error. + */ +u32 file_cbfs_type(const struct cbfs_cachenode *file); + +/* + * Read a file from CBFS into RAM + * + * @param file A handle to the file to read. + * @param buffer Where to read it into memory. + * + * @return If positive or zero, the number of characters read. If negative, an + * error occurred. + */ +long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer, + unsigned long maxsize); + +#endif /* __CBFS_H */ -- cgit v1.2.3 From af9f881a517ec54805419279885a661b762697d3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 12 Oct 2012 14:26:12 +0000 Subject: config: Enable CBFS, ext4 for coreboot Enable Coreboot and EXT4 Filesystems on the coreboot board. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 0e89242db7..3df085be51 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -92,6 +92,9 @@ #define CONFIG_MAC_PARTITION #define CONFIG_ISO_PARTITION /* Experimental */ +#define CONFIG_CMD_CBFS +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE /*----------------------------------------------------------------------- * Video Configuration -- cgit v1.2.3 From 3bb46d23f2f9b7afcd54e7d7cc35a519eb03d71e Mon Sep 17 00:00:00 2001 From: Ashok Date: Mon, 15 Oct 2012 06:20:47 +0000 Subject: README : Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111, CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96 Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111, CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96 Signed-off-by: Ashok Kumar Reddy Reviewed-by: Tom Rini --- README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README b/README index 10017c53d5..a664607b52 100644 --- a/README +++ b/README @@ -1084,7 +1084,7 @@ The following options need to be configured: CONFIG_CALXEDA_XGMAC Support for the Calxeda XGMAC device - CONFIG_DRIVER_LAN91C96 + CONFIG_LAN91C96 Support for SMSC's LAN91C96 chips. CONFIG_LAN91C96_BASE @@ -1094,7 +1094,7 @@ The following options need to be configured: CONFIG_LAN91C96_USE_32_BIT Define this to enable 32 bit addressing - CONFIG_DRIVER_SMC91111 + CONFIG_SMC91111 Support for SMSC's LAN91C111 chip CONFIG_SMC91111_BASE -- cgit v1.2.3 From 860bde3fee3092bc27d69f139a574f1a8377cc3a Mon Sep 17 00:00:00 2001 From: Ashok Date: Mon, 15 Oct 2012 06:27:47 +0000 Subject: omap2424:Rename CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96 as CONFIG_DRIVER_LAN91C96 is obsolete. Rename CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C9 as CONFIG_DRIVER_LAN91C96 is obsolete. Signed-off-by: Ashok Kumar Reddy --- board/ti/omap2420h4/omap2420h4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c index a3983e376b..188e4acc09 100644 --- a/board/ti/omap2420h4/omap2420h4.c +++ b/board/ti/omap2420h4/omap2420h4.c @@ -153,7 +153,7 @@ void wait_for_command_complete(unsigned int wd_base) ******************************************************************/ void ether_init (void) { -#ifdef CONFIG_DRIVER_LAN91C96 +#ifdef CONFIG_LAN91C96 int cnt = 20; __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ -- cgit v1.2.3 From bcf28c23f2195a91e0713337934f630a9c7bc5a9 Mon Sep 17 00:00:00 2001 From: Ashok Date: Mon, 15 Oct 2012 07:00:14 +0000 Subject: ARM : Remove unused CONFIG_DRIVER_SMC91111, CONFIG_DRIVER_LAN91C96 Remove unused CONFIG_DRIVER_SMC91111,CONFIG_DRIVER_LAN91C96, if required implement smc_set_mac_addr() in board init. Signed-off-by: Ashok Kumar Reddy Acked-by: Tom Rini --- arch/arm/lib/board.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 99cb54b8d8..92cad9a6eb 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -57,13 +57,6 @@ #include #endif -#ifdef CONFIG_DRIVER_SMC91111 -#include "../drivers/net/smc91111.h" -#endif -#ifdef CONFIG_DRIVER_LAN91C96 -#include "../drivers/net/lan91c96.h" -#endif - DECLARE_GLOBAL_DATA_PTR; ulong monitor_flash_len; @@ -613,16 +606,6 @@ void board_init_r(gd_t *id, ulong dest_addr) /* enable exceptions */ enable_interrupts(); - /* Perform network card initialisation if necessary */ -#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) - /* XXX: this needs to be moved to board init */ - if (getenv("ethaddr")) { - uchar enetaddr[6]; - eth_getenv_enetaddr("ethaddr", enetaddr); - smc_set_mac_addr(enetaddr); - } -#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ - /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -- cgit v1.2.3 From 9c889ece32d41063dd8e66e0c45a8e8c0c297149 Mon Sep 17 00:00:00 2001 From: ramneek mehresh Date: Tue, 18 Sep 2012 22:28:51 +0000 Subject: powerpc/mpc8xxx: Fix USB device-tree fixup Fix usb device-tree fixup: - wrong modification of dr_mode and phy_type when "usb1" is not mentioned inside hwconfig string; now allows hwconfig strings like: "usb2:dr_mode=host,phy_type=ulpi" - add warning message for using usb_dr_mode and usb_phy_type env variables (if either is used) Signed-off-by: Ramneek Mehresh Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc8xxx/fdt.c | 50 ++++++++++++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 32ab050962..68db8e2448 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -139,6 +139,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) const char *phys[] = { "ulpi", "utmi" }; const char *mode = NULL; const char *phy_type = NULL; + const char *dr_mode_type = NULL; + const char *dr_phy_type = NULL; char usb1_defined = 0; int usb_mode_off = -1; int usb_phy_off = -1; @@ -156,6 +158,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) break; } } + for (j = 0; j < ARRAY_SIZE(phys); j++) { if (hwconfig_subarg_cmp(str, "phy_type", phys[j])) { @@ -163,31 +166,46 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) break; } } - if (mode_idx >= 0) { - usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, - modes[mode_idx], NULL, usb_mode_off); - if (usb_mode_off < 0) - return; - } - if (phy_idx >= 0) { - usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, - NULL, phys[phy_idx], usb_phy_off); - if (usb_phy_off < 0) - return; - } + + dr_mode_type = modes[mode_idx]; + dr_phy_type = phys[phy_idx]; + + /* use usb_dr_mode and usb_phy_type if + usb1_defined = 0; these variables are to + be deprecated */ if (!strcmp(str, "usb1")) usb1_defined = 1; - if (mode_idx < 0 && phy_idx < 0) + + if (mode_idx < 0 && phy_idx < 0) { printf("WARNING: invalid phy or mode\n"); + return; + } } + + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, + dr_mode_type, NULL, usb_mode_off); + + if (usb_mode_off < 0) + return; + + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, + NULL, dr_phy_type, usb_phy_off); + + if (usb_phy_off < 0) + return; } + if (!usb1_defined) { int usb_off = -1; mode = getenv("usb_dr_mode"); phy_type = getenv("usb_phy_type"); - if (!mode && !phy_type) - return; - fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off); + if (mode || phy_type) { + printf("WARNING: usb_dr_mode and usb_phy_type " + "are to be deprecated soon. Use " + "hwconfig to set these values instead!!\n"); + fdt_fixup_usb_mode_phy_type(blob, mode, + phy_type, usb_off); + } } } #endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */ -- cgit v1.2.3 From d59c5570495a2721f4361275df668193e5f411f9 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Fri, 28 Sep 2012 21:26:19 +0000 Subject: powerpc/srio: Workaround for srio erratrm a004034 Erratum: A-004034 Affects: SRIO Description: During port initialization, the SRIO port performs lane synchronization (detecting valid symbols on a lane) and lane alignment (coordinating multiple lanes to receive valid data across lanes). Internal errors in lane synchronization and lane alignment may cause failure to achieve link initialization at the configured port width. An SRIO port configured as a 4x port may see one of these scenarios: 1. One or more lanes fails to achieve lane synchronization. Depending on which lanes fail, this may result in downtraining from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane). 2. The link may fail to achieve lane alignment as a 4x, even though all 4 lanes achieve lane synchronization, and downtrain to a 1x. An SRIO port configured as a 1x port may fail to complete port initialization (PnESCSR[PU] never deasserts) because of scenario 1. Impact: SRIO port may downtrain to 1x, or may fail to complete link initialization. Once a port completes link initialization successfully, it will operate normally. Signed-off-by: Liu Gang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc8xxx/srio.c | 191 ++++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 4 + 3 files changed, 198 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 7e4cc03640..bc7e5e36e2 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -127,6 +127,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 puts("Work-around for Erratum A004510 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 + puts("Work-around for Erratum SRIO-A004034 enabled\n"); #endif return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 0cb65b32e4..e7ff59a1ca 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -22,6 +22,7 @@ #include #include #include +#include #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 @@ -52,6 +53,185 @@ #error "No defines for DEVDISR_SRIO" #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 +/* + * Erratum A-004034 + * Affects: SRIO + * Description: During port initialization, the SRIO port performs + * lane synchronization (detecting valid symbols on a lane) and + * lane alignment (coordinating multiple lanes to receive valid data + * across lanes). Internal errors in lane synchronization and lane + * alignment may cause failure to achieve link initialization at + * the configured port width. + * An SRIO port configured as a 4x port may see one of these scenarios: + * 1. One or more lanes fails to achieve lane synchronization. Depending + * on which lanes fail, this may result in downtraining from 4x to 1x + * on lane 0, 4x to 1x on lane R (redundant lane). + * 2. The link may fail to achieve lane alignment as a 4x, even though + * all 4 lanes achieve lane synchronization, and downtrain to a 1x. + * An SRIO port configured as a 1x port may fail to complete port + * initialization (PnESCSR[PU] never deasserts) because of scenario 1. + * Impact: SRIO port may downtrain to 1x, or may fail to complete + * link initialization. Once a port completes link initialization + * successfully, it will operate normally. + */ +static int srio_erratum_a004034(u8 port) +{ + serdes_corenet_t *srds_regs; + u32 conf_lane; + u32 init_lane; + int idx, first, last; + u32 i; + unsigned long long end_tick; + struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); + conf_lane = (in_be32((void *)&srds_regs->srdspccr0) + >> (12 - port * 4)) & 0x3; + init_lane = (in_be32((void *)&srio_regs->lp_serial + .port[port].pccsr) >> 27) & 0x7; + + /* + * Start a counter set to ~2 ms after the SERDES reset is + * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n + * corresponding to the SERDES bank/PLL for the SRIO port). + */ + if (in_be32((void *)&srds_regs->bank[0].rstctl) + & SRDS_RSTCTL_RSTDONE) { + /* + * Poll the port uninitialized status (SRIO PnESCSR[PO]) until + * PO=1 or the counter expires. If the counter expires, the + * port has failed initialization: go to recover steps. If PO=1 + * and the desired port width is 1x, go to normal steps. If + * PO = 1 and the desired port width is 4x, go to recover steps. + */ + end_tick = usec2ticks(2000) + get_ticks(); + do { + if (in_be32((void *)&srio_regs->lp_serial + .port[port].pescsr) & 0x2) { + if (conf_lane == 0x1) + goto host_ok; + else { + if (init_lane == 0x2) + goto host_ok; + else + break; + } + } + } while (end_tick > get_ticks()); + + /* recover at most 3 times */ + for (i = 0; i < 3; i++) { + /* Set SRIO PnCCSR[PD]=1 */ + setbits_be32((void *)&srio_regs->lp_serial + .port[port].pccsr, + 0x800000); + /* + * Set SRIO PnPCR[OBDEN] on the host to + * enable the discarding of any pending packets. + */ + setbits_be32((void *)&srio_regs->impl.port[port].pcr, + 0x04); + /* Wait 50 us */ + udelay(50); + /* Run sync command */ + isync(); + + if (port) + first = serdes_get_first_lane(SRIO2); + else + first = serdes_get_first_lane(SRIO1); + if (unlikely(first < 0)) + return -ENODEV; + if (conf_lane == 0x1) + last = first; + else + last = first + 3; + /* + * Set SERDES BnGCRm0[RRST]=0 for each SRIO + * bank n and lane m. + */ + for (idx = first; idx <= last; idx++) + clrbits_be32(&srds_regs->lane[idx].gcr0, + SRDS_GCR0_RRST); + /* + * Read SERDES BnGCRm0 for each SRIO + * bank n and lane m + */ + for (idx = first; idx <= last; idx++) + in_be32(&srds_regs->lane[idx].gcr0); + /* Run sync command */ + isync(); + /* Wait >= 100 ns */ + udelay(1); + /* + * Set SERDES BnGCRm0[RRST]=1 for each SRIO + * bank n and lane m. + */ + for (idx = first; idx <= last; idx++) + setbits_be32(&srds_regs->lane[idx].gcr0, + SRDS_GCR0_RRST); + /* + * Read SERDES BnGCRm0 for each SRIO + * bank n and lane m + */ + for (idx = first; idx <= last; idx++) + in_be32(&srds_regs->lane[idx].gcr0); + /* Run sync command */ + isync(); + /* Wait >= 300 ns */ + udelay(1); + + /* Write 1 to clear all bits in SRIO PnSLCSR */ + out_be32((void *)&srio_regs->impl.port[port].slcsr, + 0xffffffff); + /* Clear SRIO PnPCR[OBDEN] on the host */ + clrbits_be32((void *)&srio_regs->impl.port[port].pcr, + 0x04); + /* Set SRIO PnCCSR[PD]=0 */ + clrbits_be32((void *)&srio_regs->lp_serial + .port[port].pccsr, + 0x800000); + /* Wait >= 24 ms */ + udelay(24000); + /* Poll the state of the port again */ + init_lane = + (in_be32((void *)&srio_regs->lp_serial + .port[port].pccsr) >> 27) & 0x7; + if (in_be32((void *)&srio_regs->lp_serial + .port[port].pescsr) & 0x2) { + if (conf_lane == 0x1) + goto host_ok; + else { + if (init_lane == 0x2) + goto host_ok; + } + } + if (i == 2) + return -ENODEV; + } + } else + return -ENODEV; + +host_ok: + /* Poll PnESCSR[OES] on the host until it is clear */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) + & 0x10000)) { + out_be32(((void *)&srio_regs->lp_serial + .port[port].pescsr), 0xffffffff); + out_be32(((void *)&srio_regs->phys_err + .port[port].edcsr), 0); + out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0); + return 0; + } + } while (end_tick > get_ticks()); + + return -ENODEV; +} +#endif + void srio_init(void) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; @@ -62,6 +242,11 @@ void srio_init(void) law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), LAW_TRGT_IF_RIO_1); srio1_used = 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 + if (srio_erratum_a004034(0) < 0) + printf("SRIO1: enabled but port error\n"); + else +#endif printf("SRIO1: enabled\n"); } else { printf("SRIO1: disabled\n"); @@ -73,7 +258,13 @@ void srio_init(void) law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), LAW_TRGT_IF_RIO_2); srio2_used = 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 + if (srio_erratum_a004034(1) < 0) + printf("SRIO2: enabled but port error\n"); + else +#endif printf("SRIO2: enabled\n"); + } else { printf("SRIO2: disabled\n"); } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 39a3cdede0..0013ba85ee 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -338,6 +338,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -367,6 +368,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_MAX_CPUS 8 @@ -406,6 +408,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_MAX_CPUS 2 @@ -432,6 +435,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 -- cgit v1.2.3 From 0c7e65f3d6535277e3842903079ac0704cde672b Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 5 Oct 2012 09:48:50 +0000 Subject: powerpc/mpc85xx: fix Unicode characters in release.S Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/release.S | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 22e73e0661..8662ae4381 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -159,20 +159,20 @@ __secondary_start_page: /* * PIR definition for E6500 * 0-17 Reserved (logic 0s) - * 8-19 CHIP_ID, 2’b00 - SoC 1 + * 8-19 CHIP_ID, 2'b00 - SoC 1 * all others - reserved - * 20-24 CLUSTER_ID 5’b00000 - CCM 1 + * 20-24 CLUSTER_ID 5'b00000 - CCM 1 * all others - reserved - * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1 - * 2’b01 - cluster 2 - * 2’b10 - cluster 3 - * 2’b11 - cluster 4 - * 27-28 CORE_ID 2’b00 - core 0 - * 2’b01 - core 1 - * 2’b10 - core 2 - * 2’b11 - core 3 - * 29-31 THREAD_ID 3’b000 - thread 0 - * 3’b001 - thread 1 + * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1 + * 2'b01 - cluster 2 + * 2'b10 - cluster 3 + * 2'b11 - cluster 4 + * 27-28 CORE_ID 2'b00 - core 0 + * 2'b01 - core 1 + * 2'b10 - core 2 + * 2'b11 - core 3 + * 29-31 THREAD_ID 3'b000 - thread 0 + * 3'b001 - thread 1 */ rlwinm r4,r0,29,25,31 #elif defined(CONFIG_E500MC) -- cgit v1.2.3 From e389a377ee3ad8d137c9af749ddf2354be0d4a7c Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 5 Oct 2012 09:48:51 +0000 Subject: powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/fsl_liodn.h | 5 +++++ arch/powerpc/include/asm/immap_85xx.h | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index a9973b80da..a37983ee54 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) +#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \ + SET_LIODN_ENTRY_1(compat, liodn,\ + offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\ + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) + /* reg nodes for DMA start @ 0x300 */ #define SET_DMA_LIODN(dmaNum, liodn) \ SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7de33a7dde..6c11178f0f 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -296,7 +296,9 @@ typedef struct ccsr_pcix { u32 cfg_addr; /* PCIX Configuration Addr */ u32 cfg_data; /* PCIX Configuration Data */ u32 int_ack; /* PCIX IRQ Acknowledge */ - u8 res1[3060]; + u8 res000c[52]; + u32 liodn_base; /* PCIX LIODN base register */ + u8 res0044[3004]; u32 potar0; /* PCIX Outbound Transaction Addr 0 */ u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ -- cgit v1.2.3 From fd946040f1398ce9ff58a62cb9971b0f560be028 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 5 Oct 2012 09:48:52 +0000 Subject: powerpc/85xx: define SRIO LIODN functions only if SRIO is defined The P5040 does not have SRIO support, so there are no SRIO LIODNs. Therefore, the functions that set the SRIO LIODNs should not be compiled. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/liodn.c | 8 ++++++++ arch/powerpc/include/asm/fsl_liodn.h | 4 +++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 11881c9489..e97388c7ab 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -40,6 +40,7 @@ int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset) return liodn_bases[dpaa_dev].num_ids; } +#ifdef CONFIG_SYS_SRIO static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size) { int i; @@ -54,6 +55,7 @@ static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size) } } } +#endif static void set_liodn(struct liodn_id_table *tbl, int size) { @@ -181,8 +183,10 @@ void set_liodns(void) /* setup general liodn offsets */ set_liodn(liodn_tbl, liodn_tbl_sz); +#ifdef CONFIG_SYS_SRIO /* setup SRIO port liodns */ set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz); +#endif /* setup SEC block liodn bases & offsets if we have one */ if (IS_E_PROCESSOR(get_svr())) { @@ -219,6 +223,7 @@ void set_liodns(void) #endif } +#ifdef CONFIG_SYS_SRIO static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) { int i, srio_off; @@ -247,6 +252,7 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) } } } +#endif static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) { @@ -277,7 +283,9 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) void fdt_fixup_liodn(void *blob) { +#ifdef CONFIG_SYS_SRIO fdt_fixup_srio_liodn(blob, srio_liodn_tbl); +#endif fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index a37983ee54..e591e67de6 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -189,11 +189,13 @@ extern void fdt_fixup_liodn(void *blob); extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; extern struct liodn_id_table raide_liodn_tbl[]; extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; +#ifdef CONFIG_SYS_SRIO extern struct srio_liodn_id_table srio_liodn_tbl[]; +extern int srio_liodn_tbl_sz; +#endif extern struct liodn_id_table rman_liodn_tbl[]; extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz; extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; -extern int srio_liodn_tbl_sz; extern int rman_liodn_tbl_sz; #endif -- cgit v1.2.3 From 11860d888cdc2be5da7b8738a067b84cd76e71c0 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 5 Oct 2012 09:48:53 +0000 Subject: powerpc/85xx: move SRIO configuration out of corenet_ds.h The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- include/configs/P3041DS.h | 4 ++++ include/configs/P4080DS.h | 4 ++++ include/configs/P5020DS.h | 4 ++++ include/configs/corenet_ds.h | 4 ---- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index 98e7a42e5f..cf184e74ab 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -36,6 +36,10 @@ #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index d6f2f5ceb8..53979dddf2 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -33,6 +33,10 @@ #define CONFIG_MMC #define CONFIG_PCIE3 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 8625f76290..7018d7a322 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -37,6 +37,10 @@ #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 8489d16dda..c41b039996 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -76,10 +76,6 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE -- cgit v1.2.3 From 71cfcef6499a9e2a552cbd0403fae497cc017093 Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Fri, 5 Oct 2012 09:48:54 +0000 Subject: powerpc/p5040ds: add per pci endpoint liodn offset list Add a new device tree property named "fsl,liodn-offset-list" holding a list of per pci endpoint permitted liodn offsets. This property is useful in virtualization scenarios that implement per pci endpoint partitioning. The final liodn of a partitioned pci endpoint is calculated by the hardware, by adding these offsets to pci controller's base liodn, stored in the "fsl,liodn" property of its node. The liodn offsets are interleaved to get better cache utilization. As an example, given 3 pci controllers, the following liodns are generated for the pci endpoints: pci0: 193 256 259 262 265 268 271 274 277 pci1: 194 257 260 263 266 269 272 275 278 pci2: 195 258 261 264 267 270 273 276 279 Signed-off-by: Laurentiu Tudor Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/liodn.c | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index e97388c7ab..2e533672f3 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -254,6 +254,56 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) } #endif +#define CONFIG_SYS_MAX_PCI_EPS 8 +#define CONFIG_SYS_PCI_EP_LIODN_START 256 + +static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) +{ + int off, pci_idx = 0, pci_cnt = 0, i, rc; + const uint32_t *base_liodn; + uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 }; + + /* + * Count the number of pci nodes. + * It's needed later when the interleaved liodn offsets are generated. + */ + off = fdt_node_offset_by_compatible(fdt, -1, compat); + while (off != -FDT_ERR_NOTFOUND) { + pci_cnt++; + off = fdt_node_offset_by_compatible(fdt, off, compat); + } + + for (off = fdt_node_offset_by_compatible(fdt, -1, compat); + off != -FDT_ERR_NOTFOUND; + off = fdt_node_offset_by_compatible(fdt, off, compat)) { + base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc); + if (!base_liodn) { + char path[64]; + + if (fdt_get_path(fdt, off, path, sizeof(path)) < 0) + strcpy(path, "(unknown)"); + printf("WARNING Could not get liodn of node %s: %s\n", + path, fdt_strerror(rc)); + continue; + } + for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++) + liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START + + i * pci_cnt + pci_idx - *base_liodn; + rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list", + liodn_offs, sizeof(liodn_offs)); + if (rc) { + char path[64]; + + if (fdt_get_path(fdt, off, path, sizeof(path)) < 0) + strcpy(path, "(unknown)"); + printf("WARNING Unable to set fsl,liodn-offset-list for " + "node %s: %s\n", path, fdt_strerror(rc)); + continue; + } + pci_idx++; + } +} + static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) { int i; @@ -303,4 +353,6 @@ void fdt_fixup_liodn(void *blob) #ifdef CONFIG_SYS_DPAA_RMAN fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif + + fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4"); } -- cgit v1.2.3 From 4905443f1ce7fc6159b7690e1f9e460dc6c6356d Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 5 Oct 2012 11:09:19 +0000 Subject: powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/Makefile | 3 + arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 70 ++++++++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 5 + arch/powerpc/cpu/mpc85xx/p5040_ids.c | 127 ++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p5040_serdes.c | 117 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/speed.c | 2 + arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/include/asm/config_mpc85xx.h | 29 ++++++ arch/powerpc/include/asm/immap_85xx.h | 15 +++ arch/powerpc/include/asm/processor.h | 2 + 10 files changed, 372 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/p5040_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 33e93c88d7..aad50f34ac 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -66,6 +66,7 @@ COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o @@ -80,6 +81,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o +COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o @@ -110,6 +112,7 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o +COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS = $(COBJS-y) COBJS += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 2a68060369..e6b1b1b7ee 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -92,10 +92,17 @@ static const struct { { 17, 163, FSL_SRDS_BANK_2 }, { 18, 164, FSL_SRDS_BANK_2 }, { 19, 165, FSL_SRDS_BANK_2 }, +#ifdef CONFIG_PPC_P4080 { 20, 170, FSL_SRDS_BANK_3 }, { 21, 171, FSL_SRDS_BANK_3 }, { 22, 172, FSL_SRDS_BANK_3 }, { 23, 173, FSL_SRDS_BANK_3 }, +#else + { 20, 166, FSL_SRDS_BANK_3 }, + { 21, 167, FSL_SRDS_BANK_3 }, + { 22, 168, FSL_SRDS_BANK_3 }, + { 23, 169, FSL_SRDS_BANK_3 }, +#endif }; int serdes_get_lane_idx(int lane) @@ -493,6 +500,9 @@ void fsl_serdes_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; +#ifdef CONFIG_PPC_P5040 + serdes_corenet_t *srds2_regs; +#endif int lane, bank, idx; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 @@ -574,6 +584,34 @@ void fsl_serdes_init(void) } } +#ifdef CONFIG_PPC_P5040 + /* + * Lanes on bank 4 on P5040 are commented-out, but for some SERDES + * protocols, these lanes are routed to SATA. We use serdes_prtcl_map + * to decide whether a protocol is supported on a given lane, so SATA + * will be identified as not supported, and therefore not initialized. + * So for protocols which use SATA on bank4, we add SATA support in + * serdes_prtcl_map. + */ + switch (cfg) { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2; + break; + default: + srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + + /* We don't need bank 4, so power it down */ + setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); + } +#endif + soc_serdes_init(); #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 @@ -617,6 +655,38 @@ void fsl_serdes_init(void) } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A004699 + /* + * To avoid the situation that resulted in the P4080 erratum + * SERDES-8, a given SerDes bank will use the PLLs from the previous + * bank if one of the PLL frequencies is a multiple of the other. For + * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz, + * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says + * that, in this situation, lane synchronization is not initiated. So + * when we detect a bank with a "borrowed" PLL, we have to manually + * initiate lane synchronization. + */ + for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) { + /* Determine the first lane for this bank */ + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) + if (lanes[lane].bank == bank) + break; + idx = lanes[lane].idx; + + /* + * Check if the PLL for the bank is borrowed. The UOTHL + * bit of the first lane will tell us that. + */ + if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) { + /* Manually start lane synchronization */ + setbits_be32(&srds_regs->bank[bank].pllcr0, + SRDS_PLLCR0_PVCOCNT_EN); + } + } +#endif + #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index f261351c8a..c82060dd33 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -22,6 +22,11 @@ #ifndef __FSL_CORENET_SERDES_H #define __FSL_CORENET_SERDES_H +/* + * Note: For P5040, the fourth SerDes bank is on SerDes2, but U-boot currently + * only supports one SerDes controller. For now, pretend that we have three + * banks and 18 lanes on the P5040. + */ #define SRDS_MAX_LANES 18 #define SRDS_MAX_BANK 3 diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c new file mode 100644 index 0000000000..878ee3e73e --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -0,0 +1,127 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 2), + SET_QP_INFO(7, 8, 4, 3), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(11, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 2), + SET_QP_INFO(15, 16, 8, 3), + SET_QP_INFO(17, 18, 9, 0), /* for now, set sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now, set sdest to 0 */ +}; +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + + SET_SDHC_LIODN(1, 64), + + SET_USB_LIODN(1, "fsl-usb2-mph", 93), + SET_USB_LIODN(2, "fsl-usb2-dr", 94), + + SET_SATA_LIODN(1, 95), + SET_SATA_LIODN(2, 96), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197), + + SET_DMA_LIODN(1, 193), + SET_DMA_LIODN(2, 194), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 6), + SET_FMAN_RX_1G_LIODN(1, 1, 7), + SET_FMAN_RX_1G_LIODN(1, 2, 8), + SET_FMAN_RX_1G_LIODN(1, 3, 9), + SET_FMAN_RX_1G_LIODN(1, 4, 10), + SET_FMAN_RX_10G_LIODN(1, 0, 11), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); + +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 12), + SET_FMAN_RX_1G_LIODN(2, 1, 13), + SET_FMAN_RX_1G_LIODN(2, 2, 14), + SET_FMAN_RX_1G_LIODN(2, 3, 15), + SET_FMAN_RX_1G_LIODN(2, 4, 16), + SET_FMAN_RX_10G_LIODN(2, 0, 17), +}; +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 89), + SET_SEC_RTIC_LIODN_ENTRY(b, 90), + SET_SEC_RTIC_LIODN_ENTRY(c, 91), + SET_SEC_RTIC_LIODN_ENTRY(d, 92), + SET_SEC_DECO_LIODN_ENTRY(0, 139, 140), + SET_SEC_DECO_LIODN_ENTRY(1, 141, 142), + SET_SEC_DECO_LIODN_ENTRY(2, 143, 144), + SET_SEC_DECO_LIODN_ENTRY(3, 145, 146), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct liodn_id_table raide_liodn_tbl[] = { + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), +}; +int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 101), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160), +#endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(49), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c new file mode 100644 index 0000000000..890b88e4e3 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c @@ -0,0 +1,117 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet_serdes.h" + +/* + * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but + * U-boot only supports one SerDes controller. Therefore, we ignore bank 4 in + * this table. This works because most of the SerDes code is for errata + * work-arounds, and there are no P5040 errata that effect bank 4. + */ + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ }, + [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, /* SATA1, SATA2 */ }, + [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ }, + [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + /* SATA1, SATA2 */ }, + [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + /* SATA1, SATA2 */ }, + [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ }, + [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ }, + [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, /* SATA1, SATA2 */ }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, + /* NONE, NONE */ }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, /* NONE, NONE */ }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM2, /* NONE, NONE */ }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, /* NONE, NONE */ }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, + /* NONE, NONE */ }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, /* NONE, NONE */ }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) +{ + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index abfeb268d4..6dd9e8db70 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -112,6 +112,8 @@ void get_sys_info (sys_info_t * sysInfo) #define HWA_ASYNC_DIV 0x04000000 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) #define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) +#define HWA_CC_PLL 2 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) #define HWA_CC_PLL 2 #else diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 78a8f926b3..fb78784345 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -73,6 +73,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P4080, P4080, 8), CPU_TYPE_ENTRY(P5010, P5010, 1), CPU_TYPE_ENTRY(P5020, P5020, 2), + CPU_TYPE_ENTRY(P5021, P5021, 2), + CPU_TYPE_ENTRY(P5040, P5040, 4), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), #elif defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0013ba85ee..636bd5f01d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -437,6 +437,35 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 +#elif defined(CONFIG_PPC_P5040) +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_NUM_FM2_DTSEC 5 +#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_USB138 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_ERRATUM_A004699 +#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC +#define CONFIG_SYS_FSL_ERRATUM_A004510 +#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 +#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 + #elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6c11178f0f..7c35b41004 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1761,6 +1761,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 +#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ @@ -1785,6 +1786,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 +#endif +#if defined(CONFIG_PPC_P5040) +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 +#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 +#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 +#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ @@ -2395,6 +2405,7 @@ typedef struct serdes_corenet { #define SRDS_RSTCTL_SDPD 0x00000020 u32 pllcr0; /* PLL Control Register 0 */ #define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000 +#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 @@ -2423,6 +2434,7 @@ typedef struct serdes_corenet { u32 gcr0; /* General Control Register 0 */ #define SRDS_GCR0_RRST 0x00400000 #define SRDS_GCR0_1STLANE 0x00010000 +#define SRDS_GCR0_UOTHL 0x00100000 u32 gcr1; /* General Control Register 1 */ #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 @@ -2627,6 +2639,7 @@ struct ccsr_rman { #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 +#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 @@ -2777,6 +2790,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 36695e2fb6..fd0160a2d1 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1095,6 +1095,8 @@ #define SVR_P4080 0x820000 #define SVR_P5010 0x822100 #define SVR_P5020 0x822000 +#define SVR_P5021 0X820500 +#define SVR_P5040 0x820400 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 -- cgit v1.2.3 From e4de13e38a24601e057c63f129bc80e127c91f9f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Sun, 7 Oct 2012 20:21:02 +0000 Subject: powerpc/board: add present2 register definition for QIXIS According to new QIXIS system definition, update QIXIS registers set to add present2 register instead of obsolete ctl_sys2. Signed-off-by: Shengzhou Liu Signed-off-by: Andy Fleming --- board/freescale/common/qixis.c | 2 +- board/freescale/common/qixis.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index e336b32806..c92902a92e 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -85,11 +85,11 @@ static void qixis_dump_regs(void) printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); printf("present = %02x\n", QIXIS_READ(present)); + printf("present2 = %02x\n", QIXIS_READ(present2)); printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); - printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2)); } #endif diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 83a3b693f6..b98b180655 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -26,7 +26,7 @@ struct qixis { u8 stat_sys; u8 stat_alrm; u8 present; - u8 ctl_sys2; + u8 present2; /* Presence Status Register 2,0x0c */ u8 rcw_ctl; u8 ctl_led; u8 i2cblk; -- cgit v1.2.3 From a1e4318cffb77fa604fb0d51ca09b7cef3555282 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:04 +0000 Subject: driver/pci: Fix compiling error Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT not defined. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- drivers/pci/fsl_pci_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 20dabf36f0..86ccbe7ee8 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -276,14 +276,18 @@ static void fsl_pcie_boot_master_release_slave(int port) release_addr = CONFIG_SYS_PCIE1_MEM_VIRT + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; break; +#ifdef CONFIG_SYS_PCIE2_MEM_VIRT case 2: release_addr = CONFIG_SYS_PCIE2_MEM_VIRT + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; break; +#endif +#ifdef CONFIG_SYS_PCIE3_MEM_VIRT case 3: release_addr = CONFIG_SYS_PCIE3_MEM_VIRT + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET; break; +#endif default: release_addr = 0; break; -- cgit v1.2.3 From 553ae6f8f2d860fb6a694fc3316bf80ba35ee794 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:05 +0000 Subject: powerpc/DPAA: Fix compiling error FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined. Remove the #ifdef. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/fsl_portals.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index 5644044eb8..9a764d2533 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -32,9 +32,7 @@ enum fsl_dpaa_dev { FSL_HW_PORTAL_FMAN2, #endif #endif -#ifdef CONFIG_SYS_DPAA_PME FSL_HW_PORTAL_PME, -#endif #ifdef CONFIG_SYS_FSL_RAID_ENGINE FSL_HW_PORTAL_RAID_ENGINE, #endif -- cgit v1.2.3 From 800c73c410732e1c9f852a935151c834f3b31c4d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 8 Oct 2012 07:44:06 +0000 Subject: powerpc/85xx: Add determining and report IFC frequency Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 ++++ arch/powerpc/cpu/mpc85xx/speed.c | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index a5048a1306..26fc84c9aa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -181,6 +181,10 @@ int checkcpu (void) } #endif +#if defined(CONFIG_FSL_IFC) + printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); +#endif + #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 6dd9e8db70..203f53d600 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -39,6 +39,10 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + u32 ccr; +#endif #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; @@ -230,6 +234,13 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqLocalBus = lcrr_div; } #endif + +#if defined(CONFIG_FSL_IFC) + ccr = in_be32(&ifc_regs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr; +#endif } -- cgit v1.2.3 From 69c7826759a69456df2a47fa4ef5dde19ab87e62 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:07 +0000 Subject: powerpc/mpc85xx: Introduce new macros to add and delete TLB entries These assembly macros simplify codes to add and delete temporary TLB entries. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/start.S | 309 ++++++++++++++++----------------------- 1 file changed, 130 insertions(+), 179 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9e04257d2c..e28ec558e1 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -211,6 +211,77 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b + .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch + lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l + mtspr MAS0, \scratch + lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h + ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l + mtspr MAS1, \scratch + lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h + ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l + mtspr MAS2, \scratch + lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h + ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l + mtspr MAS3, \scratch + lis \scratch, \phy_high@h + ori \scratch, \scratch, \phy_high@l + mtspr MAS7, \scratch + isync + msync + tlbwe + isync + .endm + + .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch + lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l + mtspr MAS0, \scratch + lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h + ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l + mtspr MAS1, \scratch + lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h + ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l + mtspr MAS2, \scratch + lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h + ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l + mtspr MAS3, \scratch + lis \scratch, \phy_high@h + ori \scratch, \scratch, \phy_high@l + mtspr MAS7, \scratch + isync + msync + tlbwe + isync + .endm + + .macro delete_tlb1_entry esel scratch + lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l + mtspr MAS0, \scratch + li \scratch, 0 + mtspr MAS1, \scratch + isync + msync + tlbwe + isync + .endm + + .macro delete_tlb0_entry esel epn wimg scratch + lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l + mtspr MAS0, \scratch + li \scratch, 0 + mtspr MAS1, \scratch + lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h + ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l + mtspr MAS2, \scratch + isync + msync + tlbwe + isync + .endm + #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) /* * TLB entry for debuggging in AS1 @@ -220,61 +291,35 @@ l2_disabled: * in AS1. */ - lis r6,FSL_BOOKE_MAS0(1, - CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(1, - CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l - #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) /* * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. * and this window is outside of 4K boot window. */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, - (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, - (MAS2_I|MAS2_G))@l + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_4M, \ + CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ + 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 - /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ - lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l - - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@l + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ + CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 #else /* * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * because "nexti" will resize TLB to 4K */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, - (MAS2_I))@l - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@l + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_256K, \ + CONFIG_SYS_MONITOR_BASE, MAS2_I, \ + CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 #endif - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - tlbwe - isync #endif /* @@ -392,27 +437,11 @@ l2_disabled: */ /* create a temp mapping TLB0[0] for LBCR */ - lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l - - lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l - - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@l - - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe + create_tlb0_entry 0, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \ + CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \ + 0, r6 /* Set LBCR register */ lis r4,CONFIG_SYS_LBCR_ADDR@h @@ -551,49 +580,22 @@ create_ccsr_new_tlb: ori r8, r8, CONFIG_SYS_CCSRBAR@l lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l - lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h - ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l - lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h - ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l - lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h - ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l - lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h - ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l -#ifdef CONFIG_ENABLE_36BIT_PHYS - lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - mtspr MAS7, r7 -#endif - mtspr MAS0, r0 - mtspr MAS1, r1 - mtspr MAS2, r2 - mtspr MAS3, r3 - isync - msync - tlbwe - + create_tlb0_entry 0, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ + CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 /* * Create a TLB for the current location of CCSR. Register R9 is reserved * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: - lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h - ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l - lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h - ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l - lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h - ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l -#ifdef CONFIG_ENABLE_36BIT_PHYS - li r7, 0 /* The default CCSR address is always a 32-bit number */ - mtspr MAS7, r7 -#endif - mtspr MAS0, r0 - /* MAS1 is the same as above */ - mtspr MAS2, r2 - mtspr MAS3, r3 - isync - msync - tlbwe + create_tlb0_entry 1, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ + CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ + 0, r3 /* The default CCSR address is always a 32-bit number */ + /* * We have a TLB for what we think is the current (old) CCSR. Let's @@ -743,27 +745,9 @@ write_new_ccsrbar: /* Delete the temporary TLBs */ delete_temp_tlbs: - lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h - ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l - li r1, 0 - lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h - ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l - mtspr MAS0, r0 - mtspr MAS1, r1 - mtspr MAS2, r2 - isync - msync - tlbwe + delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 - lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h - ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l - lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h - ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l - mtspr MAS0, r0 - mtspr MAS2, r2 - isync - msync - tlbwe #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 @@ -1019,83 +1003,50 @@ create_init_ram_area: #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) /* create a temp mapping in AS=1 to the 4M boot window */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_4M, \ + CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ + 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 - /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ - lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) /* create a temp mapping in AS = 1 for Flash mapping * created by PBL for ISBC code */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l - - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@l + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ + CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 #else /* * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l - - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ + CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 #endif - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - /* create a temp mapping in AS=1 to the stack */ - lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l - - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l - - lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h - ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l - #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, - (MAS3_SX|MAS3_SW|MAS3_SR))@l - li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH - mtspr MAS7,r10 + create_tlb1_entry 14, \ + 1, BOOKE_PAGESZ_16K, \ + CONFIG_SYS_INIT_RAM_ADDR, 0, \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 + #else - lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + create_tlb1_entry 14, \ + 1, BOOKE_PAGESZ_16K, \ + CONFIG_SYS_INIT_RAM_ADDR, 0, \ + CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 #endif - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - lis r6,MSR_IS|MSR_DS|MSR_DE@h ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l lis r7,switch_as@h -- cgit v1.2.3 From 6d2b9da19cbfe0b7da7e9ae0bf2a1a000f2e2804 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:08 +0000 Subject: powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 50 +++++++++++++++++++++++++++-- arch/powerpc/cpu/mpc85xx/fdt.c | 14 ++++++++- arch/powerpc/cpu/mpc85xx/release.S | 14 ++++----- arch/powerpc/cpu/mpc85xx/start.S | 37 +++++++++++++++++++++- arch/powerpc/include/asm/immap_85xx.h | 59 +++++++++++++++++++++++++++++++++++ 5 files changed, 163 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index ba558dedd7..e82c9517fe 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -295,6 +295,43 @@ static void __fsl_serdes__init(void) } __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +int enable_cluster_l2(void) +{ + int i = 0; + u32 cluster; + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct ccsr_cluster_l2 __iomem *l2cache; + + cluster = in_be32(&gur->tp_cluster[i].lower); + if (cluster & TP_CLUSTER_EOC) + return 0; + + /* The first cache has already been set up, so skip it */ + i++; + + /* Look through the remaining clusters, and set up their caches */ + do { + l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); + cluster = in_be32(&gur->tp_cluster[i].lower); + + /* set stash ID to (cluster) * 2 + 32 + 1 */ + clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); + + printf("enable l2 for cluster %d %p\n", i, l2cache); + + out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); + while ((in_be32(&l2cache->l2csr0) & + (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) + ; + out_be32(&l2cache->l2csr0, L2CSR0_L2E); + i++; + } while (!(cluster & TP_CLUSTER_EOC)); + + return 0; +} +#endif + /* * Initialize L2 as cache. * @@ -306,7 +343,12 @@ int cpu_init_r(void) { __maybe_unused u32 svr = get_svr(); #ifdef CONFIG_SYS_LBC_LCRR - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; +#endif +#ifdef CONFIG_L2_CACHE + ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) + struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ @@ -356,7 +398,6 @@ int cpu_init_r(void) puts ("L2: "); #if defined(CONFIG_L2_CACHE) - volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint ver; u32 l2siz_field; @@ -467,6 +508,11 @@ int cpu_init_r(void) } skip_l2: +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) + if (l2cache->l2csr0 & L2CSR0_L2E) + printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64); + + enable_cluster_l2(); #else puts("disabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index a0a9b4c5ae..d54527aa47 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -220,12 +220,19 @@ static inline void ft_fixup_l2cache(void *blob) /* we dont bother w/L3 since no platform of this type has one */ } -#elif defined(CONFIG_BACKSIDE_L2_CACHE) +#elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ + defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) static inline void ft_fixup_l2cache(void *blob) { int off, l2_off, l3_off = -1; u32 *ph; +#ifdef CONFIG_BACKSIDE_L2_CACHE u32 l2cfg0 = mfspr(SPRN_L2CFG0); +#else + struct ccsr_cluster_l2 *l2cache = + (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); + u32 l2cfg0 = in_be32(&l2cache->l2cfg0); +#endif u32 size, line_size, num_ways, num_sets; int has_l2 = 1; @@ -257,7 +264,12 @@ static inline void ft_fixup_l2cache(void *blob) if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + /* Only initialize every eighth thread */ + if (reg && !((*reg) % 8)) +#else if (reg) +#endif fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); #endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 8662ae4381..23a3aaf48e 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -183,13 +183,6 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8 -#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) - /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ - slwi r8,r4,1 - addi r8,r8,32 - mtspr L1CSR2,r8 -#endif - #ifdef CONFIG_E6500 mfspr r0,SPRN_PIR /* @@ -209,6 +202,13 @@ __secondary_start_page: mtspr SPRN_PIR,r4 /* write to PIR register */ +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index e28ec558e1..ac17f9d3ca 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -169,7 +169,7 @@ l2_disabled: * */ -#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) +#ifdef CONFIG_SYS_CACHE_STASHING /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ li r2,(32 + 0) mtspr L1CSR2,r2 @@ -750,6 +750,41 @@ delete_temp_tlbs: #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +create_ccsr_l2_tlb: + /* + * Create a TLB for the MMR location of CCSR + * to access L2CSR0 register + */ + create_tlb0_entry 0, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ + CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + +enable_l2_cluster_l2: + /* enable L2 cache */ + lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h + ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l + li r4, 33 /* stash id */ + stw r4, 4(r3) + lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l + sync + stw r4, 0(r3) /* invalidate L2 */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + bne 1b + lis r4, L2CSR0_L2E@h + sync + stw r4, 0(r3) /* eanble L2 */ +delete_ccsr_l2_tlb: + delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_1M 0x13 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7c35b41004..1181d2b93c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2681,6 +2681,7 @@ struct ccsr_rman { #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 +#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 #else #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 @@ -2825,4 +2826,62 @@ struct ccsr_rman { #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +struct ccsr_cluster_l2 { + u32 l2csr0; /* 0x000 L2 cache control and status register 0 */ + u32 l2csr1; /* 0x004 L2 cache control and status register 1 */ + u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */ + u8 res_0c[500];/* 0x00c - 0x1ff */ + u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */ + u8 res_204[4]; + u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */ + u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */ + u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */ + u8 res_214[4]; + u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */ + u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */ + u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */ + u8 res_224[4]; + u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */ + u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */ + u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */ + u8 res_234[4]; + u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */ + u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */ + u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */ + u8 res244[4]; + u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */ + u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */ + u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */ + u8 res_254[4]; + u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */ + u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */ + u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */ + u8 res_264[4]; + u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */ + u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */ + u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */ + u8 res274[4]; + u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */ + u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */ + u8 res_280[0xb80]; /* 0x280 - 0xdff */ + u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */ + u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */ + u32 l2errinjctl;/* 0xe08 L2 cache error injection control */ + u8 res_e0c[20]; /* 0xe0c - 0x01f */ + u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */ + u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */ + u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */ + u8 res_e2c[20]; /* 0xe2c - 0xe3f */ + u32 l2errdet; /* 0xe40 L2 cache error detect */ + u32 l2errdis; /* 0xe44 L2 cache error disable */ + u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */ + u32 l2errattr; /* 0xe4c L2 cache error attribute */ + u32 l2erreaddr; /* 0xe50 L2 cache error extended address */ + u32 l2erraddr; /* 0xe54 L2 cache error address */ + u32 l2errctl; /* 0xe58 L2 cache error control */ +}; +#define CONFIG_SYS_FSL_CLUSTER_1_L2 \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #endif /*__IMMAP_85xx__*/ -- cgit v1.2.3 From f77329cfcf65e142ffbe930594c4d411c5d66429 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:09 +0000 Subject: powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/speed.c | 4 +++- arch/powerpc/include/asm/immap_85xx.h | 7 +++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 203f53d600..6c2bc34714 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -85,7 +85,9 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = sysclk; sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f; + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) + & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; if (mem_pll_rat > 2) sysInfo->freqDDRBus *= mem_pll_rat; else diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 1181d2b93c..d0824b36e5 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1757,6 +1757,13 @@ typedef struct ccsr_gur { u32 brrl; /* Boot release */ u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ +#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f +#else +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#endif #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 -- cgit v1.2.3 From 2f1712b275af3ed960b92cd1ed9b99d23c4919a5 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:10 +0000 Subject: powerpc/mpc85xx: check number of cores Panic if the number of cores is more than CONFIG_MAX_CPUS because it will surely overflow gd structure. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 26fc84c9aa..40cce1dbda 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -127,6 +127,11 @@ int checkcpu (void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + if (nr_cores > CONFIG_MAX_CPUS) { + panic("\nUnexpected number of cores: %d, max is %d\n", + nr_cores, CONFIG_MAX_CPUS); + } + get_sys_info(&sysinfo); puts("Clock Configuration:"); -- cgit v1.2.3 From 9a653a9810160351ba1930ec55eae37c1a492b78 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:11 +0000 Subject: powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/speed.c | 138 +++++++++++++++++++++++++++++++--- arch/powerpc/include/asm/immap_85xx.h | 36 +++++---- 2 files changed, 148 insertions(+), 26 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 6c2bc34714..f07a28b462 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -76,8 +76,8 @@ void get_sys_info (sys_info_t * sysInfo) [13] = 2, /* CC4 PPL / 2 */ [14] = 4, /* CC4 PPL / 4 */ }; - uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; - uint ratio[4]; + uint i, freqCC_PLL[6], rcw_tmp; + uint ratio[6]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; @@ -97,21 +97,139 @@ void get_sys_info (sys_info_t * sysInfo) ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; - for (i = 0; i < 4; i++) { + ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f; + ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f; + for (i = 0; i < 6; i++) { if (ratio[i] > 4) freqCC_PLL[i] = sysclk * ratio[i]; else freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i]; } - rcw_tmp = in_be32(&gur->rcwsr[3]); +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + /* + * Each cluster has up to 4 cores, sharing the same PLL selection. + * The cluster assignment is fixed per SoC. There is no way identify the + * assignment so far, presuming the "first configuration" which is to + * fill the lower cluster group first before moving up to next group. + * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1 + * and core 4~7 on cluster 2 + * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3 + * and core 12~15 on cluster 4 if existing + */ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { - u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; + u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27) + & 0xf; u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + if (cplx_pll > 3) + printf("Unsupported architecture configuration" + " in function %s\n", __func__); + cplx_pll += (cpu / 8) * 3; sysInfo->freqProcessor[cpu] = freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; } +#define PME_CLK_SEL 0xe0000000 +#define PME_CLK_SHIFT 29 +#define FM1_CLK_SEL 0x1c000000 +#define FM1_CLK_SHIFT 26 + rcw_tmp = in_be32(&gur->rcwsr[7]); + +#ifdef CONFIG_SYS_DPAA_PME + switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { + case 1: + sysInfo->freqPME = freqCC_PLL[0]; + break; + case 2: + sysInfo->freqPME = freqCC_PLL[0] / 2; + break; + case 3: + sysInfo->freqPME = freqCC_PLL[0] / 3; + break; + case 4: + sysInfo->freqPME = freqCC_PLL[0] / 4; + break; + case 6: + sysInfo->freqPME = freqCC_PLL[1] / 2; + break; + case 7: + sysInfo->freqPME = freqCC_PLL[1] / 3; + break; + default: + printf("Error: Unknown PME clock select!\n"); + case 0: + sysInfo->freqPME = sysInfo->freqSystemBus / 2; + break; + + } +#endif +#ifdef CONFIG_SYS_DPAA_FMAN + switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { + case 1: + sysInfo->freqFMan[0] = freqCC_PLL[3]; + break; + case 2: + sysInfo->freqFMan[0] = freqCC_PLL[3] / 2; + break; + case 3: + sysInfo->freqFMan[0] = freqCC_PLL[3] / 3; + break; + case 4: + sysInfo->freqFMan[0] = freqCC_PLL[3] / 4; + break; + case 6: + sysInfo->freqFMan[0] = freqCC_PLL[4] / 2; + break; + case 7: + sysInfo->freqFMan[0] = freqCC_PLL[4] / 3; + break; + default: + printf("Error: Unknown FMan1 clock select!\n"); + case 0: + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + break; + } +#if (CONFIG_SYS_NUM_FMAN) == 2 +#define FM2_CLK_SEL 0x00000038 +#define FM2_CLK_SHIFT 3 + rcw_tmp = in_be32(&gur->rcwsr[15]); + switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { + case 1: + sysInfo->freqFMan[1] = freqCC_PLL[4]; + break; + case 2: + sysInfo->freqFMan[1] = freqCC_PLL[4] / 2; + break; + case 3: + sysInfo->freqFMan[1] = freqCC_PLL[4] / 3; + break; + case 4: + sysInfo->freqFMan[1] = freqCC_PLL[4] / 4; + break; + case 6: + sysInfo->freqFMan[1] = freqCC_PLL[3] / 2; + break; + case 7: + sysInfo->freqFMan[1] = freqCC_PLL[3] / 3; + break; + default: + printf("Error: Unknown FMan2 clock select!\n"); + case 0: + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + break; + } +#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CONFIG_SYS_DPAA_FMAN */ + +#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + + sysInfo->freqProcessor[cpu] = + freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; + } #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 @@ -159,11 +277,10 @@ void get_sys_info (sys_info_t * sysInfo) #endif #endif -#else - uint plat_ratio,e500_ratio,half_freqSystemBus; -#if defined(CONFIG_FSL_LBC) - uint lcrr_div; -#endif +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + +#else /* CONFIG_FSL_CORENET */ + uint plat_ratio, e500_ratio, half_freqSystemBus; int i; #ifdef CONFIG_QE __maybe_unused u32 qe_ratio; @@ -210,6 +327,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif /* CONFIG_FSL_CORENET */ #if defined(CONFIG_FSL_LBC) + uint lcrr_div; #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index d0824b36e5..f7240b0f08 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1899,34 +1899,38 @@ typedef struct ccsr_gur { #define rmuliodnr rio1maintliodnr typedef struct ccsr_clk { - u32 clkc0csr; /* Core 0 Clock control/status */ + u32 clkc0csr; /* 0x000 Core 0 Clock control/status */ u8 res1[0x1c]; - u32 clkc1csr; /* Core 1 Clock control/status */ + u32 clkc1csr; /* 0x020 Core 1 Clock control/status */ u8 res2[0x1c]; - u32 clkc2csr; /* Core 2 Clock control/status */ + u32 clkc2csr; /* 0x040 Core 2 Clock control/status */ u8 res3[0x1c]; - u32 clkc3csr; /* Core 3 Clock control/status */ + u32 clkc3csr; /* 0x060 Core 3 Clock control/status */ u8 res4[0x1c]; - u32 clkc4csr; /* Core 4 Clock control/status */ + u32 clkc4csr; /* 0x080 Core 4 Clock control/status */ u8 res5[0x1c]; - u32 clkc5csr; /* Core 5 Clock control/status */ + u32 clkc5csr; /* 0x0a0 Core 5 Clock control/status */ u8 res6[0x1c]; - u32 clkc6csr; /* Core 6 Clock control/status */ + u32 clkc6csr; /* 0x0c0 Core 6 Clock control/status */ u8 res7[0x1c]; - u32 clkc7csr; /* Core 7 Clock control/status */ + u32 clkc7csr; /* 0x0e0 Core 7 Clock control/status */ u8 res8[0x71c]; - u32 pllc1gsr; /* Cluster PLL 1 General Status */ + u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */ u8 res10[0x1c]; - u32 pllc2gsr; /* Cluster PLL 2 General Status */ + u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */ u8 res11[0x1c]; - u32 pllc3gsr; /* Cluster PLL 3 General Status */ + u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */ u8 res12[0x1c]; - u32 pllc4gsr; /* Cluster PLL 4 General Status */ - u8 res13[0x39c]; - u32 pllpgsr; /* Platform PLL General Status */ + u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */ + u8 res13[0x1c]; + u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */ u8 res14[0x1c]; - u32 plldgsr; /* DDR PLL General Status */ - u8 res15[0x3dc]; + u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */ + u8 res15[0x35c]; + u32 pllpgsr; /* 0xc00 Platform PLL General Status */ + u8 res16[0x1c]; + u32 plldgsr; /* 0xc20 DDR PLL General Status */ + u8 res17[0x3dc]; } ccsr_clk_t; #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 -- cgit v1.2.3 From f8f85b049cb22e4badcfbbf4842ee6d5297b0006 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:12 +0000 Subject: powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/immap_85xx.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index f7240b0f08..5e40f26072 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2415,12 +2415,13 @@ typedef struct serdes_corenet { #define SRDS_RSTCTL_RSTERR 0x20000000 #define SRDS_RSTCTL_SDPD 0x00000020 u32 pllcr0; /* PLL Control Register 0 */ -#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 -- cgit v1.2.3 From 92230d49da9fd51ed212d002ed7c6511eb700ce8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:13 +0000 Subject: powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/immap_85xx.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5e40f26072..005a045ab5 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2549,13 +2549,16 @@ typedef struct ccsr_sec { #endif typedef struct ccsr_qman { +#ifdef CONFIG_SYS_FSL_QMAN_V3 + u8 res0[0x200]; +#else struct { u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ u32 res; u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ } qcsp[32]; - +#endif /* Not actually reserved, but irrelevant to u-boot */ u8 res[0xbf8 - 0x200]; u32 ip_rev_1; @@ -2580,6 +2583,14 @@ typedef struct ccsr_qman { u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ u8 res7[0x2e8]; +#ifdef CONFIG_SYS_FSL_QMAN_V3 + struct { + u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ + u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ + u32 res; + u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ + } qcsp[50]; +#endif } ccsr_qman_t; typedef struct ccsr_bman { -- cgit v1.2.3 From fd3cebd020edad5fa18ff5a64cde3aa75aa896c8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:14 +0000 Subject: powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/immap_85xx.h | 98 +++++++++++++++++++++++++++++++++-- 1 file changed, 93 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 005a045ab5..cfd86bab4a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1757,13 +1757,30 @@ typedef struct ccsr_gur { u32 brrl; /* Boot release */ u8 res17[24]; u32 rcwsr[16]; /* Reset control word status */ -#ifndef CONFIG_SYS_FSL_QORIQ_CHASSIS2 -#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 -#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f -#else + +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#endif +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800 +#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 +#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 +#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 +#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 + +#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 @@ -1772,6 +1789,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 @@ -2407,6 +2426,74 @@ typedef struct ccsr_gur { #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#define MAX_SERDES 4 +typedef struct serdes_corenet { + struct { + u32 rstctl; /* Reset Control Register */ +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 +#define SRDS_RSTCTL_SWRST 0x10000000 +#define SRDS_RSTCTL_SDPD 0x00000020 + u32 pllcr0; /* PLL Control Register 0 */ +#define SRDS_PLLCR0_POFF 0x80000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 +#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 +#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 +#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 +#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 +#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 +#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 +#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 +#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 + u32 pllcr1; /* PLL Control Register 1 */ +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + u32 res_0c; /* 0x00c */ + u32 pllcr3; + u32 pllcr4; + u8 res_18[0x20-0x18]; + } bank[2]; + u8 res_40[0x90-0x40]; + u32 srdstcalcr; /* 0x90 TX Calibration Control */ + u8 res_94[0xa0-0x94]; + u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ + u8 res_a4[0xb0-0xa4]; + u32 srdsgr0; /* 0xb0 General Register 0 */ + u8 res_b4[0xe0-0xb4]; + u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ + u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ + u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ + u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ + u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ + u8 res_f4[0x100-0xf4]; + struct { + u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u8 res_104[0x120-0x104]; + } srdslnpssr[8]; + u8 res_200[0x800-0x200]; + struct { + u32 gcr0; /* 0x800 General Control Register 0 */ + u32 gcr1; /* 0x804 General Control Register 1 */ + u32 gcr2; /* 0x808 General Control Register 2 */ + u32 res_80c; + u32 recr0; /* 0x810 Receive Equalization Control */ + u32 res_814; + u32 tecr0; /* 0x818 Transmit Equalization Control */ + u32 res_81c; + u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ + u8 res_824[0x840-0x824]; + } lane[8]; /* Lane A, B, C, D, E, F, G, H */ + u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ +} serdes_corenet_t; + +#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + typedef struct serdes_corenet { struct { u32 rstctl; /* Reset Control Register */ @@ -2466,6 +2553,7 @@ typedef struct serdes_corenet { } lane[24]; u32 res6[384]; } serdes_corenet_t; +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ enum { FSL_SRDS_B1_LANE_A = 0, -- cgit v1.2.3 From d1001e3f0ce0059a55a870c42bac8aba2e4befec Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:15 +0000 Subject: powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shengzhou Liu Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/Makefile | 3 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 203 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h | 26 ++++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 8 - arch/powerpc/include/asm/config_mpc85xx.h | 4 + arch/powerpc/include/asm/fsl_serdes.h | 42 +++++ arch/powerpc/include/asm/immap_85xx.h | 4 + 7 files changed, 281 insertions(+), 9 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index aad50f34ac..c5982dbe01 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -85,7 +85,8 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o -COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o +COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o +COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o # SoC specific SERDES support COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c new file mode 100644 index 0000000000..01dcdf6bc1 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -0,0 +1,203 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "fsl_corenet2_serdes.h" + +static u64 serdes1_prtcl_map; +static u64 serdes2_prtcl_map; +#ifdef CONFIG_SYS_FSL_SRDS_3 +static u64 serdes3_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 +static u64 serdes4_prtcl_map; +#endif + +#ifdef DEBUG +static const char *serdes_prtcl_str[] = { + [NONE] = "NA", + [PCIE1] = "PCIE1", + [PCIE2] = "PCIE2", + [PCIE3] = "PCIE3", + [PCIE4] = "PCIE4", + [SATA1] = "SATA1", + [SATA2] = "SATA2", + [SRIO1] = "SRIO1", + [SRIO2] = "SRIO2", + [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", + [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", + [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", + [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", + [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", + [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6", + [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", + [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", + [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", + [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [XAUI_FM1] = "XAUI_FM1", + [XAUI_FM2] = "XAUI_FM2", + [AURORA] = "DEBUG", + [CPRI1] = "CPRI1", + [CPRI2] = "CPRI2", + [CPRI3] = "CPRI3", + [CPRI4] = "CPRI4", + [CPRI5] = "CPRI5", + [CPRI6] = "CPRI6", + [CPRI7] = "CPRI7", + [CPRI8] = "CPRI8", + [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9", + [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10", + [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9", + [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10", + [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9", + [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10", + [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9", + [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10", + [QSGMII_FM1_A] = "QSGMII_FM1_A", + [QSGMII_FM1_B] = "QSGMII_FM1_B", + [QSGMII_FM2_A] = "QSGMII_FM2_A", + [QSGMII_FM2_B] = "QSGMII_FM2_B", + [XFI_FM1_MAC9] = "XFI_FM1_MAC9", + [XFI_FM1_MAC10] = "XFI_FM1_MAC10", + [XFI_FM2_MAC9] = "XFI_FM2_MAC9", + [XFI_FM2_MAC10] = "XFI_FM2_MAC10", + [INTERLAKEN] = "INTERLAKEN", +}; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + u64 ret = 0; + + ret |= (1ULL << device) & serdes1_prtcl_map; + ret |= (1ULL << device) & serdes2_prtcl_map; +#ifdef CONFIG_SYS_FSL_SRDS_3 + ret |= (1ULL << device) & serdes3_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 + ret |= (1ULL << device) & serdes4_prtcl_map; +#endif + + return !!ret; +} + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device) +{ + const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 cfg = in_be32(&gur->rcwsr[4]); + int i; + + switch (sd) { + case FSL_SRDS_1: + cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + break; + case FSL_SRDS_2: + cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + break; +#ifdef CONFIG_SYS_FSL_SRDS_3 + case FSL_SRDS_3: + cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; + break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 + case FSL_SRDS_4: + cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; + break; +#endif + default: + printf("invalid SerDes%d\n", sd); + break; + } + /* Is serdes enabled at all? */ + if (unlikely(cfg == 0)) + return -ENODEV; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(sd, cfg, i) == device) + return i; + } + + return -ENODEV; +} + +u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u64 serdes_prtcl_map = 0; + u32 cfg; + int lane; + + cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; + /* Is serdes enabled at all? */ + if (!cfg) { + printf("SERDES%d is not enabled\n", sd + 1); + return 0; + } + + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg); + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + serdes_prtcl_map |= (1ULL << lane_prtcl); + } + + return serdes_prtcl_map; +} + +void fsl_serdes_init(void) +{ + + serdes1_prtcl_map = serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); + serdes2_prtcl_map = serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); +#ifdef CONFIG_SYS_FSL_SRDS_3 + serdes3_prtcl_map = serdes_init(FSL_SRDS_3, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 + serdes4_prtcl_map = serdes_init(FSL_SRDS_4, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); +#endif + +} diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h new file mode 100644 index 0000000000..2258f41888 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h @@ -0,0 +1,26 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_CORENET2_SERDES_H +#define __FSL_CORENET2_SERDES_H + +int is_serdes_prtcl_valid(int serdes, u32 prtcl); +int serdes_lane_enabled(int lane); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +#endif /* __FSL_CORENET2_SERDES_H */ diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index c82060dd33..3c551e9b4c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -22,14 +22,6 @@ #ifndef __FSL_CORENET_SERDES_H #define __FSL_CORENET_SERDES_H -/* - * Note: For P5040, the fourth SerDes bank is on SerDes2, but U-boot currently - * only supports one SerDes controller. For now, pretend that we have three - * banks and 18 lanes on the P5040. - */ -#define SRDS_MAX_LANES 18 -#define SRDS_MAX_BANK 3 - enum srds_bank { FSL_SRDS_BANK_1 = 0, FSL_SRDS_BANK_2 = 1, diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 636bd5f01d..a61d315be6 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -311,6 +311,7 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -341,6 +342,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P3041) +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -371,6 +373,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -411,6 +414,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 22525f1156..6cd7379c8f 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -37,11 +37,17 @@ enum srds_prtcl { SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM2_DTSEC5, + SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC10, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3, @@ -49,13 +55,49 @@ enum srds_prtcl { XAUI_FM1, XAUI_FM2, AURORA, + CPRI1, + CPRI2, + CPRI3, + CPRI4, + CPRI5, + CPRI6, + CPRI7, + CPRI8, + XAUI_FM1_MAC9, + XAUI_FM1_MAC10, + XAUI_FM2_MAC9, + XAUI_FM2_MAC10, + HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, + HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, + QSGMII_FM1_A, /* A indicates MACs 1-4 */ + QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ + QSGMII_FM2_A, + QSGMII_FM2_B, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + XFI_FM2_MAC9, + XFI_FM2_MAC10, + INTERLAKEN, +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, + FSL_SRDS_3 = 2, + FSL_SRDS_4 = 3, }; int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); #ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +#else int serdes_get_first_lane(enum srds_prtcl device); +#endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 void serdes_reset_rx(enum srds_prtcl device); #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index cfd86bab4a..b1d7e3dfff 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2428,6 +2428,8 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define MAX_SERDES 4 +#define SRDS_MAX_LANES 8 +#define SRDS_MAX_BANK 2 typedef struct serdes_corenet { struct { u32 rstctl; /* Reset Control Register */ @@ -2494,6 +2496,8 @@ typedef struct serdes_corenet { #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#define SRDS_MAX_LANES 18 +#define SRDS_MAX_BANK 3 typedef struct serdes_corenet { struct { u32 rstctl; /* Reset Control Register */ -- cgit v1.2.3 From 379c5145ef8f3adbcfeb0a47503838627959cb67 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:16 +0000 Subject: powerpc/corenet2: fix mismatch DDR sync bit from RCW Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only async mode is supported. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 40cce1dbda..f493483c1e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -60,7 +60,8 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_DDR_CLK_FREQ) || \ + (defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ @@ -68,8 +69,13 @@ int checkcpu (void) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else #ifdef CONFIG_FSL_CORENET - u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + u32 ddr_sync ; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + ddr_sync = 0; /* only async mode is supported */ +#else + ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ -- cgit v1.2.3 From aa42cb71fa28a4f2c8b8cc0e691151f4ba19dbd9 Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Mon, 8 Oct 2012 07:44:17 +0000 Subject: board/freescale/common: VSC3316/VSC3308 initialization code Add code for configuring VSC3316/3308 crosspoint switches Add README to understand the APIs - VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch capable of data rates upto 11.5Gbps. VSC3316 has 16 input and 16 output ports whereas VSC3308 has 8 input and 8 output ports. Programming of these devices are performed by two-wire or four-wire serial interface. Signed-off-by: Shaveta Leekha Signed-off-by: Andy Fleming --- board/freescale/common/Makefile | 1 + board/freescale/common/vsc3316_3308.c | 184 ++++++++++++++++++++++++++++++++++ board/freescale/common/vsc3316_3308.h | 34 +++++++ doc/README.VSC3316-3308 | 43 ++++++++ 4 files changed, 262 insertions(+) create mode 100644 board/freescale/common/vsc3316_3308.c create mode 100644 board/freescale/common/vsc3316_3308.h create mode 100644 doc/README.VSC3316-3308 diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 54cb098a91..36f7c4f30f 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o +COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o # deal with common files for P-series corenet based devices SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c new file mode 100644 index 0000000000..786856597f --- /dev/null +++ b/board/freescale/common/vsc3316_3308.c @@ -0,0 +1,184 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "vsc3316_3308.h" + +#define REVISION_ID_REG 0x7E +#define INTERFACE_MODE_REG 0x79 +#define CURRENT_PAGE_REGISTER 0x7F +#define CONNECTION_CONFIG_PAGE 0x00 +#define INPUT_STATE_REG 0x13 +#define GLOBAL_INPUT_ISE1 0x51 +#define GLOBAL_INPUT_ISE2 0x52 +#define GLOBAL_INPUT_LOS 0x55 +#define GLOBAL_CORE_CNTRL 0x5D +#define OUTPUT_MODE_PAGE 0x23 +#define CORE_CONTROL_PAGE 0x25 +#define CORE_CONFIG_REG 0x75 + +int vsc_if_enable(unsigned int vsc_addr) +{ + u8 data; + + debug("VSC:Configuring VSC at I2C address 0x%2x" + " for 2-wire interface\n", vsc_addr); + + /* enable 2-wire Serial InterFace (I2C) */ + data = 0x02; + return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); +} + +int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con) +{ + unsigned int i; + u8 rev_id = 0; + int ret; + + debug("VSC:Initializing VSC3316 at I2C address 0x%2x" + " for Tx\n", vsc_addr); + + ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Configuring the required input of the switch */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][0], 0x80); + + /* Setting Global Input LOS threshold value */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); + + vsc_wp_config(vsc_addr); + + return 0; +} + +int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con) +{ + unsigned int i; + u8 rev_id = 0; + int ret; + + debug("VSC:Initializing VSC3308 at I2C address 0x%x" + " for Tx\n", vsc_addr); + + ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); + + /*Configure Global Input ISE and gain */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12); + i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12); + + /* input state - page 0x13 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning ON the required input of the switch */ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][0], 0); + + /* Setting Global Input LOS threshold value */ + i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + i2c_reg_write(vsc_addr, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); + + vsc_wp_config(vsc_addr); + + return 0; +} + +void vsc_wp_config(unsigned int vsc_addr) +{ + debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr); + + /* For new crosspoint configuration to occur, WP bit of + * CORE_CONFIG_REG should be set 1 and then reset to 0 */ + i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); + i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); +} diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h new file mode 100644 index 0000000000..effd66dce4 --- /dev/null +++ b/board/freescale/common/vsc3316_3308.h @@ -0,0 +1,34 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VSC_CROSSBAR_H_ +#define __VSC_CROSSBAR_H 1_ + +#include +#include +#include + +int vsc_if_enable(unsigned int vsc_addr); +int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +void vsc_wp_config(unsigned int vsc_addr); + +#endif /* __VSC_CROSSBAR_H_ */ diff --git a/doc/README.VSC3316-3308 b/doc/README.VSC3316-3308 new file mode 100644 index 0000000000..925663ba50 --- /dev/null +++ b/doc/README.VSC3316-3308 @@ -0,0 +1,43 @@ +This file contains API information of the initialization code written for +Vitesse cross-point devices, VSC3316 and VSC3308 for board B4860QDS + +Author: Shaveta Leekha + +About Device: +============= +VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch capable of data rates upto 11.5Gbps. + +VSC3316 has 16 input and 16 output ports whereas VSC3308 has 8 input and 8 output ports. Programming of these devices are performed by two-wire or four-wire serial interface. + +Initialization: +=============== +On reset, VSC devices are in low-power state with all inputs, outputs and connections in an off state. +First thing required is to program it to interface with either two-wire or four-wire interface. +In our case the interface is two-wire I2C serial interface. So the value in Interface mode register at address 79.h to be written is 0x02 for two-wire interface. Also for crosspoint connections to be activated, 01.h value need to be written in 75.h (core configuration register). + +API Overview: +============= + + vsc_if_enable(u8 vsc_addr): + -------------------------- + This API programs VSC to interface with either two-wire or four-wire interface. In our case the interface is two-wire I2C serial interface. So the value in Interface mode register at address 79.h to be written is 0x02 for two-wire interface. + Parameters: + vsc_addr - Address of the VSC device on board. + + + vsc3316_config(u8 vsc_addr, int con_arr[][2], u8 num_con): + --------------------------------------------------------- + This API configures the VSC3316 device for required connections. Connection through the VSC device requires the inputs and outputs to be properly configured. + Connection registers are on page 00. It Configures the selected input and output correctly and join them to make a connection. It also program Input state register, Global input ISE, Global input LOS, Global core control, Output mode register and core control registers etc. + vsc3308_config(u8 vsc_addr, int con_arr[][2], u8 num_con) does the essential configurations for VSC3308. + + Parameters: + vsc_addr - Address of the VSC device on board. + con_arr - connection array + num_con - number of connections to be configured + + vsc_wp_config(u8 vsc_addr): + -------------------------- + For crosspoint connections to be activated, 01.h value need to be written in 75.h (core configuration register), which is done by this API. + Parameters: + vsc_addr - Address of the VSC device on board. -- cgit v1.2.3 From f311838ded0c4b08726e5a363d518babc2109493 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 8 Oct 2012 07:44:18 +0000 Subject: powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/fsl_liodn.h | 6 +++++ arch/powerpc/include/asm/fsl_portals.h | 3 +++ arch/powerpc/include/asm/immap_85xx.h | 41 ++++++++++++++++++++++++++++++++-- 3 files changed, 48 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index e591e67de6..d759de975e 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -123,6 +123,12 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_FSL_CORENET_PME_OFFSET, \ CONFIG_SYS_FSL_CORENET_PME_OFFSET) +#define SET_PMAN_LIODN(num, liodn) \ + SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \ + offsetof(struct ccsr_pman, ppa1) + \ + CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \ + CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET) + /* -1 from portID due to how immap has the registers */ #define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \ CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index 9a764d2533..b75f5b975a 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -39,6 +39,9 @@ enum fsl_dpaa_dev { #ifdef CONFIG_SYS_DPAA_RMAN FSL_HW_PORTAL_RMAN, #endif +#ifdef CONFIG_SYS_DPAA_DCE + FSL_HW_PORTAL_DCE, +#endif }; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b1d7e3dfff..51f02fcb3d 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2600,8 +2600,8 @@ typedef struct ccsr_sec { struct { u32 ms; /* DECO LIODN Register, MS */ u32 ls; /* DECO LIODN Register, LS */ - } decoliodnr[5]; - u8 res4[0x58]; + } decoliodnr[8]; + u8 res4[0x40]; u32 dar; /* DECO Avail Register */ u32 drr; /* DECO Reset Register */ u8 res5[0xe78]; @@ -2746,8 +2746,41 @@ struct ccsr_rman { }; #endif +#ifdef CONFIG_SYS_PMAN +struct ccsr_pman { + u8 res_00[0x40]; + u32 poes1; /* PMAN Operation Error Status Register 1 */ + u32 poes2; /* PMAN Operation Error Status Register 2 */ + u32 poeah; /* PMAN Operation Error Address High */ + u32 poeal; /* PMAN Operation Error Address Low */ + u8 res_50[0x50]; + u32 pr1; /* PMAN Revision Register 1 */ + u32 pr2; /* PMAN Revision Register 2 */ + u8 res_a8[0x8]; + u32 pcap; /* PMAN Capabilities Register */ + u8 res_b4[0xc]; + u32 pc1; /* PMAN Control Register 1 */ + u32 pc2; /* PMAN Control Register 2 */ + u32 pc3; /* PMAN Control Register 3 */ + u32 pc4; /* PMAN Control Register 4 */ + u32 pc5; /* PMAN Control Register 5 */ + u32 pc6; /* PMAN Control Register 6 */ + u8 res_d8[0x8]; + u32 ppa1; /* PMAN Prefetch Attributes Register 1 */ + u32 ppa2; /* PMAN Prefetch Attributes Register 2 */ + u8 res_e8[0x8]; + u32 pics; /* PMAN Interrupt Control and Status */ + u8 res_f4[0xf0c]; +}; +#endif + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 +#ifdef CONFIG_SYS_PMAN +#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 +#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 +#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 +#endif #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 #define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000 @@ -2787,7 +2820,9 @@ struct ccsr_rman { #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 +#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 +#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 @@ -2795,7 +2830,9 @@ struct ccsr_rman { #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 +#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 +#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 #else #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 -- cgit v1.2.3 From 9e758758491b0d7a71bdf1db8cd860b599d7e657 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:19 +0000 Subject: powerpc/mpc85xx: Add T4240 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming Signed-off-by: Roy Zang Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shengzhou Liu Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/Makefile | 3 + arch/powerpc/cpu/mpc85xx/t4240_ids.c | 203 +++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 237 ++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/cpu/mpc8xxx/srio.c | 21 ++- arch/powerpc/include/asm/config_mpc85xx.h | 28 ++++ arch/powerpc/include/asm/immap_85xx.h | 87 ++++++++++- arch/powerpc/include/asm/processor.h | 2 + drivers/net/fm/Makefile | 1 + drivers/net/fm/init.c | 18 +++ drivers/net/fm/t4240.c | 128 ++++++++++++++++ drivers/pci/fsl_pci_init.c | 25 +++- include/fm_eth.h | 8 + 13 files changed, 751 insertions(+), 12 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/t4240_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/t4240_serdes.c create mode 100644 drivers/net/fm/t4240.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index c5982dbe01..5440809e9c 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -67,6 +67,7 @@ COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o +COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o @@ -82,6 +83,7 @@ COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o +COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o @@ -114,6 +116,7 @@ COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o +COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o COBJS = $(COBJS-y) COBJS += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c new file mode 100644 index 0000000000..a8f16b1cd6 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -0,0 +1,203 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 4), + SET_QP_INFO(10, 36, 1, 4), + SET_QP_INFO(11, 37, 1, 5), + SET_QP_INFO(12, 38, 1, 5), + SET_QP_INFO(13, 39, 1, 6), + SET_QP_INFO(14, 40, 1, 6), + SET_QP_INFO(15, 41, 1, 7), + SET_QP_INFO(16, 42, 1, 7), + SET_QP_INFO(17, 43, 1, 8), + SET_QP_INFO(18, 44, 1, 8), + SET_QP_INFO(19, 45, 1, 9), + SET_QP_INFO(20, 46, 1, 9), + SET_QP_INFO(21, 47, 1, 10), + SET_QP_INFO(22, 48, 1, 10), + SET_QP_INFO(23, 49, 1, 11), + SET_QP_INFO(24, 50, 1, 11), + SET_QP_INFO(65, 89, 1, 0), + SET_QP_INFO(66, 90, 1, 0), + SET_QP_INFO(67, 91, 1, 1), + SET_QP_INFO(68, 92, 1, 1), + SET_QP_INFO(69, 93, 1, 2), + SET_QP_INFO(70, 94, 1, 2), + SET_QP_INFO(71, 95, 1, 3), + SET_QP_INFO(72, 96, 1, 3), + SET_QP_INFO(73, 97, 1, 4), + SET_QP_INFO(74, 98, 1, 4), + SET_QP_INFO(75, 99, 1, 5), + SET_QP_INFO(76, 100, 1, 5), + SET_QP_INFO(77, 101, 1, 6), + SET_QP_INFO(78, 102, 1, 6), + SET_QP_INFO(79, 103, 1, 7), + SET_QP_INFO(80, 104, 1, 7), + SET_QP_INFO(81, 105, 1, 8), + SET_QP_INFO(82, 106, 1, 8), + SET_QP_INFO(83, 107, 1, 9), + SET_QP_INFO(84, 108, 1, 9), + SET_QP_INFO(85, 109, 1, 10), + SET_QP_INFO(86, 110, 1, 10), + SET_QP_INFO(87, 111, 1, 11), + SET_QP_INFO(88, 112, 1, 11), + SET_QP_INFO(25, 51, 1, 0), + SET_QP_INFO(26, 52, 1, 0), +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_1(1, 307), + SET_SRIO_LIODN_1(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + +#ifdef CONFIG_SYS_PMAN + SET_PMAN_LIODN(1, 513), + SET_PMAN_LIODN(2, 514), + SET_PMAN_LIODN(3, 515), +#endif + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 88), + SET_FMAN_RX_1G_LIODN(2, 1, 89), + SET_FMAN_RX_1G_LIODN(2, 2, 90), + SET_FMAN_RX_1G_LIODN(2, 3, 91), + SET_FMAN_RX_1G_LIODN(2, 4, 92), + SET_FMAN_RX_1G_LIODN(2, 5, 93), + SET_FMAN_RX_10G_LIODN(2, 0, 94), + SET_FMAN_RX_10G_LIODN(2, 1, 95), +}; +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 678), + SET_RMAN_LIODN(1, 679), + SET_RMAN_LIODN(2, 680), + SET_RMAN_LIODN(3, 681), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { +#ifdef CONFIG_SYS_DPAA_DCE + [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), +#endif + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069), +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c new file mode 100644 index 0000000000..102defa560 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -0,0 +1,237 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {38, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC10, XAUI_FM2_MAC10, + XAUI_FM2_MAC10, XAUI_FM2_MAC10}}, + {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {38, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {57, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {} +}; +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, + {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, + {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, + {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, + {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2}}, + {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2}}, + {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {} +}; +static struct serdes_config serdes4_cfg_tbl[] = { + /* SerDes 4 */ + {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, + {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, + {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}}, + {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}}, + {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, + {} +}; +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, + serdes4_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index fb78784345..4d96d1b107 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -75,6 +75,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P5020, P5020, 2), CPU_TYPE_ENTRY(P5021, P5021, 2), CPU_TYPE_ENTRY(P5040, P5040, 4), + CPU_TYPE_ENTRY(T4240, T4240, 0), + CPU_TYPE_ENTRY(T4120, T4120, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), #elif defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e7ff59a1ca..d4f8ecee9b 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -34,8 +34,13 @@ #define SRIO_LCSBA1CSR 0x60000000 #if defined(CONFIG_FSL_CORENET) +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1 + #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2 +#else #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 +#endif #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC85xx) @@ -236,7 +241,13 @@ void srio_init(void) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; int srio1_used = 0, srio2_used = 0; + u32 *devdisr; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + devdisr = &gur->devdisr3; +#else + devdisr = &gur->devdisr; +#endif if (is_serdes_configured(SRIO1)) { set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), @@ -273,16 +284,16 @@ void srio_init(void) #ifdef CONFIG_FSL_CORENET /* On FSL_CORENET devices we can disable individual ports */ if (!srio1_used) - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); + setbits_be32(devdisr, _DEVDISR_SRIO1); if (!srio2_used) - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); + setbits_be32(devdisr, _DEVDISR_SRIO2); #endif /* neither port is used - disable everything */ if (!srio1_used && !srio2_used) { - setbits_be32(&gur->devdisr, _DEVDISR_SRIO1); - setbits_be32(&gur->devdisr, _DEVDISR_SRIO2); - setbits_be32(&gur->devdisr, _DEVDISR_RMU); + setbits_be32(devdisr, _DEVDISR_SRIO1); + setbits_be32(devdisr, _DEVDISR_SRIO2); + setbits_be32(devdisr, _DEVDISR_RMU); } } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index a61d315be6..cfa5448b5e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -482,6 +482,34 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#elif defined(CONFIG_PPC_T4240) +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_MAX_CPUS 12 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SRDS_3 +#define CONFIG_SYS_FSL_SRDS_4 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 +#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 51f02fcb3d..5001f6eba2 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1689,6 +1689,72 @@ typedef struct ccsr_gur { u32 alt_pmuxcr; /* Alt function signal multiplex control */ u8 res6[12]; u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + u32 devdisr5; /* Device disable control 5 */ +#define FSL_CORENET_DEVDISR_PBL 0x80000000 +#define FSL_CORENET_DEVDISR_PMAN 0x40000000 +#define FSL_CORENET_DEVDISR_ESDHC 0x20000000 +#define FSL_CORENET_DEVDISR_DMA1 0x00800000 +#define FSL_CORENET_DEVDISR_DMA2 0x00400000 +#define FSL_CORENET_DEVDISR_USB1 0x00080000 +#define FSL_CORENET_DEVDISR_USB2 0x00040000 +#define FSL_CORENET_DEVDISR_SATA1 0x00008000 +#define FSL_CORENET_DEVDISR_SATA2 0x00004000 +#define FSL_CORENET_DEVDISR_PME 0x00000800 +#define FSL_CORENET_DEVDISR_SEC 0x00000200 +#define FSL_CORENET_DEVDISR_RMU 0x00000080 +#define FSL_CORENET_DEVDISR_DCE 0x00000040 +#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 +#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 +#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 +#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 +#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 +#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 +#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 +#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000 +#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000 +#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000 +#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800 +#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400 +#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800 +#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 +#define FSL_CORENET_DEVDISR2_FM1 0x00000080 +#define FSL_CORENET_DEVDISR2_FM2 0x00000040 +#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 +#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 +#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 +#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000 +#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000 +#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000 +#define FSL_CORENET_DEVDISR3_QMAN 0x00080000 +#define FSL_CORENET_DEVDISR3_BMAN 0x00040000 +#define FSL_CORENET_DEVDISR3_LA1 0x00008000 +#define FSL_CORENET_DEVDISR4_I2C1 0x80000000 +#define FSL_CORENET_DEVDISR4_I2C2 0x40000000 +#define FSL_CORENET_DEVDISR4_DUART1 0x20000000 +#define FSL_CORENET_DEVDISR4_DUART2 0x10000000 +#define FSL_CORENET_DEVDISR4_ESPI 0x08000000 +#define FSL_CORENET_DEVDISR5_DDR1 0x80000000 +#define FSL_CORENET_DEVDISR5_DDR2 0x40000000 +#define FSL_CORENET_DEVDISR5_DDR3 0x20000000 +#define FSL_CORENET_DEVDISR5_CPC1 0x08000000 +#define FSL_CORENET_DEVDISR5_CPC2 0x04000000 +#define FSL_CORENET_DEVDISR5_CPC3 0x02000000 +#define FSL_CORENET_DEVDISR5_IFC 0x00800000 +#define FSL_CORENET_DEVDISR5_GPIO 0x00400000 +#define FSL_CORENET_DEVDISR5_DBG 0x00200000 +#define FSL_CORENET_DEVDISR5_NAL 0x00100000 +#define FSL_CORENET_NUM_DEVDISR 5 +#else #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 @@ -1714,7 +1780,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_I2C2 0x00000010 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 - u32 devdisr2; /* Device disable control 2 */ #define FSL_CORENET_DEVDISR2_PME 0x80000000 #define FSL_CORENET_DEVDISR2_SEC 0x40000000 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 @@ -1733,8 +1798,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 #define FSL_CORENET_NUM_DEVDISR 2 - u8 res7[8]; u32 powmgtcsr; /* Power management status & control */ +#endif u8 res8[12]; u32 coredisru; /* uppper portion for support of 64 cores */ u32 coredisrl; /* lower portion for support of 64 cores */ @@ -1761,6 +1826,7 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#if defined(CONFIG_PPC_T4240) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1769,6 +1835,7 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 +#endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000 @@ -1821,6 +1888,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 +#endif +#if defined(CONFIG_PPC_T4240) +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ @@ -2798,10 +2874,17 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 +#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 +#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 +#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 +#else #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 +#endif #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fd0160a2d1..5bc0da6df1 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1097,6 +1097,8 @@ #define SVR_P5020 0x822000 #define SVR_P5021 0X820500 #define SVR_P5040 0x820400 +#define SVR_T4240 0x824000 +#define SVR_T4120 0x824001 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index cc57354755..73f64ad45a 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_PPC_P2041) += p5020.o COBJS-$(CONFIG_PPC_P3041) += p5020.o COBJS-$(CONFIG_PPC_P4080) += p4080.o COBJS-$(CONFIG_PPC_P5020) += p5020.o +COBJS-$(CONFIG_PPC_T4240) += t4240.o endif COBJS := $(COBJS-y) diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 736b8b9582..ae389b8842 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -38,6 +38,15 @@ struct fm_eth_info fm_info[] = { #if (CONFIG_SYS_NUM_FM1_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(1, 5), #endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6) + FM_DTSEC_INFO_INITIALIZER(1, 6), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7) + FM_DTSEC_INFO_INITIALIZER(1, 9), +#endif +#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8) + FM_DTSEC_INFO_INITIALIZER(1, 10), +#endif #if (CONFIG_SYS_NUM_FM2_DTSEC >= 1) FM_DTSEC_INFO_INITIALIZER(2, 1), #endif @@ -53,6 +62,15 @@ struct fm_eth_info fm_info[] = { #if (CONFIG_SYS_NUM_FM2_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(2, 5), #endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6) + FM_DTSEC_INFO_INITIALIZER(2, 6), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7) + FM_DTSEC_INFO_INITIALIZER(2, 9), +#endif +#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8) + FM_DTSEC_INFO_INITIALIZER(2, 10), +#endif #if (CONFIG_SYS_NUM_FM1_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(1, 1), #endif diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c new file mode 100644 index 0000000000..48c530c915 --- /dev/null +++ b/drivers/net/fm/t4240.c @@ -0,0 +1,128 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, + [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, + [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, + [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, + [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, + [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, + [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6, + [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9, + [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10, + [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1, + [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1 || port == FM1_10GEC2) + && (is_serdes_configured(XAUI_FM1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM2_10GEC1 || port == FM2_10GEC2) + && (is_serdes_configured(XAUI_FM2))) + return PHY_INTERFACE_MODE_XGMII; + +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 + /* handle RGMII first */ + if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + case FM2_DTSEC5: + case FM2_DTSEC6: + case FM2_DTSEC9: + case FM2_DTSEC10: + if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 86ccbe7ee8..e8eb9d6db7 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -666,10 +666,17 @@ int fsl_configure_pcie(struct fsl_pci_info *info, } #if defined(CONFIG_FSL_CORENET) +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1 + #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2 + #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3 + #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4 +#else #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 +#endif #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC85xx) #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE @@ -749,34 +756,42 @@ int fsl_pcie_init_board(int busno) { struct fsl_pci_info pci_info; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; - u32 devdisr = in_be32(&gur->devdisr); + u32 devdisr; + u32 *addr; + +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + addr = &gur->devdisr3; +#else + addr = &gur->devdisr; +#endif + devdisr = in_be32(addr); #ifdef CONFIG_PCIE1 SET_STD_PCIE_INFO(pci_info, 1); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE1); /* disable */ #endif #ifdef CONFIG_PCIE2 SET_STD_PCIE_INFO(pci_info, 2); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE3 SET_STD_PCIE_INFO(pci_info, 3); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE4 SET_STD_PCIE_INFO(pci_info, 4); busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); #else - setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ + setbits_be32(addr, _DEVDISR_PCIE4); /* disable */ #endif return busno; diff --git a/include/fm_eth.h b/include/fm_eth.h index e56541df1b..5d80e4962e 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -30,13 +30,21 @@ enum fm_port { FM1_DTSEC3, FM1_DTSEC4, FM1_DTSEC5, + FM1_DTSEC6, + FM1_DTSEC9, + FM1_DTSEC10, FM1_10GEC1, + FM1_10GEC2, FM2_DTSEC1, FM2_DTSEC2, FM2_DTSEC3, FM2_DTSEC4, FM2_DTSEC5, + FM2_DTSEC6, + FM2_DTSEC9, + FM2_DTSEC10, FM2_10GEC1, + FM2_10GEC2, NUM_FM_PORTS, }; -- cgit v1.2.3 From d2404141f9cb45a01da3297bb873510799351a60 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:20 +0000 Subject: powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/Makefile | 3 + arch/powerpc/cpu/mpc85xx/b4860_ids.c | 141 ++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 162 ++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 7 ++ arch/powerpc/include/asm/config_mpc85xx.h | 23 +++++ arch/powerpc/include/asm/immap_85xx.h | 10 ++ arch/powerpc/include/asm/processor.h | 7 ++ drivers/net/fm/Makefile | 1 + 8 files changed, 354 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/b4860_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/b4860_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 5440809e9c..78c412d9f3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -68,6 +68,7 @@ COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o +COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o @@ -84,6 +85,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o +COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o @@ -117,6 +119,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o +COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o COBJS = $(COBJS-y) COBJS += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c new file mode 100644 index 0000000000..7d33731a7b --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -0,0 +1,141 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), + SET_QP_INFO(11, 37, 1, 1), + SET_QP_INFO(12, 38, 1, 1), + SET_QP_INFO(13, 39, 1, 2), + SET_QP_INFO(14, 40, 1, 2), + SET_QP_INFO(15, 41, 1, 3), + SET_QP_INFO(16, 42, 1, 3), + SET_QP_INFO(17, 43, 1, 0), + SET_QP_INFO(18, 44, 1, 0), + SET_QP_INFO(19, 45, 1, 1), + SET_QP_INFO(20, 46, 1, 1), + SET_QP_INFO(21, 47, 1, 2), + SET_QP_INFO(22, 48, 1, 2), + SET_QP_INFO(23, 49, 1, 3), + SET_QP_INFO(24, 50, 1, 3), + SET_QP_INFO(25, 51, 1, 0), +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_1(1, 307), + SET_SRIO_LIODN_1(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 678), + SET_RMAN_LIODN(1, 679), + SET_RMAN_LIODN(2, 680), + SET_RMAN_LIODN(3, 681), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c new file mode 100644 index 0000000000..9990202f42 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -0,0 +1,162 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x30, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x32, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x33, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x34, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, + SRIO1, SRIO1}}, + {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0x9A, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {} +}; +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 4d96d1b107..2c487cac20 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -77,6 +77,13 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P5040, P5040, 4), CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), + CPU_TYPE_ENTRY(B4860, B4860, 0), + CPU_TYPE_ENTRY(G4860, G4860, 0), + CPU_TYPE_ENTRY(G4060, G4060, 0), + CPU_TYPE_ENTRY(B4440, B4440, 0), + CPU_TYPE_ENTRY(G4440, G4440, 0), + CPU_TYPE_ENTRY(B4420, B4420, 0), + CPU_TYPE_ENTRY(B4220, B4220, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), #elif defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index cfa5448b5e..5e1d2e90f7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -510,6 +510,29 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#elif defined(CONFIG_PPC_B4860) +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_A_004934 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5001f6eba2..969f726c36 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1729,6 +1729,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 #define FSL_CORENET_DEVDISR2_FM1 0x00000080 #define FSL_CORENET_DEVDISR2_FM2 0x00000040 +#define FSL_CORENET_DEVDISR2_CPRI 0x00000008 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 @@ -1738,6 +1739,9 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR3_QMAN 0x00080000 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000 #define FSL_CORENET_DEVDISR3_LA1 0x00008000 +#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800 +#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400 +#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000 @@ -1753,6 +1757,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR5_GPIO 0x00400000 #define FSL_CORENET_DEVDISR5_DBG 0x00200000 #define FSL_CORENET_DEVDISR5_NAL 0x00100000 +#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000 #define FSL_CORENET_NUM_DEVDISR 5 #else #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 @@ -1835,6 +1840,11 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 +#elif defined(CONFIG_PPC_B4860) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 5bc0da6df1..7aa3231ad4 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1099,6 +1099,13 @@ #define SVR_P5040 0x820400 #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 +#define SVR_B4860 0X868000 +#define SVR_G4860 0x868001 +#define SVR_G4060 0x868003 +#define SVR_B4440 0x868100 +#define SVR_G4440 0x868101 +#define SVR_B4420 0x868102 +#define SVR_B4220 0x868103 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 73f64ad45a..4642c54ece 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -41,6 +41,7 @@ COBJS-$(CONFIG_PPC_P3041) += p5020.o COBJS-$(CONFIG_PPC_P4080) += p4080.o COBJS-$(CONFIG_PPC_P5020) += p5020.o COBJS-$(CONFIG_PPC_T4240) += t4240.o +COBJS-$(CONFIG_PPC_B4860) += b4860.o endif COBJS := $(COBJS-y) -- cgit v1.2.3 From 111fd19e3b9eb1005fd24ef09c163dd10103f5fa Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Mon, 8 Oct 2012 07:44:21 +0000 Subject: fm/mEMAC: add mEMAC frame work The multirate ethernet media access controller (mEMAC) interfaces to 10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface. Signed-off-by: Sandeep Singh Signed-off-by: Poonam Aggrwal Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/config_mpc85xx.h | 2 + arch/powerpc/include/asm/fsl_fman.h | 17 ++ arch/powerpc/include/asm/fsl_memac.h | 271 ++++++++++++++++++++++++++++++ drivers/net/fm/Makefile | 4 + drivers/net/fm/eth.c | 39 ++++- drivers/net/fm/memac.c | 132 +++++++++++++++ drivers/net/fm/memac_phy.c | 150 +++++++++++++++++ include/fm_eth.h | 45 ++++- include/fsl_mdio.h | 6 +- 9 files changed, 661 insertions(+), 5 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_memac.h create mode 100644 drivers/net/fm/memac.c create mode 100644 drivers/net/fm/memac_phy.c diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 5e1d2e90f7..c63f9e500a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -499,6 +499,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" @@ -523,6 +524,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h index 2c0c9bc2f2..299daca132 100644 --- a/arch/powerpc/include/asm/fsl_fman.h +++ b/arch/powerpc/include/asm/fsl_fman.h @@ -423,6 +423,14 @@ typedef struct fm_10gec_mdio { u8 res[4*1024]; } fm_10gec_mdio_t; +typedef struct fm_memac { + u8 res[4*1024]; +} fm_memac_t; + +typedef struct fm_memac_mdio { + u8 res[4*1024]; +} fm_memac_mdio_t; + typedef struct fm_1588 { u8 res[4*1024]; } fm_1588_t; @@ -446,6 +454,14 @@ typedef struct ccsr_fman { u8 res1[8*1024]; fm_soft_parser_t fm_soft_parser; u8 res2[96*1024]; +#ifdef CONFIG_SYS_FMAN_V3 + struct { + fm_memac_t fm_memac; + fm_memac_mdio_t fm_memac_mdio; + } memac[10]; + u8 res4[32*1024]; + fm_memac_mdio_t fm_dedicated_mdio[2]; +#else struct { fm_dtsec_t fm_dtesc; fm_mdio_t fm_mdio; @@ -455,6 +471,7 @@ typedef struct ccsr_fman { fm_10gec_mdio_t fm_10gec_mdio; } mac_10g[1]; u8 res4[48*1024]; +#endif fm_1588_t fm_1588; u8 res5[4*1024]; } ccsr_fman_t; diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h new file mode 100644 index 0000000000..d6b60e65bc --- /dev/null +++ b/arch/powerpc/include/asm/fsl_memac.h @@ -0,0 +1,271 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MEMAC_H__ +#define __MEMAC_H__ + +#include + +struct memac { + /* memac general control and status registers */ + u32 res_0[2]; + u32 command_config; /* Control and configuration register */ + u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ + u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ + u32 maxfrm; /* Maximum frame length register */ + u32 res_18[5]; + u32 hashtable_ctrl; /* Hash table control register */ + u32 res_30[4]; + u32 ievent; /* Interrupt event register */ + u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ + u32 res_48; + u32 imask; /* interrupt mask register */ + u32 res_50; + u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */ + u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */ + u32 rx_pause_status; /* Receive pause status register */ + u32 res_78[2]; + u32 mac_addr[14]; /* MAC address */ + u32 lpwake_timer; /* EEE low power wakeup timer register */ + u32 sleep_timer; /* Transmit EEE Low Power Timer register */ + u32 res_c0[8]; + u32 statn_config; /* Statistics configuration register */ + u32 res_e4[7]; + + /* memac statistics counter registers */ + u32 rx_eoct_l; /* Rx ethernet octests lower */ + u32 rx_eoct_u; /* Rx ethernet octests upper */ + u32 rx_oct_l; /* Rx octests lower */ + u32 rx_oct_u; /* Rx octests upper */ + u32 rx_align_err_l; /* Rx alignment error lower */ + u32 rx_align_err_u; /* Rx alignment error upper */ + u32 rx_pause_frame_l; /* Rx valid pause frame upper */ + u32 rx_pause_frame_u; /* Rx valid pause frame upper */ + u32 rx_frame_l; /* Rx frame counter lower */ + u32 rx_frame_u; /* Rx frame counter upper */ + u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ + u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ + u32 rx_vlan_l; /* Rx VLAN frame lower */ + u32 rx_vlan_u; /* Rx VLAN frame upper */ + u32 rx_err_l; /* Rx frame error lower */ + u32 rx_err_u; /* Rx frame error upper */ + u32 rx_uni_l; /* Rx unicast frame lower */ + u32 rx_uni_u; /* Rx unicast frame upper */ + u32 rx_multi_l; /* Rx multicast frame lower */ + u32 rx_multi_u; /* Rx multicast frame upper */ + u32 rx_brd_l; /* Rx broadcast frame lower */ + u32 rx_brd_u; /* Rx broadcast frame upper */ + u32 rx_drop_l; /* Rx dropped packets lower */ + u32 rx_drop_u; /* Rx dropped packets upper */ + u32 rx_pkt_l; /* Rx packets lower */ + u32 rx_pkt_u; /* Rx packets upper */ + u32 rx_undsz_l; /* Rx undersized packet lower */ + u32 rx_undsz_u; /* Rx undersized packet upper */ + u32 rx_64_l; /* Rx 64 oct packet lower */ + u32 rx_64_u; /* Rx 64 oct packet upper */ + u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ + u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ + u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ + u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ + u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ + u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ + u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ + u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ + u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ + u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ + u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ + u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ + u32 rx_oversz_l; /* Rx oversized packet lower */ + u32 rx_oversz_u; /* Rx oversized packet upper */ + u32 rx_jabber_l; /* Rx Jabber packet lower */ + u32 rx_jabber_u; /* Rx Jabber packet upper */ + u32 rx_frag_l; /* Rx Fragment packet lower */ + u32 rx_frag_u; /* Rx Fragment packet upper */ + u32 rx_cnp_l; /* Rx control packet lower */ + u32 rx_cnp_u; /* Rx control packet upper */ + u32 rx_drntp_l; /* Rx dripped not truncated packet lower */ + u32 rx_drntp_u; /* Rx dripped not truncated packet upper */ + u32 res_1d0[0xc]; + + u32 tx_eoct_l; /* Tx ethernet octests lower */ + u32 tx_eoct_u; /* Tx ethernet octests upper */ + u32 tx_oct_l; /* Tx octests lower */ + u32 tx_oct_u; /* Tx octests upper */ + u32 res_210[0x2]; + u32 tx_pause_frame_l; /* Tx valid pause frame lower */ + u32 tx_pause_frame_u; /* Tx valid pause frame upper */ + u32 tx_frame_l; /* Tx frame counter lower */ + u32 tx_frame_u; /* Tx frame counter upper */ + u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */ + u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */ + u32 tx_vlan_l; /* Tx VLAN frame lower */ + u32 tx_vlan_u; /* Tx VLAN frame upper */ + u32 tx_frame_err_l; /* Tx frame error lower */ + u32 tx_frame_err_u; /* Tx frame error upper */ + u32 tx_uni_l; /* Tx unicast frame lower */ + u32 tx_uni_u; /* Tx unicast frame upper */ + u32 tx_multi_l; /* Tx multicast frame lower */ + u32 tx_multi_u; /* Tx multicast frame upper */ + u32 tx_brd_l; /* Tx broadcast frame lower */ + u32 tx_brd_u; /* Tx broadcast frame upper */ + u32 res_258[0x2]; + u32 tx_pkt_l; /* Tx packets lower */ + u32 tx_pkt_u; /* Tx packets upper */ + u32 tx_undsz_l; /* Tx undersized packet lower */ + u32 tx_undsz_u; /* Tx undersized packet upper */ + u32 tx_64_l; /* Tx 64 oct packet lower */ + u32 tx_64_u; /* Tx 64 oct packet upper */ + u32 tx_127_l; /* Tx 65 to 127 oct packet lower */ + u32 tx_127_u; /* Tx 65 to 127 oct packet upper */ + u32 tx_255_l; /* Tx 128 to 255 oct packet lower */ + u32 tx_255_u; /* Tx 128 to 255 oct packet upper */ + u32 tx_511_l; /* Tx 256 to 511 oct packet lower */ + u32 tx_511_u; /* Tx 256 to 511 oct packet upper */ + u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */ + u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */ + u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */ + u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */ + u32 tx_1519_l; /* Tx 1519 to max oct packet lower */ + u32 tx_1519_u; /* Tx 1519 to max oct packet upper */ + u32 res_2a8[0x6]; + u32 tx_cnp_l; /* Tx control packet lower */ + u32 tx_cnp_u; /* Tx control packet upper */ + u32 res_2c8[0xe]; + + /* Line interface control register */ + u32 if_mode; /* interface mode control */ + u32 if_status; /* interface status */ + u32 res_308[0xe]; + + /* HiGig/2 Register */ + u32 hg_config; /* HiGig2 control and configuration */ + u32 res_344[0x3]; + u32 hg_pause_quanta; /* HiGig2 pause quanta */ + u32 res_354[0x3]; + u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */ + u32 res_364[0x3]; + u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */ + u32 hg_fifos_status; /* HiGig2 fifos status */ + u32 rhm; /* Rx HiGig2 message counter register */ + u32 thm;/* Tx HiGig2 message counter register */ + u32 res_380[0x320]; +}; + +/* COMMAND_CONFIG - command and configuration register */ +#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ +#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ +#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) + +/* HASHTABLE_CTRL - Hashtable control register */ +#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ +#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff + +/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ +#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff + +/* IMASK - interrupt mask register */ +#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ +#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ +#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ +#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ +#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ +#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ +#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ +#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ +#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ +#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ +#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ +#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ +#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ +#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ +#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ +#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ + +#define IMASK_MASK_ALL 0x00000000 + +/* IEVENT - interrupt event register */ +#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ +#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ +#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ +#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ +#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ +#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ +#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ +#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ +#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ +#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ +#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ +#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ +#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ +#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ +#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ +#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ + +#define IEVENT_CLEAR_ALL 0xffffffff + +/* IF_MODE - Interface Mode Register */ +#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */ +#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */ +#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */ +#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */ +#define IF_MODE_RG 0x00000004 /* 1- RGMII */ +#define IF_MODE_RM 0x00000008 /* 1- RGMII */ + +#define IF_DEFAULT (IF_GMII) + +/* Internal PHY Registers - SGMII */ +#define PHY_SGMII_CR_PHY_RESET 0x8000 +#define PHY_SGMII_CR_RESET_AN 0x0200 +#define PHY_SGMII_CR_DEF_VAL 0x1140 +#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 +#define PHY_SGMII_IF_MODE_AN 0x0002 +#define PHY_SGMII_IF_MODE_SGMII 0x0001 + +struct memac_mdio_controller { + u32 res0[0xc]; + u32 mdio_stat; /* MDIO configuration and status */ + u32 mdio_ctl; /* MDIO control */ + u32 mdio_data; /* MDIO data */ + u32 mdio_addr; /* MDIO address */ +}; + +#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) +#define MDIO_STAT_BSY (1 << 0) +#define MDIO_STAT_RD_ER (1 << 1) +#define MDIO_STAT_PRE (1 << 5) +#define MDIO_STAT_ENC (1 << 6) +#define MDIO_STAT_HOLD_15_CLK (7 << 2) + +#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) +#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) +#define MDIO_CTL_PRE_DIS (1 << 10) +#define MDIO_CTL_SCAN_EN (1 << 11) +#define MDIO_CTL_POST_INC (1 << 14) +#define MDIO_CTL_READ (1 << 15) + +#define MDIO_DATA(x) (x & 0xffff) +#define MDIO_DATA_BSY (1 << 31) + +struct fsl_enet_mac; + +void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs, + int max_rx_len); + +#endif diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 4642c54ece..7a1fcdd81f 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -32,6 +32,10 @@ COBJS-y += init.o COBJS-y += tgec.o COBJS-y += tgec_phy.o +# Soc have FMAN v3 with mEMAC +COBJS-$(CONFIG_SYS_FMAN_V3) += memac_phy.o +COBJS-$(CONFIG_SYS_FMAN_V3) += memac.o + # SoC specific SERDES support COBJS-$(CONFIG_P1017) += p1023.o COBJS-$(CONFIG_P1023) += p1023.o diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 2b616adb6e..ed23fdd4ac 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * Dave Liu * * This program is free software; you can redistribute it and/or @@ -28,6 +28,7 @@ #include #include #include +#include #include "fm.h" @@ -47,6 +48,28 @@ static int num_controllers; /* Configure the TBI for SGMII operation */ void dtsec_configure_serdes(struct fm_eth *priv) { +#ifdef CONFIG_SYS_FMAN_V3 + u32 value; + struct mii_dev bus; + bus.priv = priv->mac->phyregs; + + /* SGMII IF mode + AN enable */ + value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII; + memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); + + /* Dev ability according to SGMII specification */ + value = PHY_SGMII_DEV_ABILITY_SGMII; + memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value); + + /* Adjust link timer for SGMII - + 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */ + memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3); + memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40); + + /* Restart AN */ + value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN; + memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); +#else struct dtsec *regs = priv->mac->base; struct tsec_mii_mng *phyregs = priv->mac->phyregs; @@ -60,15 +83,18 @@ void dtsec_configure_serdes(struct fm_eth *priv) TBIANA_SGMII_ACK); tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_CR, TBICR_SETTINGS); +#endif } static void dtsec_init_phy(struct eth_device *dev) { struct fm_eth *fm_eth = dev->priv; - struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; +#ifndef CONFIG_SYS_FMAN_V3 + struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; /* Assign a Physical address to the TBI */ out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); +#endif if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) dtsec_configure_serdes(fm_eth); @@ -541,6 +567,10 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) num = fm_eth->num; +#ifdef CONFIG_SYS_FMAN_V3 + base = ®->memac[num].fm_memac; + phyregs = ®->memac[num].fm_memac_mdio; +#else /* Get the mac registers base address */ if (fm_eth->type == FM_ETH_1G_E) { base = ®->mac_1g[num].fm_dtesc; @@ -549,6 +579,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) base = ®->mac_10g[num].fm_10gec; phyregs = ®->mac_10g[num].fm_10gec_mdio; } +#endif /* alloc mac controller */ mac = malloc(sizeof(struct fsl_enet_mac)); @@ -559,10 +590,14 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) /* save the mac to fm_eth struct */ fm_eth->mac = mac; +#ifdef CONFIG_SYS_FMAN_V3 + init_memac(mac, base, phyregs, MAX_RXBUF_LEN); +#else if (fm_eth->type == FM_ETH_1G_E) init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN); else init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); +#endif return 1; } diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c new file mode 100644 index 0000000000..32c7054e35 --- /dev/null +++ b/drivers/net/fm/memac.c @@ -0,0 +1,132 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Roy Zang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* MAXFRM - maximum frame length */ +#define MAXFRM_MASK 0x0000ffff + +#include +#include +#include +#include +#include +#include + +#include "fm.h" + +static void memac_init_mac(struct fsl_enet_mac *mac) +{ + struct memac *regs = mac->base; + + /* mask all interrupt */ + out_be32(®s->imask, IMASK_MASK_ALL); + + /* clear all events */ + out_be32(®s->ievent, IEVENT_CLEAR_ALL); + + /* set the max receive length */ + out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK); + + /* multicast frame reception for the hash entry disable */ + out_be32(®s->hashtable_ctrl, 0); +} + +static void memac_enable_mac(struct fsl_enet_mac *mac) +{ + struct memac *regs = mac->base; + + setbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); +} + +static void memac_disable_mac(struct fsl_enet_mac *mac) +{ + struct memac *regs = mac->base; + + clrbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN); +} + +static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr) +{ + struct memac *regs = mac->base; + u32 mac_addr0, mac_addr1; + + /* + * if a station address of 0x12345678ABCD, perform a write to + * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB + */ + mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0]); + out_be32(®s->mac_addr_0, mac_addr0); + + mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff; + out_be32(®s->mac_addr_1, mac_addr1); +} + +static void memac_set_interface_mode(struct fsl_enet_mac *mac, + phy_interface_t type, int speed) +{ + /* Roy need more work here */ + + struct memac *regs = mac->base; + u32 if_mode, if_status; + + /* clear all bits relative with interface mode */ + if_mode = in_be32(®s->if_mode); + if_status = in_be32(®s->if_status); + + /* set interface mode */ + switch (type) { + case PHY_INTERFACE_MODE_GMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + if_mode |= (IF_MODE_GMII | IF_MODE_RG); + break; + case PHY_INTERFACE_MODE_RMII: + if_mode |= (IF_MODE_GMII | IF_MODE_RM); + break; + case PHY_INTERFACE_MODE_SGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= (IF_MODE_GMII); + break; + default: + break; + } + /* Enable automatic speed selection */ + if_mode |= IF_MODE_EN_AUTO; + + debug(" %s, if_mode = %x\n", __func__, if_mode); + debug(" %s, if_status = %x\n", __func__, if_status); + out_be32(®s->if_mode, if_mode); + return; +} + +void init_memac(struct fsl_enet_mac *mac, void *base, + void *phyregs, int max_rx_len) +{ + mac->base = base; + mac->phyregs = phyregs; + mac->max_rx_len = max_rx_len; + mac->init_mac = memac_init_mac; + mac->enable_mac = memac_enable_mac; + mac->disable_mac = memac_disable_mac; + mac->set_mac_addr = memac_set_mac_addr; + mac->set_if_mode = memac_set_interface_mode; +} diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c new file mode 100644 index 0000000000..ea6118b9b9 --- /dev/null +++ b/drivers/net/fm/memac_phy.c @@ -0,0 +1,150 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Andy Fleming + * Roy Zang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * Some part is taken from tsec.c + */ +#include +#include +#include +#include +#include +#include + +/* + * Write value to the PHY for this device to the register at regnum, waiting + * until the write is done before it returns. All PHY configuration has to be + * done through the TSEC1 MIIM regs + */ +int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value) +{ + u32 mdio_ctl; + struct memac_mdio_controller *regs = bus->priv; + u32 c45 = 1; /* Default to 10G interface */ + + if (dev_addr == MDIO_DEVAD_NONE) { + c45 = 0; /* clause 22 */ + dev_addr = regnum & 0x1f; + clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); + } else { + setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); + setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); + } + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the port and dev addr */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + if (c45) + out_be32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Write the value to the register */ + out_be32(®s->mdio_data, MDIO_DATA(value)); + + /* Wait till the MDIO write is complete */ + while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + return 0; +} + +/* + * Reads from register regnum in the PHY for device dev, returning the value. + * Clears miimcom first. All PHY configuration has to be done through the + * TSEC1 MIIM regs + */ +int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum) +{ + u32 mdio_ctl; + struct memac_mdio_controller *regs = bus->priv; + u32 c45 = 1; + + if (dev_addr == MDIO_DEVAD_NONE) { + c45 = 0; /* clause 22 */ + dev_addr = regnum & 0x1f; + clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); + } else { + setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); + setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); + } + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Set the Port and Device Addrs */ + mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr); + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Set the register address */ + if (c45) + out_be32(®s->mdio_addr, regnum & 0xffff); + + /* Wait till the bus is free */ + while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) + ; + + /* Initiate the read */ + mdio_ctl |= MDIO_CTL_READ; + out_be32(®s->mdio_ctl, mdio_ctl); + + /* Wait till the MDIO write is complete */ + while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY) + ; + + /* Return all Fs if nothing was there */ + if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) + return 0xffff; + + return in_be32(®s->mdio_data) & 0xffff; +} + +int memac_mdio_reset(struct mii_dev *bus) +{ + return 0; +} + +int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate FM TGEC MDIO bus\n"); + return -1; + } + + bus->read = memac_mdio_read; + bus->write = memac_mdio_write; + bus->reset = memac_mdio_reset; + sprintf(bus->name, info->name); + + bus->priv = info->regs; + + return mdio_register(bus); +} diff --git a/include/fm_eth.h b/include/fm_eth.h index 5d80e4962e..495765b933 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,8 +53,15 @@ enum fm_eth_type { FM_ETH_10G_E, }; +#ifdef CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) +#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) +#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) +#else #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) +#endif #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO" @@ -65,6 +72,33 @@ enum fm_eth_type { .phy_regs = (void *)pregs, \ .enet_if = PHY_INTERFACE_MODE_NONE, \ +#ifdef CONFIG_SYS_FMAN_V3 +#define FM_DTSEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_1G_E, \ + .port = FM##idx##_DTSEC##n, \ + .rx_port_id = RX_PORT_1G_BASE + n - 1, \ + .tx_port_id = TX_PORT_1G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} + +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1]),\ +} +#else #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \ @@ -90,7 +124,7 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, mac_10g[n-1]),\ } - +#endif struct fm_eth_info { u8 enabled; u8 fm; @@ -112,7 +146,14 @@ struct tgec_mdio_info { char *name; }; +struct memac_mdio_info { + struct memac_mdio_controller *regs; + char *name; +}; + int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info); +int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info); + int fm_standard_init(bd_t *bis); void fman_enet_init(void); void fdt_fixup_fman_ethernet(void *fdt); diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index ea8b54b56f..e24e828cd1 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * Jun-jie Zhang * Mingkai Hu * @@ -51,6 +51,10 @@ int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, u16 value); +int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value); +int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum); struct fsl_pq_mdio_info { struct tsec_mii_mng *regs; -- cgit v1.2.3 From 57495e4e5e70d6a4e9b8f053bdf099f9cdb363d2 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:22 +0000 Subject: powerpc/mpc8xxx: Update DDR registers DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be set for speed lower than 1250MT/s. CDR1 and CDR2 are control driver registers. ODT termination valueis for IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is 000 -> Termsel off 001 -> 120 Ohm 010 -> 180 Ohm 011 -> 75 Ohm 100 -> 110 Ohm 101 -> 60 Ohm 110 -> 70 Ohm 111 -> 47 Ohm Add two write leveling registers. Each QDS now has its own write leveling start value. In case of zero value, the value of QDS0 will be used. These values are board-specific and are set in board files. Extend DDR register timing_cfg_1 to have 4 bits for each field. DDR control driver registers and write leveling registers are added to interactive debugging for easy access. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 5 +++++ arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 22 ++++++++++++++++++++-- arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 12 +++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 30 ++++++++++++++++++++++++++++++ 5 files changed, 68 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index ca4ed62645..088cf45647 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -121,6 +121,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + if (regs->ddr_wrlvl_cntl_2) + out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + if (regs->ddr_wrlvl_cntl_3) + out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); + out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 2592873c9f..c28f9cd201 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -451,8 +451,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, | ((caslat_ctrl & 0xF) << 16) | ((refrec_ctrl & 0xF) << 12) | ((wrrec_mclk & 0x0F) << 8) - | ((acttoact_mclk & 0x07) << 4) - | ((wrtord_mclk & 0x07) << 0) + | ((acttoact_mclk & 0x0F) << 4) + | ((wrtord_mclk & 0x0F) << 0) ); debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); } @@ -659,6 +659,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int dqs_cfg; /* DQS configuration */ unsigned int odt_cfg = 0; /* ODT configuration */ unsigned int num_pr; /* Number of posted refreshes */ + unsigned int slow = 0; /* DDR will be run less than 1250 */ unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ unsigned int ap_en; /* Address Parity Enable */ unsigned int d_init; /* DRAM data initialization */ @@ -692,6 +693,10 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, obc_cfg = 0; #endif +#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) + slow = get_ddr_freq(0) < 1249000000; +#endif + if (popts->registered_dimm_en) { rcw_en = 1; ap_en = popts->ap_en; @@ -720,6 +725,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((dqs_cfg & 0x3) << 26) | ((odt_cfg & 0x3) << 21) | ((num_pr & 0xf) << 12) + | ((slow & 1) << 11) | (qd_en << 9) | (unq_mrs_en << 8) | ((obc_cfg & 0x1) << 6) @@ -1347,6 +1353,11 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, | ((wrlvl_start & 0x1F) << 0) ); debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); + ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; + debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); + ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; + debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); + } /* DDR Self Refresh Counter (DDR_SR_CNTR) */ @@ -1370,6 +1381,12 @@ static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); } +static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + ddr->ddr_cdr2 = popts->ddr_cdr2; + debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); +} + unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) { @@ -1569,6 +1586,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, cas_latency, additive_latency); set_ddr_cdr1(ddr, popts); + set_ddr_cdr2(ddr, popts); set_ddr_sdram_cfg(ddr, popts, common_dimm); ip_rev = fsl_ddr_get_version(); if (ip_rev > 0x40400) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c index f59d1051bf..cb71f94ba1 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -452,6 +452,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS(ddr_cdr1), + CTRL_OPTIONS(ddr_cdr2), CTRL_OPTIONS(tCKE_clock_pulse_width_ps), CTRL_OPTIONS(tFAW_window_four_activates_ps), CTRL_OPTIONS(trwt_override), @@ -518,6 +520,8 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) CFG_REGS(timing_cfg_5), CFG_REGS(ddr_zq_cntl), CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_wrlvl_cntl_2), + CFG_REGS(ddr_wrlvl_cntl_3), CFG_REGS(ddr_sr_cntr), CFG_REGS(ddr_sdram_rcw_1), CFG_REGS(ddr_sdram_rcw_2), @@ -525,6 +529,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) CFG_REGS(ddr_cdr2), CFG_REGS(err_disable), CFG_REGS(err_int_en), + CFG_REGS(ddr_eor), }; static const unsigned int n_opts = ARRAY_SIZE(options); @@ -584,6 +589,8 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, CFG_REGS(timing_cfg_5), CFG_REGS(ddr_zq_cntl), CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_wrlvl_cntl_2), + CFG_REGS(ddr_wrlvl_cntl_3), CFG_REGS(ddr_sr_cntr), CFG_REGS(ddr_sdram_rcw_1), CFG_REGS(ddr_sdram_rcw_2), @@ -593,7 +600,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, CFG_REGS(err_int_en), CFG_REGS(ddr_sdram_rcw_2), CFG_REGS(ddr_sdram_rcw_2), - + CFG_REGS(ddr_eor), }; static const unsigned int n_opts = ARRAY_SIZE(options); @@ -689,6 +696,8 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS_HEX(ddr_cdr1), + CTRL_OPTIONS_HEX(ddr_cdr2), CTRL_OPTIONS(tCKE_clock_pulse_width_ps), CTRL_OPTIONS(tFAW_window_four_activates_ps), CTRL_OPTIONS(trwt_override), @@ -1597,6 +1606,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo) * doesn't return */ do_reset(NULL, 0, 0, NULL); + printf("Reset didn't work\n"); } if (strcmp(argv[0], "recompute") == 0) { diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c63f9e500a..ba13ddf951 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -27,6 +27,8 @@ #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." #endif +#define FSL_DDR_VER_4_7 47 + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index e271342f08..9cf9bd4a2a 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -145,6 +145,31 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) + +#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_180ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_110ohm 0x4 +#define DDR_CDR_ODT_60hm 0x5 +#define DDR_CDR_ODT_70ohm 0x6 +#define DDR_CDR_ODT_47ohm 0x7 +#else +#define DDR_CDR_ODT_75ohm 0x0 +#define DDR_CDR_ODT_55ohm 0x1 +#define DDR_CDR_ODT_60ohm 0x2 +#define DDR_CDR_ODT_50ohm 0x3 +#define DDR_CDR_ODT_150ohm 0x4 +#define DDR_CDR_ODT_43ohm 0x5 +#define DDR_CDR_ODT_120ohm 0x6 +#endif /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { @@ -177,6 +202,8 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_5; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; + unsigned int ddr_wrlvl_cntl_2; + unsigned int ddr_wrlvl_cntl_3; unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; @@ -262,6 +289,8 @@ typedef struct memctl_options_s { unsigned int wrlvl_override; unsigned int wrlvl_sample; /* Write leveling */ unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; unsigned int half_strength_driver_enable; unsigned int twoT_en; @@ -288,6 +317,7 @@ typedef struct memctl_options_s { unsigned int rcw_2; /* control register 1 */ unsigned int ddr_cdr1; + unsigned int ddr_cdr2; unsigned int trwt_override; unsigned int trwt; /* read-to-write turnaround */ -- cgit v1.2.3 From 123922b1e583dc6bd6b8909af2d788f6e40a33a9 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:23 +0000 Subject: powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation Fix handling quad-rank DIMMs in a system with two DIMM slots and first slot supports both dual-rank DIMM and quad-rank DIMM. For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config registers need to be enabled to maintain proper ODT operation. The inactive CS should have bnds registers cleared. Fix the turnaround timing for systems with all chip-selects enabled. This wasn't an issue before because DDR was running lower than 1600MT/s with this interleaving mode. Fix DDR address calculation. It wasn't an issue until we have multiple controllers with each more than 4GB and interleaving is disabled. It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off) when debugging DDR and first DDR controller is disabled. With the fix, the first enabled controller information will be displayed. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 62 +++++++++++++++++----- .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 16 ++++-- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 12 +++++ arch/powerpc/cpu/mpc8xxx/ddr/util.c | 12 +++++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 2 + 5 files changed, 87 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index c28f9cd201..5928eb8806 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -229,6 +229,26 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ #if !defined(CONFIG_FSL_DDR1) +static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) +{ +#if CONFIG_DIMM_SLOTS_PER_CTLR == 1 + if (dimm_params[0].n_ranks == 4) + return 1; +#endif + +#if CONFIG_DIMM_SLOTS_PER_CTLR == 2 + if ((dimm_params[0].n_ranks == 2) && + (dimm_params[1].n_ranks == 2)) + return 1; + +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (dimm_params[0].n_ranks == 4) + return 1; +#endif +#endif + return 0; +} + /* * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) * @@ -236,7 +256,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) * dreams up non-zero default values to be backwards compatible. */ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) + const memctl_options_t *popts, + const dimm_params_t *dimm_params) { unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ @@ -266,7 +287,18 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, unsigned int data_rate = get_ddr_freq(0); tmrd_mclk = 4; /* set the turnaround time */ - trwt_mclk = 1; + + /* + * for single quad-rank DIMM and two dual-rank DIMMs + * to avoid ODT overlap + */ + if (avoid_odt_overlap(dimm_params)) { + twwt_mclk = 2; + trrt_mclk = 1; + } + /* for faster clock, need more time for data setup */ + trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; + if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) twrt_mclk = 1; @@ -1483,7 +1515,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, break; } sa = common_dimm->base_address; - ea = common_dimm->total_mem - 1; + ea = sa + common_dimm->total_mem - 1; } else if (!popts->memctl_interleaving) { /* * If memory interleaving between controllers is NOT @@ -1497,7 +1529,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { case FSL_DDR_CS0_CS1_CS2_CS3: sa = common_dimm->base_address; - ea = common_dimm->total_mem - 1; + ea = sa + common_dimm->total_mem - 1; break; case FSL_DDR_CS0_CS1_AND_CS2_CS3: if ((i >= 2) && (dimm_number == 0)) { @@ -1554,17 +1586,19 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, sa >>= 24; ea >>= 24; - ddr->cs[i].bnds = (0 - | ((sa & 0xFFF) << 16) /* starting address MSB */ - | ((ea & 0xFFF) << 0) /* ending address MSB */ - ); + if (cs_en) { + ddr->cs[i].bnds = (0 + | ((sa & 0xFFF) << 16)/* starting address MSB */ + | ((ea & 0xFFF) << 0) /* ending address MSB */ + ); + } else { + debug("FSLDDR: setting bnds to 0 for inactive CS\n"); + ddr->cs[i].bnds = 0; + } debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); - if (cs_en) { - set_csn_config(dimm_number, i, ddr, popts, dimm_params); - set_csn_config_2(i, ddr); - } else - debug("CS%d is disabled.\n", i); + set_csn_config(dimm_number, i, ddr, popts, dimm_params); + set_csn_config_2(i, ddr); } /* @@ -1577,7 +1611,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_eor(ddr, popts); #if !defined(CONFIG_FSL_DDR1) - set_timing_cfg_0(ddr, popts); + set_timing_cfg_0(ddr, popts, dimm_params); #endif set_timing_cfg_3(ddr, popts, common_dimm, cas_latency); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 03a784cd47..6a1f4e4e38 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -76,7 +76,7 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, unsigned int compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, - unsigned int number_of_dimms) + const unsigned int number_of_dimms) { unsigned int i, j; @@ -126,13 +126,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, temp1++; continue; } + + /* + * check if quad-rank DIMM is plugged if + * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined + * Only the board with proper design is capable + */ +#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE if (dimm_params[i].n_ranks == 4 && \ CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { printf("Found Quad-rank DIMM, not able to support."); temp1++; continue; } - +#endif /* * Find minimum tCKmax_ps to find fastest slow speed, * i.e., this is the slowest the whole system can go. @@ -236,11 +243,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, if (outpdimm->all_DIMMs_registered) for (j = 0; j < 16; j++) { outpdimm->rcw[j] = dimm_params[0].rcw[j]; - for (i = 1; i < number_of_dimms; i++) + for (i = 1; i < number_of_dimms; i++) { + if (!dimm_params[i].n_ranks) + continue; if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { temp1 = 1; break; } + } } if (temp1 != 0) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 13e4825274..1188df9178 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -510,6 +510,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { switch (pdimm[0].n_ranks) { +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + case 4: + pdodt = single_Q; + if (pdimm[1].n_ranks) + printf("Error: Quad- and Dual-rank DIMMs " + "cannot be used together\n"); + break; +#endif case 2: switch (pdimm[1].n_ranks) { case 2: @@ -912,6 +920,10 @@ done: "interleaving disabled!\n", ctrl_num); } #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (pdimm[0].n_ranks == 4) + break; +#endif if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { popts->ba_intlv_ctl = 0; printf("Not enough bank(chip-select) for " diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 664ad09298..b439cc9750 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -140,6 +140,18 @@ void board_add_ram_info(int use_default) uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); int cas_lat; +#if CONFIG_NUM_DDR_CONTROLLERS >= 2 + if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { + ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + sdram_cfg = in_be32(&ddr->sdram_cfg); + } +#endif +#if CONFIG_NUM_DDR_CONTROLLERS >= 3 + if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { + ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; + sdram_cfg = in_be32(&ddr->sdram_cfg); + } +#endif puts(" (DDR"); switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) { diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 9cf9bd4a2a..bb79335b18 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -84,6 +84,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D +#define SDRAM_CS_CONFIG_EN 0x80000000 + /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ #define SDRAM_CFG_MEM_EN 0x80000000 -- cgit v1.2.3 From f31cfd19253713eea59311dec9e99df5d43b2db9 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:24 +0000 Subject: powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT When ECC is enabled, DDR controller needs to initialize the data and ecc. The wait time can be calcuated with total memory size, bus width, bus speed and interleaving mode. If it went wrong, it is bettert to timeout than waiting for D_INIT to clear, where it probably hangs. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 80 ++++++++++++++++++++++---------- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 12 ++++- arch/powerpc/cpu/mpc8xxx/ddr/util.c | 4 +- arch/powerpc/include/asm/fsl_ddr_sdram.h | 2 + 4 files changed, 71 insertions(+), 27 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 088cf45647..8bed5fe925 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -18,12 +18,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num) { - unsigned int i; + unsigned int i, bus_width; volatile ccsr_ddr_t *ddr; u32 temp_sdram_cfg; + u32 total_gb_size_per_controller; + int timeout, timeout_save; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; - u32 total_gb_size_per_controller; unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; int csn = -1; #endif @@ -52,8 +53,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, return; } - out_be32(&ddr->eor, regs->ddr_eor); - + if (regs->ddr_eor) + out_be32(&ddr->eor, regs->ddr_eor); #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 debug("Workaround for ERRATUM_DDR111_DDR134\n"); for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { @@ -275,9 +276,46 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & 0x80000000)) + continue; + total_gb_size_per_controller += 1 << ( + ((regs->cs[i].config >> 14) & 0x3) + 2 + + ((regs->cs[i].config >> 8) & 0x7) + 12 + + ((regs->cs[i].config >> 0) & 0x7) + 8 + + 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - + 26); /* minus 26 (count of 64M) */ + } + if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ + total_gb_size_per_controller *= 3; + else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ + total_gb_size_per_controller <<= 1; + /* + * total memory / bus width = transactions needed + * transactions needed / data rate = seconds + * to add plenty of buffer, double the time + * For example, 2GB on 666MT/s 64-bit bus takes about 402ms + * Let's wait for 800ms + */ + bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) + >> SDRAM_CFG_DBW_SHIFT); + timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / + (get_ddr_freq(0) >> 20)) << 1; + timeout_save = timeout; + total_gb_size_per_controller >>= 4; /* shift down to gb size */ + debug("total %d GB\n", total_gb_size_per_controller); + debug("Need to wait up to %d * 10ms\n", timeout); + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) + while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 /* continue this workaround */ @@ -335,23 +373,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, while (in_be32(&ddr->debug[1]) & 0x400) udelay(10000); /* throttle polling rate */ - /* 7. Wait for 400ms/GB */ - total_gb_size_per_controller = 0; - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == csn) { - total_gb_size_per_controller += - ((csn_bnds_backup & 0xFFFF) >> 6) - - (csn_bnds_backup >> 22) + 1; - } else { - total_gb_size_per_controller += - ((regs->cs[i].bnds & 0xFFFF) >> 6) - - (regs->cs[i].bnds >> 22) + 1; - } - } - if (in_be32(&ddr->sdram_cfg) & 0x80000) - total_gb_size_per_controller <<= 1; - debug("Wait for %d ms\n", total_gb_size_per_controller * 400); - udelay(total_gb_size_per_controller * 400000); + /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ + debug("Wait for %d * 10ms\n", timeout_save); + udelay(timeout_save * 10000); /* 8. Set sdram_cfg_2[dinit] if options requires */ setbits_be32(&ddr->sdram_cfg_2, @@ -359,8 +383,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); /* 9. Poll until dinit is cleared */ - while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) - udelay(10000); + timeout = timeout_save; + debug("Need to wait up to %d * 10ms\n", timeout); + while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); /* 10. Clear EEBACR[3] */ clrbits_be32(&ecm->eebacr, 10000000); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index b47268c20e..2885906e87 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -526,6 +526,17 @@ phys_size_t fsl_ddr_sdram(void) #endif total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); + /* setup 3-way interleaving before enabling DDRC */ + switch (info.memctl_opts[0].memctl_interleaving_mode) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode); + break; + default: + break; + } + /* Program configuration registers. */ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { debug("Programming controller %u\n", i); @@ -561,7 +572,6 @@ phys_size_t fsl_ddr_sdram(void) case FSL_DDR_3WAY_8KB_INTERLEAVING: law_memctl = LAW_TRGT_IF_DDR_INTLV_123; if (i == 0) { - fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode); fsl_ddr_set_lawbar(&info.common_timing_params[i], law_memctl, i); } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index b439cc9750..afc5fae497 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -142,13 +142,13 @@ void board_add_ram_info(int use_default) #if CONFIG_NUM_DDR_CONTROLLERS >= 2 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR; sdram_cfg = in_be32(&ddr->sdram_cfg); } #endif #if CONFIG_NUM_DDR_CONTROLLERS >= 3 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; + ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR; sdram_cfg = in_be32(&ddr->sdram_cfg); } #endif diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index bb79335b18..640d3297d6 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -98,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 @@ -330,6 +331,7 @@ extern phys_size_t fsl_ddr_sdram_size(void); extern int fsl_use_spd(void); extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); +u32 fsl_ddr_get_intl3r(void); /* * The 85xx boards have a common prototype for fixed_sdram so put the -- cgit v1.2.3 From eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:25 +0000 Subject: powerpc/mpc85xx: software workaround for DDR erratum A-004468 Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 96 +++++++++++++++++++++++++++---- arch/powerpc/cpu/mpc86xx/fdt.c | 2 +- arch/powerpc/cpu/mpc86xx/mp.c | 9 ++- arch/powerpc/cpu/mpc8xxx/ddr/util.c | 10 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/mp.h | 2 +- arch/powerpc/lib/board.c | 4 +- 9 files changed, 111 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index bc7e5e36e2..ce5924bc13 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -76,6 +76,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) puts("Work-around for Erratum ESDHC111 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 + puts("Work-around for Erratum A004468 enabled\n"); +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) puts("Work-around for Erratum ESDHC135 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index d54527aa47..8221481359 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -48,7 +48,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) { int off; ulong spin_tbl_addr = get_spin_phys_addr(); - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); u32 id = get_my_id(); const char *enable_method; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index ffc2a9ad65..39adf8e887 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -27,9 +27,11 @@ #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; +u32 fsl_ddr_get_intl3r(void); u32 get_my_id() { @@ -191,13 +193,68 @@ int cpu_release(int nr, int argc, char * const argv[]) return 0; } -u32 determine_mp_bootpg(void) +u32 determine_mp_bootpg(unsigned int *pagesize) { + u32 bootpg; +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 + u32 svr = get_svr(); + u32 granule_size, check; + struct law_entry e; +#endif + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ if ((u64)gd->ram_size > 0xfffff000) - return (0xfffff000); + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + if (pagesize) + *pagesize = 4096; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 +/* + * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, + * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But + * the way boot page chosen in u-boot avoids hitting this erratum. So only + * thw workaround for 3-way interleaving is needed. + * + * To make sure boot page translation works with 3-Way DDR interleaving + * enforce a check for the following constrains + * 8K granule size requires BRSIZE=8K and + * bootpg >> log2(BRSIZE) %3 == 1 + * 4K and 1K granule size requires BRSIZE=4K and + * bootpg >> log2(BRSIZE) %3 == 0 + */ + if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) { + e = find_law(bootpg); + switch (e.trgt_id) { + case LAW_TRGT_IF_DDR_INTLV_123: + granule_size = fsl_ddr_get_intl3r() & 0x1f; + if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) { + if (pagesize) + *pagesize = 8192; + bootpg &= 0xffffe000; /* align to 8KB */ + check = bootpg >> 13; + while ((check % 3) != 1) + check--; + bootpg = check << 13; + debug("Boot page (8K) at 0x%08x\n", bootpg); + break; + } else { + bootpg &= 0xfffff000; /* align to 4KB */ + check = bootpg >> 12; + while ((check % 3) != 0) + check--; + bootpg = check << 12; + debug("Boot page (4K) at 0x%08x\n", bootpg); + } + break; + default: + break; + } + } +#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */ - return (gd->ram_size - 4096); + return bootpg; } ulong get_spin_phys_addr(void) @@ -219,9 +276,9 @@ ulong get_spin_virt_addr(void) } #ifdef CONFIG_FSL_CORENET -static void plat_mp_up(unsigned long bootpg) +static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) { - u32 cpu_up_mask, whoami; + u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K; u32 *table = (u32 *)get_spin_virt_addr(); volatile ccsr_gur_t *gur; volatile ccsr_local_t *ccm; @@ -241,7 +298,11 @@ static void plat_mp_up(unsigned long bootpg) out_be32(&ccm->bstrl, bootpg); e = find_law(bootpg); - out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); + /* pagesize is only 4K or 8K */ + if (pagesize == 8192) + brsize = LAW_SIZE_8K; + out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); + debug("BRSIZE is 0x%x\n", brsize); /* readback to sync write */ in_be32(&ccm->bstrar); @@ -294,7 +355,7 @@ static void plat_mp_up(unsigned long bootpg) #endif } #else -static void plat_mp_up(unsigned long bootpg) +static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) { u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_virt_addr(); @@ -374,7 +435,7 @@ static void plat_mp_up(unsigned long bootpg) void cpu_mp_lmb_reserve(struct lmb *lmb) { - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); lmb_reserve(lmb, bootpg, 4096); } @@ -383,8 +444,23 @@ void setup_mp(void) { extern ulong __secondary_start_page; extern ulong __bootpg_addr; + ulong fixup = (ulong)&__secondary_start_page; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg, bootpg_map, pagesize; + + bootpg = determine_mp_bootpg(&pagesize); + + /* + * pagesize is only 4K or 8K + * we only use the last 4K of boot page + * bootpg_map saves the address for the boot page + * 8K is used for the workaround of 3-way DDR interleaving + */ + + bootpg_map = bootpg; + + if (pagesize == 8192) + bootpg += 4096; /* use 2nd half */ /* Some OSes expect secondary cores to be held in reset */ if (hold_cores_in_reset(0)) @@ -407,7 +483,7 @@ void setup_mp(void) memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); - plat_mp_up(bootpg); + plat_mp_up(bootpg_map, pagesize); } else { puts("WARNING: No reset page TLB. " "Skipping secondary core setup\n"); diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 61f5110b7d..2f955fe930 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -20,7 +20,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP int off; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c index 30c99ebc56..de705f0ae8 100644 --- a/arch/powerpc/cpu/mpc86xx/mp.c +++ b/arch/powerpc/cpu/mpc86xx/mp.c @@ -90,8 +90,11 @@ int cpu_release(int nr, int argc, char * const argv[]) return 1; } -u32 determine_mp_bootpg(void) +u32 determine_mp_bootpg(unsigned int *pagesize) { + if (pagesize) + *pagesize = 4096; + /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ if ((u64)gd->ram_size > 0xfffff000) return (0xfff00000); @@ -101,7 +104,7 @@ u32 determine_mp_bootpg(void) void cpu_mp_lmb_reserve(struct lmb *lmb) { - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); /* tell u-boot we stole a page */ lmb_reserve(lmb, bootpg, 4096); @@ -115,7 +118,7 @@ void setup_mp(void) { extern ulong __secondary_start_page; ulong fixup = (ulong)&__secondary_start_page; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); u32 bootpg_va; if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) { diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index afc5fae497..940ffff773 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -121,6 +121,16 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size) #endif } +u32 fsl_ddr_get_intl3r(void) +{ + u32 val = 0; +#ifdef CONFIG_E6500 + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); + val = *mcintl3r; +#endif + return val; +} + void board_add_ram_info(int use_default) { #if defined(CONFIG_MPC83xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ba13ddf951..ecb156619d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -511,6 +511,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_B4860) diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h index fe490bac05..9188ede3f5 100644 --- a/arch/powerpc/include/asm/mp.h +++ b/arch/powerpc/include/asm/mp.h @@ -25,7 +25,7 @@ void setup_mp(void); void cpu_mp_lmb_reserve(struct lmb *lmb); -u32 determine_mp_bootpg(void); +u32 determine_mp_bootpg(unsigned int *pagesize); int is_core_disabled(int nr); #ifdef CONFIG_E6500 diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index b860141efd..ebf400851a 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -440,8 +440,8 @@ void board_init_f(ulong bootflag) * We need to make sure the location we intend to put secondary core * boot code is reserved and not used by any part of u-boot */ - if (addr > determine_mp_bootpg()) { - addr = determine_mp_bootpg(); + if (addr > determine_mp_bootpg(NULL)) { + addr = determine_mp_bootpg(NULL); debug("Reserving MP boot page to %08lx\n", addr); } #endif -- cgit v1.2.3 From a1d558a20f1eaeae9927abc4e0978725d33bae53 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:26 +0000 Subject: powerpc/mpc85xx: Add workaround for DDR erratum A004934 After DDR controller is enabled, it performs a calibration for the transmit data vs DQS paths. During this calibration, the DDR controller may make an inaccurate calculation, resulting in a non-optimal tap point. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 7 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ce5924bc13..2be192d578 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -133,6 +133,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 puts("Work-around for Erratum SRIO-A004034 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 + puts("Work-around for Erratum A004934 enabled\n"); #endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 8bed5fe925..21840bfc2a 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -140,6 +140,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->debug[i], regs->debug[i]); } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 + out_be32(&ddr->debug[28], 0x00003000); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 out_be32(&ddr->debug[12], 0x00000015); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ecb156619d..92ca2ad74d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -512,6 +512,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A004468 +#define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_B4860) -- cgit v1.2.3 From 89b78095681fd3dfd359082ba62d80551a114ab0 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:27 +0000 Subject: powerpc/mpc8xxx: Add auto select bank interleaving mode Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or cs0_cs1 interleaving, or non-interleaving if not available. Fix the message of interleaving disabled if controller interleaving is enabled but DIMMs don't support it. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 33 ++++++++++++++++++++++++++++++++- doc/README.fsl-ddr | 5 +++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 1188df9178..2f13b8fd93 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -474,6 +474,34 @@ static const struct dynamic_odt odt_unknown[4] = { } }; #endif + +/* + * Automatically seleect bank interleaving mode based on DIMMs + * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null. + * This function only deal with one or two slots per controller. + */ +static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) +{ +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks == 4) + return FSL_DDR_CS0_CS1_CS2_CS3; + else if (pdimm[0].n_ranks == 2) + return FSL_DDR_CS0_CS1; +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (pdimm[0].n_ranks == 4) + return FSL_DDR_CS0_CS1_CS2_CS3; +#endif + if (pdimm[0].n_ranks == 2) { + if (pdimm[1].n_ranks == 2) + return FSL_DDR_CS0_CS1_CS2_CS3; + else + return FSL_DDR_CS0_CS1; + } +#endif + return 0; +} + unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, dimm_params_t *pdimm, @@ -908,6 +936,9 @@ done: else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "auto", buf)) + popts->ba_intlv_ctl = auto_bank_intlv(pdimm); else printf("hwconfig has unrecognized parameter for bank_intlv.\n"); switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { @@ -1075,7 +1106,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) break; } debug("%d of %d controllers are interleaving.\n", j, k); - if (j != k) { + if (j && (j != k)) { for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) pinfo->memctl_opts[i].memctl_interleaving = 0; printf("Not all controllers have compatible " diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index f94b56f628..3992640ba3 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -103,6 +103,11 @@ The ways to configure the ddr interleaving mode # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" + # bank(chip-select) interleaving (auto) + setenv hwconfig "fsl_ddr:bank_intlv=auto" + This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings + on DIMMs. + Memory controller address hashing ================================== If the DDR controller supports address hashing, it can be enabled by hwconfig. -- cgit v1.2.3 From 82968a7ab5c306291f5772b5e7cfa49d1d8bb3e6 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:28 +0000 Subject: powerpc/mpc8xxx: Fix DDR SPD failed message Since empty DIMM slot is allowed on other than the first slot, remove the error message if SPD is not found in this case. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 2885906e87..d6b73c7af1 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -77,7 +77,19 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) sizeof(generic_spd_eeprom_t)); if (ret) { - printf("DDR: failed to read SPD from address %u\n", i2c_address); + if (i2c_address == +#ifdef SPD_EEPROM_ADDRESS + SPD_EEPROM_ADDRESS +#elif defined(SPD_EEPROM_ADDRESS1) + SPD_EEPROM_ADDRESS1 +#endif + ) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + } else { + debug("DDR: failed to read SPD from address %u\n", + i2c_address); + } memset(spd, 0, sizeof(generic_spd_eeprom_t)); } } -- cgit v1.2.3 From 3f0997b3255c1498ac92453aa3a7a1cc95914dfd Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:29 +0000 Subject: powerpc/mpc85xx: Remove R6 from spin table R6 was in ePAPR draft version but was dropped in official spec. Removing it to comply. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/mp.c | 8 +++----- arch/powerpc/cpu/mpc85xx/release.S | 2 +- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 39adf8e887..881b681755 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -86,9 +86,8 @@ int cpu_status(int nr) printf("\n"); printf("table @ 0x%p\n", table); printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); - printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); - printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]); + printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); } return 0; @@ -151,7 +150,6 @@ static u8 boot_entry_map[4] = { 0, BOOT_ENTRY_PIR, BOOT_ENTRY_R3_LOWER, - BOOT_ENTRY_R6_LOWER, }; int cpu_release(int nr, int argc, char * const argv[]) @@ -174,8 +172,8 @@ int cpu_release(int nr, int argc, char * const argv[]) boot_addr = simple_strtoull(argv[0], NULL, 16); - /* handle pir, r3, r6 */ - for (i = 1; i < 4; i++) { + /* handle pir, r3 */ + for (i = 1; i < 3; i++) { if (argv[i][0] != '-') { u8 entry = boot_entry_map[i]; val = simple_strtoul(argv[i], NULL, 16); diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 23a3aaf48e..d08b1f3dca 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -366,7 +366,7 @@ __secondary_start_page: lwz r3,ENTRY_R3_LOWER(r10) li r4,0 li r5,0 - lwz r6,ENTRY_R6_LOWER(r10) + li r6,0 lis r7,(64*1024*1024)@h li r8,0 li r9,0 -- cgit v1.2.3 From ffd06e0231ac3fd0c5810f39f6e23527948df1c7 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:30 +0000 Subject: powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- README | 6 + arch/powerpc/cpu/mpc85xx/fdt.c | 13 ++- arch/powerpc/cpu/mpc85xx/mp.c | 61 +++++----- arch/powerpc/cpu/mpc85xx/mp.h | 5 +- arch/powerpc/cpu/mpc85xx/release.S | 179 +++++++++++++++++------------- arch/powerpc/cpu/mpc85xx/tlb.c | 2 +- arch/powerpc/include/asm/config_mpc85xx.h | 3 + doc/README.mpc85xx-spin-table | 26 +++++ 8 files changed, 183 insertions(+), 112 deletions(-) create mode 100644 doc/README.mpc85xx-spin-table diff --git a/README b/README index df4aed14e4..4dad1594eb 100644 --- a/README +++ b/README @@ -363,6 +363,12 @@ The following options need to be configured: ICache only when Code runs from RAM. - 85xx CPU Options: + CONFIG_SYS_PPC64 + + Specifies that the core is a 64-bit PowerPC implementation (implements + the "64" category of the Power ISA). This is necessary for ePAPR + compliance, among other possible reasons. + CONFIG_SYS_FSL_TBCLK_DIV Defines the core time base clock divider ratio compared to the diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 8221481359..a364ef216a 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -47,7 +47,7 @@ extern void ft_srio_setup(void *blob); void ft_fixup_cpu(void *blob, u64 memory_limit) { int off; - ulong spin_tbl_addr = get_spin_phys_addr(); + phys_addr_t spin_tbl_addr = get_spin_phys_addr(); u32 bootpg = determine_mp_bootpg(NULL); u32 id = get_my_id(); const char *enable_method; @@ -97,7 +97,16 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) if ((u64)bootpg < memory_limit) { off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); if (off < 0) - printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); + printf("Failed to reserve memory for bootpg: %s\n", + fdt_strerror(off)); + } + /* Reserve spin table page */ + if (spin_tbl_addr < memory_limit) { + off = fdt_add_mem_rsv(blob, + (spin_tbl_addr & ~0xffful), 4096); + if (off < 0) + printf("Failed to reserve memory for spin table: %s\n", + fdt_strerror(off)); } } #endif diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 881b681755..e1197ac9e5 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -33,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; u32 fsl_ddr_get_intl3r(void); +extern u32 __spin_table[]; + u32 get_my_id() { return mfspr(SPRN_PIR); @@ -78,10 +80,10 @@ int cpu_status(int nr) return 0; if (nr == id) { - table = (u32 *)get_spin_virt_addr(); + table = (u32 *)&__spin_table; printf("table base @ 0x%p\n", table); } else { - table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; + table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; printf("Running on cpu %d\n", id); printf("\n"); printf("table @ 0x%p\n", table); @@ -154,7 +156,7 @@ static u8 boot_entry_map[4] = { int cpu_release(int nr, int argc, char * const argv[]) { - u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; + u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; u64 boot_addr; if (hold_cores_in_reset(1)) @@ -200,11 +202,11 @@ u32 determine_mp_bootpg(unsigned int *pagesize) struct law_entry e; #endif - /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ - if ((u64)gd->ram_size > 0xfffff000) - bootpg = 0xfffff000; - else - bootpg = gd->ram_size - 4096; + + /* use last 4K of mapped memory */ + bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size) + + CONFIG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; @@ -255,29 +257,16 @@ u32 determine_mp_bootpg(unsigned int *pagesize) return bootpg; } -ulong get_spin_phys_addr(void) -{ - extern ulong __secondary_start_page; - extern ulong __spin_table; - - return (determine_mp_bootpg() + - (ulong)&__spin_table - (ulong)&__secondary_start_page); -} - -ulong get_spin_virt_addr(void) +phys_addr_t get_spin_phys_addr(void) { - extern ulong __secondary_start_page; - extern ulong __spin_table; - - return (CONFIG_BPTR_VIRT_ADDR + - (ulong)&__spin_table - (ulong)&__secondary_start_page); + return virt_to_phys(&__spin_table); } #ifdef CONFIG_FSL_CORENET static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) { u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K; - u32 *table = (u32 *)get_spin_virt_addr(); + u32 *table = (u32 *)&__spin_table; volatile ccsr_gur_t *gur; volatile ccsr_local_t *ccm; volatile ccsr_rcpm_t *rcpm; @@ -356,7 +345,7 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) { u32 up, cpu_up_mask, whoami; - u32 *table = (u32 *)get_spin_virt_addr(); + u32 *table = (u32 *)&__spin_table; volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -440,10 +429,11 @@ void cpu_mp_lmb_reserve(struct lmb *lmb) void setup_mp(void) { - extern ulong __secondary_start_page; - extern ulong __bootpg_addr; + extern u32 __secondary_start_page; + extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page; - ulong fixup = (ulong)&__secondary_start_page; + int i; + ulong fixup = (u32)&__secondary_start_page; u32 bootpg, bootpg_map, pagesize; bootpg = determine_mp_bootpg(&pagesize); @@ -464,11 +454,20 @@ void setup_mp(void) if (hold_cores_in_reset(0)) return; - /* Store the bootpg's SDRAM address for use by secondary CPU cores */ - __bootpg_addr = bootpg; + /* + * Store the bootpg's cache-able half address for use by secondary + * CPU cores to continue to boot + */ + __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page); + + /* Store spin table's physical address for use by secondary cores */ + __spin_table_addr = (u32)get_spin_phys_addr(); + + /* flush bootpg it before copying invalidate any staled cacheline */ + flush_cache(bootpg, 4096); /* look for the tlb covering the reset page, there better be one */ - int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); + i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); /* we found a match */ if (i != -1) { diff --git a/arch/powerpc/cpu/mpc85xx/mp.h b/arch/powerpc/cpu/mpc85xx/mp.h index 87bac37152..ad9950bcf5 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.h +++ b/arch/powerpc/cpu/mpc85xx/mp.h @@ -3,8 +3,7 @@ #include -ulong get_spin_phys_addr(void); -ulong get_spin_virt_addr(void); +phys_addr_t get_spin_phys_addr(void); u32 get_my_id(void); int hold_cores_in_reset(int verbose); @@ -16,7 +15,7 @@ int hold_cores_in_reset(int verbose); #define BOOT_ENTRY_PIR 5 #define BOOT_ENTRY_R6_UPPER 6 #define BOOT_ENTRY_R6_LOWER 7 -#define NUM_BOOT_ENTRY 8 +#define NUM_BOOT_ENTRY 16 /* pad to 64 bytes */ #define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32)) #endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index d08b1f3dca..4ba44a9028 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -150,10 +150,14 @@ __secondary_start_page: #define toreset(x) (x - __secondary_start_page + 0xfffff000) /* get our PIR to figure out our table entry */ - lis r3,toreset(__spin_table)@h - ori r3,r3,toreset(__spin_table)@l + lis r3,toreset(__spin_table_addr)@h + ori r3,r3,toreset(__spin_table_addr)@l + lwz r3,0(r3) - /* r10 has the base address for the entry */ + /* + * r10 has the base address for the entry. + * we cannot access it yet before setting up a new TLB + */ mfspr r0,SPRN_PIR #if defined(CONFIG_E6500) /* @@ -180,7 +184,7 @@ __secondary_start_page: #else mr r4,r0 #endif - slwi r8,r4,5 + slwi r8,r4,6 /* spin table is padded to 64 byte */ add r10,r3,r8 #ifdef CONFIG_E6500 @@ -277,73 +281,111 @@ __secondary_start_page: beq 2b #endif 3: - -#define EPAPR_MAGIC (0x45504150) -#define ENTRY_ADDR_UPPER 0 -#define ENTRY_ADDR_LOWER 4 -#define ENTRY_R3_UPPER 8 -#define ENTRY_R3_LOWER 12 -#define ENTRY_RESV 16 -#define ENTRY_PIR 20 -#define ENTRY_R6_UPPER 24 -#define ENTRY_R6_LOWER 28 -#define ENTRY_SIZE 32 - - /* setup the entry */ - li r3,0 - li r8,1 - stw r4,ENTRY_PIR(r10) - stw r3,ENTRY_ADDR_UPPER(r10) - stw r8,ENTRY_ADDR_LOWER(r10) - stw r3,ENTRY_R3_UPPER(r10) - stw r4,ENTRY_R3_LOWER(r10) - stw r3,ENTRY_R6_UPPER(r10) - stw r3,ENTRY_R6_LOWER(r10) - - /* load r13 with the address of the 'bootpg' in SDRAM */ - lis r13,toreset(__bootpg_addr)@h - ori r13,r13,toreset(__bootpg_addr)@l + /* setup mapping for the spin table, WIMGE=0b00100 */ + lis r13,toreset(__spin_table_addr)@h + ori r13,r13,toreset(__spin_table_addr)@l lwz r13,0(r13) + /* mask by 4K */ + rlwinm r13,r13,0,0,19 - /* setup mapping for AS = 1, and jump there */ lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h mtspr SPRN_MAS0,r11 lis r11,(MAS1_VALID|MAS1_IPROT)@h ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr SPRN_MAS1,r11 - oris r11,r13,(MAS2_I|MAS2_G)@h - ori r11,r13,(MAS2_I|MAS2_G)@l + oris r11,r13,(MAS2_M|MAS2_G)@h + ori r11,r13,(MAS2_M|MAS2_G)@l mtspr SPRN_MAS2,r11 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l mtspr SPRN_MAS3,r11 + li r11,0 + mtspr SPRN_MAS7,r11 tlbwe - bl 1f -1: mflr r11 /* - * OR in 0xfff to create a mask of the bootpg SDRAM address. We use - * this mask to fixup the cpu spin table and the address that we want - * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the - * bootpg is at 0x7ffff000 in SDRAM. + * __bootpg_addr has the address of __second_half_boot_page + * jump there in AS=1 space with cache enabled */ - ori r13,r13,0xfff - and r11, r11, r13 - and r10, r10, r13 - - addi r11,r11,(2f-1b) + lis r13,toreset(__bootpg_addr)@h + ori r13,r13,toreset(__bootpg_addr)@l + lwz r11,0(r13) + mtspr SPRN_SRR0,r11 mfmsr r13 ori r12,r13,MSR_IS|MSR_DS@l - - mtspr SPRN_SRR0,r11 mtspr SPRN_SRR1,r12 rfi + /* + * Allocate some space for the SDRAM address of the bootpg. + * This variable has to be in the boot page so that it can + * be accessed by secondary cores when they come out of reset. + */ + .align L1_CACHE_SHIFT + .globl __bootpg_addr +__bootpg_addr: + .long 0 + + .global __spin_table_addr +__spin_table_addr: + .long 0 + + /* + * This variable is set by cpu_init_r() after parsing hwconfig + * to enable workaround for erratum NMG_CPU_A011. + */ + .align L1_CACHE_SHIFT + .global enable_cpu_a011_workaround +enable_cpu_a011_workaround: + .long 1 + + /* Fill in the empty space. The actual reset vector is + * the last word of the page */ +__secondary_start_code_end: + .space 4092 - (__secondary_start_code_end - __secondary_start_page) +__secondary_reset_vector: + b __secondary_start_page + + +/* this is a separated page for the spin table and cacheable boot code */ + .align L1_CACHE_SHIFT + .global __second_half_boot_page +__second_half_boot_page: +#define EPAPR_MAGIC 0x45504150 +#define ENTRY_ADDR_UPPER 0 +#define ENTRY_ADDR_LOWER 4 +#define ENTRY_R3_UPPER 8 +#define ENTRY_R3_LOWER 12 +#define ENTRY_RESV 16 +#define ENTRY_PIR 20 +#define ENTRY_SIZE 64 + /* + * setup the entry + * r10 has the base address of the spin table. + * spin table is defined as + * struct { + * uint64_t entry_addr; + * uint64_t r3; + * uint32_t rsvd1; + * uint32_t pir; + * }; + * we pad this struct to 64 bytes so each entry is in its own cacheline + */ + li r3,0 + li r8,1 + mfspr r4,SPRN_PIR + stw r3,ENTRY_ADDR_UPPER(r10) + stw r3,ENTRY_R3_UPPER(r10) + stw r4,ENTRY_R3_LOWER(r10) + stw r3,ENTRY_RESV(r10) + stw r4,ENTRY_PIR(r10) + msync + stw r8,ENTRY_ADDR_LOWER(r10) + /* spin waiting for addr */ -2: - lwz r4,ENTRY_ADDR_LOWER(r10) +3: lwz r4,ENTRY_ADDR_LOWER(r10) andi. r11,r4,1 - bne 2b + bne 3b isync /* setup IVORs to match fixed offsets */ @@ -362,8 +404,17 @@ __secondary_start_page: /* mask by ~64M to setup our tlb we will jump to */ rlwinm r12,r4,0,0,5 - /* setup r3, r4, r5, r6, r7, r8, r9 */ + /* + * setup r3, r4, r5, r6, r7, r8, r9 + * r3 contains the value to put in the r3 register at secondary cpu + * entry. The high 32-bits are ignored on 32-bit chip implementations. + * 64-bit chip implementations however shall load all 64-bits + */ +#ifdef CONFIG_SYS_PPC64 + ld r3,ENTRY_R3_UPPER(r10) +#else lwz r3,ENTRY_R3_LOWER(r10) +#endif li r4,0 li r5,0 li r6,0 @@ -404,32 +455,10 @@ __secondary_start_page: mtspr SPRN_SRR1,r13 rfi - /* - * Allocate some space for the SDRAM address of the bootpg. - * This variable has to be in the boot page so that it can - * be accessed by secondary cores when they come out of reset. - */ - .globl __bootpg_addr -__bootpg_addr: - .long 0 - .align L1_CACHE_SHIFT + .align 6 .globl __spin_table __spin_table: .space CONFIG_MAX_CPUS*ENTRY_SIZE - - /* - * This variable is set by cpu_init_r() after parsing hwconfig - * to enable workaround for erratum NMG_CPU_A011. - */ - .align L1_CACHE_SHIFT - .global enable_cpu_a011_workaround -enable_cpu_a011_workaround: - .long 1 - - /* Fill in the empty space. The actual reset vector is - * the last word of the page */ -__secondary_start_code_end: - .space 4092 - (__secondary_start_code_end - __secondary_start_page) -__secondary_reset_vector: - b __secondary_start_page +__spin_table_end: + .space 4096 - (__spin_table_end - __spin_table) diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 929f6a607e..a548dec9a7 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -249,7 +249,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; - unsigned int wimge = 0; + unsigned int wimge = MAS2_M; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam; u64 size, memsize = (u64)memsize_in_meg << 20; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 92ca2ad74d..8a7c81b808 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -416,6 +416,7 @@ #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ +#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 @@ -485,6 +486,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_T4240) +#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ @@ -516,6 +518,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_B4860) +#define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ diff --git a/doc/README.mpc85xx-spin-table b/doc/README.mpc85xx-spin-table new file mode 100644 index 0000000000..8da768a2a6 --- /dev/null +++ b/doc/README.mpc85xx-spin-table @@ -0,0 +1,26 @@ +Spin table in cache +===================================== +As specified by ePAPR v1.1, the spin table needs to be in cached memory. After +DDR is initialized and U-boot relocates itself into DDR, the spin table is +accessible for core 0. It is part of release.S, within 4KB range after +__secondary_start_page. For other cores to use the spin table, the booting +process is described below: + +Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory +is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of +the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot +page translation for secondary cores to use this page of memory. Then 4KB +memory is copied from __secondary_start_page to the boot page, after flusing +cache because this page is mapped as normal DDR. Before copying the reset page, +core 0 puts the physical address of the spin table (which is in release.S and +relocated to the top of mapped memory) into a variable __spin_table_addr so +that secondary cores can see it. + +When secondary cores boot up from 0xffff_f000 page, they only have one default +TLB. While booting, they set up another TLB in AS=1 space and jump into +the new space. The new TLB covers the physical address of the spin table page, +with WIMGE =0b00100. Now secondary cores can keep polling the spin table +without stress DDR bus because both the code and the spin table is in cache. + +For the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep +cache coherence. -- cgit v1.2.3 From 98ffa19053f2d10578a227de4e441698226fde0a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:31 +0000 Subject: powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 26 ++++++++++++++++---------- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++++ 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f493483c1e..892bfa4c60 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -60,26 +60,32 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if defined(CONFIG_DDR_CLK_FREQ) || \ - (defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)) +#if (defined(CONFIG_DDR_CLK_FREQ) || \ + defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ -#ifdef CONFIG_DDR_CLK_FREQ - u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) - >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; -#else + + /* + * Cornet platforms use ddr sync bit in RCW to indicate sync vs async + * mode. Previous platform use ddr ratio to do the same. This + * information is only for display here. + */ #ifdef CONFIG_FSL_CORENET - u32 ddr_sync ; #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 - ddr_sync = 0; /* only async mode is supported */ + u32 ddr_sync = 0; /* only async mode is supported */ #else - ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#else /* CONFIG_FSL_CORENET */ +#ifdef CONFIG_DDR_CLK_FREQ + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; -#endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ +#endif /* CONFIG_FSL_CORENET */ + unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f07a28b462..8a8f317f8d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -82,7 +82,11 @@ void get_sys_info (sys_info_t * sysInfo) uint mem_pll_rat; sysInfo->freqSystemBus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ; +#else sysInfo->freqDDRBus = sysclk; +#endif sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> -- cgit v1.2.3 From ee52b188ca2c631427d197056ab7b71b9e23bde7 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 11 Oct 2012 07:13:37 +0000 Subject: powerpc/t4qds: Add T4QDS board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun Signed-off-by: Andy Fleming Signed-off-by: Kumar Gala Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shengzhou Liu Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- board/freescale/t4qds/Makefile | 54 ++ board/freescale/t4qds/ddr.c | 186 +++++++ board/freescale/t4qds/eth.c | 495 +++++++++++++++++++ board/freescale/t4qds/law.c | 47 ++ board/freescale/t4qds/pci.c | 39 ++ board/freescale/t4qds/t4240qds_qixis.h | 56 +++ board/freescale/t4qds/t4qds.c | 395 +++++++++++++++ board/freescale/t4qds/t4qds.h | 37 ++ board/freescale/t4qds/tlb.c | 136 +++++ boards.cfg | 3 + doc/README.t4240qds | 98 ++++ include/configs/T4240QDS.h | 35 ++ include/configs/t4qds.h | 875 +++++++++++++++++++++++++++++++++ 13 files changed, 2456 insertions(+) create mode 100644 board/freescale/t4qds/Makefile create mode 100644 board/freescale/t4qds/ddr.c create mode 100644 board/freescale/t4qds/eth.c create mode 100644 board/freescale/t4qds/law.c create mode 100644 board/freescale/t4qds/pci.c create mode 100644 board/freescale/t4qds/t4240qds_qixis.h create mode 100644 board/freescale/t4qds/t4qds.c create mode 100644 board/freescale/t4qds/t4qds.h create mode 100644 board/freescale/t4qds/tlb.c create mode 100644 doc/README.t4240qds create mode 100644 include/configs/T4240QDS.h create mode 100644 include/configs/t4qds.h diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile new file mode 100644 index 0000000000..ff09ffa51e --- /dev/null +++ b/board/freescale/t4qds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-$(CONFIG_T4240QDS)+= eth.o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c new file mode 100644 index 0000000000..692616aed4 --- /dev/null +++ b/board/freescale/t4qds/ddr.c @@ -0,0 +1,186 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + */ + {4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, + {4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, + {4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, + {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {} +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); + } +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c new file mode 100644 index 0000000000..a49c7d4f15 --- /dev/null +++ b/board/freescale/t4qds/eth.c @@ -0,0 +1,495 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "../common/fman.h" + +#include "t4240qds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII 0 +#define EMI1_SLOT1 1 +#define EMI1_SLOT2 2 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT7 7 +#define EMI2 8 /* tmp, FIXME */ +/* Slot6 and Slot8 do not have EMI connections */ + +static int mdio_mux[NUM_FM_PORTS]; + +static const char *mdio_names[] = { + "T4240QDS_MDIO0", + "T4240QDS_MDIO1", + "T4240QDS_MDIO2", + "T4240QDS_MDIO3", + "T4240QDS_MDIO4", + "T4240QDS_MDIO5", + "NULL", + "T4240QDS_MDIO7", + "T4240QDS_10GC", +}; + +static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; +static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; + +static const char *t4240qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t4240qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct t4240qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void t4240qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if ((muxval < 6) || (muxval == 7)) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t4240qds_mdio *priv = bus->priv; + + t4240qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t4240qds_mdio *priv = bus->priv; + + t4240qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t4240qds_mdio_reset(struct mii_dev *bus) +{ + struct t4240qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t4240qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t4240qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate T4240QDS MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate T4240QDS private data\n"); + free(bus); + return -1; + } + + bus->read = t4240qds_mdio_read; + bus->write = t4240qds_mdio_write; + bus->reset = t4240qds_mdio_reset; + sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + if (mdio_mux[port] == EMI1_RGMII) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); + + /* TODO: will do with dts */ +} + +void fdt_fixup_board_enet(void *fdt) +{ + /* TODO: will do with dts */ +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); + t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + + switch (srds_prtcl_s1) { + case 1: + case 2: + case 4: + /* XAUI/HiGig in Slot1 and Slot2 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + break; + case 28: + case 36: + /* SGMII in Slot1 and Slot2 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, + SGMII_CARD_PORT3_PHY_ADDR); + } + break; + case 38: + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR); + if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + fm_info_set_phy_address(FM1_DTSEC9, + QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, + QSGMII_CARD_PHY_ADDR); + } + break; + case 40: + case 46: + case 48: + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { + fm_info_set_phy_address(FM1_DTSEC10, + SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT4_PHY_ADDR); + } + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR); + break; + default: + puts("Invalid SerDes1 protocol for T4240QDS\n"); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + /* FM1 DTSEC5 routes to RGMII with EC2 */ + debug("FM1@DTSEC%u is RGMII at address %u\n", + idx + 1, 2); + if (i == FM1_DTSEC5) + fm_info_set_phy_address(i, 2); + mdio_mux[i] = EMI1_RGMII; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + +#if (CONFIG_SYS_NUM_FMAN == 2) + switch (srds_prtcl_s2) { + case 1: + case 2: + case 4: + /* XAUI/HiGig in Slot3 and Slot4 */ + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); + break; + case 7: + case 13: + case 14: + case 16: + case 22: + case 23: + case 25: + case 26: + /* XAUI/HiGig in Slot3, SGMII in Slot4 */ + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 28: + case 36: + /* SGMII in Slot3 and Slot4 */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + break; + case 38: + /* QSGMII in Slot3 and Slot4 */ + fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR); + break; + case 40: + case 46: + case 48: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + /* QSGMII in Slot4 */ + fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + break; + case 50: + case 52: + case 54: + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + break; + case 56: + case 57: + /* XFI in Slot3, SGMII in Slot4 */ + fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + puts("Invalid SerDes2 protocol for T4240QDS\n"); + break; + } + + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_2, + SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + debug("FM2@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * If DTSEC5 is RGMII, then it's routed via via EC1 to + * the first on-board RGMII port. If DTSEC6 is RGMII, + * then it's routed via via EC2 to the second on-board + * RGMII port. + */ + debug("FM2@DTSEC%u is RGMII at address %u\n", + idx + 1, i == FM2_DTSEC5 ? 1 : 2); + fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); + mdio_mux[i] = EMI1_RGMII; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c new file mode 100644 index 0000000000..5debcf612a --- /dev/null +++ b/board/freescale/t4qds/law.c @@ -0,0 +1,47 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t4qds/pci.c b/board/freescale/t4qds/pci.c new file mode 100644 index 0000000000..fc00b4ad6d --- /dev/null +++ b/board/freescale/t4qds/pci.c @@ -0,0 +1,39 @@ +/* + * Copyright 2007-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h new file mode 100644 index 0000000000..efb718d2c3 --- /dev/null +++ b/board/freescale/t4qds/t4240qds_qixis.h @@ -0,0 +1,56 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __T4020QDS_QIXIS_H__ +#define __T4020QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T4020QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG5_RESET 0x00 + +#define BRDCFG12_SD3EN_MASK 0x20 +#define BRDCFG12_SD3MX_MASK 0x08 +#define BRDCFG12_SD3MX_SLOT5 0x08 +#define BRDCFG12_SD3MX_SLOT6 0x00 +#define BRDCFG12_SD4EN_MASK 0x04 +#define BRDCFG12_SD4MX_MASK 0x03 +#define BRDCFG12_SD4MX_SLOT7 0x02 +#define BRDCFG12_SD4MX_SLOT8 0x01 +#define BRDCFG12_SD4MX_AURO_SATA 0x00 +#endif diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c new file mode 100644 index 0000000000..88b8cedf48 --- /dev/null +++ b/board/freescale/t4qds/t4qds.c @@ -0,0 +1,395 @@ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "t4qds.h" +#include "t4240qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < MAX_SERDES; i++) { + static const char *freq[] = { + "100", "125", "156.25", "161.1328125"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("SERDES%u=%sMHz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +/* Configure Crossbar switches for Front-Side SerDes Ports */ +int config_frontside_crossbar_vsc3316(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + int ret; + + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); + if (ret) + return ret; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + if (srds_prtcl_s1) { + ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); + if (ret) + return ret; + } + + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + if (srds_prtcl_s2) { + ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); + if (ret) + return ret; + } + + return 0; +} + +int config_backside_crossbar_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s3, srds_prtcl_s4; + u8 brdcfg; + + srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS3_PRTCL; + srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; + switch (srds_prtcl_s3) { + case 0: + /* SerDes3 is not enabled */ + break; + case 2: + case 9: + case 10: + /* SD3(0:7) => SLOT5(0:7) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD3MX_MASK; + brdcfg |= BRDCFG12_SD3MX_SLOT5; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 4: + case 6: + case 8: + case 12: + case 14: + case 16: + case 17: + case 19: + case 20: + /* SD3(4:7) => SLOT6(0:3) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD3MX_MASK; + brdcfg |= BRDCFG12_SD3MX_SLOT6; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + default: + printf("WARNING: unsupported for SerDes3 Protocol %d\n", + srds_prtcl_s3); + return -1; + } + + srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS4_PRTCL; + srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; + switch (srds_prtcl_s4) { + case 0: + /* SerDes4 is not enabled */ + break; + case 2: + /* 10b, SD4(0:7) => SLOT7(0:7) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_SLOT7; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 4: + case 6: + case 8: + /* x1b, SD4(4:7) => SLOT8(0:3) */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_SLOT8; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + case 10: + case 12: + case 14: + case 16: + case 18: + /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ + brdcfg = QIXIS_READ(brdcfg[12]); + brdcfg &= ~BRDCFG12_SD4MX_MASK; + brdcfg |= BRDCFG12_SD4MX_AURO_SATA; + QIXIS_WRITE(brdcfg[12], brdcfg); + break; + default: + printf("WARNING: unsupported for SerDes4 Protocol %d\n", + srds_prtcl_s4); + return -1; + } + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Disable remote I2C connectoin */ + QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET); + + /* Configure board SERDES ports crossbar */ + config_frontside_crossbar_vsc3316(); + config_backside_crossbar_mux(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328125"; + default: + return "???"; + } +} + +int misc_init_r(void) +{ + u8 sw; + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[MAX_SERDES]; + unsigned int i; + + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < MAX_SERDES; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + case 3: + actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; + break; + } + } + + for (i = 0; i < MAX_SERDES; i++) { + u32 pllcr0 = srds_regs->bank[i].pllcr0; + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES%u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h new file mode 100644 index 0000000000..c6a3492cb6 --- /dev/null +++ b/board/freescale/t4qds/t4qds.h @@ -0,0 +1,37 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, + {8, 8}, {9, 9}, {14, 14}, {15, 15} }; + +static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, + {10, 10}, {11, 11}, {12, 12}, {13, 13} }; + +static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, + {10, 11}, {11, 10}, {12, 2}, {13, 3} }; + +static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, + {8, 9}, {9, 8}, {14, 1}, {15, 0} }; +#endif diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c new file mode 100644 index 0000000000..078a6e415c --- /dev/null +++ b/board/freescale/t4qds/tlb.c @@ -0,0 +1,136 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_1M, 1), +#endif + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 83e7084de7..3e19647783 100644 --- a/boards.cfg +++ b/boards.cfg @@ -838,6 +838,9 @@ BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freesca stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M +T4240QDS powerpc mpc85xx t4qds freescale +T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 xpedite520x powerpc mpc85xx - xes xpedite537x powerpc mpc85xx - xes xpedite550x powerpc mpc85xx - xes diff --git a/doc/README.t4240qds b/doc/README.t4240qds new file mode 100644 index 0000000000..677d120a80 --- /dev/null +++ b/doc/README.t4240qds @@ -0,0 +1,98 @@ +Overview +-------- +The T4240QDS is a high-performance computing evaluation, development and test +platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is +optimized to support the high-bandwidth DDR3 memory ports, as well as the +highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. + +Board Features + SERDES Connections + 32 lanes grouped into four 8-lane banks + Two “front side” banks dedicated to Ethernet + - High-speed crosspoint switch fabric on selected lanes + - Two PCI Express slots with side-band connector supporting + - SGMII + - XAUI + - HiGig + - I-pass connectors allow board-to-board and loopback support + Two “back side” banks dedicated to other protocols + - High-speed crosspoint switch fabric on all lanes + - Four PCI Express slots with side-band connector supporting + - PCI Express 3.0 + - SATA 2.0 + - SRIO 2.0 + - Supports 4X Aurora debug with two connectors + DDR Controllers + Three independant 64-bit DDR3 controllers + Supports rates of 1866 up to 2133 MHz data-rate + Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller + DDR power supplies 1.5V to all devices with automatic tracking of VTT. + Power software-switchable to 1.35V if software detects all DDR3LP devices. + MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and + 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time + increases by 1 clock. + + IFC/Local Bus + NAND flash: 8-bit, async or sync, up to 2GB. + NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB + NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB + - NOR devices support 16 virtual banks + GASIC: Minimal target within Qixis FPGA + PromJET rapid memory download support + Address demultiplexing handled within FPGA. + - Flexible demux allows 8 or 16 bit evaluation. + IFC Debug/Development card + - Support for 32-bit devices + Ethernet + Support two on-board RGMII 10/100/1G ethernet ports. + SGMII and XAUI support via SERDES block (see above). + 1588 support via Symmetricom board. + QIXIS System Logic FPGA + Manages system power and reset sequencing + Manages DUT, board, clock, etc. configuration for dynamic shmoo + Collects V-I-T data in background for code/power profiling. + Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) + General fault monitoring and logging + Runs from ATX “hot” power rails allowing operation while system is off. + Clocks + System and DDR clock (SYSCLK, “DDRCLK”) + - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. + - Software selectable in 1MHz increments from 1-200MHz. + SERDES clocks + - Provides clocks to all SerDes blocks and slots + - 100, 125 and 156.25 MHz + Power Supplies + Dedicated regulators for VDD + - Adjustable from (0.7V to 1.3V at 80A + - Regulators can be controlled by VID and/or software + Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A + - VTT/MVREF automatically track operating voltage + Dedicated regulators/filters for AVDD supplies + Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. + USB + Supports two USB 2.0 ports with integrated PHYs + - One type A, one type micro-AB with 1.0A power per port. + Other IO + eSDHC/MMC + - SDHC card slot + eSPI port + - High-speed serial flash + Two Serial port + Four I2C ports + +Memory map +---------- +The addresses in brackets are physical addresses. + +0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) +0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory +0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff 4MB DCSR +0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan +0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan +0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO +0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash +0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR +0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS +0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores + +The physical address of the last (boot page translation) varies with the actual DDR size. diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h new file mode 100644 index 0000000000..76b3ca6898 --- /dev/null +++ b/include/configs/T4240QDS.h @@ -0,0 +1,35 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * T4240 QDS board configuration file + */ +#define CONFIG_T4240QDS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_T4240 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "t4qds.h" diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h new file mode 100644 index 0000000000..d58c24c4aa --- /dev/null +++ b/include/configs/t4qds.h @@ -0,0 +1,875 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Corenet DS style board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +#define CONFIG_CMD_REGINFO + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E6500 +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1097) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif +#else /* CONFIG_SYS_NO_FLASH */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + + + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#if 0 +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#endif +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + +#define CONFIG_DDR_SPD +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ + FTIM0_NOR_TEADC(0x01) | \ + FTIM0_NOR_TEAHC(0x20)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ + FTIM2_NOR_TCH(0x0E) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#ifdef CONFIG_PHYS_64BIT +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) +#else +#define QIXIS_BASE_PHYS QIXIS_BASE +#endif + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C2_OFFSET 0x118100 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +/* VSC Crossbar switches */ +#define CONFIG_VSC_CROSSBAR +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VSC3316_FS 0xc +#define I2C_MUX_CH_VSC3316_BS 0xd +#define VSC3316_FSM_TX_ADDR 0x70 +#define VSC3316_FSM_RX_ADDR 0x71 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ + +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ + +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_TERANETICS +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */ +#define XFI_CARD_PORT2_PHY_ADDR 0x2 +#define XFI_CARD_PORT3_PHY_ADDR 0x3 +#define XFI_CARD_PORT4_PHY_ADDR 0x4 +#define QSGMII_CARD_PHY_ADDR 0x5 +#define FM1_10GEC1_PHY_ADDR 0x6 +#define FM1_10GEC2_PHY_ADDR 0x7 +#define FM2_10GEC1_PHY_ADDR 0x8 +#define FM2_10GEC2_PHY_ADDR 0x9 +#endif + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t4240qds/t4240qds.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +/* For emulation this causes u-boot to jump to the start of the proof point + app code automatically */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#endif + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From b0e8115741cbba252e64f3b4e81799de57248a26 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 11 Oct 2012 07:13:38 +0000 Subject: mpc85xx/portals: Add qman and bman ip_cfg field into portal info Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the total portal number, buffer pool number etc, we can use this info to limit those resources in kernel driver. Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/portals.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 6199633541..b59ef69f1f 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -182,14 +182,18 @@ void fdt_fixup_qportals(void *blob) { int off, err; unsigned int maj, min; + unsigned int ip_cfg; u32 rev_1 = in_be32(&qman->ip_rev_1); + u32 rev_2 = in_be32(&qman->ip_rev_2); char compat[64]; int compat_len; maj = (rev_1 >> 8) & 0xff; min = rev_1 & 0xff; + ip_cfg = rev_2 & 0xff; - compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1; + compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u", + maj, min, ip_cfg) + 1; compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1; off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); @@ -267,14 +271,19 @@ void fdt_fixup_bportals(void *blob) { int off, err; unsigned int maj, min; + unsigned int ip_cfg; u32 rev_1 = in_be32(&bman->ip_rev_1); + u32 rev_2 = in_be32(&bman->ip_rev_2); char compat[64]; int compat_len; maj = (rev_1 >> 8) & 0xff; min = rev_1 & 0xff; - compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1; + ip_cfg = rev_2 & 0xff; + + compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u", + maj, min, ip_cfg) + 1; compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1; off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal"); -- cgit v1.2.3 From 990e1a8ce1415b9010faccd1402d499e203ea2fb Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 11 Oct 2012 07:13:39 +0000 Subject: poweprc/85xx: add QMan frequency info and fdt fixup. Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel driver can use it to calculate the shaper prescaler and rate. Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 ++++ arch/powerpc/cpu/mpc85xx/fdt.c | 5 +++++ arch/powerpc/cpu/mpc85xx/speed.c | 4 ++++ include/e500.h | 3 +++ 4 files changed, 16 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 892bfa4c60..db232e64f8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -217,6 +217,10 @@ int checkcpu (void) } #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); +#endif + #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index a364ef216a..ab0933076d 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -411,6 +411,11 @@ static void ft_fixup_dpaa_clks(void *blob) #endif #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + do_fixup_by_compat_u32(blob, "fsl,qman", + "clock-frequency", sysinfo.freqQMAN, 1); +#endif + #ifdef CONFIG_SYS_DPAA_PME do_fixup_by_compat_u32(blob, "fsl,pme", "clock-frequency", sysinfo.freqPME, 1); diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 8a8f317f8d..801ee078c0 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -167,6 +167,10 @@ void get_sys_info (sys_info_t * sysInfo) } #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + sysInfo->freqQMAN = sysInfo->freqSystemBus / 2; +#endif + #ifdef CONFIG_SYS_DPAA_FMAN switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: diff --git a/include/e500.h b/include/e500.h index e1708b9dc9..0ff8e89a1e 100644 --- a/include/e500.h +++ b/include/e500.h @@ -18,6 +18,9 @@ typedef struct #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freqFMan[CONFIG_SYS_NUM_FMAN]; #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freqQMAN; +#endif #ifdef CONFIG_SYS_DPAA_PME unsigned long freqPME; #endif -- cgit v1.2.3 From 1f3bd3e239fb0542128f7c911829c9f0360b0d8f Mon Sep 17 00:00:00 2001 From: shaohui xie Date: Thu, 11 Oct 2012 20:25:36 +0000 Subject: powerpc/fm: fix TBI PHY address settings TBI PHY address (TBIPA) register is set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1 isn't used directly, which provides MDIO for other ports. So following code is wrong in case of FM2, which has a different mac base. struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; /* Assign a Physical address to the TBI */ out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); Signed-off-by: Shaohui Xie Signed-off-by: Andy Fleming --- drivers/net/fm/eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index ed23fdd4ac..82c787bf38 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -89,9 +89,9 @@ void dtsec_configure_serdes(struct fm_eth *priv) static void dtsec_init_phy(struct eth_device *dev) { struct fm_eth *fm_eth = dev->priv; - #ifndef CONFIG_SYS_FMAN_V3 - struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; + struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + /* Assign a Physical address to the TBI */ out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); #endif -- cgit v1.2.3 From 9905757e298f37c59587d1a07b1ad8cdbed4e063 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 11 Oct 2012 20:31:46 +0000 Subject: powerpc/espi: remove write command length check Current espi controller driver assumes the command length of write command is not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash driver such as SST does use write command length as '1', so write command on SST SPI flash will not work. And the length check for write command is not necessary for SPANSION, though it's harmless for SPANSION, it will stop write operation on flashes like SST, so we remove the check. Signed-off-by: Shaohui Xie Signed-off-by: Andy Fleming --- drivers/spi/fsl_espi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index a1ebd330d7..eb99e90bec 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -216,10 +216,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, return 1; } memcpy(buffer, cmd_buf, cmd_len); - if (cmd_len != 1) { - if (data_in == NULL) - memcpy(buffer + cmd_len, data_out, data_len); - } + if (data_in == NULL) + memcpy(buffer + cmd_len, data_out, data_len); break; case SPI_XFER_BEGIN | SPI_XFER_END: len = data_len; -- cgit v1.2.3 From d8812bdbba21eefdf773ab3a42dcdf966d68ab92 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 12 Oct 2012 02:34:15 +0000 Subject: phylib: Enable SMSC LAN87xx PHY support LAN8720 PHY is used on Freescale C2X0QDS board. Signed-off-by: Mingkai Hu Signed-off-by: Andy Fleming --- include/config_phylib_all_drivers.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h index 1db7cec209..12828c67e3 100644 --- a/include/config_phylib_all_drivers.h +++ b/include/config_phylib_all_drivers.h @@ -23,6 +23,7 @@ #define CONFIG_PHY_NATSEMI #define CONFIG_PHY_LXT #define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_SMSC #ifdef CONFIG_PHYLIB_10G #define CONFIG_PHY_TERANETICS -- cgit v1.2.3 From 19e4a00965f03d5d64af00b7b4258dff43e57d17 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Sun, 14 Oct 2012 20:55:17 +0000 Subject: powerpc/boot: Change the compile macro for SRIO & PCIE boot master module Currently, the SRIO and PCIE boot master module will be compiled into the u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this macro has been included by all the corenet architecture platform boards. But in fact, it's uncertain whether all corenet platform boards support this feature. So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add a special macro for every board which can support the feature. This special macro will be defined in the header file "arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO and PCIE boot master module should be compiled into the board u-boot image. Signed-off-by: Liu Gang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc8xxx/srio.c | 4 +++- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++++ drivers/pci/fsl_pci_init.c | 6 +++--- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e82c9517fe..736293c41d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -524,7 +524,7 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER char *s = getenv("bootmaster"); if (s) { if (!strcmp(s, "SRIO1")) { diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index d4f8ecee9b..6e6f7dcc3f 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -24,6 +24,7 @@ #include #include +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 #define SRIO_OB_ATMU_AR_MAINT 0x80077000 @@ -32,6 +33,7 @@ #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ #define SRIO_LCSBA1CSR 0x60000000 +#endif #if defined(CONFIG_FSL_CORENET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 @@ -297,7 +299,7 @@ void srio_init(void) } } -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER void srio_boot_master(int port) { struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8a7c81b808..03baaee1b7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -334,6 +334,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -365,6 +366,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -405,6 +407,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -436,6 +439,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index e8eb9d6db7..48ae16374d 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER static void fsl_pcie_boot_master(pit_t *pi) { /* configure inbound window for slave's u-boot image */ @@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* see if we are a PCIe or PCI controller */ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ char *s = getenv("bootmaster"); char pcie[6]; @@ -602,7 +602,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); hose->last_busno = hose->first_busno; -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER } else { /* boot from PCIE --master releases slave's core 0 */ char *s = getenv("bootmaster"); -- cgit v1.2.3 From 23028d69e950023a3cb605751dbcb1e314be8b36 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 22 Oct 2012 17:28:18 -0500 Subject: 85xx: Protect timeout_save variable with ifdefs The timeout_save variable was only used by the DDR111_134 erratum code. It was being set, but never used. Newer compilers will actually complain about this. Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 21840bfc2a..f118dd5daf 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -22,8 +22,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, volatile ccsr_ddr_t *ddr; u32 temp_sdram_cfg; u32 total_gb_size_per_controller; - int timeout, timeout_save; + int timeout; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + int timeout_save; volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; int csn = -1; @@ -305,7 +306,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / (get_ddr_freq(0) >> 20)) << 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 timeout_save = timeout; +#endif total_gb_size_per_controller >>= 4; /* shift down to gb size */ debug("total %d GB\n", total_gb_size_per_controller); debug("Need to wait up to %d * 10ms\n", timeout); -- cgit v1.2.3 From 3f0be8ea9217311ec41156fd89e3e23a0308f3b2 Mon Sep 17 00:00:00 2001 From: Pankaj Bharadiya Date: Thu, 13 Sep 2012 09:38:16 +0000 Subject: USB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY The endpoint rx count register value will be zero if it is read before receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set. Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before reading endpoint rx count register. Proceed with rx count read and FIFO read only if RXPKTRDY bit is set. Signed-off-by: Pankaj Bharadiya Signed-off-by: Tom Rini --- drivers/usb/musb/musb_udc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c index 09cdec31a9..e0b4217dc3 100644 --- a/drivers/usb/musb/musb_udc.c +++ b/drivers/usb/musb/musb_udc.c @@ -640,8 +640,17 @@ static void musb_peri_ep0(void) static void musb_peri_rx_ep(unsigned int ep) { - u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount); + u16 peri_rxcount; + u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr); + if (!(peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) { + if (debug_level > 0) + serial_printf("ERROR : %s %d without MUSB_RXCSR_RXPKTRDY set\n", + __PRETTY_FUNCTION__, ep); + return; + } + + peri_rxcount = readw(&musbr->ep[ep].epN.rxcount); if (peri_rxcount) { struct usb_endpoint_instance *endpoint; u32 length; -- cgit v1.2.3 From 391a741162861a887fd226e53048aad2daed62fd Mon Sep 17 00:00:00 2001 From: Joel A Fernandes Date: Tue, 25 Sep 2012 06:49:47 +0000 Subject: am33xx: Enable DDR3 for DDR3 version of beaglebone DDR3 support is tested and working with beaglebone hardware. Include a check for this board type and configure DDR3. The timings and other configuration match EVM SK. Signed-off-by: Joel A Fernandes Acked-by: Jason Kridner --- arch/arm/cpu/armv7/am33xx/board.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 978b184fb2..6de03fd657 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -64,6 +64,11 @@ static inline int board_is_bone(void) return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); } +static inline int board_is_bone_lt(void) +{ + return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); +} + static inline int board_is_evm_sk(void) { return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); @@ -124,7 +129,7 @@ static int read_eeprom(void) static short inline board_memory_type(void) { /* The following boards are known to use DDR3. */ - if (board_is_evm_sk()) + if (board_is_evm_sk() || board_is_bone_lt()) return EMIF_REG_SDRAM_TYPE_DDR3; return EMIF_REG_SDRAM_TYPE_DDR2; @@ -285,7 +290,7 @@ int board_eth_init(bd_t *bis) return -1; } - if (board_is_bone()) { + if (board_is_bone() || board_is_bone_lt()) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; -- cgit v1.2.3 From 669681104daac2bfbdc733d7426b19e358eced8a Mon Sep 17 00:00:00 2001 From: Andrew Bradford Date: Mon, 1 Oct 2012 05:06:52 +0000 Subject: configs: Fix usage of mmc rescan Fix usage of 'mmc rescan' by many configs. Proper use is 'mmc dev ${mmcdev}; mmc rescan' to set the mmc device and then rescan the device. 'mmc rescan' itself does not take any arguments. Signed-off-by: Andrew Bradford --- include/configs/am335x_evm.h | 2 +- include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/devkit8000.h | 2 +- include/configs/igep00x0.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53ard.h | 2 +- include/configs/mx53evk.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx53smd.h | 2 +- include/configs/mx6qarm2.h | 2 +- include/configs/mx6qsabrelite.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap4_common.h | 2 +- include/configs/omap5_evm.h | 2 +- include/configs/tricorder.h | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 339d4bdb63..9d807391ba 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -81,7 +81,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootenv; then " \ "echo Loaded environment from ${bootenv};" \ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 8ddeff46f4..20a3df5db2 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -209,7 +209,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 698081100e..ce71d1335c 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -206,7 +206,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 46c556ddc8..6f355c7af0 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -231,7 +231,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 1e658067e0..da3263f4f5 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -233,7 +233,7 @@ "dhcp ${loadaddr}; " \ "run netargs; " \ "bootm ${loadaddr}\0" \ - "autoboot=if mmc rescan ${mmcdev}; then " \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index b1071e892c..c81ab7622e 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -180,7 +180,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootenv; then " \ "run importbootenv;" \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 7cdbec68de..e188f029c7 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -313,7 +313,7 @@ "dhcp ${uimage}; bootm\0" #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 34b07831cb..dcae53786b 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -182,7 +182,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index fea93b4dc0..62cb42bc4c 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -119,7 +119,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 832050ea97..69937d834e 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -132,7 +132,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 6a6aaa1923..55efeb741c 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -140,7 +140,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index ff2a290d7a..9e8331970c 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -118,7 +118,7 @@ "dhcp ${uimage}; bootm\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 965bea37ca..fbc51625ba 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -106,7 +106,7 @@ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index e7bf6582c3..ec9ab26493 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -164,7 +164,7 @@ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev};" \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index f79f996450..7a3cc16a09 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -289,7 +289,7 @@ "userbutton_nonxm=gpio input 7;\0" /* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run userbutton; then " \ "setenv bootenv uEnv.txt;" \ "else " \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 632a13fa9f..f6e4236998 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -162,7 +162,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index b975a6c9a4..b2457d0bc6 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -202,7 +202,7 @@ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ - "autoboot=if mmc rescan ${mmcdev}; then " \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index f6d6f75fca..626cf7afd5 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -188,7 +188,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 891e6f4363..e152055a64 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -198,7 +198,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index cbc9bdb402..a32369af32 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -165,7 +165,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 743edfdcc5..623da777fa 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -167,7 +167,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc rescan ${mmcdev}; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 00d02e8ca0..5859a7337b 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -201,7 +201,7 @@ "run nandargs; " \ "run loaduimage_ubi; " \ "bootm ${loadaddr}\0" \ - "autoboot=if mmc rescan ${mmcdev}; then " \ + "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ -- cgit v1.2.3 From 3530a35d747508e98976a1d86a6d3f9b31cb3fd2 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Sun, 7 Oct 2012 01:17:34 +0000 Subject: cm-t35: clean unused defines from config Neither cm-t35, nor cm-t3730 is using OneNAND or flash. Remove the related defines from config file. Signed-off-by: Igor Grinberg --- include/configs/cm_t35.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 6f355c7af0..568ae8e097 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -289,25 +289,15 @@ */ /* **** PISMO SUPPORT *** */ - /* Configure the PISMO */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE -#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_ENV_IS_IN_NAND -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ - #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -- cgit v1.2.3 From 91eb52ade2d929015a86ade10314908c1a74973e Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:05 +0000 Subject: cosmetic: suvd3: align #defines Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- include/configs/km/km8321-common.h | 2 +- include/configs/suvd3.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 580b72f4e7..8ad6fc3a33 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -115,7 +115,7 @@ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index ae197018b8..68680c5f9c 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -33,9 +33,9 @@ #include "km/km8321-common.h" #define CONFIG_SYS_APP1_BASE 0xA0000000 -#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ #define CONFIG_SYS_APP2_BASE 0xB0000000 -#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ +#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -- cgit v1.2.3 From 4b5282de99291c31e0afe4b44e805395fadd7c8f Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:06 +0000 Subject: cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) for qe variables with #if defined(CONFIG_QE) Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/speed.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index f78099d2fe..33835682a8 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -127,7 +127,7 @@ int get_clocks(void) #if defined(CONFIG_MPC8360) u32 mem_sec_clk; #endif -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_QE) u32 qepmf; u32 qepdf; u32 qe_clk; @@ -444,7 +444,7 @@ int get_clocks(void) return -13; } -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_QE) qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT; qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT; qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); @@ -479,7 +479,7 @@ int get_clocks(void) #if defined(CONFIG_MPC8360) gd->mem_sec_clk = mem_sec_clk; #endif -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_QE) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif @@ -523,7 +523,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) printf("Clock configuration:\n"); printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk)); printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) +#if defined(CONFIG_QE) printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); #endif -- cgit v1.2.3 From 8afad91f15880d34c7456159209b26918977c400 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:07 +0000 Subject: cleanup: introduce CONFIG_MPC830x Introduce a new configuration token CONFIG_MPC830x to be shared among mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor existing common code so to make future introduction of 8309 simpler. Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/speed.c | 3 +++ arch/powerpc/include/asm/immap_83xx.h | 4 ++-- include/configs/MPC8308RDB.h | 1 + include/configs/mpc8308_p1m.h | 1 + include/mpc83xx.h | 2 +- 5 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 33835682a8..4ad3ec3382 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -185,7 +185,10 @@ int get_clocks(void) /* unkown SCCR_TSEC1CM value */ return -2; } +#endif +#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 2ba502ad11..b7d4c59db1 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -73,8 +73,8 @@ typedef struct sysconf83xx { u32 obir; /* Output Buffer Impedance Register */ u8 res8[0xC]; u32 pecr1; /* PCI Express control register 1 */ -#ifdef CONFIG_MPC8308 - u32 sdhccr; /* eSDHC Control Registers for MPC8308 */ +#if defined(CONFIG_MPC830x) + u32 sdhccr; /* eSDHC Control Registers for MPC830x */ #else u32 pecr2; /* PCI Express control register 2 */ #endif diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index a1fbece8e8..95a1885ace 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -30,6 +30,7 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 035a1b6798..aa681f0628 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -30,6 +30,7 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ #define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index a78f1a223f..7a19740302 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -969,7 +969,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 -- cgit v1.2.3 From a88731a6c23113c713351847d019d23df46f26d7 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:08 +0000 Subject: mpc83xx: add support for mpc8309 This processor, though very similar to other members of the PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides yet another feature set than any supported sibling. Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/cpu.c | 1 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 3 + arch/powerpc/cpu/mpc83xx/speed.c | 16 ++++ arch/powerpc/include/asm/global_data.h | 2 + arch/powerpc/include/asm/immap_83xx.h | 61 +++++++++++++ arch/powerpc/include/asm/immap_qe.h | 2 +- drivers/qe/qe.c | 21 +++-- include/mpc83xx.h | 153 +++++++++++++++++++++++++++++++++ 8 files changed, 249 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 663510987d..e64b0c3411 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -56,6 +56,7 @@ int checkcpu(void) u32 partid; } cpu_type_list [] = { CPU_TYPE_ENTRY(8308), + CPU_TYPE_ENTRY(8309), CPU_TYPE_ENTRY(8311), CPU_TYPE_ENTRY(8313), CPU_TYPE_ENTRY(8314), diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 76afba5dd2..20d06003e5 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -268,6 +268,9 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SICRL __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); #endif +#ifdef CONFIG_SYS_GPR1 + __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); +#endif #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 4ad3ec3382..fb0f7aad6d 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -105,6 +105,8 @@ int get_clocks(void) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; +#elif defined(CONFIG_MPC8309) + u32 usbdr_clk; #endif #ifdef CONFIG_MPC834x u32 usbmph_clk; @@ -120,7 +122,9 @@ int get_clocks(void) #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif +#if !defined(CONFIG_MPC8309) u32 enc_clk; +#endif u32 lbiu_clk; u32 lclk_clk; u32 mem_clk; @@ -263,6 +267,7 @@ int get_clocks(void) return -6; } #endif +#if !defined(CONFIG_MPC8309) switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: enc_clk = 0; @@ -280,6 +285,7 @@ int get_clocks(void) /* unkown SCCR_ENCCM value */ return -7; } +#endif #if defined(CONFIG_FSL_ESDHC) switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { @@ -332,6 +338,8 @@ int get_clocks(void) i2c1_clk = sdhc_clk; #elif defined(CONFIG_MPC837x) i2c1_clk = enc_clk; +#elif defined(CONFIG_MPC8309) + i2c1_clk = csb_clk; #endif #if !defined(CONFIG_MPC832x) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ @@ -460,6 +468,8 @@ int get_clocks(void) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbdr_clk = usbdr_clk; +#elif defined(CONFIG_MPC8309) + gd->usbdr_clk = usbdr_clk; #endif #if defined(CONFIG_MPC834x) gd->usbmph_clk = usbmph_clk; @@ -475,7 +485,9 @@ int get_clocks(void) #if !defined(CONFIG_MPC832x) gd->i2c2_clk = i2c2_clk; #endif +#if !defined(CONFIG_MPC8309) gd->enc_clk = enc_clk; +#endif gd->lbiu_clk = lbiu_clk; gd->lclk_clk = lclk_clk; gd->mem_clk = mem_clk; @@ -536,7 +548,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_MPC8360) printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk)); #endif +#if !defined(CONFIG_MPC8309) printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk)); +#endif printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk)); #if !defined(CONFIG_MPC832x) printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk)); @@ -552,6 +566,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk)); printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk)); printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); +#elif defined(CONFIG_MPC8309) + printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); #endif #if defined(CONFIG_MPC834x) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 374fc6d5ab..cb3a80bb2b 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -63,6 +63,8 @@ typedef struct global_data { u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; +#elif defined(CONFIG_MPC8309) + u32 usbdr_clk; #endif #if defined (CONFIG_MPC834x) u32 usbmph_clk; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index b7d4c59db1..679832cd6c 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -78,7 +78,14 @@ typedef struct sysconf83xx { #else u32 pecr2; /* PCI Express control register 2 */ #endif +#if defined(CONFIG_MPC8309) + u32 can_dbg_ctrl; + u32 res9a; + u32 gpr1; + u8 res9b[0xAC]; +#else u8 res9[0xB8]; +#endif } sysconf83xx_t; /* @@ -708,7 +715,11 @@ typedef struct serdes83xx { * On Chip ROM */ typedef struct rom83xx { +#if defined(CONFIG_MPC8309) + u8 mem[0x8000]; +#else u8 mem[0x10000]; +#endif } rom83xx_t; /* @@ -972,6 +983,56 @@ typedef struct immap { u8 res8[0xC0000]; u8 qe[0x100000]; /* QE block */ } immap_t; +#elif defined(CONFIG_MPC8309) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[2]; /* General purpose I/O module */ + u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */ + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + qepio83xx_t qepio; /* QE Parallel I/O ports */ + u8 res1[0x800]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x200]; + duart83xx_t duart1[2]; /* DUART */ + u8 res4[0x500]; + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ + u8 res5[0x1000]; + u8 spi[0x100]; + u8 res6[0xf00]; + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */ + u8 res7[0x80]; + ios83xx_t ios; /* Sequencer (IOS) */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */ + u8 res8[0x13A00]; + u8 can1[0x1000]; /* Flexcan 1 */ + u8 can2[0x1000]; /* Flexcan 2 */ + u8 res9[0x5000]; + usb83xx_t usb; + u8 res10[0x5000]; + u8 can3[0x1000]; /* Flexcan 3 */ + u8 can4[0x1000]; /* Flexcan 4 */ + u8 res11[0x1000]; + u8 dma1[0x2000]; /* DMA */ + sdhc83xx_t sdhc; /* SDHC Controller */ + u8 res12[0xC1000]; + rom83xx_t rom; /* On Chip ROM */ + u8 res13[0x8000]; + u8 qe[0x100000]; /* QE block */ + u8 res14[0xE00000];/* Added for 8309 */ +} immap_t; #endif #define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000) diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 9be9dca1f7..f0b989a3b0 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -20,7 +20,7 @@ #define QE_MURAM_SIZE 0xc000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC832x) +#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309) #define QE_MURAM_SIZE 0x4000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 9f711519ed..345587be63 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -113,18 +113,21 @@ static void qe_sdma_init(void) * we just need to know what the SNUMs are for the threads. */ static u8 thread_snum[] = { +/* Evthreads 16-29 are not supported in MPC8309 */ +#if !defined(CONFIG_MPC8309) 0x04, 0x05, 0x0c, 0x0d, 0x14, 0x15, 0x1c, 0x1d, 0x24, 0x25, 0x2c, 0x2d, - 0x34, 0x35, 0x88, 0x89, - 0x98, 0x99, 0xa8, 0xa9, - 0xb8, 0xb9, 0xc8, 0xc9, - 0xd8, 0xd9, 0xe8, 0xe9, - 0x08, 0x09, 0x18, 0x19, - 0x28, 0x29, 0x38, 0x39, - 0x48, 0x49, 0x58, 0x59, - 0x68, 0x69, 0x78, 0x79, - 0x80, 0x81 + 0x34, 0x35, +#endif + 0x88, 0x89, 0x98, 0x99, + 0xa8, 0xa9, 0xb8, 0xb9, + 0xc8, 0xc9, 0xd8, 0xd9, + 0xe8, 0xe9, 0x08, 0x09, + 0x18, 0x19, 0x28, 0x29, + 0x38, 0x39, 0x48, 0x49, + 0x58, 0x59, 0x68, 0x69, + 0x78, 0x79, 0x80, 0x81 }; static void qe_snums_init(void) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 7a19740302..b295d6d71b 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -74,6 +74,7 @@ #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) #define SPR_8308 0x8100 +#define SPR_8309 0x8110 #define SPR_831X_FAMILY 0x80B #define SPR_8311 0x80B2 #define SPR_8313 0x80B0 @@ -389,6 +390,86 @@ #define SICRH_TSOBI1_V2P5 (1 << 1) #define SICRH_TSOBI2_V3P3 (0 << 0) #define SICRH_TSOBI2_V2P5 (1 << 0) + +#elif defined(CONFIG_MPC8309) +/* SICR_1 */ +#define SICR_1_UART1_UART1S (0 << (30-2)) +#define SICR_1_UART1_UART1RTS (1 << (30-2)) +#define SICR_1_I2C_I2C (0 << (30-4)) +#define SICR_1_I2C_CKSTOP (1 << (30-4)) +#define SICR_1_IRQ_A_IRQ (0 << (30-6)) +#define SICR_1_IRQ_A_MCP (1 << (30-6)) +#define SICR_1_IRQ_B_IRQ (0 << (30-8)) +#define SICR_1_IRQ_B_CKSTOP (1 << (30-8)) +#define SICR_1_GPIO_A_GPIO (0 << (30-10)) +#define SICR_1_GPIO_A_SD (2 << (30-10)) +#define SICR_1_GPIO_A_DDR (3 << (30-10)) +#define SICR_1_GPIO_B_GPIO (0 << (30-12)) +#define SICR_1_GPIO_B_SD (2 << (30-12)) +#define SICR_1_GPIO_B_QE (3 << (30-12)) +#define SICR_1_GPIO_C_GPIO (0 << (30-14)) +#define SICR_1_GPIO_C_CAN (1 << (30-14)) +#define SICR_1_GPIO_C_DDR (2 << (30-14)) +#define SICR_1_GPIO_C_LCS (3 << (30-14)) +#define SICR_1_GPIO_D_GPIO (0 << (30-16)) +#define SICR_1_GPIO_D_CAN (1 << (30-16)) +#define SICR_1_GPIO_D_DDR (2 << (30-16)) +#define SICR_1_GPIO_D_LCS (3 << (30-16)) +#define SICR_1_GPIO_E_GPIO (0 << (30-18)) +#define SICR_1_GPIO_E_CAN (1 << (30-18)) +#define SICR_1_GPIO_E_DDR (2 << (30-18)) +#define SICR_1_GPIO_E_LCS (3 << (30-18)) +#define SICR_1_GPIO_F_GPIO (0 << (30-20)) +#define SICR_1_GPIO_F_CAN (1 << (30-20)) +#define SICR_1_GPIO_F_CK (2 << (30-20)) +#define SICR_1_USB_A_USBDR (0 << (30-22)) +#define SICR_1_USB_A_UART2S (1 << (30-22)) +#define SICR_1_USB_B_USBDR (0 << (30-24)) +#define SICR_1_USB_B_UART2S (1 << (30-24)) +#define SICR_1_USB_B_UART2RTS (2 << (30-24)) +#define SICR_1_USB_C_USBDR (0 << (30-26)) +#define SICR_1_USB_C_QE_EXT (3 << (30-26)) +#define SICR_1_FEC1_FEC1 (0 << (30-28)) +#define SICR_1_FEC1_GTM (1 << (30-28)) +#define SICR_1_FEC1_GPIO (2 << (30-28)) +#define SICR_1_FEC2_FEC2 (0 << (30-30)) +#define SICR_1_FEC2_GTM (1 << (30-30)) +#define SICR_1_FEC2_GPIO (2 << (30-30)) +/* SICR_2 */ +#define SICR_2_FEC3_FEC3 (0 << (30-0)) +#define SICR_2_FEC3_TMR (1 << (30-0)) +#define SICR_2_FEC3_GPIO (2 << (30-0)) +#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2)) +#define SICR_2_HDLC1_A_GPIO (1 << (30-2)) +#define SICR_2_HDLC1_A_TDM1 (2 << (30-2)) +#define SICR_2_ELBC_A_LA (0 << (30-4)) +#define SICR_2_ELBC_B_LCLK (0 << (30-6)) +#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8)) +#define SICR_2_HDLC2_A_GPIO (0 << (30-8)) +#define SICR_2_HDLC2_A_TDM2 (0 << (30-8)) +/* bits 10-11 unused */ +#define SICR_2_USB_D_USBDR (0 << (30-12)) +#define SICR_2_USB_D_GPIO (2 << (30-12)) +#define SICR_2_USB_D_QE_BRG (3 << (30-12)) +#define SICR_2_PCI_PCI (0 << (30-14)) +#define SICR_2_PCI_CPCI_HS (2 << (30-14)) +#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16)) +#define SICR_2_HDLC1_B_GPIO (1 << (30-16)) +#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16)) +#define SICR_2_HDLC1_B_TDM1 (3 << (30-16)) +#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18)) +#define SICR_2_HDLC1_C_GPIO (1 << (30-18)) +#define SICR_2_HDLC1_C_TDM1 (2 << (30-18)) +#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20)) +#define SICR_2_HDLC2_B_GPIO (1 << (30-20)) +#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20)) +#define SICR_2_HDLC2_B_TDM2 (3 << (30-20)) +#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22)) +#define SICR_2_HDLC2_C_GPIO (1 << (30-22)) +#define SICR_2_HDLC2_C_TDM2 (2 << (30-22)) +#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22)) +#define SICR_2_QUIESCE_B (0 << (30-24)) + #endif /* @@ -580,6 +661,63 @@ #define HRCWL_SVCOD_DIV_8 0x10000000 #define HRCWL_SVCOD_DIV_2 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 +#elif defined(CONFIG_MPC8309) + +#define HRCWL_CEVCOD 0x000000C0 +#define HRCWL_CEVCOD_SHIFT 6 +/* + * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012 + * these are different than with 8360, 832x + */ +#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000 +#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040 +#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080 + +#define HRCWL_CEPDF 0x00000020 +#define HRCWL_CEPDF_SHIFT 5 +#define HRCWL_CE_PLL_DIV_1X1 0x00000000 +#define HRCWL_CE_PLL_DIV_2X1 0x00000020 + +#define HRCWL_CEPMF 0x0000001F +#define HRCWL_CEPMF_SHIFT 0 +#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 +#define HRCWL_CE_TO_PLL_1X2 0x00000002 +#define HRCWL_CE_TO_PLL_1X3 0x00000003 +#define HRCWL_CE_TO_PLL_1X4 0x00000004 +#define HRCWL_CE_TO_PLL_1X5 0x00000005 +#define HRCWL_CE_TO_PLL_1X6 0x00000006 +#define HRCWL_CE_TO_PLL_1X7 0x00000007 +#define HRCWL_CE_TO_PLL_1X8 0x00000008 +#define HRCWL_CE_TO_PLL_1X9 0x00000009 +#define HRCWL_CE_TO_PLL_1X10 0x0000000A +#define HRCWL_CE_TO_PLL_1X11 0x0000000B +#define HRCWL_CE_TO_PLL_1X12 0x0000000C +#define HRCWL_CE_TO_PLL_1X13 0x0000000D +#define HRCWL_CE_TO_PLL_1X14 0x0000000E +#define HRCWL_CE_TO_PLL_1X15 0x0000000F +#define HRCWL_CE_TO_PLL_1X16 0x00000010 +#define HRCWL_CE_TO_PLL_1X17 0x00000011 +#define HRCWL_CE_TO_PLL_1X18 0x00000012 +#define HRCWL_CE_TO_PLL_1X19 0x00000013 +#define HRCWL_CE_TO_PLL_1X20 0x00000014 +#define HRCWL_CE_TO_PLL_1X21 0x00000015 +#define HRCWL_CE_TO_PLL_1X22 0x00000016 +#define HRCWL_CE_TO_PLL_1X23 0x00000017 +#define HRCWL_CE_TO_PLL_1X24 0x00000018 +#define HRCWL_CE_TO_PLL_1X25 0x00000019 +#define HRCWL_CE_TO_PLL_1X26 0x0000001A +#define HRCWL_CE_TO_PLL_1X27 0x0000001B +#define HRCWL_CE_TO_PLL_1X28 0x0000001C +#define HRCWL_CE_TO_PLL_1X29 0x0000001D +#define HRCWL_CE_TO_PLL_1X30 0x0000001E +#define HRCWL_CE_TO_PLL_1X31 0x0000001F + +#define HRCWL_SVCOD 0x30000000 +#define HRCWL_SVCOD_SHIFT 28 +#define HRCWL_SVCOD_DIV_2 0x00000000 +#define HRCWL_SVCOD_DIV_4 0x10000000 +#define HRCWL_SVCOD_DIV_8 0x20000000 +#define HRCWL_SVCOD_DIV_1 0x30000000 #endif /* @@ -940,6 +1078,21 @@ #define SCCR_SATACM_1 0x00000055 #define SCCR_SATACM_2 0x000000aa #define SCCR_SATACM_3 0x000000ff +#elif defined(CONFIG_MPC8309) +/* SCCR bits - MPC8309 specific */ +#define SCCR_SDHCCM 0x0c000000 +#define SCCR_SDHCCM_SHIFT 26 +#define SCCR_SDHCCM_0 0x00000000 +#define SCCR_SDHCCM_1 0x04000000 +#define SCCR_SDHCCM_2 0x08000000 +#define SCCR_SDHCCM_3 0x0c000000 + +#define SCCR_USBDRCM 0x00c00000 +#define SCCR_USBDRCM_SHIFT 22 +#define SCCR_USBDRCM_0 0x00000000 +#define SCCR_USBDRCM_1 0x00400000 +#define SCCR_USBDRCM_2 0x00800000 +#define SCCR_USBDRCM_3 0x00c00000 #endif #define SCCR_PCIEXP1CM 0x00300000 -- cgit v1.2.3 From 6967840b83d06c7d56fb6ba6322393a9c254c27b Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:09 +0000 Subject: km83xx: add common support for km8309 boards Add support for Keymile boards based on mpc8309 (it would be only kmvect1 for now) Signed-off-by: Gerlando Falauto [#elseif -> #if to allow kmcoge5ne and kmeter1 to build successfully] Signed-off-by: Kim Phillips --- board/keymile/km83xx/km83xx.c | 2 +- include/configs/km/km8309-common.h | 176 +++++++++++++++++++++++++++++++++++++ include/configs/km/km83xx-common.h | 6 ++ 3 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 include/configs/km/km8309-common.h diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index e01a633aae..83a8753e5a 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -56,7 +56,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {5, 2, 1, 0, 1}, /* UART2_RTS */ {5, 3, 2, 0, 2}, /* UART2_SIN */ {5, 1, 2, 0, 3}, /* UART2_CTS */ -#else +#elif !defined(CONFIG_MPC8309) /* Local Bus */ {0, 16, 1, 0, 3}, /* LA00 */ {0, 17, 1, 0, 3}, /* LA01 */ diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h new file mode 100644 index 0000000000..b36e892cbe --- /dev/null +++ b/include/configs/km/km8309-common.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2012 Keymile AG + * Gerlando Falauto + * + * Based on km8321-common.h, see respective copyright notice for credits + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_KM8309_COMMON_H +#define __CONFIG_KM8309_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC830x 1 /* MPC830x family */ +#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ + +#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" +#define CONFIG_CMD_DIAG 1 + +/* include common defines/options for all 83xx Keymile boards */ +#include "km83xx-common.h" + +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +/* at end of uboot partition, before env */ +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 + +#define CONFIG_MISC_INIT_R + +/* + * System IO Config + */ +/* 0x14000180 SICR_1 */ +#define CONFIG_SYS_SICRL (0 \ + | SICR_1_UART1_UART1RTS \ + | SICR_1_I2C_CKSTOP \ + | SICR_1_IRQ_A_IRQ \ + | SICR_1_IRQ_B_IRQ \ + | SICR_1_GPIO_A_GPIO \ + | SICR_1_GPIO_B_GPIO \ + | SICR_1_GPIO_C_GPIO \ + | SICR_1_GPIO_D_GPIO \ + | SICR_1_GPIO_E_GPIO \ + | SICR_1_GPIO_F_GPIO \ + | SICR_1_USB_A_UART2S \ + | SICR_1_USB_B_UART2RTS \ + | SICR_1_FEC1_FEC1 \ + | SICR_1_FEC2_FEC2 \ + ) + +/* 0x00080400 SICR_2 */ +#define CONFIG_SYS_SICRH (0 \ + | SICR_2_FEC3_FEC3 \ + | SICR_2_HDLC1_A_HDLC1 \ + | SICR_2_ELBC_A_LA \ + | SICR_2_ELBC_B_LCLK \ + | SICR_2_HDLC2_A_HDLC2 \ + | SICR_2_USB_D_GPIO \ + | SICR_2_PCI_PCI \ + | SICR_2_HDLC1_B_HDLC1 \ + | SICR_2_HDLC1_C_HDLC1 \ + | SICR_2_HDLC2_B_GPIO \ + | SICR_2_HDLC2_C_HDLC2 \ + | SICR_2_QUIESCE_B \ + ) + +/* GPR_1 */ +#define CONFIG_SYS_GPR1 0x50008060 + +#define CONFIG_SYS_GP1DIR 0x00000000 +#define CONFIG_SYS_GP1ODR 0x00000000 +#define CONFIG_SYS_GP2DIR 0xFF000000 +#define CONFIG_SYS_GP2ODR 0x00000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ + HRCWL_DDR_TO_SCB_CLK_2X1 | \ + HRCWL_CSB_TO_CLKIN_2X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X3) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_AGENT | \ + HRCWH_PCI_ARBITER_DISABLE | \ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_DISABLE | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LALE_NORMAL) + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_32_BE | \ + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ODT_RD_NEVER | \ + CSCONFIG_ODT_WR_ONLY_CURRENT | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10) + +#define CONFIG_SYS_DDR_MODE 0x47860242 +#define CONFIG_SYS_DDR_MODE2 0x8080c000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (5 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 + +/* EEprom support */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + +#define CONFIG_SYS_LBC_LBCR 0x00000000 + +/* + * MMU Setup + */ +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +#endif /* __CONFIG_KM8309_COMMON_H */ diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 877d8418c0..a9823d6ef9 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -169,9 +169,15 @@ #define UEC_VERBOSE_DEBUG 1 #ifdef CONFIG_UEC_ETH1 +#if defined(CONFIG_MPC8309) +#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 +#else #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#endif #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -- cgit v1.2.3 From c4d22de817738e9f1f6a7c34664fc4ac112024a3 Mon Sep 17 00:00:00 2001 From: Gerlando Falauto Date: Wed, 10 Oct 2012 22:13:10 +0000 Subject: km83xx: add kmvect1 board Add support for the new kmvect1 board powered by the mpc8309 processor. As this board is very similar to the existing suvd3, instead of adding a new config header file, just add a new config option to suvd3.h Signed-off-by: Gerlando Falauto Signed-off-by: Kim Phillips --- boards.cfg | 3 ++- include/configs/suvd3.h | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/boards.cfg b/boards.cfg index 3e19647783..b14a08ff15 100644 --- a/boards.cfg +++ b/boards.cfg @@ -679,7 +679,8 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP TQM834x powerpc mpc83xx tqm834x tqc -suvd3 powerpc mpc83xx km83xx keymile +suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3 +kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1 tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,TUGE1 tuxx1 powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,KMSUPX5 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 68680c5f9c..c50832c1e0 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -23,14 +23,23 @@ /* * High Level Configuration Options */ -#define CONFIG_SUVD3 /* SUVD3 board specific */ -#define CONFIG_HOSTNAME suvd3 -#define CONFIG_KM_BOARD_NAME "suvd3" +/* This needs to be set prior to including km/km83xx-common.h */ #define CONFIG_SYS_TEXT_BASE 0xF0000000 +#if defined(CONFIG_SUVD3) /* SUVD3 board specific */ +#define CONFIG_HOSTNAME suvd3 +#define CONFIG_KM_BOARD_NAME "suvd3" /* include common defines/options for all 8321 Keymile boards */ #include "km/km8321-common.h" +#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */ +#define CONFIG_HOSTNAME kmvect1 +#define CONFIG_KM_BOARD_NAME "kmvect1" +/* include common defines/options for all 8309 Keymile boards */ +#include "km/km8309-common.h" +#else +#error Supported boards are: SUVD3, KMVECT1 +#endif #define CONFIG_SYS_APP1_BASE 0xA0000000 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -- cgit v1.2.3 From 7adbd11e78518c21b4ea363b8a74b224c8ae8967 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Sun, 21 Oct 2012 21:27:48 +0000 Subject: ColdFire: Fix unused variable in cpu_init.c Fix the following build warnings in cpu_init.c: cpu_init.c: In function 'cpu_init_f': cpu_init.c:47:9: warning: unused variable 'pll' cpu_init.c:46:10: warning: unused variable 'fbcs' cpu_init.c:44:10: warning: unused variable 'scm1' Signed-off-by: Alison Wang --- arch/m68k/cpu/mcf5227x/cpu_init.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c index e23b20df91..1928eb384e 100644 --- a/arch/m68k/cpu/mcf5227x/cpu_init.c +++ b/arch/m68k/cpu/mcf5227x/cpu_init.c @@ -31,6 +31,7 @@ #include #include #include +#include /* * Breath some life into the CPU... @@ -41,12 +42,13 @@ */ void cpu_init_f(void) { - scm1_t *scm1 = (scm1_t *) MMAP_SCM1; gpio_t *gpio = (gpio_t *) MMAP_GPIO; - fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - pll_t *pll = (pll_t *)MMAP_PLL; + fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; #if !defined(CONFIG_CF_SBF) + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + pll_t *pll = (pll_t *)MMAP_PLL; + /* Workaround, must place before fbcs */ out_be32(&pll->psr, 0x12); -- cgit v1.2.3 From 45370e1836dc0a7ac8e1d4828924e971d01fd92a Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Thu, 18 Oct 2012 19:25:51 +0000 Subject: ColdFire: Add MCF5441x CPU support Add MCF5441x CPU support. The MCF5441x devices are a family of highly-integrated 32-bit microprocessors based on the Version 4m ColdFire microarchitecture, comprising of the V4 integer core, memory management unit(MMU) and enchanced multiply-accumulate unit(EMAC). Signed-off-by: TsiChung Liew Signed-off-by: Jason Jin Signed-off-by: Alison Wang --- arch/m68k/cpu/mcf5445x/config.mk | 10 + arch/m68k/cpu/mcf5445x/cpu.c | 17 + arch/m68k/cpu/mcf5445x/cpu_init.c | 313 +++++++++++-- arch/m68k/cpu/mcf5445x/speed.c | 80 +++- arch/m68k/cpu/mcf5445x/start.S | 273 ++++++++++- arch/m68k/include/asm/cache.h | 11 +- arch/m68k/include/asm/immap.h | 43 +- arch/m68k/include/asm/immap_5441x.h | 387 ++++++++++++++++ arch/m68k/include/asm/m5441x.h | 887 ++++++++++++++++++++++++++++++++++++ 9 files changed, 1967 insertions(+), 54 deletions(-) create mode 100644 arch/m68k/include/asm/immap_5441x.h create mode 100644 arch/m68k/include/asm/m5441x.h diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk index 61a731eeff..0c48783e4c 100644 --- a/arch/m68k/cpu/mcf5445x/config.mk +++ b/arch/m68k/cpu/mcf5445x/config.mk @@ -4,6 +4,8 @@ # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# Copyright 2011-2012 Freescale Semiconductor, Inc. +# # See file CREDITS for list of people who contributed to this # project. # @@ -24,7 +26,15 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data + +cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg)) + +ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x))) +PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC +else PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC +endif ifneq (,$(findstring -linux-,$(shell $(CC) --version))) ifneq (,$(findstring GOT,$(shell $(LD) --help))) diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c index adfc708c35..b612cdaea1 100644 --- a/arch/m68k/cpu/mcf5445x/cpu.c +++ b/arch/m68k/cpu/mcf5445x/cpu.c @@ -39,6 +39,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { rcm_t *rcm = (rcm_t *) (MMAP_RCM); udelay(1000); + out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT); + udelay(10000); setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ @@ -74,6 +76,21 @@ int checkcpu(void) case 0x4f: id = 54450; break; + case 0x9F: + id = 54410; + break; + case 0xA0: + id = 54415; + break; + case 0xA1: + id = 54416; + break; + case 0xA2: + id = 54417; + break; + case 0xA3: + id = 54418; + break; } if (id) { diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index b6ceac32e8..6e947d06f9 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -39,37 +39,11 @@ #include #endif -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) +void init_fbcs(void) { - scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; - out_be32(&scm1->mpr, 0x77777777); - out_be32(&scm1->pacra, 0); - out_be32(&scm1->pacrb, 0); - out_be32(&scm1->pacrc, 0); - out_be32(&scm1->pacrd, 0); - out_be32(&scm1->pacre, 0); - out_be32(&scm1->pacrf, 0); - out_be32(&scm1->pacrg, 0); - - /* FlexBus */ - out_8(&gpio->par_be, - GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | - GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); - out_8(&gpio->par_fbctl, - GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | - GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); - -#if !defined(CONFIG_CF_SBF) +#if !defined(CONFIG_SERIAL_BOOT) #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); @@ -107,6 +81,145 @@ void cpu_init_f(void) out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif +} + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + +#ifdef CONFIG_MCF5441x + scm_t *scm = (scm_t *) MMAP_SCM; + pm_t *pm = (pm_t *) MMAP_PM; + + /* Disable Switch */ + *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0; + + /* Disable core watchdog */ + out_be16(&scm->cwcr, 0); + out_8(&gpio->par_fbctl, + GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE | + GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW | + GPIO_PAR_FBCTL_TA_TA); + out_8(&gpio->par_be, + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | + GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); + + /* eDMA */ + out_8(&pm->pmcr0, 17); + + /* INTR0 - INTR2 */ + out_8(&pm->pmcr0, 18); + out_8(&pm->pmcr0, 19); + out_8(&pm->pmcr0, 20); + + /* I2C */ + out_8(&pm->pmcr0, 22); + out_8(&pm->pmcr1, 4); + out_8(&pm->pmcr1, 7); + + /* DTMR0 - DTMR3*/ + out_8(&pm->pmcr0, 28); + out_8(&pm->pmcr0, 29); + out_8(&pm->pmcr0, 30); + out_8(&pm->pmcr0, 31); + + /* PIT0 - PIT3 */ + out_8(&pm->pmcr0, 32); + out_8(&pm->pmcr0, 33); + out_8(&pm->pmcr0, 34); + out_8(&pm->pmcr0, 35); + + /* Edge Port */ + out_8(&pm->pmcr0, 36); + out_8(&pm->pmcr0, 37); + + /* USB OTG */ + out_8(&pm->pmcr0, 44); + /* USB Host */ + out_8(&pm->pmcr0, 45); + + /* ESDHC */ + out_8(&pm->pmcr0, 51); + + /* ENET0 - ENET1 */ + out_8(&pm->pmcr0, 53); + out_8(&pm->pmcr0, 54); + + /* NAND */ + out_8(&pm->pmcr0, 63); + +#ifdef CONFIG_SYS_I2C_0 + out_8(&gpio->par_cani2c, 0xF0); + /* I2C0 pull up */ + out_be16(&gpio->pcr_b, 0x003C); + /* I2C0 max speed */ + out_8(&gpio->srcr_cani2c, 0x03); +#endif +#ifdef CONFIG_SYS_I2C_2 + /* I2C2 */ + out_8(&gpio->par_ssi0h, 0xA0); + /* I2C2, UART7 */ + out_8(&gpio->par_ssi0h, 0xA8); + /* UART7 */ + out_8(&gpio->par_ssi0l, 0x2); + /* UART8, UART9 */ + out_8(&gpio->par_cani2c, 0xAA); + /* UART4, UART0 */ + out_8(&gpio->par_uart0, 0xAF); + /* UART5, UART1 */ + out_8(&gpio->par_uart1, 0xAF); + /* UART6, UART2 */ + out_8(&gpio->par_uart2, 0xAF); + /* I2C2 pull up */ + out_be16(&gpio->pcr_h, 0xF000); +#endif +#ifdef CONFIG_SYS_I2C_5 + /* I2C5 */ + out_8(&gpio->par_uart1, 0x0A); + /* I2C5 pull up */ + out_be16(&gpio->pcr_e, 0x0003); + out_be16(&gpio->pcr_f, 0xC000); +#endif + + /* Lowest slew rate for UART0,1,2 */ + out_8(&gpio->srcr_uart, 0x00); +#endif /* CONFIG_MCF5441x */ + +#ifdef CONFIG_MCF5445x + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); + out_be32(&scm1->pacrg, 0); + + /* FlexBus */ + out_8(&gpio->par_be, + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | + GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); + out_8(&gpio->par_fbctl, + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | + GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); + +#ifdef CONFIG_FSL_I2C + out_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); +#endif +#endif /* CONFIG_MCF5445x */ + + /* FlexBus Chipselect */ + init_fbcs(); /* * now the flash base address is no longer at 0 (Newer ColdFire family @@ -116,11 +229,6 @@ void cpu_init_f(void) if (CONFIG_SYS_CS0_BASE != 0) setvbr(CONFIG_SYS_CS0_BASE); -#ifdef CONFIG_FSL_I2C - out_be16(&gpio->par_feci2c, - GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); -#endif - icache_enable(); } @@ -143,9 +251,95 @@ int cpu_init_r(void) void uart_port_conf(int port) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; +#ifdef CONFIG_MCF5441x + pm_t *pm = (pm_t *) MMAP_PM; +#endif /* Setup Ports: */ switch (port) { +#ifdef CONFIG_MCF5441x + case 0: + /* UART0 */ + out_8(&pm->pmcr0, 24); + clrbits_8(&gpio->par_uart0, + ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK)); + setbits_8(&gpio->par_uart0, + GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD); + break; + case 1: + /* UART1 */ + out_8(&pm->pmcr0, 25); + clrbits_8(&gpio->par_uart1, + ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK)); + setbits_8(&gpio->par_uart1, + GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD); + break; + case 2: + /* UART2 */ + out_8(&pm->pmcr0, 26); + clrbits_8(&gpio->par_uart2, + ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK)); + setbits_8(&gpio->par_uart2, + GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD); + break; + case 3: + /* UART3 */ + out_8(&pm->pmcr0, 27); + clrbits_8(&gpio->par_dspi0, + ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK)); + setbits_8(&gpio->par_dspi0, + GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD); + break; + case 4: + /* UART4 */ + out_8(&pm->pmcr1, 24); + clrbits_8(&gpio->par_uart0, + ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK)); + setbits_8(&gpio->par_uart0, + GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD); + break; + case 5: + /* UART5 */ + out_8(&pm->pmcr1, 25); + clrbits_8(&gpio->par_uart1, + ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK)); + setbits_8(&gpio->par_uart1, + GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD); + break; + case 6: + /* UART6 */ + out_8(&pm->pmcr1, 26); + clrbits_8(&gpio->par_uart2, + ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK)); + setbits_8(&gpio->par_uart2, + GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD); + break; + case 7: + /* UART7 */ + out_8(&pm->pmcr1, 27); + clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK); + clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK); + setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD); + setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD); + break; + case 8: + /* UART8 */ + out_8(&pm->pmcr0, 28); + clrbits_8(&gpio->par_cani2c, + ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK)); + setbits_8(&gpio->par_cani2c, + GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD); + break; + case 9: + /* UART9 */ + out_8(&pm->pmcr1, 29); + clrbits_8(&gpio->par_cani2c, + ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK)); + setbits_8(&gpio->par_cani2c, + GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD); + break; +#endif +#ifdef CONFIG_MCF5445x case 0: clrbits_8(&gpio->par_uart, GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); @@ -178,6 +372,7 @@ void uart_port_conf(int port) GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); #endif break; +#endif /* CONFIG_MCF5445x */ } } @@ -187,6 +382,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_s *info = (struct fec_info_s *)dev->priv; +#ifdef CONFIG_MCF5445x if (setclear) { #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY if (info->iobase == CONFIG_SYS_FEC0_IOBASE) @@ -224,6 +420,21 @@ int fecpin_setclear(struct eth_device *dev, int setclear) #endif } } +#endif /* CONFIG_MCF5445x */ + +#ifdef CONFIG_MCF5441x + if (setclear) { + out_8(&gpio->par_fec, 0x03); + out_8(&gpio->srcr_fec, 0x0F); + clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK, + GPIO_PAR_SIMP0H_DAT_GPIO); + clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK, + GPIO_PDDR_G4_OUTPUT); + clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK); + + } else + clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK); +#endif return 0; } #endif @@ -233,10 +444,24 @@ void cfspi_port_conf(void) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; +#ifdef CONFIG_MCF5445x out_8(&gpio->par_dspi, GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | GPIO_PAR_DSPI_SCK_SCK); +#endif + +#ifdef CONFIG_MCF5441x + pm_t *pm = (pm_t *) MMAP_PM; + + out_8(&gpio->par_dspi0, + GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT | + GPIO_PAR_DSPI0_SCK_DSPI0SCK); + out_8(&gpio->srcr_dspiow, 3); + + /* DSPI0 */ + out_8(&pm->pmcr0, 23); +#endif } int cfspi_claim_bus(uint bus, uint cs) @@ -250,6 +475,7 @@ int cfspi_claim_bus(uint bus, uint cs) /* Clear FIFO and resume transfer */ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); +#ifdef CONFIG_MCF5445x switch (cs) { case 0: clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); @@ -272,6 +498,20 @@ int cfspi_claim_bus(uint bus, uint cs) setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); break; } +#endif + +#ifdef CONFIG_MCF5441x + switch (cs) { + case 0: + clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK); + setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0); + break; + case 1: + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); + setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); + break; + } +#endif return 0; } @@ -284,6 +524,7 @@ void cfspi_release_bus(uint bus, uint cs) /* Clear FIFO */ clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); +#ifdef CONFIG_MCF5445x switch (cs) { case 0: clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); @@ -301,5 +542,11 @@ void cfspi_release_bus(uint bus, uint cs) clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); break; } +#endif + +#ifdef CONFIG_MCF5441x + if (cs == 1) + clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); +#endif } #endif diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index d71b5fe842..55d1c488a3 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -57,8 +57,10 @@ void clock_enter_limp(int lpdiv) /* Round divider down to nearest power of two */ for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; +#ifdef CONFIG_MCF5445x /* Apply the divider to the system clock */ clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); +#endif /* Enable Limp Mode */ setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); @@ -81,12 +83,66 @@ void clock_exit_limp(void) ; } -/* - * get_clocks() fills in gd->cpu_clock and gd->bus_clk - */ -int get_clocks(void) +#ifdef CONFIG_MCF5441x +void setup_5441x_clocks(void) { + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; + int temp, vco = 0, bootmod_ccr, pdr; + + bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; + + switch (bootmod_ccr) { + case 0: + out_be32(&pll->pcr, 0x00000013); + out_be32(&pll->pdr, 0x00e70c61); + clock_exit_limp(); + break; + case 2: + break; + case 3: + break; + } + /*Change frequency for Modelo SER1 USB host*/ +#ifdef CONFIG_LOW_MCFCLK + temp = in_be32(&pll->pcr); + temp &= ~0x3f; + temp |= 5; + out_be32(&pll->pcr, temp); + + temp = in_be32(&pll->pdr); + temp &= ~0x001f0000; + temp |= 0x00040000; + out_be32(&pll->pdr, temp); + __asm__("tpf"); +#endif + + setbits_be16(&ccm->misccr2, 0x02); + + vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * + CONFIG_SYS_INPUT_CLKSRC; + gd->vco_clk = vco; + + gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ + + pdr = in_be32(&pll->pdr); + temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1; + gd->cpu_clk = vco / temp; /* cpu clock */ + gd->flb_clk = vco / temp; /* FlexBus clock */ + gd->flb_clk >>= 1; + if (in_be16(ccm->misccr2) & 2) /* fsys/4 */ + gd->flb_clk >>= 1; + + temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1; + gd->bus_clk = vco / temp; /* bus clock */ + +} +#endif + +#ifdef CONFIG_MCF5445x +void setup_5445x_clocks(void) +{ ccm_t *ccm = (ccm_t *)MMAP_CCM; pll_t *pll = (pll_t *)MMAP_PLL; int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; @@ -217,6 +273,22 @@ int get_clocks(void) #endif } +#ifdef CONFIG_FSL_I2C + gd->i2c1_clk = gd->bus_clk; +#endif +} +#endif + +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ +int get_clocks(void) +{ +#ifdef CONFIG_MCF5441x + setup_5441x_clocks(); +#endif +#ifdef CONFIG_MCF5445x + setup_5445x_clocks(); +#endif + #ifdef CONFIG_FSL_I2C gd->i2c1_clk = gd->bus_clk; #endif diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 99060141d8..5fc944d2f3 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -2,6 +2,9 @@ * Copyright (C) 2003 Josef Baumgartner * Based on code from Bernhard Kuhn * + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -21,8 +24,10 @@ * MA 02111-1307 USA */ +#include #include #include +#include #include "version.h" #include @@ -43,8 +48,9 @@ addl #60,%sp; /* space for 15 regs */ \ rte; -#if defined(CONFIG_CF_SBF) +#if defined(CONFIG_SERIAL_BOOT) #define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE) #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) #endif @@ -55,10 +61,15 @@ * These vectors are to catch any un-intended traps. */ _vectors: -#if defined(CONFIG_CF_SBF) +#if defined(CONFIG_SERIAL_BOOT) INITSP: .long 0 /* Initial SP */ +#ifdef CONFIG_CF_SBF INITPC: .long ASM_DRAMINIT /* Initial PC */ +#endif +#ifdef CONFIG_SYS_NAND_BOOT +INITPC: .long ASM_DRAMINIT_N /* Initial PC */ +#endif #else @@ -95,7 +106,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */ vector1E: .long _FAULT /* Autovector Level 6 */ vector1F: .long _FAULT /* Autovector Level 7 */ -#if !defined(CONFIG_CF_SBF) +#if !defined(CONFIG_SERIAL_BOOT) /* TRAP #0 - #15 */ vector20_2F: @@ -138,16 +149,26 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT #endif -#if defined(CONFIG_CF_SBF) +#if defined(CONFIG_SERIAL_BOOT) /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ asm_sbf_img_hdr: .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00030000 /* image length */ + .long 0x00040000 /* image length */ .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */ asm_dram_init: move.w #0x2700,%sr /* Mask off Interrupt */ +#ifdef CONFIG_SYS_NAND_BOOT + /* for assembly stack */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- +#endif + +#ifdef CONFIG_CF_SBF move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 movec %d0, %VBR @@ -180,7 +201,90 @@ asm_dram_init: move.l #(CONFIG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 move.l #(CONFIG_SYS_CS0_MASK), (%a1) +#endif /* CONFIG_CF_SBF */ + +#ifdef CONFIG_MCF5441x + /* TC: enable all peripherals, + in the future only enable certain peripherals */ + move.l #0xFC04002D, %a1 +#if defined(CONFIG_CF_SBF) + move.b #23, (%a1) /* dspi */ +#endif + move.b #46, (%a1) /* DDR */ + + /* slew settings */ + move.l #0xEC094060, %a1 + move.b #0, (%a1) + + /* use vco instead of cpu*2 clock for ddr clock */ + move.l #0xEC09001A, %a1 + move.w #0xE01D, (%a1) + + /* DDR settings */ + move.l #0xFC0B8180, %a1 + move.l #0x00000000, (%a1) + move.l #0x40000000, (%a1) + + move.l #0xFC0B81AC, %a1 + move.l #0x01030203, (%a1) + + move.l #0xFC0B8000, %a1 + move.l #0x01010101, (%a1)+ /* 0x00 */ + move.l #0x00000101, (%a1)+ /* 0x04 */ + move.l #0x01010100, (%a1)+ /* 0x08 */ + move.l #0x01010000, (%a1)+ /* 0x0C */ + move.l #0x00010101, (%a1)+ /* 0x10 */ + move.l #0xFC0B8018, %a1 + move.l #0x00010100, (%a1)+ /* 0x18 */ + move.l #0x00000001, (%a1)+ /* 0x1C */ + move.l #0x01000001, (%a1)+ /* 0x20 */ + move.l #0x00000100, (%a1)+ /* 0x24 */ + move.l #0x00010001, (%a1)+ /* 0x28 */ + move.l #0x00000200, (%a1)+ /* 0x2C */ + move.l #0x01000002, (%a1)+ /* 0x30 */ + move.l #0x00000000, (%a1)+ /* 0x34 */ + move.l #0x00000100, (%a1)+ /* 0x38 */ + move.l #0x02000100, (%a1)+ /* 0x3C */ + move.l #0x02000407, (%a1)+ /* 0x40 */ + move.l #0x02030007, (%a1)+ /* 0x44 */ + move.l #0x02000100, (%a1)+ /* 0x48 */ + move.l #0x0A030203, (%a1)+ /* 0x4C */ + move.l #0x00020708, (%a1)+ /* 0x50 */ + move.l #0x00050008, (%a1)+ /* 0x54 */ + move.l #0x04030002, (%a1)+ /* 0x58 */ + move.l #0x00000004, (%a1)+ /* 0x5C */ + move.l #0x020A0000, (%a1)+ /* 0x60 */ + move.l #0x0C00000E, (%a1)+ /* 0x64 */ + move.l #0x00002004, (%a1)+ /* 0x68 */ + move.l #0x00000000, (%a1)+ /* 0x6C */ + move.l #0x00100010, (%a1)+ /* 0x70 */ + move.l #0x00100010, (%a1)+ /* 0x74 */ + move.l #0x00000000, (%a1)+ /* 0x78 */ + move.l #0x07990000, (%a1)+ /* 0x7C */ + move.l #0xFC0B80A0, %a1 + move.l #0x00000000, (%a1)+ /* 0xA0 */ + move.l #0x00C80064, (%a1)+ /* 0xA4 */ + move.l #0x44520002, (%a1)+ /* 0xA8 */ + move.l #0x00C80023, (%a1)+ /* 0xAC */ + move.l #0xFC0B80B4, %a1 + move.l #0x0000C350, (%a1) /* 0xB4 */ + move.l #0xFC0B80E0, %a1 + move.l #0x04000000, (%a1)+ /* 0xE0 */ + move.l #0x03000304, (%a1)+ /* 0xE4 */ + move.l #0x40040000, (%a1)+ /* 0xE8 */ + move.l #0xC0004004, (%a1)+ /* 0xEC */ + move.l #0x0642C000, (%a1)+ /* 0xF0 */ + move.l #0x00000642, (%a1)+ /* 0xF4 */ + move.l #0xFC0B8024, %a1 + tpf + move.l #0x01000100, (%a1) /* 0x24 */ + + move.l #0x2000, %d1 + jsr asm_delay +#endif /* CONFIG_MCF5441x */ + +#ifdef CONFIG_MCF5445x /* Dram Initialization a1, a2, and d0 */ /* mscr sdram */ move.l #0xFC0A4074, %a1 @@ -203,7 +307,9 @@ dramsz_loop: add.l #1, %d1 cmp.l #1, %d2 bne dramsz_loop - +#ifdef CONFIG_SYS_NAND_BOOT + beq asm_nand_chk_status +#endif /* SDRAM Chip 0 and 1 */ move.l #(CONFIG_SYS_SDRAM_BASE), (%a1) or.l %d1, (%a1) @@ -275,7 +381,9 @@ dramsz_loop: move.l #2000, %d1 jsr asm_delay +#endif /* CONFIG_MCF5445x */ +#ifdef CONFIG_CF_SBF /* * DSPI Initialization * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h @@ -286,15 +394,28 @@ dramsz_loop: */ /* Enable pins for DSPI mode - chip-selects are enabled later */ asm_dspi_init: +#ifdef CONFIG_MCF5441x + move.l #0xEC09404E, %a1 + move.l #0xEC09404F, %a2 + move.b #0xFF, (%a1) + move.b #0x80, (%a2) +#endif + +#ifdef CONFIG_MCF5445x move.l #0xFC0A4063, %a0 move.b #0x7F, (%a0) - +#endif /* Configure DSPI module */ move.l #0xFC05C000, %a0 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ move.l #0xFC05C00C, %a0 +#ifdef CONFIG_MCF5441x + move.l #0x3E000016, (%a0) +#endif +#ifdef CONFIG_MCF5445x move.l #0x3E000011, (%a0) +#endif move.l #0xFC05C034, %a2 /* dtfr */ move.l #0xFC05C03B, %a3 /* drfr */ @@ -379,19 +500,148 @@ asm_dspi_rd_status: move.b (%a3), %d1 rts +#endif /* CONFIG_CF_SBF */ + +#ifdef CONFIG_SYS_NAND_BOOT + /* copy 4 boot pages to dram as soon as possible */ + /* each page is 996 bytes (1056 total with 60 ECC bytes */ + move.l #0x00000000, %a1 /* src */ + move.l #TEXT_BASE, %a2 /* dst */ + move.l #0x3E0, %d0 /* sz in long */ + +asm_boot_nand_copy: + move.l (%a1)+, (%a2)+ + subq.l #1, %d0 + bne asm_boot_nand_copy + + /* jump to memory and execute */ + move.l #(asm_nand_init), %a0 + jmp (%a0) + +asm_nand_init: + /* exit nand boot-mode */ + move.l #0xFC0FFF30, %a1 + or.l #0x00000040, %d1 + move.l %d1, (%a1) + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(CACR_STATUS), %a1 /* CACR */ + move.l #(ICACHE_STATUS), %a2 /* icache */ + move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* invalidate and disable cache */ + move.l #0x01004100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + /* Must disable global address */ + move.l #0xFC008000, %a1 + move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #0xFC008008, %a1 + move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #0xFC008004, %a1 + move.l #(CONFIG_SYS_CS0_MASK), (%a1) + + /* NAND port configuration */ + move.l #0xEC094048, %a1 + move.b #0xFD, (%a1)+ + move.b #0x5F, (%a1)+ + move.b #0x04, (%a1)+ + + /* reset nand */ + move.l #0xFC0FFF38, %a1 /* isr */ + move.l #0x000e0000, (%a1) + move.l #0xFC0FFF08, %a2 + move.l #0x00000000, (%a2)+ /* car */ + move.l #0x11000000, (%a2)+ /* rar */ + move.l #0x00000000, (%a2)+ /* rpt */ + move.l #0x00000000, (%a2)+ /* rai */ + move.l #0xFC0FFF2c, %a2 /* cfg */ + move.l #0x00000000, (%a2)+ /* secsz */ + move.l #0x000e0681, (%a2)+ + move.l #0xFC0FFF04, %a2 /* cmd2 */ + move.l #0xFF404001, (%a2) + move.l #0x000e0000, (%a1) + + move.l #0x2000, %d1 + jsr asm_delay + + /* setup nand */ + move.l #0xFC0FFF00, %a1 + move.l #0x30700000, (%a1)+ /* cmd1 */ + move.l #0x007EF000, (%a1)+ /* cmd2 */ + + move.l #0xFC0FFF2C, %a1 + move.l #0x00000841, (%a1)+ /* secsz */ + move.l #0x000e0681, (%a1)+ /* cfg */ + + move.l #100, %d4 /* 100 pages ~200KB */ + move.l #4, %d2 /* start at 4 */ + move.l #0xFC0FFF04, %a0 /* cmd2 */ + move.l #0xFC0FFF0C, %a1 /* rar */ + move.l #(TEXT_BASE + 0xF80), %a2 /* dst */ + +asm_nand_read: + move.l #0x11000000, %d0 /* rar */ + or.l %d2, %d0 + move.l %d0, (%a1) + add.l #1, %d2 + + move.l (%a0), %d0 /* cmd2 */ + or.l #1, %d0 + move.l %d0, (%a0) + + move.l #0x200, %d1 + jsr asm_delay + +asm_nand_chk_status: + move.l #0xFC0FFF38, %a4 /* isr */ + move.l (%a4), %d0 + and.l #0x40000000, %d0 + tst.l %d0 + beq asm_nand_chk_status + + move.l #0xFC0FFF38, %a4 /* isr */ + move.l (%a4), %d0 + or.l #0x000E0000, %d0 + move.l %d0, (%a4) + + move.l #0x200, %d3 + move.l #0xFC0FC000, %a3 /* buf 1 */ +asm_nand_copy: + move.l (%a3)+, (%a2)+ + subq.l #1, %d3 + bgt asm_nand_copy + + subq.l #1, %d4 + bgt asm_nand_read + + /* jump to memory and execute */ + move.l #(TEXT_BASE + 0x400), %a0 + jmp (%a0) + +#endif /* CONFIG_SYS_NAND_BOOT */ asm_delay: nop subq.l #1, %d1 bne asm_delay rts -#endif /* CONFIG_CF_SBF */ +#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */ .text . = 0x400 .globl _start _start: -#if !defined(CONFIG_CF_SBF) +#if !defined(CONFIG_SERIAL_BOOT) nop nop move.w #0x2700,%sr /* Mask off Interrupt */ @@ -418,12 +668,15 @@ _start: movec %d0, %ACR1 movec %d0, %ACR2 movec %d0, %ACR3 +#else + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 +#endif /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- -#endif move.l #__got_start, %a5 /* put relocation table address to a5 */ diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 5c9bb30835..f9e2d15f43 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -1,7 +1,7 @@ /* * ColdFire cache * - * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * Copyright 2004-2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -37,10 +37,9 @@ #if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) #define CONFIG_CF_V4 -#if defined(CONFIG_MCF5441x) +#elif defined(CONFIG_MCF5441x) #define CONFIG_CF_V4E /* Four Extra ACRn */ #endif -#endif /* ***** CACR ***** */ /* V2 Core */ @@ -87,7 +86,7 @@ #endif /* CONFIG_CF_V3 */ /* V4 Core */ -#ifdef CONFIG_CF_V4 +#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) #define CF_CACR_DEC (1 << 31) #define CF_CACR_DW (1 << 30) @@ -113,7 +112,7 @@ #define CF_CACR_IDSP (1 << 7) #define CF_CACR_EUSP (1 << 5) -#ifdef CONFIG_MCF5445x +#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x) #define CF_CACR_IVO (1 << 20) #define CF_CACR_SPA (1 << 14) #else @@ -148,7 +147,7 @@ #endif /* CONFIG_CF_V2 */ /* V4 Core */ -#ifdef CONFIG_CF_V4 +#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) #define CF_ACR_AMM (1 << 10) #define CF_ACR_SP (1 << 3) #endif /* CONFIG_CF_V4 */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index e83ce08d57..2aab463a90 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -1,7 +1,7 @@ /* * ColdFire Internal Memory Map and Defines * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright 2004-2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -318,6 +318,47 @@ #define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5329 && CONFIG_M5373 */ +#if defined(CONFIG_M54418) +#include +#include + +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) +#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) + +#if (CONFIG_SYS_UART_PORT < 4) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ + (CONFIG_SYS_UART_PORT * 0x4000)) +#else +#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ + ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) +#endif + +#define MMAP_DSPI MMAP_DSPI0 +#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (6) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) +#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) +#define CONFIG_SYS_PIT_PRESCALE (6) +#endif + +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) + +#endif /* CONFIG_M54418 */ + #if defined(CONFIG_M54451) || defined(CONFIG_M54455) #include #include diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h new file mode 100644 index 0000000000..300f4d2868 --- /dev/null +++ b/arch/m68k/include/asm/immap_5441x.h @@ -0,0 +1,387 @@ +/* + * MCF5441x Internal Memory Map + * + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5441X__ +#define __IMMAP_5441X__ + +/* Module Base Addresses */ +#define MMAP_XBS 0xFC004000 +#define MMAP_FBCS 0xFC008000 +#define MMAP_CAN0 0xFC020000 +#define MMAP_CAN1 0xFC024000 +#define MMAP_I2C1 0xFC038000 +#define MMAP_DSPI1 0xFC03C000 +#define MMAP_SCM 0xFC040000 +#define MMAP_PM 0xFC04002C +#define MMAP_EDMA 0xFC044000 +#define MMAP_INTC0 0xFC048000 +#define MMAP_INTC1 0xFC04C000 +#define MMAP_INTC2 0xFC050000 +#define MMAP_IACK 0xFC054000 +#define MMAP_I2C0 0xFC058000 +#define MMAP_DSPI0 0xFC05C000 +#define MMAP_UART0 0xFC060000 +#define MMAP_UART1 0xFC064000 +#define MMAP_UART2 0xFC068000 +#define MMAP_UART3 0xFC06C000 +#define MMAP_DTMR0 0xFC070000 +#define MMAP_DTMR1 0xFC074000 +#define MMAP_DTMR2 0xFC078000 +#define MMAP_DTMR3 0xFC07C000 +#define MMAP_PIT0 0xFC080000 +#define MMAP_PIT1 0xFC084000 +#define MMAP_PIT2 0xFC088000 +#define MMAP_PIT3 0xFC08C000 +#define MMAP_EPORT0 0xFC090000 +#define MMAP_ADC 0xFC094000 +#define MMAP_DAC0 0xFC098000 +#define MMAP_DAC1 0xFC09C000 +#define MMAP_RRTC 0xFC0A8000 +#define MMAP_SIM 0xFC0AC000 +#define MMAP_USBOTG 0xFC0B0000 +#define MMAP_USBEHCI 0xFC0B4000 +#define MMAP_SDRAM 0xFC0B8000 +#define MMAP_SSI0 0xFC0BC000 +#define MMAP_PLL 0xFC0C0000 +#define MMAP_RNG 0xFC0C4000 +#define MMAP_SSI1 0xFC0C8000 +#define MMAP_ESDHC 0xFC0CC000 +#define MMAP_FEC0 0xFC0D4000 +#define MMAP_FEC1 0xFC0D8000 +#define MMAP_L2_SW0 0xFC0DC000 +#define MMAP_L2_SW1 0xFC0E0000 + +#define MMAP_NFC_RAM 0xFC0FC000 +#define MMAP_NFC 0xFC0FF000 + +#define MMAP_1WIRE 0xEC008000 +#define MMAP_I2C2 0xEC010000 +#define MMAP_I2C3 0xEC014000 +#define MMAP_I2C4 0xEC018000 +#define MMAP_I2C5 0xEC01C000 +#define MMAP_DSPI2 0xEC038000 +#define MMAP_DSPI3 0xEC03C000 +#define MMAP_UART4 0xEC060000 +#define MMAP_UART5 0xEC064000 +#define MMAP_UART6 0xEC068000 +#define MMAP_UART7 0xEC06C000 +#define MMAP_UART8 0xEC070000 +#define MMAP_UART9 0xEC074000 +#define MMAP_RCM 0xEC090000 +#define MMAP_CCM 0xEC090000 +#define MMAP_GPIO 0xEC094000 + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Serial Boot Facility (SBF) */ +typedef struct sbf { + u8 resv0[0x18]; + u16 sbfsr; /* Serial Boot Facility Status */ + u8 resv1[0x6]; + u16 sbfcr; /* Serial Boot Facility Control */ +} sbf_t; + +/* Reset Controller Module (RCM) */ +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +/* Chip Configuration Module (CCM) */ +typedef struct ccm { + u8 ccm_resv0[0x4]; /* 0x00 */ + u16 ccr; /* 0x04 Chip Configuration */ + u8 resv1[0x2]; /* 0x06 */ + u16 rcon; /* 0x08 Reset Configuration */ + u16 cir; /* 0x0A Chip Identification */ + u8 resv2[0x2]; /* 0x0C */ + u16 misccr; /* 0x0E Miscellaneous Control */ + u16 cdrh; /* 0x10 Clock Divider */ + u16 cdrl; /* 0x12 Clock Divider */ + u16 uocsr; /* 0x14 USB On-the-Go Controller Status */ + u16 uhcsr; /* 0x16 */ + u16 misccr3; /* 0x18 */ + u16 misccr2; /* 0x1A */ + u16 adctsr; /* 0x1C */ + u16 dactsr; /* 0x1E */ + u16 sbfsr; /* 0x20 */ + u16 sbfcr; /* 0x22 */ + u32 fnacr; /* 0x24 */ +} ccm_t; + +/* General Purpose I/O Module (GPIO) */ +typedef struct gpio { + u8 podr_a; /* 0x00 */ + u8 podr_b; /* 0x01 */ + u8 podr_c; /* 0x02 */ + u8 podr_d; /* 0x03 */ + u8 podr_e; /* 0x04 */ + u8 podr_f; /* 0x05 */ + u8 podr_g; /* 0x06 */ + u8 podr_h; /* 0x07 */ + u8 podr_i; /* 0x08 */ + u8 podr_j; /* 0x09 */ + u8 podr_k; /* 0x0A */ + u8 rsvd0; /* 0x0B */ + + u8 pddr_a; /* 0x0C */ + u8 pddr_b; /* 0x0D */ + u8 pddr_c; /* 0x0E */ + u8 pddr_d; /* 0x0F */ + u8 pddr_e; /* 0x10 */ + u8 pddr_f; /* 0x11 */ + u8 pddr_g; /* 0x12 */ + u8 pddr_h; /* 0x13 */ + u8 pddr_i; /* 0x14 */ + u8 pddr_j; /* 0x15 */ + u8 pddr_k; /* 0x16 */ + u8 rsvd1; /* 0x17 */ + + u8 ppdsdr_a; /* 0x18 */ + u8 ppdsdr_b; /* 0x19 */ + u8 ppdsdr_c; /* 0x1A */ + u8 ppdsdr_d; /* 0x1B */ + u8 ppdsdr_e; /* 0x1C */ + u8 ppdsdr_f; /* 0x1D */ + u8 ppdsdr_g; /* 0x1E */ + u8 ppdsdr_h; /* 0x1F */ + u8 ppdsdr_i; /* 0x20 */ + u8 ppdsdr_j; /* 0x21 */ + u8 ppdsdr_k; /* 0x22 */ + u8 rsvd2; /* 0x23 */ + + u8 pclrr_a; /* 0x24 */ + u8 pclrr_b; /* 0x25 */ + u8 pclrr_c; /* 0x26 */ + u8 pclrr_d; /* 0x27 */ + u8 pclrr_e; /* 0x28 */ + u8 pclrr_f; /* 0x29 */ + u8 pclrr_g; /* 0x2A */ + u8 pclrr_h; /* 0x2B */ + u8 pclrr_i; /* 0x2C */ + u8 pclrr_j; /* 0x2D */ + u8 pclrr_k; /* 0x2E */ + u8 rsvd3; /* 0x2F */ + + u16 pcr_a; /* 0x30 */ + u16 pcr_b; /* 0x32 */ + u16 pcr_c; /* 0x34 */ + u16 pcr_d; /* 0x36 */ + u16 pcr_e; /* 0x38 */ + u16 pcr_f; /* 0x3A */ + u16 pcr_g; /* 0x3C */ + u16 pcr_h; /* 0x3E */ + u16 pcr_i; /* 0x40 */ + u16 pcr_j; /* 0x42 */ + u16 pcr_k; /* 0x44 */ + u16 rsvd4; /* 0x46 */ + + u8 par_fbctl; /* 0x48 */ + u8 par_be; /* 0x49 */ + u8 par_cs; /* 0x4A */ + u8 par_cani2c; /* 0x4B */ + u8 par_irqh; /* 0x4C */ + u8 par_irql; /* 0x4D */ + u8 par_dspi0; /* 0x4E */ + u8 par_dspiow; /* 0x4F */ + u8 par_timer; /* 0x50 */ + u8 par_uart2; /* 0x51 */ + u8 par_uart1; /* 0x52 */ + u8 par_uart0; /* 0x53 */ + u8 par_sdhch; /* 0x54 */ + u8 par_sdhcl; /* 0x55 */ + u8 par_simp0h; /* 0x56 */ + u8 par_simp1h; /* 0x57 */ + u8 par_ssi0h; /* 0x58 */ + u8 par_ssi0l; /* 0x59 */ + u8 par_dbg1h; /* 0x5A */ + u8 par_dbg0h; /* 0x5B */ + u8 par_dbgl; /* 0x5C */ + u8 rsvd5; /* 0x5D */ + u8 par_fec; /* 0x5E */ + u8 rsvd6; /* 0x5F */ + + u8 mscr_sdram; /* 0x60 */ + u8 rsvd7[3]; /* 0x61-0x63 */ + + u8 srcr_fb1; /* 0x64 */ + u8 srcr_fb2; /* 0x65 */ + u8 srcr_fb3; /* 0x66 */ + u8 srcr_fb4; /* 0x67 */ + u8 srcr_dspiow; /* 0x68 */ + u8 srcr_cani2c; /* 0x69 */ + u8 srcr_irq; /* 0x6A */ + u8 srcr_timer; /* 0x6B */ + u8 srcr_uart; /* 0x6C */ + u8 srcr_fec; /* 0x6D */ + u8 srcr_sdhc; /* 0x6E */ + u8 srcr_simp0; /* 0x6F */ + u8 srcr_ssi0; /* 0x70 */ + u8 rsvd8[3]; /* 0x71-0x73 */ + + u16 urts_pol; /* 0x74 */ + u16 ucts_pol; /* 0x76 */ + u16 utxd_wom; /* 0x78 */ + u32 urxd_wom; /* 0x7c */ + + u32 hcr1; /* 0x80 */ + u32 hcr0; /* 0x84 */ +} gpio_t; + +/* SDRAM Controller (SDRAMC) */ +typedef struct sdramc { + u32 cr00; /* 0x00 */ + u32 cr01; /* 0x04 */ + u32 cr02; /* 0x08 */ + u32 cr03; /* 0x0C */ + u32 cr04; /* 0x10 */ + u32 cr05; /* 0x14 */ + u32 cr06; /* 0x18 */ + u32 cr07; /* 0x1C */ + + u32 cr08; /* 0x20 */ + u32 cr09; /* 0x24 */ + u32 cr10; /* 0x28 */ + u32 cr11; /* 0x2C */ + u32 cr12; /* 0x30 */ + u32 cr13; /* 0x34 */ + u32 cr14; /* 0x38 */ + u32 cr15; /* 0x3C */ + + u32 cr16; /* 0x40 */ + u32 cr17; /* 0x44 */ + u32 cr18; /* 0x48 */ + u32 cr19; /* 0x4C */ + u32 cr20; /* 0x50 */ + u32 cr21; /* 0x54 */ + u32 cr22; /* 0x58 */ + u32 cr23; /* 0x5C */ + + u32 cr24; /* 0x60 */ + u32 cr25; /* 0x64 */ + u32 cr26; /* 0x68 */ + u32 cr27; /* 0x6C */ + u32 cr28; /* 0x70 */ + u32 cr29; /* 0x74 */ + u32 cr30; /* 0x78 */ + u32 cr31; /* 0x7C */ + + u32 cr32; /* 0x80 */ + u32 cr33; /* 0x84 */ + u32 cr34; /* 0x88 */ + u32 cr35; /* 0x8C */ + u32 cr36; /* 0x90 */ + u32 cr37; /* 0x94 */ + u32 cr38; /* 0x98 */ + u32 cr39; /* 0x9C */ + + u32 cr40; /* 0xA0 */ + u32 cr41; /* 0xA4 */ + u32 cr42; /* 0xA8 */ + u32 cr43; /* 0xAC */ + u32 cr44; /* 0xB0 */ + u32 cr45; /* 0xB4 */ + u32 cr46; /* 0xB8 */ + u32 cr47; /* 0xBC */ + u32 cr48; /* 0xC0 */ + u32 cr49; /* 0xC4 */ + u32 cr50; /* 0xC8 */ + u32 cr51; /* 0xCC */ + u32 cr52; /* 0xD0 */ + u32 cr53; /* 0xD4 */ + u32 cr54; /* 0xD8 */ + u32 cr55; /* 0xDC */ + u32 cr56; /* 0xE0 */ + u32 cr57; /* 0xE4 */ + u32 cr58; /* 0xE8 */ + u32 cr59; /* 0xEC */ + u32 cr60; /* 0xF0 */ + u32 cr61; /* 0xF4 */ + u32 cr62; /* 0xF8 */ + u32 cr63; /* 0xFC */ + + u32 rsvd3[32]; /* 0xF4-0x1A8 */ + + u32 rcrcr; /* 0x180 */ + u32 swrcr; /* 0x184 */ + u32 rcr; /* 0x188 */ + u32 msovr; /* 0x18C */ + u32 rcrdbg; /* 0x190 */ + u32 sl0adj; /* 0x194 */ + u32 sl1adj; /* 0x198 */ + u32 sl2adj; /* 0x19C */ + u32 sl3adj; /* 0x1A0 */ + u32 sl4adj; /* 0x1A4 */ + u32 flight_tm; /* 0x1A8 */ + u32 padcr; /* 0x1AC */ +} sdramc_t; + +/* Phase Locked Loop (PLL) */ +typedef struct pll { + u32 pcr; /* Control */ + u32 pdr; /* Divider */ + u32 psr; /* Status */ +} pll_t; + +typedef struct scm { + u8 rsvd1[19]; /* 0x00 - 0x12 */ + u8 wcr; /* 0x13 */ + u16 rsvd2; /* 0x14 - 0x15 */ + u16 cwcr; /* 0x16 */ + u8 rsvd3[3]; /* 0x18 - 0x1A */ + u8 cwsr; /* 0x1B */ + u8 rsvd4[3]; /* 0x1C - 0x1E */ + u8 scmisr; /* 0x1F */ + u32 rsvd5; /* 0x20 - 0x23 */ + u32 bcr; /* 0x24 */ + u8 rsvd6[72]; /* 0x28 - 0x6F */ + u32 cfadr; /* 0x70 */ + u8 rsvd7; /* 0x74 */ + u8 cfier; /* 0x75 */ + u8 cfloc; /* 0x76 */ + u8 cfatr; /* 0x77 */ + u32 rsvd8; /* 0x78 - 0x7B */ + u32 cfdtr; /* 0x7C */ +} scm_t; + +typedef struct pm { + u8 pmsr0; /* */ + u8 pmcr0; + u8 pmsr1; + u8 pmcr1; + u32 pmhr0; + u32 pmlr0; + u32 pmhr1; + u32 pmlr1; +} pm_t; + +#endif /* __IMMAP_5441X__ */ diff --git a/arch/m68k/include/asm/m5441x.h b/arch/m68k/include/asm/m5441x.h new file mode 100644 index 0000000000..f5c82d4b56 --- /dev/null +++ b/arch/m68k/include/asm/m5441x.h @@ -0,0 +1,887 @@ +/* + * MCF5441X Internal Memory Map + * + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCF5441X__ +#define __MCF5441X__ + +/* Interrupt Controller (INTC) */ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT2 (2) +#define INT0_LO_EPORT3 (3) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT5 (5) +#define INT0_LO_EPORT6 (6) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_UART3 (29) +#define INT0_LO_I2C0 (30) +#define INT0_LO_DSPI0 (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_MACNET0_TXF (36) +#define INT0_HI_MACNET0_TXB (37) +#define INT0_HI_MACNET0_UN (38) +#define INT0_HI_MACNET0_RL (39) +#define INT0_HI_MACNET0_RXF (40) +#define INT0_HI_MACNET0_RXB (41) +#define INT0_HI_MACNET0_MII (42) +#define INT0_HI_MACNET0_LC (43) +/* not used 44 */ +#define INT0_HI_MACNET0_GRA (45) +#define INT0_HI_MACNET0_EBERR (46) +#define INT0_HI_MACNET0_BABT (47) +#define INT0_HI_MACNET0_BABR (48) +#define INT0_HI_MACNET1_TXF (49) +#define INT0_HI_MACNET1_TXB (50) +#define INT0_HI_MACNET1_UN (51) +#define INT0_HI_MACNET1_RL (52) +#define INT0_HI_MACNET1_RXF (53) +#define INT0_HI_MACNET1_RXB (54) +#define INT0_HI_MACNET1_MII (55) +#define INT0_HI_MACNET1_LC (56) +/* not used 57 */ +#define INT0_HI_MACNET1_GRA (58) +#define INT0_HI_MACNET1_EBERR (59) +#define INT0_HI_MACNET1_BABT (60) +#define INT0_HI_MACNET1_BABR (61) +#define INT0_HI_SCMIR (62) +#define INT0_HI_OW (63) + +#define INT1_LO_CAN0_IFG (0) +#define INT1_LO_CAN0_BOFF (1) +/* not used 2 */ +#define INT1_LO_CAN0_TXRXWRN (3) +#define INT1_LO_CAN1_IFG (4) +#define INT1_LO_CAN1_BOFF (5) +/* not used 6 */ +#define INT1_LO_CAN1_TXRXWRN (7) +#define INT1_LO_EDMA_16 (8) +#define INT1_LO_EDMA_17 (9) +#define INT1_LO_EDMA_18 (10) +#define INT1_LO_EDMA_19 (11) +#define INT1_LO_EDMA_20 (12) +#define INT1_LO_EDMA_21 (13) +#define INT1_LO_EDMA_22 (14) +#define INT1_LO_EDMA_23 (15) +#define INT1_LO_EDMA_24 (16) +#define INT1_LO_EDMA_25 (17) +#define INT1_LO_EDMA_26 (18) +#define INT1_LO_EDMA_27 (19) +#define INT1_LO_EDMA_28 (20) +#define INT1_LO_EDMA_29 (21) +#define INT1_LO_EDMA_30 (22) +#define INT1_LO_EDMA_31 (23) +#define INT1_LO_EDMA_32 (24) +#define INT1_LO_EDMA_33 (25) +#define INT1_LO_EDMA_34 (26) +#define INT1_LO_EDMA_35 (27) +#define INT1_LO_EDMA_36 (28) +#define INT1_LO_EDMA_37 (29) +#define INT1_LO_EDMA_38 (30) +#define INT1_LO_EDMA_39 (31) +#define INT1_LO_EDMA_40 (32) +#define INT1_HI_EDMA_41 (33) +#define INT1_HI_EDMA_42 (34) +#define INT1_HI_EDMA_43 (35) +#define INT1_HI_EDMA_44 (36) +#define INT1_HI_EDMA_45 (37) +#define INT1_HI_EDMA_46 (38) +#define INT1_HI_EDMA_47 (39) +#define INT1_HI_EDMA_48 (40) +#define INT1_HI_EDMA_49 (41) +#define INT1_HI_EDMA_50 (42) +#define INT1_HI_EDMA_51 (43) +#define INT1_HI_EDMA_52 (44) +#define INT1_HI_EDMA_53 (45) +#define INT1_HI_EDMA_54 (46) +#define INT1_HI_EDMA_55 (47) +#define INT1_HI_UART4 (48) +#define INT1_HI_UART5 (49) +#define INT1_HI_UART6 (50) +#define INT1_HI_UART7 (51) +#define INT1_HI_UART8 (52) +#define INT1_HI_UART9 (53) +#define INT1_HI_DSPI1 (54) +#define INT1_HI_DSPI2 (55) +#define INT1_HI_DSPI3 (56) +#define INT1_HI_I2C1 (57) +#define INT1_HI_I2C2 (58) +#define INT1_HI_I2C3 (59) +#define INT1_HI_I2C4 (60) +#define INT1_HI_I2C5 (61) + +#define INT2_LO_EDMA56_63 (0) +#define INT2_LO_PWM_SM0SR_CF (1) +#define INT2_LO_PWM_SM1SR_CF (2) +#define INT2_LO_PWM_SM2SR_CF (3) +#define INT2_LO_PWM_SM3SR_CF (4) +#define INT2_LO_PWM_SM0SR_RF (5) +#define INT2_LO_PWM_SM1SR_RF (6) +#define INT2_LO_PWM_SM2SR_RF (7) +#define INT2_LO_PWM_SM3SR_RF (8) +#define INT2_LO_PWM_FSR (9) +#define INT2_LO_PWM_SMSR_REF (10) +#define INT2_LO_PLL_SR_LOCF (11) +#define INT2_LO_PLL_SR_LOLF (12) +#define INT2_LO_PIT0_PIF (13) +#define INT2_LO_PIT1_PIF (14) +#define INT2_LO_PIT2_PIF (15) +#define INT2_LO_PIT3_PIF (16) +#define INT2_LO_USBOTG_USBSTS (17) +#define INT2_LO_USBH_USBSTS (18) +/* not used 19-20 */ +#define INT2_LO_SSI0 (21) +#define INT2_LO_SSI1 (22) +#define INT2_LO_NFC (23) +/* not used 24-25 */ +#define INT2_LO_RTC (26) +#define INT2_LO_CCM_UOCSR (27) +#define INT2_LO_RNG_EI (28) +#define INT2_LO_SIM1_DATA (29) +#define INT2_LO_SIM1 (30) +#define INT2_LO_SDHC (31) +/* not used 32-37 */ +#define INT2_HI_L2SW_BERR (38) +#define INT2_HI_L2SW_RXB (39) +#define INT2_HI_L2SW_RXF (40) +#define INT2_HI_L2SW_TXB (41) +#define INT2_HI_L2SW_TXF (42) +#define INT2_HI_L2SW_QM (43) +#define INT2_HI_L2SW_OD0 (44) +#define INT2_HI_L2SW_OD1 (45) +#define INT2_HI_L2SW_OD2 (46) +#define INT2_HI_L2SW_LRN (47) +#define INT2_HI_MACNET0_TS (48) +#define INT2_HI_MACNET0_WAKE (49) +#define INT2_HI_MACNET0_PLR (50) +/* not used 51-54 */ +#define INT2_HI_MACNET1_TS (51) +#define INT2_HI_MACNET1_WAKE (52) +#define INT2_HI_MACNET1_PLR (53) + +/* Serial Boot Facility (SBF) */ +#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) +#define SBF_SBFCR_FR (0x0010) + +/* Reset Controller Module (RCM) */ +#define RCM_RCR_SOFTRST (0x80) +#define RCM_RCR_FRCRSTOUT (0x40) + +#define RCM_RSR_SOFT (0x20) +#define RCM_RSR_LOC (0x10) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_LOL (0x01) + +/* Chip Configuration Module (CCM) */ +#define CCM_CCR_BOOTMOD (0xC000) +#define CCM_CCR_PLLMULT (0x0FC0) +#define CCM_CCR_BOOTPS (0x0030) +#define CCM_CCR_BOOTPS_32 (0x0000) +#define CCM_CCR_BOOTPS_16 (0x0020) +#define CCM_CCR_BOOTPS_8 (0x0010) +#define CCM_CCR_BOOTPS_ (0x0000) +#define CCM_CCR_ALESEL (0x0008) +#define CCM_CCR_OSCMOD (0x0004) +#define CCM_CCR_PLLMOD (0x0002) +#define CCM_CCR_BOOTMEM (0x0001) + +#define CCM_CIR_PIN_MASK (0xFFC0) +#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN_MCF54410 (0x9F<<6) +#define CCM_CIR_PIN_MCF54415 (0xA0<<6) +#define CCM_CIR_PIN_MCF54416 (0xA1<<6) +#define CCM_CIR_PIN_MCF54417 (0xA2<<6) +#define CCM_CIR_PIN_MCF54418 (0xA3<<6) + +#define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14) +#define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF) +#define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000) +#define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000) +#define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000) +#define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000) +#define CCM_MISCCR_LIMP (0x1000) +#define CCM_MISCCR_BME (0x0800) +#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) +#define CCM_MISCCR_BMT_65536 (0) +#define CCM_MISCCR_BMT_32768 (1) +#define CCM_MISCCR_BMT_16384 (2) +#define CCM_MISCCR_BMT_8192 (3) +#define CCM_MISCCR_BMT_4096 (4) +#define CCM_MISCCR_BMT_2048 (5) +#define CCM_MISCCR_BMT_1024 (6) +#define CCM_MISCCR_BMT_512 (7) +#define CCM_MISCCR_SDHCSRC (0x0040) +#define CCM_MISCCR_SSI1SRC (0x0020) +#define CCM_MISCCR_SSI0SRC (0x0010) +#define CCM_MISCCR_USBHOC (0x0008) +#define CCM_MISCCR_USBOOC (0x0004) +#define CCM_MISCCR_USBPUE (0x0002) +#define CCM_MISCCR_USBSRC (0x0001) + +#define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8) +#define CCM_CDRH_SSI0DIV_MASK (0x00FF) +#define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF)) +#define CCM_CDRH_SSI1DIV_MASK (0xFF00) +#define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8) +#define CCM_CDRL_LPDIV_MASK (0xFF0F) +#define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x) + +#define CCM_UOCSR_DPPD (0x2000) +#define CCM_UOCSR_DMPD (0x1000) +#define CCM_UOCSR_DRV_VBUS (0x0800) +#define CCM_UOCSR_CRG_VBUS (0x0400) +#define CCM_UOCSR_DCR_VBUS (0x0200) +#define CCM_UOCSR_DPPU (0x0100) +#define CCM_UOCSR_AVLD (0x0080) +#define CCM_UOCSR_BVLD (0x0040) +#define CCM_UOCSR_VVLD (0x0020) +#define CCM_UOCSR_SEND (0x0010) +#define CCM_UOCSR_PWRFLT (0x0008) +#define CCM_UOCSR_WKUP (0x0004) +#define CCM_UOCSR_UOMIE (0x0002) +#define CCM_UOCSR_XPDE (0x0001) + +#define CCM_UHCSR_DRV_VBUS (0x0010) +#define CCM_UHCSR_PWRFLT (0x0008) +#define CCM_UHCSR_WKUP (0x0004) +#define CCM_UHCSR_UOMIE (0x0002) +#define CCM_UHCSR_XPDE (0x0001) + +#define CCM_MISCCR3_TMR_ENET (0x1000) +#define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8) +#define CCM_MISCCR3_ENETCLK_MASK (0xF8FF) +#define CCM_MISCCR3_ENETCLK_MII (0x0700) +#define CCM_MISCCR3_ENETCLK_OSC (0x0600) +#define CCM_MISCCR3_ENETCLK_USB (0x0500) +#define CCM_MISCCR3_ENETCLK_TMR3 (0x0400) +#define CCM_MISCCR3_ENETCLK_TMR2 (0x0300) +#define CCM_MISCCR3_ENETCLK_TMR1 (0x0200) +#define CCM_MISCCR3_ENETCLK_TMR0 (0x0100) +#define CCM_MISCCR3_ENETCLK_INTBUS (0x0000) + +#define CCM_MISCCR2_EXTCLKBYP (0x8000) +#define CCM_MISCCR2_DDR2CLK (0x4000) +#define CCM_MISCCR2_RGPIO_HALF (0x2000) +#define CCM_MISCCR2_SWTSCR (0x1000) +#define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8) +#define CCM_MISCCR2_PLLMODE_MASK (0xF8FF) +#define CCM_MISCCR2_DCCBYP (0x0080) +#define CCM_MISCCR2_DAC1SEL (0x0040) +#define CCM_MISCCR2_DAC0SEL (0x0020) +#define CCM_MISCCR2_ADCEN (0x0010) +#define CCM_MISCCR2_ADC7SEL (0x0008) +#define CCM_MISCCR2_ADC3SEL (0x0004) +#define CCM_MISCCR2_FBHALF (0x0002) +#define CCM_MISCCR2_ULPI (0x0001) + +#define CCM_FNACR_PCR(x) (((x)&0x0F)<<24) +#define CCM_FNACR_PCR_MASK (0xF0FFFFFF) +#define CCM_FNACR_MCC(x) ((x)&0xFFFF) +#define CCM_FNACR_MCC_MASK (0xFFFF0000) + +/* General Purpose I/O Module (GPIO) */ +#define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6) +#define GPIO_PAR_FBCTL_ALE_MASK (0x3F) +#define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0) +#define GPIO_PAR_FBCTL_ALE_FB_TS (0x80) +#define GPIO_PAR_FBCTL_ALE_GPIO (0x00) +#define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4) +#define GPIO_PAR_FBCTL_OE_MASK (0xCF) +#define GPIO_PAR_FBCTL_OE_FB_OE (0x30) +#define GPIO_PAR_FBCTL_OE_FB_TBST (0x20) +#define GPIO_PAR_FBCTL_OE_NFC_RE (0x20) +#define GPIO_PAR_FBCTL_OE_GPIO (0x00) +#define GPIO_PAR_FBCTL_FBCLK (0x08) +#define GPIO_PAR_FBCTL_RW (0x04) +#define GPIO_PAR_FBCTL_TA(x) ((x)&3) +#define GPIO_PAR_FBCTL_TA_MASK (0xFC) +#define GPIO_PAR_FBCTL_TA_TA (0x03) +#define GPIO_PAR_FBCTL_TA_NFC_RB (0x01) +#define GPIO_PAR_FBCTL_TA_GPIO (0x00) + +#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6) +#define GPIO_PAR_BE_BE3_MASK (0x3F) +#define GPIO_PAR_BE_BE3_BE3 (0xC0) +#define GPIO_PAR_BE_BE3_CS3 (0x80) +#define GPIO_PAR_BE_BE3_FB_A1 (0x40) +#define GPIO_PAR_BE_BE3_NFC_ALE (0x40) +#define GPIO_PAR_BE_BE3_GPIO (0x00) +#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4) +#define GPIO_PAR_BE_BE2_MASK (0xCF) +#define GPIO_PAR_BE_BE2_BE2 (0x30) +#define GPIO_PAR_BE_BE2_CS2 (0x20) +#define GPIO_PAR_BE_BE2_FB_A0 (0x10) +#define GPIO_PAR_BE_BE2_NFC_CLE (0x10) +#define GPIO_PAR_BE_BE2_GPIO (0x00) +#define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2) +#define GPIO_PAR_BE_BE1_MASK (0xF3) +#define GPIO_PAR_BE_BE1_BE1 (0x0C) +#define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08) +#define GPIO_PAR_BE_BE1_GPIO (0x00) +#define GPIO_PAR_BE_BS0(x) ((x)&0x03) +#define GPIO_PAR_BE_BE0_MASK (0xFC) +#define GPIO_PAR_BE_BE0_BE0 (0x03) +#define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02) +#define GPIO_PAR_BE_BE0_GPIO (0x00) + +#define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6) +#define GPIO_PAR_CS_CS5_MASK (0x3F) +#define GPIO_PAR_CS_CS5_CS5 (0xC0) +#define GPIO_PAR_CS_CS5_DACK1 (0x80) +#define GPIO_PAR_CS_CS5_GPIO (0x00) +#define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4) +#define GPIO_PAR_CS_CS4_MASK (0xCF) +#define GPIO_PAR_CS_CS4_CS4 (0x30) +#define GPIO_PAR_CS_CS4_DREQ1 (0x20) +#define GPIO_PAR_CS_CS4_GPIO (0x00) +#define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2) +#define GPIO_PAR_CS_CS1_MASK (0xF3) +#define GPIO_PAR_CS_CS1_CS1 (0x0C) +#define GPIO_PAR_CS_CS1_NFC_CE (0x04) +#define GPIO_PAR_CS_CS1_GPIO (0x00) +#define GPIO_PAR_CS_CS0_CS0 (0x01) + +#define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6) +#define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F) +#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0) +#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80) +#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40) +#define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00) +#define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4) +#define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF) +#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30) +#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20) +#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10) +#define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00) +#define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2) +#define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3) +#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C) +#define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08) +#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04) +#define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00) +#define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03) +#define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC) +#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03) +#define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02) +#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01) +#define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00) + +#define GPIO_PAR_IRQH_IRQ7 (0x10) +#define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2) +#define GPIO_PAR_IRQH_IRQ4_MASK (0xF3) +#define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C) +#define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08) +#define GPIO_PAR_IRQH_IRQ4_GPIO (0x00) +#define GPIO_PAR_IRQH_IRQ1 (0x03) + +#define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6) +#define GPIO_PAR_IRQL_IRQ6_MASK (0x3F) +#define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0) +#define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40) +#define GPIO_PAR_IRQL_IRQ6_GPIO (0x00) +#define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4) +#define GPIO_PAR_IRQL_IRQ3_MASK (0xCF) +#define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30) +#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20) +#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10) +#define GPIO_PAR_IRQL_IRQ3_GPIO (0x00) +#define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2) +#define GPIO_PAR_IRQL_IRQ2_MASK (0xF3) +#define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C) +#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08) +#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04) +#define GPIO_PAR_IRQL_IRQ2_GPIO (0x00) + +#define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6) +#define GPIO_PAR_DSPI0_SIN_MASK (0x3F) +#define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0) +#define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0) +#define GPIO_PAR_DSPI0_SIN_U3RXD (0x80) +#define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40) +#define GPIO_PAR_DSPI0_SIN_GPIO (0x00) +#define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4) +#define GPIO_PAR_DSPI0_SOUT_MASK (0xCF) +#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30) +#define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30) +#define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20) +#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10) +#define GPIO_PAR_DSPI0_SOUT_GPIO (0x00) +#define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2) +#define GPIO_PAR_DSPI0_SCK_MASK (0xF3) +#define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C) +#define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C) +#define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08) +#define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04) +#define GPIO_PAR_DSPI0_SCK_GPIO (0x00) +#define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03) +#define GPIO_PAR_DSPI0_PCS0_MASK (0xFC) +#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03) +#define GPIO_PAR_DSPI0_PCS0_SS (0x03) +#define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02) +#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01) +#define GPIO_PAR_DSPI0_PCS0_GPIO (0x00) + +#define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80) +#define GPIO_PAR_DSPIOW_SBF_CS (0x80) +#define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4) +#define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF) +#define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30) +#define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20) +#define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00) + +#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6) +#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0) +#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40) +#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40) +#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4) +#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30) +#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10) +#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2) +#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C) +#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04) +#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03) +#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03) +#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01) +#define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01) +#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +#define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6) +#define GPIO_PAR_UART2_U2CTS_MASK (0x3F) +#define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0) +#define GPIO_PAR_UART2_U2CTS_U6TXD (0x80) +#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40) +#define GPIO_PAR_UART2_U2CTS_GPIO (0x00) +#define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4) +#define GPIO_PAR_UART2_U2RTS_MASK (0xCF) +#define GPIO_PAR_UART2_U2RTS_U2RTS (0x30) +#define GPIO_PAR_UART2_U2RTS_U6RXD (0x20) +#define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10) +#define GPIO_PAR_UART2_U2RTS_GPIO (0x00) +#define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2) +#define GPIO_PAR_UART2_U2RXD_MASK (0xF3) +#define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C) +#define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08) +#define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04) +#define GPIO_PAR_UART2_U2RXD_GPIO (0x00) +#define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03) +#define GPIO_PAR_UART2_U2TXD_MASK (0xFC) +#define GPIO_PAR_UART2_U2TXD_U2TXD (0x03) +#define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02) +#define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01) +#define GPIO_PAR_UART2_U2TXD_GPIO (0x00) + +#define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6) +#define GPIO_PAR_UART1_U1CTS_MASK (0x3F) +#define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0) +#define GPIO_PAR_UART1_U1CTS_U5TXD (0x80) +#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40) +#define GPIO_PAR_UART1_U1CTS_GPIO (0x00) +#define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4) +#define GPIO_PAR_UART1_U1RTS_MASK (0xCF) +#define GPIO_PAR_UART1_U1RTS_U1RTS (0x30) +#define GPIO_PAR_UART1_U1RTS_U5RXD (0x20) +#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10) +#define GPIO_PAR_UART1_U1RTS_GPIO (0x00) +#define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2) +#define GPIO_PAR_UART1_U1RXD_MASK (0xF3) +#define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C) +#define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08) +#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04) +#define GPIO_PAR_UART1_U1RXD_GPIO (0x00) +#define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03) +#define GPIO_PAR_UART1_U1TXD_MASK (0xFC) +#define GPIO_PAR_UART1_U1TXD_U1TXD (0x03) +#define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02) +#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01) +#define GPIO_PAR_UART1_U1TXD_GPIO (0x00) + +#define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6) +#define GPIO_PAR_UART0_U0CTS_MASK (0x3F) +#define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0) +#define GPIO_PAR_UART0_U0CTS_U4TXD (0x80) +#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40) +#define GPIO_PAR_UART0_U0CTS_GPIO (0x00) +#define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4) +#define GPIO_PAR_UART0_U0RTS_MASK (0xCF) +#define GPIO_PAR_UART0_U0RTS_U0RTS (0x30) +#define GPIO_PAR_UART0_U0RTS_U4RXD (0x20) +#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10) +#define GPIO_PAR_UART0_U0RTS_GPIO (0x00) +#define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2) +#define GPIO_PAR_UART0_U0RXD_MASK (0xF3) +#define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C) +#define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08) +#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04) +#define GPIO_PAR_UART0_U0RXD_GPIO (0x00) +#define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03) +#define GPIO_PAR_UART0_U0TXD_MASK (0xFC) +#define GPIO_PAR_UART0_U0TXD_U0TXD (0x03) +#define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02) +#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01) +#define GPIO_PAR_UART0_U0TXD_GPIO (0x00) + +#define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6) +#define GPIO_PAR_SDHCH_DAT3_MASK (0x3F) +#define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0) +#define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80) +#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40) +#define GPIO_PAR_SDHCH_DAT3_GPIO (0x00) +#define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4) +#define GPIO_PAR_SDHCH_DAT2_MASK (0xCF) +#define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30) +#define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20) +#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10) +#define GPIO_PAR_SDHCH_DAT2_GPIO (0x00) +#define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2) +#define GPIO_PAR_SDHCH_DAT1_MASK (0xF3) +#define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C) +#define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08) +#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04) +#define GPIO_PAR_SDHCH_DAT1_GPIO (0x00) +#define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03) +#define GPIO_PAR_SDHCH_DAT0_MASK (0xFC) +#define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03) +#define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02) +#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01) +#define GPIO_PAR_SDHCH_DAT0_GPIO (0x00) + +#define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2) +#define GPIO_PAR_SDHCL_CMD_MASK (0xF3) +#define GPIO_PAR_SDHCL_CMD_CMD (0x0C) +#define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08) +#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04) +#define GPIO_PAR_SDHCL_CMD_GPIO (0x00) +#define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03) +#define GPIO_PAR_SDHCL_CLK_MASK (0xFC) +#define GPIO_PAR_SDHCL_CLK_CLK (0x03) +#define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02) +#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01) +#define GPIO_PAR_SDHCL_CLK_GPIO (0x00) + +#define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6) +#define GPIO_PAR_SIMP0H_DAT_MASK (0x3F) +#define GPIO_PAR_SIMP0H_DAT_DAT (0xC0) +#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80) +#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40) +#define GPIO_PAR_SIMP0H_DAT_GPIO (0x00) +#define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4) +#define GPIO_PAR_SIMP0H_VEN_MASK (0xCF) +#define GPIO_PAR_SIMP0H_VEN_VEN (0x30) +#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20) +#define GPIO_PAR_SIMP0H_VEN_GPIO (0x00) +#define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2) +#define GPIO_PAR_SIMP0H_RST_MASK (0xF3) +#define GPIO_PAR_SIMP0H_RST_RST (0x0C) +#define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08) +#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04) +#define GPIO_PAR_SIMP0H_RST_GPIO (0x00) +#define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03) +#define GPIO_PAR_SIMP0H_PD_MASK (0xFC) +#define GPIO_PAR_SIMP0H_PD_PD (0x03) +#define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02) +#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01) +#define GPIO_PAR_SIMP0H_PD_GPIO (0x00) + +#define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03) +#define GPIO_PAR_SIMP0L_CLK_MASK (0xFC) +#define GPIO_PAR_SIMP0L_CLK_CLK (0x03) +#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02) +#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01) +#define GPIO_PAR_SIMP0L_CLK_GPIO (0x00) + +#define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6) +#define GPIO_PAR_SSI0H_RXD_MASK (0x3F) +#define GPIO_PAR_SSI0H_RXD_RXD (0xC0) +#define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80) +#define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40) +#define GPIO_PAR_SSI0H_RXD_GPIO (0x00) +#define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4) +#define GPIO_PAR_SSI0H_TXD_MASK (0xCF) +#define GPIO_PAR_SSI0H_TXD_TXD (0x30) +#define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20) +#define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10) +#define GPIO_PAR_SSI0H_TXD_GPIO (0x00) +#define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2) +#define GPIO_PAR_SSI0H_FS_MASK (0xF3) +#define GPIO_PAR_SSI0H_FS_FS (0x0C) +#define GPIO_PAR_SSI0H_FS_U7TXD (0x08) +#define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04) +#define GPIO_PAR_SSI0H_FS_GPIO (0x00) +#define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03) +#define GPIO_PAR_SSI0H_MCLK_MASK (0xFC) +#define GPIO_PAR_SSI0H_MCLK_MCLK (0x03) +#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02) +#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01) +#define GPIO_PAR_SSI0H_MCLK_GPIO (0x00) + +#define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03) +#define GPIO_PAR_SSI0L_BCLK_MASK (0xFC) +#define GPIO_PAR_SSI0L_BCLK_BCLK (0x03) +#define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02) +#define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01) +#define GPIO_PAR_SSI0L_BCLK_GPIO (0x00) + +#define GPIO_PAR_DEBUGH1_DAT3 (0x40) +#define GPIO_PAR_DEBUGH1_DAT2 (0x10) +#define GPIO_PAR_DEBUGH1_DAT1 (0x04) +#define GPIO_PAR_DEBUGH1_DAT0 (0x01) + +#define GPIO_PAR_DEBUGH0_PST3 (0x40) +#define GPIO_PAR_DEBUGH0_PST2 (0x10) +#define GPIO_PAR_DEBUGH0_PST1 (0x04) +#define GPIO_PAR_DEBUGH0_PST0 (0x01) + +#define GPIO_PODR_G4_VAL (0x01 << 4) +#define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL) +#define GPIO_PDDR_G4_OUTPUT (0x01 << 4) +#define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT) + +#define GPIO_PAR_DEBUGL_ALLPST (0x01) + +#define GPIO_PAR_FEC_FEC(x) ((x)&0x0F) +#define GPIO_PAR_FEC_FEC_MASK (0xF0) +#define GPIO_PAR_FEC_FEC_GPIO (0x0D) +#define GPIO_PAR_FEC_FEC_RMII1 (0x0C) +#define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B) +#define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A) +#define GPIO_PAR_FEC_FEC_RMII0 (0x09) +#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08) +#define GPIO_PAR_FEC_FEC_RMII0FUL (0x07) +#define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06) +#define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */ +/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */ +#define GPIO_PAR_FEC_FEC_RMII0_1 (0x04) +#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03) +#define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */ +#define GPIO_PAR_FEC_FEC_MIIFUL (0x00) + + +/* TC: Need to edit here.... */ + +/* Mode Select Control */ +#define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03) +#define GPIO_MSCR_SDRAM_MSC_MASK (0xFC) + +/* Slew Rate Control */ + +#define GPIO_SRCR_FB3_FB3(x) ((x)&0x03) +#define GPIO_SRCR_FB3_FB3_MASK (0xFC) + +#define GPIO_SRCR_FB2_FB2(x) ((x)&0x03) +#define GPIO_SRCR_FB2_FB2_MASK (0xFC) + +#define GPIO_SRCR_FB1_FB1(x) ((x)&0x03) +#define GPIO_SRCR_FB1_FB1_MASK (0xFC) + +#define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2) +#define GPIO_SRCR_FB4_FB5_MASK (0xF3) +#define GPIO_SRCR_FB4_FB4(x) ((x)&0x03) +#define GPIO_SRCR_FB4_FB4_MASK (0xFC) + +#define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4) +#define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF) +#define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03) +#define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC) + +#define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2) +#define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3) +#define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03) +#define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC) + +#define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03) +#define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC) + +#define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6) +#define GPIO_SRCR_TIMER_TMR3_MASK (0x3F) +#define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4) +#define GPIO_SRCR_TIMER_TMR2_MASK (0xCF) +#define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2) +#define GPIO_SRCR_TIMER_TMR1_MASK (0xF3) +#define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03) +#define GPIO_SRCR_TIMER_TMR0_MASK (0xFC) + +#define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4) +#define GPIO_SRCR_UART_U2_MASK (0xCF) +#define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2) +#define GPIO_SRCR_UART_U1_MASK (0xF3) +#define GPIO_SRCR_UART_U0(x) ((x)&0x03) +#define GPIO_SRCR_UART_U0_MASK (0xFC) + +#define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2) +#define GPIO_SRCR_FEC_RMII0_MASK (0xF3) +#define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03) +#define GPIO_SRCR_FEC_RMII1_MASK (0xFC) + +#define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03) +#define GPIO_SRCR_SDHC_SDHC_MASK (0xFC) + +#define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03) +#define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC) + +#define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03) +#define GPIO_SRCR_SSI0_SSI0_MASK (0xFC) + +#define GPIO_PCR_URTS_U2 (0x0004) +#define GPIO_PCR_URTS_U1 (0x0002) +#define GPIO_PCR_URTS_U0 (0x0001) + +#define GPIO_PCR_UCTS_U2 (0x0004) +#define GPIO_PCR_UCTS_U1 (0x0002) +#define GPIO_PCR_UCTS_U0 (0x0001) + +#define GPIO_UTXD_WOM_U9 (0x0200) +#define GPIO_UTXD_WOM_U8 (0x0100) +#define GPIO_UTXD_WOM_U7 (0x0080) +#define GPIO_UTXD_WOM_U6 (0x0040) +#define GPIO_UTXD_WOM_U5 (0x0020) +#define GPIO_UTXD_WOM_U4 (0x0010) +#define GPIO_UTXD_WOM_U3 (0x0008) +#define GPIO_UTXD_WOM_U2 (0x0004) +#define GPIO_UTXD_WOM_U1 (0x0002) +#define GPIO_UTXD_WOM_U0 (0x0001) + +#define GPIO_URXD_WOM_U9(x) (((x)&3)<<18) +#define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF) +#define GPIO_URXD_WOM_U8(x) (((x)&3)<<16) +#define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF) +#define GPIO_URXD_WOM_U7(x) (((x)&3)<<14) +#define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF) +#define GPIO_URXD_WOM_U6(x) (((x)&3)<<12) +#define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF) +#define GPIO_URXD_WOM_U5(x) (((x)&3)<<10) +#define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF) +#define GPIO_URXD_WOM_U4(x) (((x)&3)<<8) +#define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF) +#define GPIO_URXD_WOM_U3(x) (((x)&3)<<6) +#define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F) +#define GPIO_URXD_WOM_U2(x) (((x)&3)<<4) +#define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF) +#define GPIO_URXD_WOM_U1(x) (((x)&3)<<2) +#define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3) +#define GPIO_URXD_WOM_U0(x) ((x)&3) +#define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC) + +#define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27) +#define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF) +#define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22) +#define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF) +#define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15) +#define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF) +#define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10) +#define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF) +#define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3) +#define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07) +#define GPIO_HCR1_PB2_0(x) ((x)&7) +#define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8) + +#define GPIO_HCR0_PK3 (0x00000400) +#define GPIO_HCR0_PK0 (0x00000200) +#define GPIO_HCR0_PD2_0(x) (((x)&7)<<6) +#define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F) +#define GPIO_HCR0_PE7 (0x00000020) +#define GPIO_HCR0_PH7_3(x) ((x)&0x1F) +#define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0) + +/* SDRAM Controller (SDRAMC) */ + +/* Phase Locked Loop (PLL) */ +#define PLL_CR_LOCIRQ (0x00040000) +#define PLL_CR_LOCRE (0x00020000) +#define PLL_CR_LOCEN (0x00010000) +#define PLL_CR_LOLIRQ (0x00004000) +#define PLL_CR_LOLRE (0x00002000) +#define PLL_CR_LOLEN (0x00001000) +#define PLL_CR_REFDIV(x) (((x)&7)<<8) +#define PLL_CR_REFDIV_MASK (0xFFFFF8FF) +#define PLL_CR_FBKDIV(x) ((x)&0x3F) +#define PLL_CR_FBKDIV_MASK (0xFFFFFFC0) +#define PLL_CR_FBKDIV_BITS (0x3F) + +#define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21) +#define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF) +#define PLL_DR_OUTDIV5_BITS (0x03E00000) +#define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16) +#define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF) +#define PLL_DR_OUTDIV4_BITS (0x001F0000) +#define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10) +#define PLL_DR_OUTDIV3_MASK (0xFFFF83FF) +#define PLL_DR_OUTDIV3_BITS (0x00007C00) +#define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5) +#define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F) +#define PLL_DR_OUTDIV2_BITS (0x000003E0) +#define PLL_DR_OUTDIV1(x) ((x)&0x1F) +#define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0) +#define PLL_DR_OUTDIV1_BITS (0x0000001F) + +#define PLL_SR_LOCF (0x00000200) +#define PLL_SR_LOC (0x00000100) +#define PLL_SR_LOLF (0x00000040) +#define PLL_SR_LOCKS (0x00000020) +#define PLL_SR_LOCK (0x00000010) +#define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */ +#define PLL_SR_MODE(x) ((x)&7) +#define PLL_SR_MODE_MASK (0xFFFFFFF8) + +#endif /* __MCF5441X__ */ -- cgit v1.2.3 From 186fc4db263fc6332d6712be99a9a387087d29c7 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Thu, 18 Oct 2012 19:25:52 +0000 Subject: ColdFire: Add Freescale MCF54418TWR ColdFire development board support Add Freescale MCF54418TWR ColdFire development board support. Signed-off-by: TsiChung Liew Signed-off-by: Jason Jin Signed-off-by: Alison Wang --- board/freescale/m54418twr/Makefile | 43 ++++ board/freescale/m54418twr/config.mk | 25 ++ board/freescale/m54418twr/m54418twr.c | 129 ++++++++++ board/freescale/m54418twr/u-boot.lds | 97 ++++++++ boards.cfg | 6 + doc/README.m54418twr | 244 ++++++++++++++++++ include/configs/M54418TWR.h | 448 ++++++++++++++++++++++++++++++++++ 7 files changed, 992 insertions(+) create mode 100644 board/freescale/m54418twr/Makefile create mode 100644 board/freescale/m54418twr/config.mk create mode 100644 board/freescale/m54418twr/m54418twr.c create mode 100644 board/freescale/m54418twr/u-boot.lds create mode 100644 doc/README.m54418twr create mode 100644 include/configs/M54418TWR.h diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile new file mode 100644 index 0000000000..1e53f48f5d --- /dev/null +++ b/board/freescale/m54418twr/Makefile @@ -0,0 +1,43 @@ +# Copyright 2010-2012 Freescale Semiconductor, Inc. +# TsiChung Liew (Tsi-Chung.Liew@freescale.com) +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk new file mode 100644 index 0000000000..a592335861 --- /dev/null +++ b/board/freescale/m54418twr/config.mk @@ -0,0 +1,25 @@ +# Copyright 2010-2012 Freescale Semiconductor, Inc. +# TsiChung Liew (Tsi-Chung.Liew@freescale.com) +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c new file mode 100644 index 0000000000..6e57bef896 --- /dev/null +++ b/board/freescale/m54418twr/m54418twr.c @@ -0,0 +1,129 @@ +/* + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + /* + * need to to: + * Check serial flash size. if 2mb evb, else 8mb demo + */ + puts("Board: "); + puts("Freescale MCF54418 Tower System\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + u32 dramsize; + +#if defined(CONFIG_SERIAL_BOOT) + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; +#else + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM); + ccm_t *ccm = (ccm_t *)MMAP_CCM; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + pm_t *pm = (pm_t *) MMAP_PM; + u32 i; + + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + + out_8(&pm->pmcr0, 0x2E); + out_8(&gpio->mscr_sdram, 1); + + clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF); + setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK); + + out_be32(&sdram->rcrcr, 0x40000000); + out_be32(&sdram->padcr, 0x01030203); + + out_be32(&sdram->cr00, 0x01010101); + out_be32(&sdram->cr01, 0x00000101); + out_be32(&sdram->cr02, 0x01010100); + out_be32(&sdram->cr03, 0x01010000); + out_be32(&sdram->cr04, 0x00010101); + out_be32(&sdram->cr06, 0x00010100); + out_be32(&sdram->cr07, 0x00000001); + out_be32(&sdram->cr08, 0x01000001); + out_be32(&sdram->cr09, 0x00000100); + out_be32(&sdram->cr10, 0x00010001); + out_be32(&sdram->cr11, 0x00000200); + out_be32(&sdram->cr12, 0x01000002); + out_be32(&sdram->cr13, 0x00000000); + out_be32(&sdram->cr14, 0x00000100); + out_be32(&sdram->cr15, 0x02000100); + out_be32(&sdram->cr16, 0x02000407); + out_be32(&sdram->cr17, 0x02030007); + out_be32(&sdram->cr18, 0x02000100); + out_be32(&sdram->cr19, 0x0A030203); + out_be32(&sdram->cr20, 0x00020708); + out_be32(&sdram->cr21, 0x00050008); + out_be32(&sdram->cr22, 0x04030002); + out_be32(&sdram->cr23, 0x00000004); + out_be32(&sdram->cr24, 0x020A0000); + out_be32(&sdram->cr25, 0x0C00000E); + out_be32(&sdram->cr26, 0x00002004); + out_be32(&sdram->cr28, 0x00100010); + out_be32(&sdram->cr29, 0x00100010); + out_be32(&sdram->cr31, 0x07990000); + out_be32(&sdram->cr40, 0x00000000); + out_be32(&sdram->cr41, 0x00C80064); + out_be32(&sdram->cr42, 0x44520002); + out_be32(&sdram->cr43, 0x00C80023); + out_be32(&sdram->cr45, 0x0000C350); + out_be32(&sdram->cr56, 0x04000000); + out_be32(&sdram->cr57, 0x03000304); + out_be32(&sdram->cr58, 0x40040000); + out_be32(&sdram->cr59, 0xC0004004); + out_be32(&sdram->cr60, 0x0642C000); + out_be32(&sdram->cr61, 0x00000642); + asm("tpf"); + + out_be32(&sdram->cr09, 0x01000100); + + udelay(100); +#endif + return dramsize; +}; + +int testdram(void) +{ + return 0; +} diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds new file mode 100644 index 0000000000..f341449346 --- /dev/null +++ b/board/freescale/m54418twr/u-boot.lds @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text : + { + arch/m68k/cpu/mcf5445x/start.o (.text*) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + KEEP(*(.got)) + __got_end = .; + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + _sbss = .; + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + __bss_end__ = . ; + PROVIDE (end = .); +} diff --git a/boards.cfg b/boards.cfg index b14a08ff15..4c63789041 100644 --- a/boards.cfg +++ b/boards.cfg @@ -380,6 +380,12 @@ M53017EVB m68k mcf532x m53017evb freesca M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0 M5329BFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=16 M5373EVB m68k mcf532x m5373evb freescale - M5373EVB:NANDFLASH_SIZE=16 +M54418TWR m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 +M54418TWR_nand_mii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 +M54418TWR_nand_rmii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 +M54418TWR_nand_rmii_lowfreq m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 +M54418TWR_serial_mii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 +M54418TWR_serial_rmii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 M54451EVB m68k mcf5445x m54451evb freescale - M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 M54451EVB_stmicro m68k mcf5445x m54451evb freescale - M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 M54455EVB m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 diff --git a/doc/README.m54418twr b/doc/README.m54418twr new file mode 100644 index 0000000000..f69ae01912 --- /dev/null +++ b/doc/README.m54418twr @@ -0,0 +1,244 @@ +Freescale MCF54418TWR ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created Mar 22, 2012 +=========================================== + + +Changed files: +============== + +- board/freescale/m54418twr/m54418twr.c Dram setup +- board/freescale/m54418twr/Makefile Makefile +- board/freescale/m54418twr/config.mk config make +- board/freescale/m54418twr/u-boot.lds Linker description + +- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code +- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs +- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf5445x/Makefile Makefile +- arch/m68k/cpu/mcf5445x/config.mk config make +- arch/m68k/cpu/mcf5445x/start.S start up assembly code + +- doc/README.m54418twr This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/net/mcfmii.c ColdFire common MII driver +- drivers/serial/mcfuart.c ColdFire common UART driver + +- arch/m68k/include/asm/bitops.h Bit operation function export +- arch/m68k/include/asm/byteorder.h Byte order functions +- arch/m68k/include/asm/fec.h FEC structure and definition +- arch/m68k/include/asm/global_data.h Global data structure +- arch/m68k/include/asm/immap.h ColdFire specific header file and driver macros +- arch/m68k/include/asm/immap_5441x.h mcf5441x specific header file +- arch/m68k/include/asm/io.h io functions +- arch/m68k/include/asm/m5441x.h mcf5441x specific header file +- arch/m68k/include/asm/posix_types.h Posix +- arch/m68k/include/asm/processor.h header file +- arch/m68k/include/asm/ptrace.h Exception structure +- arch/m68k/include/asm/rtc.h Realtime clock header file +- arch/m68k/include/asm/string.h String function export +- arch/m68k/include/asm/timer.h Timer structure and definition +- arch/m68k/include/asm/types.h Data types definition +- arch/m68k/include/asm/uart.h Uart structure and definition +- arch/m68k/include/asm/u-boot.h u-boot structure + +- include/configs/M54418TWR.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts.c Coldfire common interrupt functions +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code + +1 MCF5441x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M54418TWR Development Board +CONFIG_MCF5441x -- define for all MCF5441x CPUs +CONFIG_M54418 -- define for all Freescale MCF54418 CPUs +CONFIG_M54418TWR -- define for M54418TWR board + +CONFIG_MCFUART -- define to use common CF Uart driver +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_MII -- enable to use MII driver +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN -- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop +CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot + +CONFIG_MCFTMR -- define to use DMA timer + +CONFIG_SYS_IMMR -- define for MBAR offset + +CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc + +CONFIG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + MRAM: 0x00000000-0x0003FFFF (256KB) + DDR: 0x40000000-0x47FFFFFF (128MB) + SRAM: 0x80000000-0x8000FFFF (64KB) + IP: 0xE0000000-0xFFFFFFFF (512MB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF version) +from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot + make distclean + make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock + make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock + make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock + make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input clock + make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock + make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock + make + +4. SCREEN DUMP +============== +4.1 M54418TWR Development board + Boot from NAND flash (NOTE: May not show exactly the same) + +U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54) + +CPU: Freescale MCF54418 (Mask:a3 Version:1) + CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz + INP CLK 50 MHz VCO CLK 500 MHz +Board: Freescale MCF54418 Tower System +SPI: ready +DRAM: 128 MiB +NAND: 256 MiB +In: serial +Out: serial +Err: serial +Net: FEC0, FEC1 +-> pri +baudrate=115200 +bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k +ernel)ro,-(jffs2) console=ttyS0,115200 +bootdelay=2 +eth1addr=00:e0:0c:bc:e5:61 +ethact=FEC0 +ethaddr=00:e0:0c:bc:e5:60 +fileaddr=40010000 +filesize=27354 +gatewayip=192.168.1.1 +hostname=M54418TWR +inpclk=50000000 +ipaddr=192.168.1.2 +load=tftp ${loadaddr} ${u-boot}; +loadaddr=0x40010000 +mem=129024k +netdev=eth0 +netmask=255.255.255.0 +prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save +serverip=192.168.1.1 +stderr=serial +stdin=serial +stdout=serial +u-boot=u-boot.bin +upd=run load; run prog + +Environment size: 653/131068 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x08000000 +flashstart = 0x00000000 +flashsize = 0x00000000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00010000 +mbar = 0xFC000000 +cpufreq = 250 MHz +busfreq = 125 MHz +flbfreq = 125 MHz +inpfreq = 50 MHz +vcofreq = 500 MHz +ethaddr = 00:e0:0c:bc:e5:60 +eth1addr = 00:e0:0c:bc:e5:61 +ip_addr = 192.168.1.2 +baudrate = 115200 bps +-> help +? - alias for 'help' +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BOOTP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +dcache - enable or disable data cache +dhcp - boot image via network using DHCP/TFTP protocol +echo - echo args to console +editenv - edit environment variable +env - environment handling commands +exit - exit script +false - do nothing, unsuccessfully +go - start application at address 'addr' +help - print command description/usage +icache - enable or disable instruction cache +iminfo - print header information for application image +imxtract- extract a part of a multi-image +itest - return true/false on integer compare +loop - infinite loop on address range +md - memory display +mdio - MDIO utility commands +mii - MII utility commands +mm - memory modify (auto-incrementing address) +mtest - simple RAM read/write test +mw - memory write (fill) +nand - NAND sub-system +nb_update- Nand boot update program +nboot - boot from NAND device +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +reginfo - print register information +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sf - SPI flash sub-system +showvar - print local hushshell variables +sleep - delay execution for some time +source - run script from memory +sspi - SPI utility command +test - minimal test like /bin/sh +tftpboot- boot image via network using TFTP protocol +true - do nothing, successfully +version - print monitor, compiler and linker version diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h new file mode 100644 index 0000000000..6c96111a7e --- /dev/null +++ b/include/configs/M54418TWR.h @@ -0,0 +1,448 @@ +/* + * Configuation settings for the Freescale MCF54418 TWR board. + * + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M54418TWR_H +#define _M54418TWR_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5441x /* define processor family */ +#define CONFIG_M54418 /* define processor type */ +#define CONFIG_M54418TWR /* M54418TWR board */ + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_UBI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_NAND_YAFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +/* + * NAND FLASH + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_JFFS2_NAND +#define CONFIG_NAND_FSL_NFC +#define CONFIG_SYS_NAND_BASE 0xFC0FC000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 +#define CONFIG_SYS_DISCOVER_PHY +#define CONFIG_SYS_RX_ETH_BUFFER 2 +#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN +#define CONFIG_SYS_TX_ETH_BUFFER 2 +#define CONFIG_HAS_ETH1 + +#define CONFIG_SYS_FEC0_PINMUX 0 +#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE +#define CONFIG_SYS_FEC1_PINMUX 0 +#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE +#define MCFFEC_TOUT_LOOP 50000 +#define CONFIG_SYS_FEC0_PHYADDR 0 +#define CONFIG_SYS_FEC1_PHYADDR 1 + +#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ + +#ifdef CONFIG_SYS_NAND_BOOT +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ + "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ + "-(jffs2) console=ttyS0,115200" +#else +#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ + __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ + __stringify(CONFIG_IPADDR) " ip=" \ + __stringify(CONFIG_IPADDR) ":" \ + __stringify(CONFIG_SERVERIP)":" \ + __stringify(CONFIG_GATEWAYIP)": " \ + __stringify(CONFIG_NETMASK) \ + "::eth0:off:rw console=ttyS0,115200" +#endif + +#define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +#define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_IPADDR 192.168.1.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 + +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SYS_FEC_BUF_USE_SRAM +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ +#ifndef CONFIG_SYS_DISCOVER_PHY +#define FECDUPLEX FULL +#define FECSPEED _100BASET +#define LINKSTATUS 1 +#else +#define LINKSTATUS 0 +#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#endif +#endif /* CONFIG_SYS_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME M54418TWR + +#if defined(CONFIG_CF_SBF) +/* ST Micro serial flash */ +#define CONFIG_SYS_LOAD_ADDR2 0x40010007 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "sbfhdr=sbfhdr.bin\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${sbfhdr};" \ + "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ + "upd=run load; run prog\0" \ + "prog=sf probe 0:1 1000000 3;" \ + "sf erase 0 40000;" \ + "sf write ${loadaddr} 0 40000;" \ + "save\0" \ + "" +#elif defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=0x40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr} ${u-boot};\0" \ + "upd=run load; run prog\0" \ + "prog=nand device 0;" \ + "nand erase 0 40000;" \ + "nb_update ${loadaddr} ${filesize};" \ + "save\0" \ + "" +#else +#define CONFIG_SYS_UBOOT_END 0x3FFFF +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off mram" " ;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" +#endif + +/* Realtime clock */ +#undef CONFIG_MCFRTC +#define CONFIG_RTC_MCFRRTC +#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#undef CONFIG_FSL_I2C +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +/* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x58000 +#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR + +/* DSPI and Serial Flash */ +#define CONFIG_CF_SPI +#define CONFIG_CF_DSPI +#define CONFIG_SERIAL_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#ifdef CONFIG_CMD_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_ATMEL + +# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1)) +# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) +# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) +#endif + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ + +/* HUSH */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_PROMPT "-> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +/* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 256 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) +#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) +#define CONFIG_SYS_DRAM_TEST + +#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_SERIAL_BOOT +#endif + +#if defined(CONFIG_SERIAL_BOOT) +#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400) +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_MRAM 1 +#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ +#define CONFIG_ENV_SIZE 0x1000 +#endif + +#if defined(CONFIG_CF_SBF) +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SPI_CS 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#endif +#if defined(CONFIG_SYS_NAND_BOOT) +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#endif +#undef CONFIG_ENV_OVERWRITE + +/* FLASH organization */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE + +#undef CONFIG_SYS_FLASH_CFI +#ifdef CONFIG_SYS_FLASH_CFI + +#define CONFIG_FLASH_CFI_DRIVER 1 +/* Max size that the board might have */ +#define CONFIG_SYS_FLASH_SIZE 0x1000000 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 270 +/* "Real" (hardware) sectors protection */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } +#else +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 270 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 0 +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_OFFSET (0x800000) +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=m54418twr.nand" + +#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ + "7m(kernel)," \ + "-(rootfs)" + +#endif + +#ifdef CONFIG_CMD_UBI +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts command */ +#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ +#define CONFIG_RBTREE +#define MTDIDS_DEFAULT "nand0=NAND" +#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ + "-(ubi)" +#endif +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 12) + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 16MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ + + /* Flash */ +#define CONFIG_SYS_CS0_BASE 0x00000000 +#define CONFIG_SYS_CS0_MASK 0x000F0101 +#define CONFIG_SYS_CS0_CTRL 0x00001D60 + +#endif /* _M54418TWR_H */ -- cgit v1.2.3 From 000820b5835c2b8b863af992b66dc973dc4bd202 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Thu, 8 Mar 2012 17:15:47 +0530 Subject: am335x: Enable RTC 32K OSC clock In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 21 ++++++++++++++++++++- arch/arm/cpu/armv7/am33xx/clock.c | 6 ++++++ arch/arm/include/asm/arch-am33xx/cpu.h | 15 +++++++++++++++ arch/arm/include/asm/arch-am33xx/hardware.h | 4 ++++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 6de03fd657..772203fe5b 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -116,11 +116,27 @@ static int read_eeprom(void) return 0; } -/* UART Defines */ #ifdef CONFIG_SPL_BUILD +/* UART Defines */ #define UART_RESET (0x1 << 1) #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) + +static void rtc32k_enable(void) +{ + struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(0x83e70b13, &rtc->kick0r); + writel(0x95a4f1e0, &rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), &rtc->osc); +} #endif /* @@ -154,6 +170,9 @@ void s_init(void) /* Setup the PLLs and the clocks for the peripherals */ pll_init(); + /* Enable RTC32K clock */ + rtc32k_enable(); + /* UART softreset */ u32 regVal; diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 2b19506a34..f870859414 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -44,6 +44,7 @@ const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; +const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; static void enable_interface_clocks(void) { @@ -153,6 +154,11 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmper->spi0clkctrl); while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) ; + + /* RTC */ + writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); + while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 6cfbef76a7..819fd2f026 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -169,6 +169,12 @@ struct cm_dpll { unsigned int clktimer2clk; /* offset 0x08 */ }; +/* Control Module RTC registers */ +struct cm_rtc { + unsigned int rtcclkctrl; /* offset 0x0 */ + unsigned int clkstctrl; /* offset 0x4 */ +}; + /* Watchdog timer registers */ struct wd_timer { unsigned int resv1[4]; @@ -218,6 +224,15 @@ struct gptimer { unsigned int tcar2; /* offset 0x58 */ }; +/* RTC Registers */ +struct rtc_regs { + unsigned int res[21]; + unsigned int osc; /* offset 0x54 */ + unsigned int res2[5]; + unsigned int kick0r; /* offset 0x6c */ + unsigned int kick1r; /* offset 0x70 */ +}; + /* UART Registers */ struct uart_sys { unsigned int resv1[21]; diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 62332f2ded..5bd4bc8722 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -61,6 +61,7 @@ #define CM_WKUP 0x44E00400 #define CM_DPLL 0x44E00500 #define CM_DEVICE 0x44E00700 +#define CM_RTC 0x44E00800 #define CM_CEFUSE 0x44E00A00 #define PRM_DEVICE 0x44E00F00 @@ -83,4 +84,7 @@ #define AM335X_CPSW_BASE 0x4A100000 #define AM335X_CPSW_MDIO_BASE 0x4A101000 +/* RTC base address */ +#define AM335X_RTC_BASE 0x44E3E000 + #endif /* __AM33XX_HARDWARE_H */ -- cgit v1.2.3 From 9f670540143bb43cf6e659aba26b59ee76e845eb Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Oct 2012 04:02:20 +0000 Subject: OMAP3: mt_ventoux: power on USB at startup Updated revision of the board uses GPIOs to activate the USB ports. Signed-off-by: Stefano Babic --- board/teejet/mt_ventoux/mt_ventoux.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index ecb9b6c413..9622a81280 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -45,6 +45,8 @@ DECLARE_GLOBAL_DATA_PTR; #define BUZZER 140 #define SPEAKER 141 +#define USB1_PWR 127 +#define USB2_PWR 149 #ifndef CONFIG_FPGA #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" @@ -247,6 +249,12 @@ int board_init(void) gpio_direction_output(BUZZER, 0); gpio_direction_output(SPEAKER, 0); + /* Activate USB power */ + gpio_request(USB1_PWR, "USB1_PWR"); + gpio_request(USB2_PWR, "USB2_PWR"); + gpio_direction_output(USB1_PWR, 1); + gpio_direction_output(USB2_PWR, 1); + return 0; } -- cgit v1.2.3 From e47c9e8608df6c95b6a324925573bac12045e059 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Oct 2012 04:07:03 +0000 Subject: OMAP3: updated pinmux and environment for new revision of mcx board The mcx board was slightly modified and the pinmux must be updated. There is no need to support the old board, that becomes obsolete. Signed-off-by: Stefano Babic --- board/htkw/mcx/mcx.h | 26 +++++++++++++------------- include/configs/mcx.h | 12 +++++++----- 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h index 867cc9e88d..1003bfddd9 100644 --- a/board/htkw/mcx/mcx.h +++ b/board/htkw/mcx/mcx.h @@ -143,28 +143,28 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\ - MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ - MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ /* CAMERA */\ @@ -313,11 +313,11 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \ /* HSUSB */\ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 359522a649..d3061a294c 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -256,22 +256,24 @@ "run nandargs; " \ "ubi part nand0,4;" \ "ubi readvol ${loadaddr} kernel;" \ - "run addip addtty addmtd addfb addeth addmisc;" \ + "run addtty addmtd addfb addeth addmisc;" \ "bootm ${loadaddr}\0" \ - "swupdate_args=setenv bootargs ubi.mtd=6 root=ubi0:fs_recovery "\ - "rootfstype=ubifs quiet loglevel=1 " \ - "consoleblank=0 ${swupdate_misc}\0" \ + "swupdate_args=setenv bootargs root=/dev/ram " \ + "quiet loglevel=1 " \ + "consoleblank=0 ${swupdate_misc}\0" \ "swupdate=echo Running Sw-Update...;" \ "if printenv mtdparts;then echo Starting SwUpdate...; " \ "else mtdparts default;fi; " \ "ubi part nand0,5;" \ "ubi readvol 0x82000000 kernel_recovery;" \ + "ubi part nand0,6;" \ + "ubi readvol 0x84000000 fs_recovery;" \ "run swupdate_args; " \ "setenv bootargs ${bootargs} " \ "${mtdparts} " \ "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ "omapdss.def_disp=lcd;" \ - "bootm ${loadaddr}\0" + "bootm 0x82000000 0x84000000\0" #define CONFIG_BOOTCOMMAND \ "run nandboot" -- cgit v1.2.3 From 8c735b990989bcd3909081aff7e6913222ac38e9 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Oct 2012 04:07:04 +0000 Subject: OMAP3: mcx: updated to new hardware revision Some GPIOs differ in the new revision board. Previous revision are considered obsolete and they will not anymore supported. Signed-off-by: Stefano Babic --- board/htkw/mcx/mcx.c | 19 +++---------------- board/htkw/mcx/mcx.h | 2 +- include/configs/mcx.h | 3 +-- 3 files changed, 5 insertions(+), 19 deletions(-) diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 7c9d34ab84..1f9840c34d 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -37,12 +37,12 @@ DECLARE_GLOBAL_DATA_PTR; -#define HOT_WATER_BUTTON 38 +#define HOT_WATER_BUTTON 42 #ifdef CONFIG_USB_EHCI static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, }; @@ -87,6 +87,7 @@ int board_late_init(void) return 0; setenv("bootcmd", "run swupdate"); + return 0; } #endif @@ -108,17 +109,3 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0); } #endif - -#ifdef CONFIG_USB_EHCI_OMAP -#define USB_HOST_PWR_EN 132 -int board_usb_init(void) -{ - if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) { - puts("Failed to get USB_HOST_PWR_EN pin\n"); - return -ENODEV; - } - gpio_direction_output(USB_HOST_PWR_EN, 1); - - return 0; -} -#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h index 1003bfddd9..f9601c641f 100644 --- a/board/htkw/mcx/mcx.h +++ b/board/htkw/mcx/mcx.h @@ -96,7 +96,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \ + MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \ /* GPIO_43 LCD buffer enable */ \ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index d3061a294c..96e1059965 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -115,8 +115,7 @@ #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT_OMAP /*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 /* commands to include */ -- cgit v1.2.3 From 60c41d907e234871b40f14283dc2e18abc324461 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Oct 2012 04:07:05 +0000 Subject: VIDEO: add macro to set LCD size for DSS driver Signed-off-by: Stefano Babic Acked-by: Anatolij Gustschin --- arch/arm/include/asm/arch-omap3/dss.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index 54add4b456..ffaffbb3bf 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -190,6 +190,7 @@ struct panel_config { #define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw)) #define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw)) +#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1)) /* Generic DSS Functions */ void omap3_dss_venc_config(const struct venc_regs *venc_cfg, -- cgit v1.2.3 From 8f1fae26a7fb4c0c2897f2f086fe8a3e1da58a9a Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Sat, 20 Oct 2012 23:56:07 +0000 Subject: OMAP3: add video support to the mcx board Add video support to the board with the display focaltech etm070003dh6. Signed-off-by: Stefano Babic --- board/htkw/mcx/mcx.c | 41 +++++++++++++++++++++++++++++++++++++++++ board/htkw/mcx/mcx.h | 2 ++ include/configs/mcx.h | 16 +++++++++++++++- 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 1f9840c34d..9fe6408ecf 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include "errno.h" #include #ifdef CONFIG_USB_EHCI @@ -38,6 +40,10 @@ DECLARE_GLOBAL_DATA_PTR; #define HOT_WATER_BUTTON 42 +#define LCD_OUTPUT 55 + +/* Address of the framebuffer in RAM. */ +#define FB_START_ADDRESS 0x88000000 #ifdef CONFIG_USB_EHCI static struct omap_usbhs_board_data usbhs_bdata = { @@ -67,6 +73,8 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + gpio_direction_output(LCD_OUTPUT, 0); + return 0; } @@ -109,3 +117,36 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0); } #endif + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) + +static struct panel_config lcd_cfg = { + .timing_h = PANEL_TIMING_H(40, 40, 48), + .timing_v = PANEL_TIMING_V(29, 13, 3), + .pol_freq = 0x00003000, /* Pol Freq */ + .divisor = 0x0001000E, + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = 0, + .lcd_size = PANEL_LCD_SIZE(800, 480), +}; + +int board_video_init(void) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + void *fb; + + fb = (void *)FB_START_ADDRESS; + + lcd_cfg.frame_buffer = fb; + + setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); + setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); + + omap3_dss_panel_config(&lcd_cfg); + omap3_dss_enable(); + + return 0; +} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h index f9601c641f..0d4c642203 100644 --- a/board/htkw/mcx/mcx.h +++ b/board/htkw/mcx/mcx.h @@ -264,6 +264,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \ + /* GPIO_170 Touchscreen ISR */\ /* McSPI */\ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 96e1059965..bf49cc1381 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -181,7 +181,7 @@ #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" @@ -257,6 +257,10 @@ "ubi readvol ${loadaddr} kernel;" \ "run addtty addmtd addfb addeth addmisc;" \ "bootm ${loadaddr}\0" \ + "preboot=ubi part nand0,7;" \ + "ubi readvol ${loadaddr} splash;" \ + "bmp display ${loadaddr};" \ + "gpio set 55\0" \ "swupdate_args=setenv bootargs root=/dev/ram " \ "quiet loglevel=1 " \ "consoleblank=0 ${swupdate_misc}\0" \ @@ -303,6 +307,7 @@ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ /* address */ +#define CONFIG_PREBOOT /* * AM3517 has 12 GP timers, they can be driven by the system clock @@ -422,4 +427,13 @@ #define CONFIG_NET_RETRY_COUNT 10 #endif +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_OMAP3 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 22cbeed454087ffa6ae6e56880bfff125497619b Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Wed, 17 Oct 2012 09:20:46 +0000 Subject: omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED D0/D1 Swapped or not is a board property, not anything specific to the am33xx SoC, so add a custom define for it. At the same time correct the bit handling for the swapped mode (DPE0 should be cleared and SI/DPE1 set). Signed-off-by: Peter Korsgaard --- drivers/spi/omap3_spi.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index e40a632caa..6791a7e0ec 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -173,14 +173,13 @@ int spi_claim_bus(struct spi_slave *slave) /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS * REVISIT: this controller could support SPI_3WIRE mode. */ -#ifdef CONFIG_AM33XX +#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED /* - * The reference design on AM33xx has D0 and D1 wired up opposite - * of how it has been done on previous platforms. We assume that - * custom hardware will also follow this convention. + * Some boards have D0 wired as MOSI / D1 as MISO instead of + * The normal D0 as MISO / D1 as MOSI. */ - conf &= OMAP3_MCSPI_CHCONF_DPE0; - conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); + conf &= ~OMAP3_MCSPI_CHCONF_DPE0; + conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1; #else conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); conf |= OMAP3_MCSPI_CHCONF_DPE0; -- cgit v1.2.3 From 79b9ebb7007cd99409ff506c1bf57b2ab0975243 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 16 Oct 2012 13:06:06 +0000 Subject: omapimage: Add support for byteswapped SPI images Add MLO.byteswap as a target to spl/Makefile and un-guard the first MLO rule so we don't have to duplicate it. Signed-off-by: Tom Rini --- spl/Makefile | 9 ++---- tools/omapimage.c | 83 +++++++++++++++++++++++++++++++++++++++++++------------ 2 files changed, 68 insertions(+), 24 deletions(-) diff --git a/spl/Makefile b/spl/Makefile index 92267d6dea..7b52bd1070 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -112,16 +112,13 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -ifdef CONFIG_OMAP $(OBJTREE)/MLO: $(obj)u-boot-spl.bin $(OBJTREE)/tools/mkimage -T omapimage \ -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ -endif -ifdef CONFIG_AM33XX -$(OBJTREE)/MLO: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mkimage -T omapimage \ + +$(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin + $(OBJTREE)/tools/mkimage -T omapimage -n byteswap \ -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ -endif ALL-y += $(obj)u-boot-spl.bin diff --git a/tools/omapimage.c b/tools/omapimage.c index 5e739ac647..d242cca3a8 100644 --- a/tools/omapimage.c +++ b/tools/omapimage.c @@ -42,6 +42,18 @@ #define OMAP_GP_HDR_SIZE (sizeof(struct gp_header)) #define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE) +static int do_swap32 = 0; + +static uint32_t omapimage_swap32(uint32_t data) +{ + uint32_t result = 0; + result = (data & 0xFF000000) >> 24; + result |= (data & 0x00FF0000) >> 8; + result |= (data & 0x0000FF00) << 8; + result |= (data & 0x000000FF) << 24; + return result; +} + static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE]; static int omapimage_check_image_types(uint8_t type) @@ -80,12 +92,17 @@ static int omapimage_verify_header(unsigned char *ptr, int image_size, { struct ch_toc *toc = (struct ch_toc *)ptr; struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); - uint32_t offset, size; + uint32_t offset, size, gph_size, gph_load_addr; while (toc->section_offset != 0xffffffff && toc->section_size != 0xffffffff) { - offset = toc->section_offset; - size = toc->section_size; + if (do_swap32) { + offset = omapimage_swap32(toc->section_offset); + size = omapimage_swap32(toc->section_size); + } else { + offset = toc->section_offset; + size = toc->section_size; + } if (!offset || !size) return -1; if (offset >= OMAP_CH_HDR_SIZE || @@ -93,9 +110,18 @@ static int omapimage_verify_header(unsigned char *ptr, int image_size, return -1; toc++; } - if (!valid_gph_size(gph->size)) + + if (do_swap32) { + gph_size = omapimage_swap32(gph->size); + gph_load_addr = omapimage_swap32(gph->load_addr); + } else { + gph_size = gph->size; + gph_load_addr = gph->load_addr; + } + + if (!valid_gph_size(gph_size)) return -1; - if (!valid_gph_load_addr(gph->load_addr)) + if (!valid_gph_load_addr(gph_load_addr)) return -1; return 0; @@ -128,12 +154,17 @@ static void omapimage_print_header(const void *ptr) const struct ch_toc *toc = (struct ch_toc *)ptr; const struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); - uint32_t offset, size; + uint32_t offset, size, gph_size, gph_load_addr; while (toc->section_offset != 0xffffffff && toc->section_size != 0xffffffff) { - offset = toc->section_offset; - size = toc->section_size; + if (do_swap32) { + offset = omapimage_swap32(toc->section_offset); + size = omapimage_swap32(toc->section_size); + } else { + offset = toc->section_offset; + size = toc->section_size; + } if (offset >= OMAP_CH_HDR_SIZE || offset+size >= OMAP_CH_HDR_SIZE) @@ -148,22 +179,26 @@ static void omapimage_print_header(const void *ptr) toc++; } - if (!valid_gph_size(gph->size)) { - fprintf(stderr, - "Error: invalid image size %x\n", - gph->size); + if (do_swap32) { + gph_size = omapimage_swap32(gph->size); + gph_load_addr = omapimage_swap32(gph->load_addr); + } else { + gph_size = gph->size; + gph_load_addr = gph->load_addr; + } + + if (!valid_gph_size(gph_size)) { + fprintf(stderr, "Error: invalid image size %x\n", gph_size); exit(EXIT_FAILURE); } - if (!valid_gph_load_addr(gph->load_addr)) { - fprintf(stderr, - "Error: invalid image load address %x\n", - gph->size); + if (!valid_gph_load_addr(gph_load_addr)) { + fprintf(stderr, "Error: invalid image load address %x\n", + gph_load_addr); exit(EXIT_FAILURE); } - printf("GP Header: Size %x LoadAddr %x\n", - gph->size, gph->load_addr); + printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr); } static int toc_offset(void *hdr, void *member) @@ -194,6 +229,18 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE; gph->load_addr = params->addr; + + if (strncmp(params->imagename, "byteswap", 8) == 0) { + do_swap32 = 1; + int swapped = 0; + uint32_t *data = (uint32_t *)ptr; + + while (swapped <= (sbuf->st_size / sizeof(uint32_t))) { + *data = omapimage_swap32(*data); + swapped++; + data++; + } + } } int omapimage_check_params(struct mkimage_params *params) -- cgit v1.2.3 From 69916bcf71766d85cc6a7131a1d5716a724a8475 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 16 Oct 2012 13:06:07 +0000 Subject: am33xx: Add SPI SPL as an option Add the required config.mk logic for this SoC as well as the BOOT_DEVICE define. Finally, enable the options on the am335x_evm. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/config.mk | 1 + arch/arm/include/asm/arch-am33xx/spl.h | 1 + include/configs/am335x_evm.h | 7 +++++++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk index 5750bbdcb6..babf0eb5cc 100644 --- a/arch/arm/cpu/armv7/am33xx/config.mk +++ b/arch/arm/cpu/armv7/am33xx/config.mk @@ -13,6 +13,7 @@ # ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/MLO +ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap else ALL-y += $(obj)u-boot.img endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 63ed10b257..644ff353fe 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -27,6 +27,7 @@ #define BOOT_DEVICE_NAND 5 #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ +#define BOOT_DEVICE_SPI 11 #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 9d807391ba..58d62d0c7d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -218,6 +218,13 @@ #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" #define CONFIG_SPL_ETH_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* -- cgit v1.2.3 From c50cce275866b4b0e36e1102041d7ee7aa24ee28 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Oct 2012 01:21:08 +0000 Subject: am33xx/board.c: make wdtimer/uart_base static Only used here (and uart_base only for SPL). Signed-off-by: Peter Korsgaard --- arch/arm/cpu/armv7/am33xx/board.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 772203fe5b..0b8b76d1f2 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -36,8 +36,10 @@ DECLARE_GLOBAL_DATA_PTR; -struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; +#ifdef CONFIG_SPL_BUILD +static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +#endif static const struct gpio_bank gpio_bank_am33xx[4] = { { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, -- cgit v1.2.3 From e363426e999b786ee4791f49d90ae84a3210f7b8 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Oct 2012 01:21:09 +0000 Subject: am33xx: move ti i2c baseboard header handling to board/ti/am335x/ The i2c header is specific to ti(-derived) boards, and not generic for all am335x boards. Signed-off-by: Peter Korsgaard [trini: Make re-apply with rtc32k_enable() applied] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 261 ----------------------- arch/arm/include/asm/arch-am33xx/sys_proto.h | 27 --- board/ti/am335x/Makefile | 1 + board/ti/am335x/board.c | 299 +++++++++++++++++++++++++++ board/ti/am335x/board.h | 49 +++++ board/ti/am335x/mux.c | 1 + 6 files changed, 350 insertions(+), 288 deletions(-) create mode 100644 board/ti/am335x/board.c create mode 100644 board/ti/am335x/board.h diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 0b8b76d1f2..8280b35508 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -36,11 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#ifdef CONFIG_SPL_BUILD -static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; -#endif - static const struct gpio_bank gpio_bank_am33xx[4] = { { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -50,172 +45,6 @@ static const struct gpio_bank gpio_bank_am33xx[4] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; -/* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0xA - -/* GPIO that controls power to DDR on EVM-SK */ -#define GPIO_DDR_VTT_EN 7 - -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -static struct am335x_baseboard_id __attribute__((section (".data"))) header; - -static inline int board_is_bone(void) -{ - return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); -} - -static inline int board_is_bone_lt(void) -{ - return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); -} - -static inline int board_is_evm_sk(void) -{ - return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); -} - -/* - * Read header information from EEPROM into global structure. - */ -static int read_eeprom(void) -{ - /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { - puts("Could not probe the EEPROM; something fundamentally " - "wrong on the I2C bus.\n"); - return -ENODEV; - } - - /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, - sizeof(header))) { - puts("Could not read the EEPROM; something fundamentally" - " wrong on the I2C bus.\n"); - return -EIO; - } - - if (header.magic != 0xEE3355AA) { - /* - * read the eeprom using i2c again, - * but use only a 1 byte address - */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, - (uchar *)&header, sizeof(header))) { - puts("Could not read the EEPROM; something " - "fundamentally wrong on the I2C bus.\n"); - return -EIO; - } - - if (header.magic != 0xEE3355AA) { - printf("Incorrect magic number (0x%x) in EEPROM\n", - header.magic); - return -EINVAL; - } - } - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -/* UART Defines */ -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -static void rtc32k_enable(void) -{ - struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; - - /* - * Unlock the RTC's registers. For more details please see the - * RTC_SS section of the TRM. In order to unlock we need to - * write these specific values (keys) in this order. - */ - writel(0x83e70b13, &rtc->kick0r); - writel(0x95a4f1e0, &rtc->kick1r); - - /* Enable the RTC 32K OSC by setting bits 3 and 6. */ - writel((1 << 3) | (1 << 6), &rtc->osc); -} -#endif - -/* - * Determine what type of DDR we have. - */ -static short inline board_memory_type(void) -{ - /* The following boards are known to use DDR3. */ - if (board_is_evm_sk() || board_is_bone_lt()) - return EMIF_REG_SDRAM_TYPE_DDR3; - - return EMIF_REG_SDRAM_TYPE_DDR2; -} - -/* - * early system init of muxing and clocks. - */ -void s_init(void) -{ - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - - /* UART softreset */ - u32 regVal; - - enable_uart0_pin_mux(); - - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_RESET; - writel(regVal, &uart_base->uartsyscfg); - while ((readl(&uart_base->uartsyssts) & - UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) - ; - - /* Disable smart idle */ - regVal = readl(&uart_base->uartsyscfg); - regVal |= UART_SMART_IDLE_EN; - writel(regVal, &uart_base->uartsyscfg); - - gd = &gdata; - - preloader_console_init(); - - /* Initalize the board header */ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) - puts("Could not get board ID.\n"); - - enable_board_pin_mux(&header); - if (board_is_evm_sk()) { - /* - * EVM SK 1.2A and later use gpio0_7 to enable DDR3. - * This is safe enough to do on older revs. - */ - gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); - gpio_direction_output(GPIO_DDR_VTT_EN, 1); - } - - config_ddr(board_memory_type()); -#endif -} - #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { @@ -234,93 +63,3 @@ void setup_clocks_for_console(void) /* Not yet implemented */ return; } - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - if (read_eeprom() < 0) - puts("Could not get board ID.\n"); - - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_id = 0, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_id = 1, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = AM335X_CPSW_MDIO_BASE, - .cpsw_base = AM335X_CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -int board_eth_init(bd_t *bis) -{ - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { - debug(" not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - if (is_valid_ether_addr(mac_addr)) - eth_setenv_enetaddr("ethaddr", mac_addr); - else - return -1; - } - - if (board_is_bone() || board_is_bone_lt()) { - writel(MII_MODE_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = - PHY_INTERFACE_MODE_MII; - } else { - writel(RGMII_MODE_ENABLE, &cdev->miisel); - cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = - PHY_INTERFACE_MODE_RGMII; - } - - return cpsw_register(&cpsw_data); -} -#endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 819ea650f0..9cf35e0257 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -19,24 +19,6 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -/* - * AM335x parts define a system EEPROM that defines certain sub-fields. - * We use these fields to in turn see what board we are on, and what - * that might require us to set or not set. - */ -#define HDR_NO_OF_MAC_ADDR 3 -#define HDR_ETH_ALEN 6 -#define HDR_NAME_LEN 8 - -struct am335x_baseboard_id { - unsigned int magic; - char name[HDR_NAME_LEN]; - char version[4]; - char serial[12]; - char config[32]; - char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; -}; - #define BOARD_REV_ID 0x0 u32 get_cpu_rev(void); @@ -51,13 +33,4 @@ u32 get_device_type(void); void setup_clocks_for_console(void); void ddr_pll_config(unsigned int ddrpll_M); -/* - * We have three pin mux functions that must exist. We must be able to enable - * uart0, for initial output and i2c0 to read the main EEPROM. We then have a - * main pinmux function that can be overridden to enable all other pinmux that - * is required on the board. - */ -void enable_uart0_pin_mux(void); -void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(struct am335x_baseboard_id *header); #endif diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index ca50eef613..67a87a1aaf 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -22,6 +22,7 @@ ifdef CONFIG_SPL_BUILD COBJS := mux.o endif +COBJS += board.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c new file mode 100644 index 0000000000..5279d1a4a3 --- /dev/null +++ b/board/ti/am335x/board.c @@ -0,0 +1,299 @@ +/* + * board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; +#ifdef CONFIG_SPL_BUILD +static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +#endif + +/* MII mode defines */ +#define MII_MODE_ENABLE 0x0 +#define RGMII_MODE_ENABLE 0xA + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static struct am335x_baseboard_id __attribute__((section (".data"))) header; + +static inline int board_is_bone(void) +{ + return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(void) +{ + return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(void) +{ + return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); +} + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, + sizeof(header))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + /* + * read the eeprom using i2c again, + * but use only a 1 byte address + */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, + (uchar *)&header, sizeof(header))) { + puts("Could not read the EEPROM; something " + "fundamentally wrong on the I2C bus.\n"); + return -EIO; + } + + if (header.magic != 0xEE3355AA) { + printf("Incorrect magic number (0x%x) in EEPROM\n", + header.magic); + return -EINVAL; + } + } + + return 0; +} + +/* UART Defines */ +#ifdef CONFIG_SPL_BUILD +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +static void rtc32k_enable(void) +{ + struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(0x83e70b13, &rtc->kick0r); + writel(0x95a4f1e0, &rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), &rtc->osc); +} +#endif + +/* + * Determine what type of DDR we have. + */ +static short inline board_memory_type(void) +{ + /* The following boards are known to use DDR3. */ + if (board_is_evm_sk() || board_is_bone_lt()) + return EMIF_REG_SDRAM_TYPE_DDR3; + + return EMIF_REG_SDRAM_TYPE_DDR2; +} + +/* + * early system init of muxing and clocks. + */ +void s_init(void) +{ + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + +#ifdef CONFIG_SPL_BUILD + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + + /* UART softreset */ + u32 regVal; + + enable_uart0_pin_mux(); + + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_RESET; + writel(regVal, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_SMART_IDLE_EN; + writel(regVal, &uart_base->uartsyscfg); + + gd = &gdata; + + preloader_console_init(); + + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + enable_board_pin_mux(&header); + if (board_is_evm_sk()) { + /* + * EVM SK 1.2A and later use gpio0_7 to enable DDR3. + * This is safe enough to do on older revs. + */ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + } + + config_ddr(board_memory_type()); +#endif +} + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = AM335X_CPSW_MDIO_BASE, + .cpsw_base = AM335X_CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + debug(" not set. Reading from E-fuse\n"); + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + else + return -1; + } + + if (board_is_bone() || board_is_bone_lt()) { + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_MII; + } else { + writel(RGMII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = + PHY_INTERFACE_MODE_RGMII; + } + + return cpsw_register(&cpsw_data); +} +#endif diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h new file mode 100644 index 0000000000..7985ab2c14 --- /dev/null +++ b/board/ti/am335x/board.h @@ -0,0 +1,49 @@ +/* + * board.h + * + * TI AM335x boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * TI AM335x parts define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am335x_baseboard_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(struct am335x_baseboard_id *header); +#endif diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 80becd5c7a..82bb9fd3ba 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -18,6 +18,7 @@ #include #include #include +#include "board.h" #define MUX_CFG(value, offset) \ __raw_writel(value, (CTRL_BASE + offset)); -- cgit v1.2.3 From 75a23880a5ae2afff3578b56d0948429a8ccc1fc Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Oct 2012 01:21:10 +0000 Subject: am33xx/board: use cpu_mmc_init() for default mmc initialization So platforms can override it with board_mmc_init() if needed. Signed-off-by: Peter Korsgaard --- arch/arm/cpu/armv7/am33xx/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 8280b35508..e4c123cd21 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -46,10 +46,10 @@ static const struct gpio_bank gpio_bank_am33xx[4] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) -int board_mmc_init(bd_t *bis) +int cpu_mmc_init(bd_t *bis) { int ret; - + ret = omap_mmc_init(0, 0, 0); if (ret) return ret; -- cgit v1.2.3 From 7f26a5a26f2c24a29a120702f2607e99ac8e1fef Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Oct 2012 01:21:11 +0000 Subject: am33xx: move generic parts of pinmux handling out from board/ti/am335x So they are available for other boards. Signed-off-by: Peter Korsgaard --- arch/arm/cpu/armv7/am33xx/Makefile | 1 + arch/arm/cpu/armv7/am33xx/mux.c | 33 +++++ arch/arm/include/asm/arch-am33xx/mux.h | 261 +++++++++++++++++++++++++++++++++ board/ti/am335x/mux.c | 249 +------------------------------ 4 files changed, 296 insertions(+), 248 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/mux.c create mode 100644 arch/arm/include/asm/arch-am33xx/mux.h diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 7768912603..74875b3255 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -21,6 +21,7 @@ COBJS += sys_info.o COBJS += ddr.o COBJS += emif4.o COBJS += board.o +COBJS += mux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c new file mode 100644 index 0000000000..2ded47228d --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/mux.c @@ -0,0 +1,33 @@ +/* + * mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* + * Configure the pin mux for the module + */ +void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux) +{ + int i; + + if (!mod_pin_mux) + return; + + for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) + MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); +} diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h new file mode 100644 index 0000000000..aed6b00cc6 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -0,0 +1,261 @@ +/* + * mux.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_H_ +#define _MUX_H_ + +#include +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +struct module_pin_mux { + short reg_offset; + unsigned char val; +}; + +/* Pad control register offset */ +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ + (PAD_CTRL_BASE))->x) + +/* + * Configure the pin mux for the module + */ +void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); + +#endif diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 82bb9fd3ba..29929791fc 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -16,244 +16,11 @@ #include #include #include +#include #include #include #include "board.h" -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 6) -#define RXACTIVE (0x1 << 5) -#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int gpmc_ad0; - int gpmc_ad1; - int gpmc_ad2; - int gpmc_ad3; - int gpmc_ad4; - int gpmc_ad5; - int gpmc_ad6; - int gpmc_ad7; - int gpmc_ad8; - int gpmc_ad9; - int gpmc_ad10; - int gpmc_ad11; - int gpmc_ad12; - int gpmc_ad13; - int gpmc_ad14; - int gpmc_ad15; - int gpmc_a0; - int gpmc_a1; - int gpmc_a2; - int gpmc_a3; - int gpmc_a4; - int gpmc_a5; - int gpmc_a6; - int gpmc_a7; - int gpmc_a8; - int gpmc_a9; - int gpmc_a10; - int gpmc_a11; - int gpmc_wait0; - int gpmc_wpn; - int gpmc_be1n; - int gpmc_csn0; - int gpmc_csn1; - int gpmc_csn2; - int gpmc_csn3; - int gpmc_clk; - int gpmc_advn_ale; - int gpmc_oen_ren; - int gpmc_wen; - int gpmc_be0n_cle; - int lcd_data0; - int lcd_data1; - int lcd_data2; - int lcd_data3; - int lcd_data4; - int lcd_data5; - int lcd_data6; - int lcd_data7; - int lcd_data8; - int lcd_data9; - int lcd_data10; - int lcd_data11; - int lcd_data12; - int lcd_data13; - int lcd_data14; - int lcd_data15; - int lcd_vsync; - int lcd_hsync; - int lcd_pclk; - int lcd_ac_bias_en; - int mmc0_dat3; - int mmc0_dat2; - int mmc0_dat1; - int mmc0_dat0; - int mmc0_clk; - int mmc0_cmd; - int mii1_col; - int mii1_crs; - int mii1_rxerr; - int mii1_txen; - int mii1_rxdv; - int mii1_txd3; - int mii1_txd2; - int mii1_txd1; - int mii1_txd0; - int mii1_txclk; - int mii1_rxclk; - int mii1_rxd3; - int mii1_rxd2; - int mii1_rxd1; - int mii1_rxd0; - int rmii1_refclk; - int mdio_data; - int mdio_clk; - int spi0_sclk; - int spi0_d0; - int spi0_d1; - int spi0_cs0; - int spi0_cs1; - int ecap0_in_pwm0_out; - int uart0_ctsn; - int uart0_rtsn; - int uart0_rxd; - int uart0_txd; - int uart1_ctsn; - int uart1_rtsn; - int uart1_rxd; - int uart1_txd; - int i2c0_sda; - int i2c0_scl; - int mcasp0_aclkx; - int mcasp0_fsx; - int mcasp0_axr0; - int mcasp0_ahclkr; - int mcasp0_aclkr; - int mcasp0_fsr; - int mcasp0_axr1; - int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; - int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; - int rsvd1; - int tms; - int tdi; - int tdo; - int tck; - int ntrst; - int emu0; - int emu1; - int osc1_in; - int osc1_out; - int pmic_power_en; - int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; - int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; - int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; - int ddr_a0; - int ddr_a1; - int ddr_a2; - int ddr_a3; - int ddr_a4; - int ddr_a5; - int ddr_a6; - int ddr_a7; - int ddr_a8; - int ddr_a9; - int ddr_a10; - int ddr_a11; - int ddr_a12; - int ddr_a13; - int ddr_a14; - int ddr_a15; - int ddr_odt; - int ddr_d0; - int ddr_d1; - int ddr_d2; - int ddr_d3; - int ddr_d4; - int ddr_d5; - int ddr_d6; - int ddr_d7; - int ddr_d8; - int ddr_d9; - int ddr_d10; - int ddr_d11; - int ddr_d12; - int ddr_d13; - int ddr_d14; - int ddr_d15; - int ddr_dqm0; - int ddr_dqm1; - int ddr_dqs0; - int ddr_dqsn0; - int ddr_dqs1; - int ddr_dqsn1; - int ddr_vref; - int ddr_vtp; - int ddr_strben0; - int ddr_strben1; - int ain7; - int ain6; - int ain5; - int ain4; - int ain3; - int ain2; - int ain1; - int ain0; - int vrefp; - int vrefn; -}; - -struct module_pin_mux { - short reg_offset; - unsigned char val; -}; - -/* Pad control register offset */ -#define PAD_CTRL_BASE 0x800 -#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ - (PAD_CTRL_BASE))->x) - static struct module_pin_mux uart0_pin_mux[] = { {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ @@ -363,20 +130,6 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; -/* - * Configure the pin mux for the module - */ -static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux) -{ - int i; - - if (!mod_pin_mux) - return; - - for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) - MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); -} - void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); -- cgit v1.2.3 From c00f69dbcd4a5e59d381274743b78e62485c5e4a Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Oct 2012 01:21:12 +0000 Subject: am33xx: support board specific ddr settings Move the hardcoded ddr2/ddr3 settings for the ti boards to board code, so other boards can use different types/timings. Signed-off-by: Peter Korsgaard [trini: Make apply with rtc32k_enable() in the file] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/emif4.c | 114 +++------------------------- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 5 +- board/ti/am335x/board.c | 89 +++++++++++++++++++--- 3 files changed, 92 insertions(+), 116 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index b2d7c0d956..01e3a5204e 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -47,78 +47,6 @@ void dram_init_banksize(void) static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; -static const struct ddr_data ddr2_data = { - .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) - |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), - .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) - |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), - .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) - |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), - .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) - |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), - .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) - |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) - |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), - .datauserank0delay = DDR2_PHY_RANK0_DELAY, - .datadldiff0 = PHY_DLL_LOCK_DIFF, -}; - -static const struct cmd_control ddr2_cmd_ctrl_data = { - .cmd0csratio = DDR2_RATIO, - .cmd0dldiff = DDR2_DLL_LOCK_DIFF, - .cmd0iclkout = DDR2_INVERT_CLKOUT, - - .cmd1csratio = DDR2_RATIO, - .cmd1dldiff = DDR2_DLL_LOCK_DIFF, - .cmd1iclkout = DDR2_INVERT_CLKOUT, - - .cmd2csratio = DDR2_RATIO, - .cmd2dldiff = DDR2_DLL_LOCK_DIFF, - .cmd2iclkout = DDR2_INVERT_CLKOUT, -}; - -static const struct emif_regs ddr2_emif_reg_data = { - .sdram_config = DDR2_EMIF_SDCFG, - .ref_ctrl = DDR2_EMIF_SDREF, - .sdram_tim1 = DDR2_EMIF_TIM1, - .sdram_tim2 = DDR2_EMIF_TIM2, - .sdram_tim3 = DDR2_EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = DDR3_RD_DQS, - .datawdsratio0 = DDR3_WR_DQS, - .datafwsratio0 = DDR3_PHY_FIFO_WE, - .datawrsratio0 = DDR3_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = DDR3_RATIO, - .cmd0dldiff = DDR3_DLL_LOCK_DIFF, - .cmd0iclkout = DDR3_INVERT_CLKOUT, - - .cmd1csratio = DDR3_RATIO, - .cmd1dldiff = DDR3_DLL_LOCK_DIFF, - .cmd1iclkout = DDR3_INVERT_CLKOUT, - - .cmd2csratio = DDR3_RATIO, - .cmd2dldiff = DDR3_DLL_LOCK_DIFF, - .cmd2iclkout = DDR3_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = DDR3_EMIF_SDCFG, - .ref_ctrl = DDR3_EMIF_SDREF, - .sdram_tim1 = DDR3_EMIF_TIM1, - .sdram_tim2 = DDR3_EMIF_TIM2, - .sdram_tim3 = DDR3_EMIF_TIM3, - .zq_config = DDR3_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, -}; - static void config_vtp(void) { writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE, @@ -134,46 +62,26 @@ static void config_vtp(void) ; } -void config_ddr(short ddr_type) +void config_ddr(unsigned int pll, unsigned int ioctrl, + const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs) { - int ddr_pll, ioctrl_val; - const struct emif_regs *emif_regs; - const struct ddr_data *ddr_data; - const struct cmd_control *cmd_ctrl_data; - - if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) { - ddr_pll = 266; - cmd_ctrl_data = &ddr2_cmd_ctrl_data; - ddr_data = &ddr2_data; - ioctrl_val = DDR2_IOCTRL_VALUE; - emif_regs = &ddr2_emif_reg_data; - } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) { - ddr_pll = 303; - cmd_ctrl_data = &ddr3_cmd_ctrl_data; - ddr_data = &ddr3_data; - ioctrl_val = DDR3_IOCTRL_VALUE; - emif_regs = &ddr3_emif_reg_data; - } else { - puts("Unknown memory type"); - hang(); - } - enable_emif_clocks(); - ddr_pll_config(ddr_pll); + ddr_pll_config(pll); config_vtp(); - config_cmd_ctrl(cmd_ctrl_data); + config_cmd_ctrl(ctrl); - config_ddr_data(0, ddr_data); - config_ddr_data(1, ddr_data); + config_ddr_data(0, data); + config_ddr_data(1, data); - config_io_ctrl(ioctrl_val); + config_io_ctrl(ioctrl); /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); /* Program EMIF instance */ - config_ddr_phy(emif_regs); - set_sdram_timings(emif_regs); - config_sdram(emif_regs); + config_ddr_phy(regs); + set_sdram_timings(regs); + config_sdram(regs); } #endif diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 6b22c45f77..40a13e9d8d 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -29,6 +29,7 @@ #define PHY_DLL_LOCK_DIFF 0x0 #define DDR_CKE_CTRL_NORMAL 0x1 +/* Micron MT47H128M16RT-25E */ #define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */ #define DDR2_EMIF_TIM1 0x0666B3C9 #define DDR2_EMIF_TIM2 0x243631CA @@ -189,6 +190,8 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -void config_ddr(short ddr_type); +void config_ddr(unsigned int pll, unsigned int ioctrl, + const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs); #endif /* _DDR_DEFS_H */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 5279d1a4a3..309a425a17 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -131,19 +131,79 @@ static void rtc32k_enable(void) /* Enable the RTC 32K OSC by setting bits 3 and 6. */ writel((1 << 3) | (1 << 6), &rtc->osc); } -#endif -/* - * Determine what type of DDR we have. - */ -static short inline board_memory_type(void) -{ - /* The following boards are known to use DDR3. */ - if (board_is_evm_sk() || board_is_bone_lt()) - return EMIF_REG_SDRAM_TYPE_DDR3; +static const struct ddr_data ddr2_data = { + .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) + |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), + .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) + |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), + .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) + |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), + .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) + |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), + .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) + |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), + .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) + |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), + .datauserank0delay = DDR2_PHY_RANK0_DELAY, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; - return EMIF_REG_SDRAM_TYPE_DDR2; -} +static const struct cmd_control ddr2_cmd_ctrl_data = { + .cmd0csratio = DDR2_RATIO, + .cmd0dldiff = DDR2_DLL_LOCK_DIFF, + .cmd0iclkout = DDR2_INVERT_CLKOUT, + + .cmd1csratio = DDR2_RATIO, + .cmd1dldiff = DDR2_DLL_LOCK_DIFF, + .cmd1iclkout = DDR2_INVERT_CLKOUT, + + .cmd2csratio = DDR2_RATIO, + .cmd2dldiff = DDR2_DLL_LOCK_DIFF, + .cmd2iclkout = DDR2_INVERT_CLKOUT, +}; + +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = DDR2_EMIF_SDCFG, + .ref_ctrl = DDR2_EMIF_SDREF, + .sdram_tim1 = DDR2_EMIF_TIM1, + .sdram_tim2 = DDR2_EMIF_TIM2, + .sdram_tim3 = DDR2_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, +}; + +static const struct ddr_data ddr3_data = { + .datardsratio0 = DDR3_RD_DQS, + .datawdsratio0 = DDR3_WR_DQS, + .datafwsratio0 = DDR3_PHY_FIFO_WE, + .datawrsratio0 = DDR3_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = DDR3_RATIO, + .cmd0dldiff = DDR3_DLL_LOCK_DIFF, + .cmd0iclkout = DDR3_INVERT_CLKOUT, + + .cmd1csratio = DDR3_RATIO, + .cmd1dldiff = DDR3_DLL_LOCK_DIFF, + .cmd1iclkout = DDR3_INVERT_CLKOUT, + + .cmd2csratio = DDR3_RATIO, + .cmd2dldiff = DDR3_DLL_LOCK_DIFF, + .cmd2iclkout = DDR3_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = DDR3_EMIF_SDCFG, + .ref_ctrl = DDR3_EMIF_SDREF, + .sdram_tim1 = DDR3_EMIF_TIM1, + .sdram_tim2 = DDR3_EMIF_TIM2, + .sdram_tim3 = DDR3_EMIF_TIM3, + .zq_config = DDR3_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, +}; +#endif /* * early system init of muxing and clocks. @@ -204,7 +264,12 @@ void s_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } - config_ddr(board_memory_type()); + if (board_is_evm_sk() || board_is_bone_lt()) + config_ddr(303, DDR3_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); + else + config_ddr(266, DDR2_IOCTRL_VALUE, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); #endif } -- cgit v1.2.3 From c7d35bef255dedb3ec3856982f042dde514676b0 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Thu, 18 Oct 2012 01:21:13 +0000 Subject: am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers So other parts can be added. Signed-off-by: Peter Korsgaard --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 64 ++++++++-------- board/ti/am335x/board.c | 112 +++++++++++++++------------- 2 files changed, 94 insertions(+), 82 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 40a13e9d8d..8e69fb67b1 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -30,40 +30,40 @@ #define DDR_CKE_CTRL_NORMAL 0x1 /* Micron MT47H128M16RT-25E */ -#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */ -#define DDR2_EMIF_TIM1 0x0666B3C9 -#define DDR2_EMIF_TIM2 0x243631CA -#define DDR2_EMIF_TIM3 0x0000033F -#define DDR2_EMIF_SDCFG 0x41805332 -#define DDR2_EMIF_SDREF 0x0000081a -#define DDR2_DLL_LOCK_DIFF 0x0 -#define DDR2_RATIO 0x80 -#define DDR2_INVERT_CLKOUT 0x00 -#define DDR2_RD_DQS 0x12 -#define DDR2_WR_DQS 0x00 -#define DDR2_PHY_WRLVL 0x00 -#define DDR2_PHY_GATELVL 0x00 -#define DDR2_PHY_WR_DATA 0x40 -#define DDR2_PHY_FIFO_WE 0x80 -#define DDR2_PHY_RANK0_DELAY 0x1 -#define DDR2_IOCTRL_VALUE 0x18B +#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 +#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 +#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA +#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F +#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 +#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a +#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 +#define MT47H128M16RT25E_RATIO 0x80 +#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 +#define MT47H128M16RT25E_RD_DQS 0x12 +#define MT47H128M16RT25E_WR_DQS 0x00 +#define MT47H128M16RT25E_PHY_WRLVL 0x00 +#define MT47H128M16RT25E_PHY_GATELVL 0x00 +#define MT47H128M16RT25E_PHY_WR_DATA 0x40 +#define MT47H128M16RT25E_PHY_FIFO_WE 0x80 +#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 +#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B /* Micron MT41J128M16JT-125 */ -#define DDR3_EMIF_READ_LATENCY 0x06 -#define DDR3_EMIF_TIM1 0x0888A39B -#define DDR3_EMIF_TIM2 0x26337FDA -#define DDR3_EMIF_TIM3 0x501F830F -#define DDR3_EMIF_SDCFG 0x61C04AB2 -#define DDR3_EMIF_SDREF 0x0000093B -#define DDR3_ZQ_CFG 0x50074BE4 -#define DDR3_DLL_LOCK_DIFF 0x1 -#define DDR3_RATIO 0x40 -#define DDR3_INVERT_CLKOUT 0x1 -#define DDR3_RD_DQS 0x3B -#define DDR3_WR_DQS 0x85 -#define DDR3_PHY_WR_DATA 0xC1 -#define DDR3_PHY_FIFO_WE 0x100 -#define DDR3_IOCTRL_VALUE 0x18B +#define MT41J128MJT125_EMIF_READ_LATENCY 0x06 +#define MT41J128MJT125_EMIF_TIM1 0x0888A39B +#define MT41J128MJT125_EMIF_TIM2 0x26337FDA +#define MT41J128MJT125_EMIF_TIM3 0x501F830F +#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 +#define MT41J128MJT125_EMIF_SDREF 0x0000093B +#define MT41J128MJT125_ZQ_CFG 0x50074BE4 +#define MT41J128MJT125_DLL_LOCK_DIFF 0x1 +#define MT41J128MJT125_RATIO 0x40 +#define MT41J128MJT125_INVERT_CLKOUT 0x1 +#define MT41J128MJT125_RD_DQS 0x3B +#define MT41J128MJT125_WR_DQS 0x85 +#define MT41J128MJT125_PHY_WR_DATA 0xC1 +#define MT41J128MJT125_PHY_FIFO_WE 0x100 +#define MT41J128MJT125_IOCTRL_VALUE 0x18B /** * Configure SDRAM diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 309a425a17..5d279ecdbc 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -133,75 +133,87 @@ static void rtc32k_enable(void) } static const struct ddr_data ddr2_data = { - .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) - |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), - .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) - |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), - .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) - |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), - .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) - |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), - .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) - |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) - |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), - .datauserank0delay = DDR2_PHY_RANK0_DELAY, + .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | + (MT47H128M16RT25E_RD_DQS<<20) | + (MT47H128M16RT25E_RD_DQS<<10) | + (MT47H128M16RT25E_RD_DQS<<0)), + .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | + (MT47H128M16RT25E_WR_DQS<<20) | + (MT47H128M16RT25E_WR_DQS<<10) | + (MT47H128M16RT25E_WR_DQS<<0)), + .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | + (MT47H128M16RT25E_PHY_WRLVL<<20) | + (MT47H128M16RT25E_PHY_WRLVL<<10) | + (MT47H128M16RT25E_PHY_WRLVL<<0)), + .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | + (MT47H128M16RT25E_PHY_GATELVL<<20) | + (MT47H128M16RT25E_PHY_GATELVL<<10) | + (MT47H128M16RT25E_PHY_GATELVL<<0)), + .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | + (MT47H128M16RT25E_PHY_FIFO_WE<<20) | + (MT47H128M16RT25E_PHY_FIFO_WE<<10) | + (MT47H128M16RT25E_PHY_FIFO_WE<<0)), + .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | + (MT47H128M16RT25E_PHY_WR_DATA<<20) | + (MT47H128M16RT25E_PHY_WR_DATA<<10) | + (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr2_cmd_ctrl_data = { - .cmd0csratio = DDR2_RATIO, - .cmd0dldiff = DDR2_DLL_LOCK_DIFF, - .cmd0iclkout = DDR2_INVERT_CLKOUT, + .cmd0csratio = MT47H128M16RT25E_RATIO, + .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, + .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, - .cmd1csratio = DDR2_RATIO, - .cmd1dldiff = DDR2_DLL_LOCK_DIFF, - .cmd1iclkout = DDR2_INVERT_CLKOUT, + .cmd1csratio = MT47H128M16RT25E_RATIO, + .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, + .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, - .cmd2csratio = DDR2_RATIO, - .cmd2dldiff = DDR2_DLL_LOCK_DIFF, - .cmd2iclkout = DDR2_INVERT_CLKOUT, + .cmd2csratio = MT47H128M16RT25E_RATIO, + .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, + .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = { - .sdram_config = DDR2_EMIF_SDCFG, - .ref_ctrl = DDR2_EMIF_SDREF, - .sdram_tim1 = DDR2_EMIF_TIM1, - .sdram_tim2 = DDR2_EMIF_TIM2, - .sdram_tim3 = DDR2_EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, + .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, + .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, + .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, + .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, + .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, }; static const struct ddr_data ddr3_data = { - .datardsratio0 = DDR3_RD_DQS, - .datawdsratio0 = DDR3_WR_DQS, - .datafwsratio0 = DDR3_PHY_FIFO_WE, - .datawrsratio0 = DDR3_PHY_WR_DATA, + .datardsratio0 = MT41J128MJT125_RD_DQS, + .datawdsratio0 = MT41J128MJT125_WR_DQS, + .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, + .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = DDR3_RATIO, - .cmd0dldiff = DDR3_DLL_LOCK_DIFF, - .cmd0iclkout = DDR3_INVERT_CLKOUT, + .cmd0csratio = MT41J128MJT125_RATIO, + .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, - .cmd1csratio = DDR3_RATIO, - .cmd1dldiff = DDR3_DLL_LOCK_DIFF, - .cmd1iclkout = DDR3_INVERT_CLKOUT, + .cmd1csratio = MT41J128MJT125_RATIO, + .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, - .cmd2csratio = DDR3_RATIO, - .cmd2dldiff = DDR3_DLL_LOCK_DIFF, - .cmd2iclkout = DDR3_INVERT_CLKOUT, + .cmd2csratio = MT41J128MJT125_RATIO, + .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, + .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = DDR3_EMIF_SDCFG, - .ref_ctrl = DDR3_EMIF_SDREF, - .sdram_tim1 = DDR3_EMIF_TIM1, - .sdram_tim2 = DDR3_EMIF_TIM2, - .sdram_tim3 = DDR3_EMIF_TIM3, - .zq_config = DDR3_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, + .sdram_config = MT41J128MJT125_EMIF_SDCFG, + .ref_ctrl = MT41J128MJT125_EMIF_SDREF, + .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, + .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, + .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, + .zq_config = MT41J128MJT125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, }; #endif @@ -265,10 +277,10 @@ void s_init(void) } if (board_is_evm_sk() || board_is_bone_lt()) - config_ddr(303, DDR3_IOCTRL_VALUE, &ddr3_data, + config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); else - config_ddr(266, DDR2_IOCTRL_VALUE, &ddr2_data, + config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); #endif } -- cgit v1.2.3 From 62f730fffdd2b6e354773fdcb4b4c01262153319 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 16 Oct 2012 14:28:43 +0000 Subject: drivers/i2c/fsl_i2c.c: sparse fix fsl_i2c.c:217:14: warning: symbol 'get_i2c_clock' was not declared. Should it be static? Signed-off-by: Kim Phillips Acked-by: Heiko Schocher --- drivers/i2c/fsl_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 5b017a910c..3cb232fdd1 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -214,7 +214,7 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, return speed; } -unsigned int get_i2c_clock(int bus) +static unsigned int get_i2c_clock(int bus) { if (bus) return gd->i2c2_clk; /* I2C2 clock */ -- cgit v1.2.3 From d07e7f9b3d62a17f60f40638e942406b03d977c3 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 16 Oct 2012 14:28:48 +0000 Subject: drivers/serial/serial_ns16550.c: sparse fixes serial_ns16550.c:222:1: warning: symbol 'eserial1_init' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_setbrg' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_getc' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_tstc' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_putc' was not declared. Should it be static? serial_ns16550.c:222:1: warning: symbol 'eserial1_puts' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_init' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_setbrg' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_getc' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_tstc' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_putc' was not declared. Should it be static? serial_ns16550.c:225:1: warning: symbol 'eserial2_puts' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_init' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_setbrg' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_getc' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_tstc' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_putc' was not declared. Should it be static? serial_ns16550.c:228:1: warning: symbol 'eserial3_puts' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_init' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_setbrg' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_getc' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_tstc' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_putc' was not declared. Should it be static? serial_ns16550.c:231:1: warning: symbol 'eserial4_puts' was not declared. Should it be static? Signed-off-by: Kim Phillips --- drivers/serial/serial_ns16550.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index b5d12481ca..4176e257e0 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -78,20 +78,20 @@ static NS16550_t serial_ports[4] = { /* Multi serial device functions */ #define DECLARE_ESERIAL_FUNCTIONS(port) \ - int eserial##port##_init (void) {\ + static int eserial##port##_init (void) {\ int clock_divisor; \ clock_divisor = calc_divisor(serial_ports[port-1]); \ NS16550_init(serial_ports[port-1], clock_divisor); \ return(0);}\ - void eserial##port##_setbrg (void) {\ + static void eserial##port##_setbrg (void) {\ serial_setbrg_dev(port);}\ - int eserial##port##_getc (void) {\ + static int eserial##port##_getc (void) {\ return serial_getc_dev(port);}\ - int eserial##port##_tstc (void) {\ + static int eserial##port##_tstc (void) {\ return serial_tstc_dev(port);}\ - void eserial##port##_putc (const char c) {\ + static void eserial##port##_putc (const char c) {\ serial_putc_dev(port, c);}\ - void eserial##port##_puts (const char *s) {\ + static void eserial##port##_puts (const char *s) {\ serial_puts_dev(port, s);} /* Serial device descriptor */ -- cgit v1.2.3 From 461f86e69650ae3c449ecb3ead607ee35277d385 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 17 Oct 2012 06:44:57 +0000 Subject: FAT: remove cur_part_nr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A future patch will implement the more standard filesystem API fat_set_blk_dev(). This API has no way to know which partition number the partition represents. Equally, future DM rework will make the concept of partition number harder to pass around. So, simply remove cur_part_nr from fat.c; its only use is in a diagnostic printf, and the context where it's printed should make it obvious which partition is referred to anyway (since the partition ID would come from the user command-line that caused it). Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- fs/fat/fat.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 4a60a2503e..731d3690c3 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -46,7 +46,6 @@ static void downcase(char *str) } static block_dev_desc_t *cur_dev; -static unsigned int cur_part_nr; static disk_partition_t cur_part_info; #define DOS_BOOT_MAGIC_OFFSET 0x1fe @@ -77,10 +76,8 @@ int fat_register_device(block_dev_desc_t * dev_desc, int part_no) defined(CONFIG_SYSTEMACE) ) /* Read the partition table, if present */ - if (!get_partition_info(dev_desc, part_no, &cur_part_info)) { + if (!get_partition_info(dev_desc, part_no, &cur_part_info)) cur_dev = dev_desc; - cur_part_nr = part_no; - } #endif /* Otherwise it might be a superfloppy (whole-disk FAT filesystem) */ @@ -92,7 +89,6 @@ int fat_register_device(block_dev_desc_t * dev_desc, int part_no) } cur_dev = dev_desc; - cur_part_nr = 1; cur_part_info.start = 0; cur_part_info.size = dev_desc->lba; cur_part_info.blksz = dev_desc->blksz; @@ -1239,8 +1235,7 @@ int file_fat_detectfs(void) vol_label[11] = '\0'; volinfo.fs_type[5] = '\0'; - printf("Partition %d: Filesystem: %s \"%s\"\n", cur_part_nr, - volinfo.fs_type, vol_label); + printf("Filesystem: %s \"%s\"\n", volinfo.fs_type, vol_label); return 0; } -- cgit v1.2.3 From a1687b858e5670683199f6923b32aec0ea82ba19 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 17 Oct 2012 06:44:58 +0000 Subject: FAT: initialize all fields in cur_part_info, simplify init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cur_part_info.{name,type} are strings. So, we don't need to memset() the entire thing, just put the NULL-termination in the first byte. Add missing initialization of the bootable and uuid fields. None of these fields are actually used by fat.c. However, since it stores the entire disk_partition_t, we should make sure that all fields are valid. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- fs/fat/fat.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 731d3690c3..31042e5357 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -92,8 +92,12 @@ int fat_register_device(block_dev_desc_t * dev_desc, int part_no) cur_part_info.start = 0; cur_part_info.size = dev_desc->lba; cur_part_info.blksz = dev_desc->blksz; - memset(cur_part_info.name, 0, sizeof(cur_part_info.name)); - memset(cur_part_info.type, 0, sizeof(cur_part_info.type)); + cur_part_info.name[0] = 0; + cur_part_info.type[0] = 0; + cur_part_info.bootable = 0; +#ifdef CONFIG_PARTITION_UUIDS + cur_part_info.uuid[0] = 0; +#endif } /* Make sure it has a valid FAT header */ -- cgit v1.2.3 From 5e8f98319d8582d6a066610b5f1ec9b1a3f79704 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 17 Oct 2012 06:44:59 +0000 Subject: FAT: implement fat_set_blk_dev(), convert cmd_fat.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the FAT filesystem API more consistent with other block-based filesystems. If in the future standard multi-filesystem commands such as "ls" or "load" are implemented, having FAT work the same way as other filesystems will be necessary. Convert cmd_fat.c to the new API, so the code looks more like other files implementing the same commands for other filesystems. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- common/cmd_fat.c | 8 +++---- fs/fat/fat.c | 66 ++++++++++++++++++++++++++------------------------------ include/fat.h | 1 + 3 files changed, 36 insertions(+), 39 deletions(-) diff --git a/common/cmd_fat.c b/common/cmd_fat.c index 5a5698b056..c38302d447 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -55,7 +55,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; dev = dev_desc->dev; - if (fat_register_device(dev_desc,part)!=0) { + if (fat_set_blk_dev(dev_desc, &info) != 0) { printf("\n** Unable to use %s %d:%d for fatload **\n", argv[1], dev, part); return 1; @@ -111,7 +111,7 @@ int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; dev = dev_desc->dev; - if (fat_register_device(dev_desc,part)!=0) { + if (fat_set_blk_dev(dev_desc, &info) != 0) { printf("\n** Unable to use %s %d:%d for fatls **\n", argv[1], dev, part); return 1; @@ -149,7 +149,7 @@ int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; dev = dev_desc->dev; - if (fat_register_device(dev_desc,part)!=0) { + if (fat_set_blk_dev(dev_desc, &info) != 0) { printf("\n** Unable to use %s %d:%d for fatinfo **\n", argv[1], dev, part); return 1; @@ -185,7 +185,7 @@ static int do_fat_fswrite(cmd_tbl_t *cmdtp, int flag, dev = dev_desc->dev; - if (fat_register_device(dev_desc, part) != 0) { + if (fat_set_blk_dev(dev_desc, &info) != 0) { printf("\n** Unable to use %s %d:%d for fatwrite **\n", argv[1], dev, part); return 1; diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 31042e5357..393c3781eb 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -61,44 +61,12 @@ static int disk_read(__u32 block, __u32 nr_blocks, void *buf) cur_part_info.start + block, nr_blocks, buf); } -int fat_register_device(block_dev_desc_t * dev_desc, int part_no) +int fat_set_blk_dev(block_dev_desc_t *dev_desc, disk_partition_t *info) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); - /* First close any currently found FAT filesystem */ - cur_dev = NULL; - -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) ) - - /* Read the partition table, if present */ - if (!get_partition_info(dev_desc, part_no, &cur_part_info)) - cur_dev = dev_desc; -#endif - - /* Otherwise it might be a superfloppy (whole-disk FAT filesystem) */ - if (!cur_dev) { - if (part_no != 0) { - printf("** Partition %d not valid on device %d **\n", - part_no, dev_desc->dev); - return -1; - } - - cur_dev = dev_desc; - cur_part_info.start = 0; - cur_part_info.size = dev_desc->lba; - cur_part_info.blksz = dev_desc->blksz; - cur_part_info.name[0] = 0; - cur_part_info.type[0] = 0; - cur_part_info.bootable = 0; -#ifdef CONFIG_PARTITION_UUIDS - cur_part_info.uuid[0] = 0; -#endif - } + cur_dev = dev_desc; + cur_part_info = *info; /* Make sure it has a valid FAT header */ if (disk_read(0, 1, buffer) != 1) { @@ -122,6 +90,34 @@ int fat_register_device(block_dev_desc_t * dev_desc, int part_no) return -1; } +int fat_register_device(block_dev_desc_t *dev_desc, int part_no) +{ + disk_partition_t info; + + /* First close any currently found FAT filesystem */ + cur_dev = NULL; + + /* Read the partition table, if present */ + if (get_partition_info(dev_desc, part_no, &info)) { + if (part_no != 0) { + printf("** Partition %d not valid on device %d **\n", + part_no, dev_desc->dev); + return -1; + } + + info.start = 0; + info.size = dev_desc->lba; + info.blksz = dev_desc->blksz; + info.name[0] = 0; + info.type[0] = 0; + info.bootable = 0; +#ifdef CONFIG_PARTITION_UUIDS + info.uuid[0] = 0; +#endif + } + + return fat_set_blk_dev(dev_desc, &info); +} /* * Get the first occurence of a directory delimiter ('/' or '\') in a string. diff --git a/include/fat.h b/include/fat.h index cc85b06395..706cd7a4bd 100644 --- a/include/fat.h +++ b/include/fat.h @@ -212,6 +212,7 @@ long file_fat_read_at(const char *filename, unsigned long pos, void *buffer, unsigned long maxsize); long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); const char *file_getfsname(int idx); +int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); int fat_register_device(block_dev_desc_t *dev_desc, int part_no); int file_fat_write(const char *filename, void *buffer, unsigned long maxsize); -- cgit v1.2.3 From 25164218b7c2abc3316c2a3ba7247487b4c81541 Mon Sep 17 00:00:00 2001 From: Andrew Bradford Date: Thu, 25 Oct 2012 08:21:29 -0400 Subject: am33xx: Enable UART{1,2,3,4,5} clocks If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or the am335x_evm daughterboard, enable the required clocks for the UART in use. Signed-off-by: Andrew Bradford --- arch/arm/cpu/armv7/am33xx/clock.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index f870859414..bc2abb657c 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -115,6 +115,41 @@ static void enable_per_clocks(void) while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN) ; + /* UART1 */ +#ifdef CONFIG_SERIAL2 + writel(PRCM_MOD_EN, &cmper->uart1clkctrl); + while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN) + ; +#endif /* CONFIG_SERIAL2 */ + + /* UART2 */ +#ifdef CONFIG_SERIAL3 + writel(PRCM_MOD_EN, &cmper->uart2clkctrl); + while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN) + ; +#endif /* CONFIG_SERIAL3 */ + + /* UART3 */ +#ifdef CONFIG_SERIAL4 + writel(PRCM_MOD_EN, &cmper->uart3clkctrl); + while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN) + ; +#endif /* CONFIG_SERIAL4 */ + + /* UART4 */ +#ifdef CONFIG_SERIAL5 + writel(PRCM_MOD_EN, &cmper->uart4clkctrl); + while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN) + ; +#endif /* CONFIG_SERIAL5 */ + + /* UART5 */ +#ifdef CONFIG_SERIAL6 + writel(PRCM_MOD_EN, &cmper->uart5clkctrl); + while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN) + ; +#endif /* CONFIG_SERIAL6 */ + /* MMC0*/ writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) -- cgit v1.2.3 From 6422b70bd511483231955431e6cb66546266acdc Mon Sep 17 00:00:00 2001 From: Andrew Bradford Date: Thu, 25 Oct 2012 08:21:30 -0400 Subject: am33xx: Enable UART{1,2,3,4,5} pin-mux If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or on the am335x_evm daughterboard, enable the proper pin-muxing. Signed-off-by: Andrew Bradford --- board/ti/am335x/board.c | 17 ++++++++++++++++ board/ti/am335x/board.h | 5 +++++ board/ti/am335x/mux.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 5d279ecdbc..013ad881f0 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -242,7 +242,24 @@ void s_init(void) /* UART softreset */ u32 regVal; +#ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); +#endif /* CONFIG_SERIAL1 */ +#ifdef CONFIG_SERIAL2 + enable_uart1_pin_mux(); +#endif /* CONFIG_SERIAL2 */ +#ifdef CONFIG_SERIAL3 + enable_uart2_pin_mux(); +#endif /* CONFIG_SERIAL3 */ +#ifdef CONFIG_SERIAL4 + enable_uart3_pin_mux(); +#endif /* CONFIG_SERIAL4 */ +#ifdef CONFIG_SERIAL5 + enable_uart4_pin_mux(); +#endif /* CONFIG_SERIAL5 */ +#ifdef CONFIG_SERIAL6 + enable_uart5_pin_mux(); +#endif /* CONFIG_SERIAL6 */ regVal = readl(&uart_base->uartsyscfg); regVal |= UART_RESET; diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 7985ab2c14..48e112e230 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -44,6 +44,11 @@ struct am335x_baseboard_id { * is required on the board. */ void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); void enable_i2c0_pin_mux(void); void enable_board_pin_mux(struct am335x_baseboard_id *header); #endif diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 29929791fc..6a5f23a551 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -27,6 +27,36 @@ static struct module_pin_mux uart0_pin_mux[] = { {-1}, }; +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ @@ -135,6 +165,30 @@ void enable_uart0_pin_mux(void) configure_module_pin_mux(uart0_pin_mux); } +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} void enable_i2c0_pin_mux(void) { -- cgit v1.2.3 From 96708a06052e49489b46fb91bf83f3f7d20430b8 Mon Sep 17 00:00:00 2001 From: Andrew Bradford Date: Thu, 25 Oct 2012 08:21:31 -0400 Subject: serial: ns16550: Enable COM5 and COM6 Increase the possible number of ns16550 serial devices from 4 to 6. Signed-off-by: Andrew Bradford --- drivers/serial/serial_ns16550.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index b5d12481ca..5fb38410a8 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; #if !defined(CONFIG_CONS_INDEX) -#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4) +#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6) #error "Invalid console index value." #endif @@ -46,12 +46,16 @@ DECLARE_GLOBAL_DATA_PTR; #error "Console port 3 defined but not configured." #elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." +#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#error "Console port 5 defined but not configured." +#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#error "Console port 6 defined but not configured." #endif /* Note: The port number specified in the functions is 1 based. * the array is 0 based. */ -static NS16550_t serial_ports[4] = { +static NS16550_t serial_ports[6] = { #ifdef CONFIG_SYS_NS16550_COM1 (NS16550_t)CONFIG_SYS_NS16550_COM1, #else @@ -68,7 +72,17 @@ static NS16550_t serial_ports[4] = { NULL, #endif #ifdef CONFIG_SYS_NS16550_COM4 - (NS16550_t)CONFIG_SYS_NS16550_COM4 + (NS16550_t)CONFIG_SYS_NS16550_COM4, +#else + NULL, +#endif +#ifdef CONFIG_SYS_NS16550_COM5 + (NS16550_t)CONFIG_SYS_NS16550_COM5, +#else + NULL, +#endif +#ifdef CONFIG_SYS_NS16550_COM6 + (NS16550_t)CONFIG_SYS_NS16550_COM6 #else NULL #endif @@ -231,6 +245,12 @@ struct serial_device eserial3_device = DECLARE_ESERIAL_FUNCTIONS(4); struct serial_device eserial4_device = INIT_ESERIAL_STRUCTURE(4, "eserial3"); +DECLARE_ESERIAL_FUNCTIONS(5); +struct serial_device eserial5_device = + INIT_ESERIAL_STRUCTURE(5, "eserial4"); +DECLARE_ESERIAL_FUNCTIONS(6); +struct serial_device eserial6_device = + INIT_ESERIAL_STRUCTURE(6, "eserial5"); __weak struct serial_device *default_serial_console(void) { @@ -242,6 +262,10 @@ __weak struct serial_device *default_serial_console(void) return &eserial3_device; #elif CONFIG_CONS_INDEX == 4 return &eserial4_device; +#elif CONFIG_CONS_INDEX == 5 + return &eserial5_device; +#elif CONFIG_CONS_INDEX == 6 + return &eserial6_device; #else #error "Bad CONFIG_CONS_INDEX." #endif @@ -261,4 +285,10 @@ void ns16550_serial_initialize(void) #if defined(CONFIG_SYS_NS16550_COM4) serial_register(&eserial4_device); #endif +#if defined(CONFIG_SYS_NS16550_COM5) + serial_register(&eserial5_device); +#endif +#if defined(CONFIG_SYS_NS16550_COM6) + serial_register(&eserial6_device); +#endif } -- cgit v1.2.3 From c3f8318f33eb4eb79b3b5c5204a438d499572de0 Mon Sep 17 00:00:00 2001 From: Andrew Bradford Date: Thu, 25 Oct 2012 08:21:32 -0400 Subject: am335x_evm: Enable use of UART{1,2,3,4,5} Add targets of am335x_evm_uart{1,2,3,4,5} to have serial input/output on UART{1,2,3,4,5} for use with the Beaglebone RS232 cape, am335x_evm daughterboard, and other custom configurations. Modify target for am335x_evm to include SERIAL1 and CONS_INDEX=1 options in order to clarify UART selection requirements. Signed-off-by: Andrew Bradford --- boards.cfg | 7 ++++++- include/configs/am335x_evm.h | 12 +++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/boards.cfg b/boards.cfg index d467f566c0..a1bae069c2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -225,7 +225,12 @@ versatileqemu arm arm926ejs versatile armltd integratorap_cm946es arm arm946es integrator armltd - integratorap:CM946ES integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES ca9x4_ct_vxp arm armv7 vexpress armltd -am335x_evm arm armv7 am335x ti am33xx +am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1 +am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2 +am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3 +am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4 +am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 +am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 highbank arm armv7 highbank - highbank mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 58d62d0c7d..cdb6697890 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -158,9 +158,15 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SERIAL_MULTI #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* I2C Configuration */ #define CONFIG_I2C @@ -182,11 +188,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 -#define CONFIG_CONS_INDEX 1 +#define CONFIG_ENV_OVERWRITE 1 #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_ENV_IS_NOWHERE -- cgit v1.2.3 From 8440f18a4818d52ba51bb9f0b07ce6439f1b6a57 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Thu, 25 Oct 2012 13:30:14 +0000 Subject: serial: remove calls to serial_assign() Remove calls to serial_assign() that are failing now that it returns a proper error code. This calls were not actually doing anything because they passed the name of a stdio_dev when a serial_device name is exptectd. Signed-off-by: Allen Martin Acked-by: Joe Hershberger Acked-by: Marek Vasut Acked-by: Simon Glass Tested-by: Simon Glass Tested-by: Stephen Warren --- common/cmd_nvedit.c | 3 --- common/iomux.c | 10 ---------- 2 files changed, 13 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 1f9c674260..68c38f4e5c 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -238,9 +238,6 @@ int env_check_apply(const char *name, const char *oldval, /* Try assigning specified device */ if (console_assign(console, newval) < 0) return 1; - - if (serial_assign(newval) < 0) - return 1; #endif /* CONFIG_CONSOLE_MUX */ } diff --git a/common/iomux.c b/common/iomux.c index dbc231250c..6a757041f6 100644 --- a/common/iomux.c +++ b/common/iomux.c @@ -135,16 +135,6 @@ int iomux_doenv(const int console, const char *arg) */ if (console_assign(console, start[j]) < 0) continue; - /* - * This was taken from common/cmd_nvedit.c. - * This will never work because serial_assign() returns - * 1 upon error, not -1. - * This would almost always return an error anyway because - * serial_assign() expects the name of a serial device, like - * serial_smc, but the user generally only wants to set serial. - */ - if (serial_assign(start[j]) < 0) - continue; cons_set[cs_idx++] = dev; } free(console_args); -- cgit v1.2.3 From 6f62f4207112013852be87dc2b9c7c570eba11c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:08 +0000 Subject: arm: Remove support for lpc2292 This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut --- arch/arm/cpu/arm720t/cpu.c | 2 +- arch/arm/cpu/arm720t/interrupts.c | 28 +-- arch/arm/cpu/arm720t/lpc2292/Makefile | 50 ----- arch/arm/cpu/arm720t/lpc2292/flash.c | 249 --------------------- arch/arm/cpu/arm720t/lpc2292/iap_entry.S | 7 - arch/arm/cpu/arm720t/lpc2292/mmc.c | 131 ----------- arch/arm/cpu/arm720t/lpc2292/mmc_hw.c | 233 ------------------- arch/arm/cpu/arm720t/lpc2292/mmc_hw.h | 29 --- arch/arm/cpu/arm720t/lpc2292/spi.c | 40 ---- arch/arm/cpu/arm720t/start.S | 69 +----- arch/arm/include/asm/arch-lpc2292/hardware.h | 33 --- .../include/asm/arch-lpc2292/lpc2292_registers.h | 225 ------------------- arch/arm/include/asm/arch-lpc2292/spi.h | 82 ------- doc/driver-model/UDM-serial.txt | 30 ++- drivers/i2c/soft_i2c.c | 3 - drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_lpc2292.c | 117 ---------- include/flash.h | 1 - 19 files changed, 16 insertions(+), 1316 deletions(-) delete mode 100644 arch/arm/cpu/arm720t/lpc2292/Makefile delete mode 100644 arch/arm/cpu/arm720t/lpc2292/flash.c delete mode 100644 arch/arm/cpu/arm720t/lpc2292/iap_entry.S delete mode 100644 arch/arm/cpu/arm720t/lpc2292/mmc.c delete mode 100644 arch/arm/cpu/arm720t/lpc2292/mmc_hw.c delete mode 100644 arch/arm/cpu/arm720t/lpc2292/mmc_hw.h delete mode 100644 arch/arm/cpu/arm720t/lpc2292/spi.c delete mode 100644 arch/arm/include/asm/arch-lpc2292/hardware.h delete mode 100644 arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h delete mode 100644 arch/arm/include/asm/arch-lpc2292/spi.h delete mode 100644 drivers/serial/serial_lpc2292.c diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index ce7b3c9c24..e25f6f2ea7 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -46,7 +46,7 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */ -#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index c2f898f2cc..5b21cc3cea 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -37,11 +37,6 @@ /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff) -#ifdef CONFIG_LPC2292 -#undef READ_TIMER -#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) -#endif - #else #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) @@ -73,13 +68,6 @@ void do_irq (struct pt_regs *pt_regs) } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No do_irq() for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - - void (*pfnct)(void); - - pfnct = (void (*)(void))VICVectAddr; - - (*pfnct)(); #else #error do_irq() not defined for this CPU type #endif @@ -172,14 +160,6 @@ int timer_init (void) /* Start timer */ SET_REG( REG_TMOD, TM0_RUN); -#elif defined(CONFIG_LPC2292) - PUT32(T0IR, 0); /* disable all timer0 interrupts */ - PUT32(T0TCR, 0); /* disable timer0 */ - PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ); - PUT32(T0MCR, 0); - PUT32(T0TC, 0); - PUT32(T0TCR, 1); /* enable timer0 */ - #elif defined(CONFIG_TEGRA) /* No timer routines for tegra as yet */ lastdec = 0; @@ -198,7 +178,7 @@ int timer_init (void) */ -#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292) +#if defined(CONFIG_NETARM) ulong get_timer (ulong base) { @@ -216,12 +196,6 @@ void __udelay (unsigned long usec) tmo += get_timer (0); while (get_timer_masked () < tmo) -#ifdef CONFIG_LPC2292 - /* GJ - not sure whether this is really needed or a misunderstanding */ - __asm__ __volatile__(" nop"); -#else - /*NOP*/; -#endif } ulong get_timer_masked (void) diff --git a/arch/arm/cpu/arm720t/lpc2292/Makefile b/arch/arm/cpu/arm720t/lpc2292/Makefile deleted file mode 100644 index 1b93008685..0000000000 --- a/arch/arm/cpu/arm720t/lpc2292/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS = flash.o mmc.o mmc_hw.o spi.o -SOBJS = $(obj)iap_entry.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -# this MUST be compiled as thumb code! -$(SOBJS): - $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c deleted file mode 100644 index 3d2dc32231..0000000000 --- a/arch/arm/cpu/arm720t/lpc2292/flash.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2006 Embedded Artists AB - * - * Modified to remove all but the IAP-command related code by - * Gary Jennejohn - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* IAP commands use 32 bytes at the top of CPU internal sram, we - use 512 bytes below that */ -#define COPY_BUFFER_LOCATION 0x40003de0 - -#define IAP_LOCATION 0x7ffffff1 -#define IAP_CMD_PREPARE 50 -#define IAP_CMD_COPY 51 -#define IAP_CMD_ERASE 52 -#define IAP_CMD_CHECK 53 -#define IAP_CMD_ID 54 -#define IAP_CMD_VERSION 55 -#define IAP_CMD_COMPARE 56 - -#define IAP_RET_CMD_SUCCESS 0 - -static unsigned long command[5]; -static unsigned long result[2]; - -extern void iap_entry(unsigned long * command, unsigned long * result); - -/*----------------------------------------------------------------------- - * - */ -static int get_flash_sector(flash_info_t * info, ulong flash_addr) -{ - int i; - - for(i = 1; i < (info->sector_count); i++) { - if (flash_addr < (info->start[i])) - break; - } - - return (i-1); -} - -/*----------------------------------------------------------------------- - * This function assumes that flash_addr is aligned on 512 bytes boundary - * in flash. This function also assumes that prepare have been called - * for the sector in question. - */ -int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) -{ - int first_sector; - int last_sector; - - first_sector = get_flash_sector(info, flash_addr); - last_sector = get_flash_sector(info, flash_addr + 512 - 1); - - /* prepare sectors for write */ - command[0] = IAP_CMD_PREPARE; - command[1] = first_sector; - command[2] = last_sector; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP prepare failed\n"); - return ERR_PROG_ERROR; - } - - command[0] = IAP_CMD_COPY; - command[1] = flash_addr; - command[2] = COPY_BUFFER_LOCATION; - command[3] = 512; - command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP copy failed\n"); - return 1; - } - - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag; - int prot; - int sect; - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - - flag = disable_interrupts(); - - printf ("Erasing %d sectors starting at sector %2d.\n" - "This make take some time ... ", - s_last - s_first + 1, s_first); - - command[0] = IAP_CMD_PREPARE; - command[1] = s_first; - command[2] = s_last; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP prepare failed\n"); - return ERR_PROTECTED; - } - - command[0] = IAP_CMD_ERASE; - command[1] = s_first; - command[2] = s_last; - command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP erase failed\n"); - return ERR_PROTECTED; - } - - if (flag) - enable_interrupts(); - - return ERR_OK; -} - -int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr, - ulong cnt) -{ - int first_copy_size; - int last_copy_size; - int first_block; - int last_block; - int nbr_mid_blocks; - uchar memmap_value; - ulong i; - uchar* src_org; - uchar* dst_org; - int ret = ERR_OK; - - src_org = src; - dst_org = (uchar*)addr; - - first_block = addr / 512; - last_block = (addr + cnt) / 512; - nbr_mid_blocks = last_block - first_block - 1; - - first_copy_size = 512 - (addr % 512); - last_copy_size = (addr + cnt) % 512; - - debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " - "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", - (ulong)(first_block * 512), - (ulong)COPY_BUFFER_LOCATION, - (ulong)src, - (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size), - first_copy_size, - (ulong)COPY_BUFFER_LOCATION, - (ulong)(first_block * 512)); - - /* copy first block */ - memcpy((void*)COPY_BUFFER_LOCATION, - (void*)(first_block * 512), 512); - memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size), - src, first_copy_size); - lpc2292_copy_buffer_to_flash(info, first_block * 512); - src += first_copy_size; - addr += first_copy_size; - - /* copy middle blocks */ - for (i = 0; i < nbr_mid_blocks; i++) { - debug("copy middle block: %lX -> %lX 512 bytes, " - "%lX -> %lX 512 bytes\n", - (ulong)src, - (ulong)COPY_BUFFER_LOCATION, - (ulong)COPY_BUFFER_LOCATION, - (ulong)addr); - - memcpy((void*)COPY_BUFFER_LOCATION, src, 512); - lpc2292_copy_buffer_to_flash(info, addr); - src += 512; - addr += 512; - } - - - if (last_copy_size > 0) { - debug("copy last block: (1) %lX -> %lX 0x200 bytes, " - "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", - (ulong)(last_block * 512), - (ulong)COPY_BUFFER_LOCATION, - (ulong)src, - (ulong)(COPY_BUFFER_LOCATION), - last_copy_size, - (ulong)COPY_BUFFER_LOCATION, - (ulong)addr); - - /* copy last block */ - memcpy((void*)COPY_BUFFER_LOCATION, - (void*)(last_block * 512), 512); - memcpy((void*)COPY_BUFFER_LOCATION, - src, last_copy_size); - lpc2292_copy_buffer_to_flash(info, addr); - } - - /* verify write */ - memmap_value = GET8(MEMMAP); - - disable_interrupts(); - - PUT8(MEMMAP, 01); /* we must make sure that initial 64 - bytes are taken from flash when we - do the compare */ - - for (i = 0; i < cnt; i++) { - if (*dst_org != *src_org){ - printf("Write failed. Byte %lX differs\n", i); - ret = ERR_PROG_ERROR; - break; - } - dst_org++; - src_org++; - } - - PUT8(MEMMAP, memmap_value); - enable_interrupts(); - - return ret; -} diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S deleted file mode 100644 index c31d5190bd..0000000000 --- a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S +++ /dev/null @@ -1,7 +0,0 @@ -IAP_ADDRESS: .word 0x7FFFFFF1 - -.globl iap_entry -iap_entry: - ldr r2, IAP_ADDRESS - bx r2 - mov pc, lr diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c deleted file mode 100644 index beaffe944c..0000000000 --- a/arch/arm/cpu/arm720t/lpc2292/mmc.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include "mmc_hw.h" -#include - -#ifdef CONFIG_MMC - -#undef MMC_DEBUG - -static block_dev_desc_t mmc_dev; - -/* these are filled out by a call to mmc_hw_get_parameters */ -static int hw_size; /* in kbytes */ -static int hw_nr_sects; -static int hw_sect_size; /* in bytes */ - -block_dev_desc_t * mmc_get_dev(int dev) -{ - return (block_dev_desc_t *)(&mmc_dev); -} - -unsigned long mmc_block_read(int dev, - unsigned long start, - lbaint_t blkcnt, - void *buffer) -{ - unsigned long rc = 0; - unsigned char *p = (unsigned char *)buffer; - unsigned long i; - unsigned long addr = start; - -#ifdef MMC_DEBUG - printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start, - (unsigned long)blkcnt); -#endif - - for(i = 0; i < (unsigned long)blkcnt; i++) { -#ifdef MMC_DEBUG - printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p); -#endif - (void)mmc_read_sector(addr, p); - rc++; - addr++; - p += hw_sect_size; - } - - return rc; -} - -/*----------------------------------------------------------------------------- - * Read hardware paramterers (sector size, size, number of sectors) - */ -static int mmc_hw_get_parameters(void) -{ - unsigned char csddata[16]; - unsigned int sizemult; - unsigned int size; - - mmc_read_csd(csddata); - hw_sect_size = 1<<(csddata[5] & 0x0f); - size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0); - sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1); - hw_nr_sects = (size+1)*(1<<(sizemult+2)); - hw_size = hw_nr_sects*hw_sect_size/1024; - -#ifdef MMC_DEBUG - printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, " - "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size); -#endif - - return 0; -} - -int mmc_legacy_init(int verbose) -{ - int ret = -ENODEV; - - if (verbose) - printf("mmc_legacy_init\n"); - - spi_init(); - /* this meeds to be done twice */ - mmc_hw_init(); - udelay(1000); - mmc_hw_init(); - - mmc_hw_get_parameters(); - - mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; - mmc_dev.blksz = hw_sect_size; - mmc_dev.lba = hw_nr_sects; - sprintf((char*)mmc_dev.vendor, "Unknown vendor"); - sprintf((char*)mmc_dev.product, "Unknown product"); - sprintf((char*)mmc_dev.revision, "N/A"); - mmc_dev.removable = 0; /* should be true??? */ - mmc_dev.block_read = mmc_block_read; - - fat_register_device(&mmc_dev, 1); - - ret = 0; - - return ret; -} - -#endif /* CONFIG_MMC */ diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c deleted file mode 100644 index bd6a5b1206..0000000000 --- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - This code was original written by Ulrich Radig and modified by - Embedded Artists AB (www.embeddedartists.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include - -#define MMC_Enable() PUT32(IO1CLR, 1l << 22) -#define MMC_Disable() PUT32(IO1SET, 1l << 22) -#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0); - -static unsigned char Write_Command_MMC (unsigned char *CMD); -static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, - unsigned short int Bytes); - -/* initialize the hardware */ -int mmc_hw_init(void) -{ - unsigned long a; - unsigned short int Timeout = 0; - unsigned char b; - unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95}; - - /* set-up GPIO and SPI */ - (*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */ - (*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */ - - MMC_Disable(); - - spi_lock(); - spi_set_clock(248); - spi_set_cfg(0, 1, 0); - MMC_Enable(); - - /* waste some time */ - for(a=0; a < 20000; a++) - asm("nop"); - - /* Put the MMC/SD-card into SPI-mode */ - for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */ - spi_write(0xff); - - /* Sends command CMD0 to MMC/SD-card */ - while (Write_Command_MMC(CMD) != 1) { - if (Timeout++ > 200) { - MMC_Disable(); - spi_unlock(); - return(1); /* Abort with command 1 (return 1) */ - } - } - /* Sends Command CMD1 an MMC/SD-card */ - Timeout = 0; - CMD[0] = 0x41;/* Command 1 */ - CMD[5] = 0xFF; - - while (Write_Command_MMC(CMD) != 0) { - if (Timeout++ > 200) { - MMC_Disable(); - spi_unlock(); - return (2); /* Abort with command 2 (return 2) */ - } - } - - MMC_Disable(); - spi_unlock(); - - return 0; -} - -/* ############################################################################ - Sends a command to the MMC/SD-card - ######################################################################### */ -static unsigned char Write_Command_MMC (unsigned char *CMD) -{ - unsigned char a, tmp = 0xff; - unsigned short int Timeout = 0; - - MMC_Disable(); - spi_write(0xFF); - MMC_Enable(); - - for (a = 0; a < 0x06; a++) - spi_write(*CMD++); - - while (tmp == 0xff) { - tmp = spi_read(); - if (Timeout++ > 5000) - break; - } - - return (tmp); -} - -/* ############################################################################ - Routine to read the CID register from the MMC/SD-card (16 bytes) - ######################################################################### */ -void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short - int Bytes) -{ - unsigned short int a; - - spi_lock(); - mmc_spi_cfg(); - MMC_Enable(); - - if (Write_Command_MMC(CMD) != 0) { - MMC_Disable(); - spi_unlock(); - return; - } - - while (spi_read() != 0xfe) {}; - for (a = 0; a < Bytes; a++) - *Buffer++ = spi_read(); - - /* Read the CRC-byte */ - spi_read(); /* CRC - byte is discarded */ - spi_read(); /* CRC - byte is discarded */ - /* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */ - MMC_Disable(); - spi_unlock(); - - return; -} - -/* ############################################################################ - Routine to read a block (512 bytes) from the MMC/SD-card - ######################################################################### */ -unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) -{ - /* Command 16 to read aBlocks from the MMC/SD - caed */ - unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; - - /* The address on the MMC/SD-card is in bytes, - addr is transformed from blocks to bytes and the result is - placed into the command */ - - addr = addr << 9; /* addr = addr * 512 */ - - CMD[1] = ((addr & 0xFF000000) >> 24); - CMD[2] = ((addr & 0x00FF0000) >> 16); - CMD[3] = ((addr & 0x0000FF00) >> 8 ); - - MMC_Read_Block(CMD, Buffer, 512); - - return (0); -} - -/* ############################################################################ - Routine to write a block (512 byte) to the MMC/SD-card - ######################################################################### */ -unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) -{ - unsigned char tmp, a; - unsigned short int b; - /* Command 24 to write a block to the MMC/SD - card */ - unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; - - /* The address on the MMC/SD-card is in bytes, - addr is transformed from blocks to bytes and the result is - placed into the command */ - - addr = addr << 9; /* addr = addr * 512 */ - - CMD[1] = ((addr & 0xFF000000) >> 24); - CMD[2] = ((addr & 0x00FF0000) >> 16); - CMD[3] = ((addr & 0x0000FF00) >> 8 ); - - spi_lock(); - mmc_spi_cfg(); - MMC_Enable(); - - /* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */ - tmp = Write_Command_MMC(CMD); - if (tmp != 0) { - MMC_Disable(); - spi_unlock(); - return(tmp); - } - - /* Do a short delay and send a clock-pulse to the MMC/SD-card */ - for (a = 0; a < 100; a++) - spi_read(); - - /* Send a start byte to the MMC/SD-card */ - spi_write(0xFE); - - /* Write the block (512 bytes) to the MMC/SD-card */ - for (b = 0; b < 512; b++) - spi_write(*Buffer++); - - /* write the CRC-Byte */ - spi_write(0xFF); /* write a dummy CRC */ - spi_write(0xFF); /* CRC code is not used */ - - /* Wait for MMC/SD-card busy */ - while (spi_read() != 0xff) {}; - - /* set MMC_Chip_Select to high (MMC/SD-card inactive) */ - MMC_Disable(); - spi_unlock(); - return (0); -} - -/* ######################################################################### - Routine to read the CSD register from the MMC/SD-card (16 bytes) - ######################################################################### */ -unsigned char mmc_read_csd (unsigned char *Buffer) -{ - /* Command to read the CSD register */ - unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF}; - - MMC_Read_Block(CMD, Buffer, 16); - - return (0); -} diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h deleted file mode 100644 index 3687dbf696..0000000000 --- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - This module implements a linux character device driver for the 24c256 chip. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef _MMC_HW_ -#define _MMC_HW_ - -unsigned char mmc_read_csd(unsigned char *Buffer); -unsigned char mmc_read_sector (unsigned long addr, - unsigned char *Buffer); -unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer); -int mmc_hw_init(void); - -#endif /* _MMC_HW_ */ diff --git a/arch/arm/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c deleted file mode 100644 index d296bdac68..0000000000 --- a/arch/arm/cpu/arm720t/lpc2292/spi.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - This module implements an interface to the SPI on the lpc22xx. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include - -unsigned long spi_flags; -unsigned char spi_idle = 0x00; - -int spi_init(void) -{ - unsigned long pinsel0_value; - - /* activate spi pins */ - pinsel0_value = GET32(PINSEL0); - pinsel0_value &= ~(0xFFl << 8); - pinsel0_value |= (0x55l << 8); - PUT32(PINSEL0, pinsel0_value); - - return 0; -} diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 2f914e9b4e..0daf84811a 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -43,11 +43,7 @@ _start: b reset ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort -#ifdef CONFIG_LPC2292 - .word 0xB4405F76 /* 2's complement of the checksum of the vectors */ -#else ldr pc, _not_used -#endif ldr pc, _irq ldr pc, _fiq @@ -151,10 +147,6 @@ reset: bl cpu_init_crit #endif -#ifdef CONFIG_LPC2292 - bl lowlevel_init -#endif - /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) @@ -291,16 +283,6 @@ _dynsym_start_ofs: ************************************************************************* */ -#if defined(CONFIG_LPC2292) -PLLCFG_ADR: .word PLLCFG -PLLFEED_ADR: .word PLLFEED -PLLCON_ADR: .word PLLCON -PLLSTAT_ADR: .word PLLSTAT -VPBDIV_ADR: .word VPBDIV -MEMMAP_ADR: .word MEMMAP - -#endif - cpu_init_crit: #if defined(CONFIG_NETARM) /* @@ -371,50 +353,6 @@ cpu_init_crit: #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific initialisation for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - /* Set-up PLL */ - mov r3, #0xAA - mov r4, #0x55 - /* First disconnect and disable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x00 - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set new M and P values */ - ldr r0, PLLCFG_ADR - mov r1, #0x23 /* M=4 and P=2 */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Then enable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x01 /* PLL enable bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Wait for the lock */ - ldr r0, PLLSTAT_ADR - mov r1, #0x400 /* lock bit */ -lock_loop: - ldr r2, [r0] - and r2, r1, r2 - cmp r2, #0 - beq lock_loop - /* And finally connect the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x03 /* PLL enable bit and connect bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set-up VPBDIV register */ - ldr r0, VPBDIV_ADR - mov r1, #0x01 /* VPB clock is same as process clock */ - str r1, [r0] #elif defined(CONFIG_TEGRA) /* No cpu_init_crit for tegra as yet */ #else @@ -432,7 +370,7 @@ lock_loop: str r1, [r0] #endif -#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA) +#if !defined(CONFIG_TEGRA) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -636,11 +574,6 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - .align 5 -.globl reset_cpu -reset_cpu: - mov pc, r0 #elif defined(CONFIG_TEGRA) /* No specific reset actions for tegra as yet */ #else diff --git a/arch/arm/include/asm/arch-lpc2292/hardware.h b/arch/arm/include/asm/arch-lpc2292/hardware.h deleted file mode 100644 index 5e227e367c..0000000000 --- a/arch/arm/include/asm/arch-lpc2292/hardware.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if defined(CONFIG_LPC2292) -#include -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h b/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h deleted file mode 100644 index 5715f3ef74..0000000000 --- a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h +++ /dev/null @@ -1,225 +0,0 @@ -#ifndef __LPC2292_REGISTERS_H -#define __LPC2292_REGISTERS_H - -#include - -/* Macros for reading/writing registers */ -#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) -#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) -#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) -#define GET8(reg) (*(volatile unsigned char*)(reg)) -#define GET16(reg) (*(volatile unsigned short*)(reg)) -#define GET32(reg) (*(volatile unsigned int*)(reg)) - -/* External Memory Controller */ - -#define BCFG0 0xFFE00000 /* 32-bits */ -#define BCFG1 0xFFE00004 /* 32-bits */ -#define BCFG2 0xFFE00008 /* 32-bits */ -#define BCFG3 0xFFE0000c /* 32-bits */ - -/* System Control Block */ - -#define EXTINT 0xE01FC140 -#define EXTWAKE 0xE01FC144 -#define EXTMODE 0xE01FC148 -#define EXTPOLAR 0xE01FC14C -#define MEMMAP 0xE01FC040 -#define PLLCON 0xE01FC080 -#define PLLCFG 0xE01FC084 -#define PLLSTAT 0xE01FC088 -#define PLLFEED 0xE01FC08C -#define PCON 0xE01FC0C0 -#define PCONP 0xE01FC0C4 -#define VPBDIV 0xE01FC100 - -/* Memory Acceleration Module */ - -#define MAMCR 0xE01FC000 -#define MAMTIM 0xE01FC004 - -/* Vectored Interrupt Controller */ - -#define VICIRQStatus 0xFFFFF000 -#define VICFIQStatus 0xFFFFF004 -#define VICRawIntr 0xFFFFF008 -#define VICIntSelect 0xFFFFF00C -#define VICIntEnable 0xFFFFF010 -#define VICIntEnClr 0xFFFFF014 -#define VICSoftInt 0xFFFFF018 -#define VICSoftIntClear 0xFFFFF01C -#define VICProtection 0xFFFFF020 -#define VICVectAddr 0xFFFFF030 -#define VICDefVectAddr 0xFFFFF034 -#define VICVectAddr0 0xFFFFF100 -#define VICVectAddr1 0xFFFFF104 -#define VICVectAddr2 0xFFFFF108 -#define VICVectAddr3 0xFFFFF10C -#define VICVectAddr4 0xFFFFF110 -#define VICVectAddr5 0xFFFFF114 -#define VICVectAddr6 0xFFFFF118 -#define VICVectAddr7 0xFFFFF11C -#define VICVectAddr8 0xFFFFF120 -#define VICVectAddr9 0xFFFFF124 -#define VICVectAddr10 0xFFFFF128 -#define VICVectAddr11 0xFFFFF12C -#define VICVectAddr12 0xFFFFF130 -#define VICVectAddr13 0xFFFFF134 -#define VICVectAddr14 0xFFFFF138 -#define VICVectAddr15 0xFFFFF13C -#define VICVectCntl0 0xFFFFF200 -#define VICVectCntl1 0xFFFFF204 -#define VICVectCntl2 0xFFFFF208 -#define VICVectCntl3 0xFFFFF20C -#define VICVectCntl4 0xFFFFF210 -#define VICVectCntl5 0xFFFFF214 -#define VICVectCntl6 0xFFFFF218 -#define VICVectCntl7 0xFFFFF21C -#define VICVectCntl8 0xFFFFF220 -#define VICVectCntl9 0xFFFFF224 -#define VICVectCntl10 0xFFFFF228 -#define VICVectCntl11 0xFFFFF22C -#define VICVectCntl12 0xFFFFF230 -#define VICVectCntl13 0xFFFFF234 -#define VICVectCntl14 0xFFFFF238 -#define VICVectCntl15 0xFFFFF23C - -/* Pin connect block */ - -#define PINSEL0 0xE002C000 /* 32 bits */ -#define PINSEL1 0xE002C004 /* 32 bits */ -#define PINSEL2 0xE002C014 /* 32 bits */ - -/* GPIO */ - -#define IO0PIN 0xE0028000 -#define IO0SET 0xE0028004 -#define IO0DIR 0xE0028008 -#define IO0CLR 0xE002800C -#define IO1PIN 0xE0028010 -#define IO1SET 0xE0028014 -#define IO1DIR 0xE0028018 -#define IO1CLR 0xE002801C -#define IO2PIN 0xE0028020 -#define IO2SET 0xE0028024 -#define IO2DIR 0xE0028028 -#define IO2CLR 0xE002802C -#define IO3PIN 0xE0028030 -#define IO3SET 0xE0028034 -#define IO3DIR 0xE0028038 -#define IO3CLR 0xE002803C - -/* Uarts */ - -#define U0RBR 0xE000C000 -#define U0THR 0xE000C000 -#define U0IER 0xE000C004 -#define U0IIR 0xE000C008 -#define U0FCR 0xE000C008 -#define U0LCR 0xE000C00C -#define U0LSR 0xE000C014 -#define U0SCR 0xE000C01C -#define U0DLL 0xE000C000 -#define U0DLM 0xE000C004 - -#define U1RBR 0xE0010000 -#define U1THR 0xE0010000 -#define U1IER 0xE0010004 -#define U1IIR 0xE0010008 -#define U1FCR 0xE0010008 -#define U1LCR 0xE001000C -#define U1MCR 0xE0010010 -#define U1LSR 0xE0010014 -#define U1MSR 0xE0010018 -#define U1SCR 0xE001001C -#define U1DLL 0xE0010000 -#define U1DLM 0xE0010004 - -/* I2C */ - -#define I2CONSET 0xE001C000 -#define I2STAT 0xE001C004 -#define I2DAT 0xE001C008 -#define I2ADR 0xE001C00C -#define I2SCLH 0xE001C010 -#define I2SCLL 0xE001C014 -#define I2CONCLR 0xE001C018 - -/* SPI */ - -#define S0SPCR 0xE0020000 -#define S0SPSR 0xE0020004 -#define S0SPDR 0xE0020008 -#define S0SPCCR 0xE002000C -#define S0SPINT 0xE002001C - -#define S1SPCR 0xE0030000 -#define S1SPSR 0xE0030004 -#define S1SPDR 0xE0030008 -#define S1SPCCR 0xE003000C -#define S1SPINT 0xE003001C - -/* CAN controller */ - -/* skip for now */ - -/* Timers */ - -#define T0IR 0xE0004000 -#define T0TCR 0xE0004004 -#define T0TC 0xE0004008 -#define T0PR 0xE000400C -#define T0PC 0xE0004010 -#define T0MCR 0xE0004014 -#define T0MR0 0xE0004018 -#define T0MR1 0xE000401C -#define T0MR2 0xE0004020 -#define T0MR3 0xE0004024 -#define T0CCR 0xE0004028 -#define T0CR0 0xE000402C -#define T0CR1 0xE0004030 -#define T0CR2 0xE0004034 -#define T0CR3 0xE0004038 -#define T0EMR 0xE000403C - -#define T1IR 0xE0008000 -#define T1TCR 0xE0008004 -#define T1TC 0xE0008008 -#define T1PR 0xE000800C -#define T1PC 0xE0008010 -#define T1MCR 0xE0008014 -#define T1MR0 0xE0008018 -#define T1MR1 0xE000801C -#define T1MR2 0xE0008020 -#define T1MR3 0xE0008024 -#define T1CCR 0xE0008028 -#define T1CR0 0xE000802C -#define T1CR1 0xE0008030 -#define T1CR2 0xE0008034 -#define T1CR3 0xE0008038 -#define T1EMR 0xE000803C - -/* PWM */ - -/* skip for now */ - -/* A/D converter */ - -/* skip for now */ - -/* Real Time Clock */ - -/* skip for now */ - -/* Watchdog */ - -#define WDMOD 0xE0000000 -#define WDTC 0xE0000004 -#define WDFEED 0xE0000008 -#define WDTV 0xE000000C - -/* EmbeddedICE LOGIC */ - -/* skip for now */ - -#endif diff --git a/arch/arm/include/asm/arch-lpc2292/spi.h b/arch/arm/include/asm/arch-lpc2292/spi.h deleted file mode 100644 index 6ae66e8ba7..0000000000 --- a/arch/arm/include/asm/arch-lpc2292/spi.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - This file defines the interface to the lpc22xx SPI module. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This file may be included in software not adhering to the GPL. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef SPI_H -#define SPI_H - -#include -#include -#include -#include - -#define SPIF 0x80 - -#define spi_lock() disable_interrupts(); -#define spi_unlock() enable_interrupts(); - -extern unsigned long spi_flags; -extern unsigned char spi_idle; - -int spi_init(void); - -static inline unsigned char spi_read(void) -{ - unsigned char b; - - PUT8(S0SPDR, spi_idle); - while (!(GET8(S0SPSR) & SPIF)); - b = GET8(S0SPDR); - - return b; -} - -static inline void spi_write(unsigned char b) -{ - PUT8(S0SPDR, b); - while (!(GET8(S0SPSR) & SPIF)); - GET8(S0SPDR); /* this will clear the SPIF bit */ -} - -static inline void spi_set_clock(unsigned char clk_value) -{ - PUT8(S0SPCCR, clk_value); -} - -static inline void spi_set_cfg(unsigned char phase, - unsigned char polarity, - unsigned char lsbf) -{ - unsigned char v = 0x20; /* master bit set */ - - if (phase) - v |= 0x08; /* set phase bit */ - if (polarity) { - v |= 0x10; /* set polarity bit */ - spi_idle = 0xFF; - } else { - spi_idle = 0x00; - } - if (lsbf) - v |= 0x40; /* set lsbf bit */ - - PUT8(S0SPCR, v); -} -#endif /* SPI_H */ diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index 9feb2e55a3..c6a8ab0521 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -125,63 +125,59 @@ III) Analysis of in-tree drivers ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 17) serial_lpc2292.c + 17) serial_max3100.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 18) serial_max3100.c - -------------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 19) serial_mxc.c + 18) serial_mxc.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 20) serial_netarm.c + 19) serial_netarm.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 21) serial_pl01x.c + 20) serial_pl01x.c ------------------ No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this driver in fact contains two drivers in total. - 22) serial_pxa.c + 21) serial_pxa.c ---------------- This driver is a bit complicated, but due to clean support for CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the conversion process. - 23) serial_s3c24x0.c + 22) serial_s3c24x0.c -------------------- This driver, being quite ad-hoc might need some work to bring back to shape. - 24) serial_s3c44b0.c + 23) serial_s3c44b0.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 25) serial_s5p.c + 24) serial_s5p.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 26) serial_sa1100.c + 25) serial_sa1100.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 27) serial_sh.c + 26) serial_sh.c --------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 28) serial_xuartlite.c + 27) serial_xuartlite.c ---------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 29) usbtty.c + 28) usbtty.c ------------ This driver seems very complicated and entangled with USB framework. The conversion might be complicated here. - 30) arch/powerpc/cpu/mpc512x/serial.c + 29) arch/powerpc/cpu/mpc512x/serial.c ------------------------------------- This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to proper place. diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 36c6114e3c..1595c0714a 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -41,9 +41,6 @@ #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include #endif -#ifdef CONFIG_LPC2292 -#include -#endif #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) #include #endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 920ce6910e..51af313f51 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -44,7 +44,6 @@ COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o -COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MXC_UART) += serial_mxc.o COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index e0886d562e..1d68f5568d 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -104,7 +104,6 @@ serial_initfunc(imx_serial_initialize); serial_initfunc(ixp_serial_initialize); serial_initfunc(ks8695_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); -serial_initfunc(lpc2292_serial_initialize); serial_initfunc(max3100_serial_initialize); serial_initfunc(mxc_serial_initialize); serial_initfunc(netarm_serial_initialize); @@ -202,7 +201,6 @@ void serial_initialize(void) ixp_serial_initialize(); ks8695_serial_initialize(); lh7a40x_serial_initialize(); - lpc2292_serial_initialize(); max3100_serial_initialize(); mxc_serial_initialize(); netarm_serial_initialize(); diff --git a/drivers/serial/serial_lpc2292.c b/drivers/serial/serial_lpc2292.c deleted file mode 100644 index 8abc476713..0000000000 --- a/drivers/serial/serial_lpc2292.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void lpc2292_serial_setbrg(void) -{ - unsigned short divisor = 0; - - switch (gd->baudrate) { - case 1200: divisor = 3072; break; - case 9600: divisor = 384; break; - case 19200: divisor = 192; break; - case 38400: divisor = 96; break; - case 57600: divisor = 64; break; - case 115200: divisor = 32; break; - default: hang (); break; - } - - /* init serial UART0 */ - PUT8(U0LCR, 0); - PUT8(U0IER, 0); - PUT8(U0LCR, 0x80); /* DLAB=1 */ - PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); - PUT8(U0DLM, (unsigned char)(divisor >> 8)); - PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ - PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ -} - -static int lpc2292_serial_init(void) -{ - unsigned long pinsel0; - - serial_setbrg (); - - pinsel0 = GET32(PINSEL0); - pinsel0 &= ~(0x00000003); - pinsel0 |= 5; - PUT32(PINSEL0, pinsel0); - - return (0); -} - -static void lpc2292_serial_putc(const char c) -{ - if (c == '\n') - { - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, '\r'); - } - - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, c); -} - -static int lpc2292_serial_getc(void) -{ - while((GET8(U0LSR) & 1) == 0); - return GET8(U0RBR); -} - -/* Test if there is a byte to read */ -static int lpc2292_serial_tstc(void) -{ - return (GET8(U0LSR) & 1); -} - -static struct serial_device lpc2292_serial_drv = { - .name = "lpc2292_serial", - .start = lpc2292_serial_init, - .stop = NULL, - .setbrg = lpc2292_serial_setbrg, - .putc = lpc2292_serial_putc, - .puts = default_serial_puts, - .getc = lpc2292_serial_getc, - .tstc = lpc2292_serial_tstc, -}; - -void lpc2292_serial_initialize(void) -{ - serial_register(&lpc2292_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &lpc2292_serial_drv; -} diff --git a/include/flash.h b/include/flash.h index 6d70bdd81d..7db599e783 100644 --- a/include/flash.h +++ b/include/flash.h @@ -348,7 +348,6 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ -#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ #define NUMONYX_256MBIT 0x8922 /* Numonyx P33/30 256MBit 65nm */ /*----------------------------------------------------------------------- -- cgit v1.2.3 From afad40299eea12dfd032b44d04c2d4151d7e9862 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:09 +0000 Subject: arm: Remove support for s3c4510 This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut --- CREDITS | 5 - arch/arm/cpu/arm720t/cpu.c | 2 +- arch/arm/cpu/arm720t/interrupts.c | 106 +--------- arch/arm/cpu/arm720t/s3c4510b/Makefile | 45 ----- arch/arm/cpu/arm720t/s3c4510b/cache.c | 86 -------- arch/arm/cpu/arm720t/start.S | 19 -- arch/arm/include/asm/arch-s3c4510b/hardware.h | 272 -------------------------- drivers/serial/Makefile | 1 - drivers/serial/s3c4510b_uart.c | 231 ---------------------- drivers/serial/s3c4510b_uart.h | 109 ----------- drivers/serial/serial.c | 2 - 11 files changed, 2 insertions(+), 876 deletions(-) delete mode 100644 arch/arm/cpu/arm720t/s3c4510b/Makefile delete mode 100644 arch/arm/cpu/arm720t/s3c4510b/cache.c delete mode 100644 arch/arm/include/asm/arch-s3c4510b/hardware.h delete mode 100644 drivers/serial/s3c4510b_uart.c delete mode 100644 drivers/serial/s3c4510b_uart.h diff --git a/CREDITS b/CREDITS index fa9a14ebdd..7c1458f51d 100644 --- a/CREDITS +++ b/CREDITS @@ -79,11 +79,6 @@ N: Oliver Brown E: obrown@adventnetworks.com D: Port to the gw8260 board -N: Curt Brune -E: curt@cucy.com -D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC) -W: http://www.cucy.com - N: Jonathan De Bruyne E: jonathan.debruyne@siemens.atea.be D: Port to Siemens IAD210 board diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index e25f6f2ea7..864720fcdf 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -46,7 +46,7 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */ -#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) +#if defined(CONFIG_NETARM) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 5b21cc3cea..e3b59fef09 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -45,28 +45,10 @@ #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) #endif -#ifdef CONFIG_S3C4510B -/* require interrupts for the S3C4510B */ -# ifndef CONFIG_USE_IRQ -# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B -# else -static struct _irq_handler IRQ_HANDLER[N_IRQS]; -# endif -#endif /* CONFIG_S3C4510B */ - #ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) { -#if defined(CONFIG_S3C4510B) - unsigned int pending; - - while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */ - IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data); - - /* clear pending interrupt */ - PUT_REG( REG_INTPEND, (1<<(pending>>2))); - } -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No do_irq() for IntegratorAP/CM720T as yet */ #else #error do_irq() not defined for this CPU type @@ -74,23 +56,6 @@ void do_irq (struct pt_regs *pt_regs) } #endif -#ifdef CONFIG_S3C4510B -static void default_isr( void *data) { - printf ("default_isr(): called for IRQ %d\n", (int)data); -} - -static void timer_isr( void *data) { - unsigned int *pTime = (unsigned int *)data; - - (*pTime)++; - if ( !(*pTime % (CONFIG_SYS_HZ/4))) { - /* toggle LED 0 */ - PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1); - } - -} -#endif - #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* Use IntegratorAP routines in board/integratorap.c */ #else @@ -98,32 +63,6 @@ static void timer_isr( void *data) { static ulong timestamp; static ulong lastdec; -#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B) -int arch_interrupt_init (void) -{ - int i; - - /* install default interrupt handlers */ - for ( i = 0; i < N_IRQS; i++) { - IRQ_HANDLER[i].m_data = (void *)i; - IRQ_HANDLER[i].m_func = default_isr; - } - - /* configure interrupts for IRQ mode */ - PUT_REG( REG_INTMODE, 0x0); - /* clear any pending interrupts */ - PUT_REG( REG_INTPEND, 0x1FFFFF); - - lastdec = 0; - - /* install interrupt handler for timer */ - IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp; - IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; - - return 0; -} -#endif - int timer_init (void) { #if defined(CONFIG_NETARM) @@ -137,29 +76,6 @@ int timer_init (void) /* set timer 2 counter */ lastdec = TIMER_LOAD_VAL; -#elif defined(CONFIG_S3C4510B) - /* configure free running timer 0 */ - PUT_REG( REG_TMOD, 0x0); - /* Stop timer 0 */ - CLR_REG( REG_TMOD, TM0_RUN); - - /* Configure for interval mode */ - CLR_REG( REG_TMOD, TM1_TOGGLE); - - /* - * Load Timer data register with count down value. - * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ - */ - PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ)); - - /* - * Enable global interrupt - * Enable timer0 interrupt - */ - CLR_REG( REG_INTMASK, ((1<= 0); } -#elif defined(CONFIG_S3C4510B) - -ulong get_timer (ulong base) -{ - return timestamp - base; -} - -void __udelay (unsigned long usec) -{ - u32 ticks; - - ticks = (usec * CONFIG_SYS_HZ) / 1000000; - - ticks += get_timer (0); - - while (get_timer (0) < ticks) - /*NOP*/; - -} - #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_TEGRA) diff --git a/arch/arm/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile deleted file mode 100644 index 5c6df08b1a..0000000000 --- a/arch/arm/cpu/arm720t/s3c4510b/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -COBJS-y += cache.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c deleted file mode 100644 index 104d287b26..0000000000 --- a/arch/arm/cpu/arm720t/s3c4510b/cache.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -void icache_enable (void) -{ - s32 i; - - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); - - /* 8KB cache, write enable */ - SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); - - /* clear TAG RAM bits */ - for ( i = 0; i < 256; i++) - PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); - - /* clear SET0 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); - - /* clear SET1 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); - - /* enable cache */ - SET_REG( REG_SYSCFG, CACHE_ENABLE); - -} - -void icache_disable (void) -{ - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); -} - -int icache_status (void) -{ - return GET_REG( REG_SYSCFG) & CACHE_ENABLE; -} - -void dcache_enable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_enable(); -} - -void dcache_disable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_disable(); -} - -int dcache_status (void) -{ - /* we don't have seperate instruction/data caches */ - return icache_status(); -} diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 0daf84811a..3a90e0d775 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -335,22 +335,6 @@ cpu_init_crit: ldr r0, =NETARM_GEN_MODULE_BASE str r1, [r0, #+NETARM_GEN_INTR_ENABLE] -#elif defined(CONFIG_S3C4510B) - - /* - * Mask off all IRQ sources - */ - ldr r1, =REG_INTMASK - ldr r0, =0x3FFFFF - str r0, [r1] - - /* - * Disable Cache - */ - ldr r0, =REG_SYSCFG - ldr r1, =0x83ffffa0 /* cache-disabled */ - str r1, [r0] - #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific initialisation for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_TEGRA) @@ -569,9 +553,6 @@ reset_cpu: ldr r1, =NETARM_GEN_SW_SVC_RESETB str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] mov pc, r0 -#elif defined(CONFIG_S3C4510B) -/* Nothing done here as reseting the CPU is board specific, depending - * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_TEGRA) diff --git a/arch/arm/include/asm/arch-s3c4510b/hardware.h b/arch/arm/include/asm/arch-s3c4510b/hardware.h deleted file mode 100644 index 6b8c8edd7a..0000000000 --- a/arch/arm/include/asm/arch-s3c4510b/hardware.h +++ /dev/null @@ -1,272 +0,0 @@ -#ifndef __HW_S3C4510_H -#define __HW_S3C4510_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Description: Samsung S3C4510B register layout - */ - -/*------------------------------------------------------------------------ - * ASIC Address Definition - *----------------------------------------------------------------------*/ - -/* L1 8KB on chip SRAM base address */ -#define SRAM_BASE (0x03fe0000) - -/* Special Register Start Address After System Reset */ -#define REG_BASE (0x03ff0000) -#define SPSTR (REG_BASE) - -/* *********************** */ -/* System Manager Register */ -/* *********************** */ -#define REG_SYSCFG (REG_BASE+0x0000) - -#define REG_CLKCON (REG_BASE+0x3000) -#define REG_EXTACON0 (REG_BASE+0x3008) -#define REG_EXTACON1 (REG_BASE+0x300c) -#define REG_EXTDBWTH (REG_BASE+0x3010) -#define REG_ROMCON0 (REG_BASE+0x3014) -#define REG_ROMCON1 (REG_BASE+0x3018) -#define REG_ROMCON2 (REG_BASE+0x301c) -#define REG_ROMCON3 (REG_BASE+0x3020) -#define REG_ROMCON4 (REG_BASE+0x3024) -#define REG_ROMCON5 (REG_BASE+0x3028) -#define REG_DRAMCON0 (REG_BASE+0x302c) -#define REG_DRAMCON1 (REG_BASE+0x3030) -#define REG_DRAMCON2 (REG_BASE+0x3034) -#define REG_DRAMCON3 (REG_BASE+0x3038) -#define REG_REFEXTCON (REG_BASE+0x303c) - -/* *********************** */ -/* Ethernet BDMA Register */ -/* *********************** */ -#define REG_BDMATXCON (REG_BASE+0x9000) -#define REG_BDMARXCON (REG_BASE+0x9004) -#define REG_BDMATXPTR (REG_BASE+0x9008) -#define REG_BDMARXPTR (REG_BASE+0x900c) -#define REG_BDMARXLSZ (REG_BASE+0x9010) -#define REG_BDMASTAT (REG_BASE+0x9014) - -/* Content Address Memory */ -#define REG_CAM_BASE (REG_BASE+0x9100) - -#define REG_BDMATXBUF (REG_BASE+0x9200) -#define REG_BDMARXBUF (REG_BASE+0x9800) - -/* *********************** */ -/* Ethernet MAC Register */ -/* *********************** */ -#define REG_MACCON (REG_BASE+0xa000) -#define REG_CAMCON (REG_BASE+0xa004) -#define REG_MACTXCON (REG_BASE+0xa008) -#define REG_MACTXSTAT (REG_BASE+0xa00c) -#define REG_MACRXCON (REG_BASE+0xa010) -#define REG_MACRXSTAT (REG_BASE+0xa014) -#define REG_STADATA (REG_BASE+0xa018) -#define REG_STACON (REG_BASE+0xa01c) -#define REG_CAMEN (REG_BASE+0xa028) -#define REG_EMISSCNT (REG_BASE+0xa03c) -#define REG_EPZCNT (REG_BASE+0xa040) -#define REG_ERMPZCNT (REG_BASE+0xa044) -#define REG_ETXSTAT (REG_BASE+0x9040) -#define REG_MACRXDESTR (REG_BASE+0xa064) -#define REG_MACRXSTATEM (REG_BASE+0xa090) -#define REG_MACRXFIFO (REG_BASE+0xa200) - -/********************/ -/* I2C Bus Register */ -/********************/ -#define REG_I2C_CON (REG_BASE+0xf000) -#define REG_I2C_BUF (REG_BASE+0xf004) -#define REG_I2C_PS (REG_BASE+0xf008) -#define REG_I2C_COUNT (REG_BASE+0xf00c) - -/********************/ -/* GDMA 0 */ -/********************/ -#define REG_GDMACON0 (REG_BASE+0xb000) -#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020) -#define REG_GDMASRC0 (REG_BASE+0xb004) -#define REG_GDMADST0 (REG_BASE+0xb008) -#define REG_GDMACNT0 (REG_BASE+0xb00c) - -/********************/ -/* GDMA 1 */ -/********************/ -#define REG_GDMACON1 (REG_BASE+0xc000) -#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020) -#define REG_GDMASRC1 (REG_BASE+0xc004) -#define REG_GDMADST1 (REG_BASE+0xc008) -#define REG_GDMACNT1 (REG_BASE+0xc00c) - -/********************/ -/* UART 0 */ -/********************/ -#define UART0_BASE (REG_BASE+0xd000) -#define REG_UART0_LCON (REG_BASE+0xd000) -#define REG_UART0_CTRL (REG_BASE+0xd004) -#define REG_UART0_STAT (REG_BASE+0xd008) -#define REG_UART0_TXB (REG_BASE+0xd00c) -#define REG_UART0_RXB (REG_BASE+0xd010) -#define REG_UART0_BAUD_DIV (REG_BASE+0xd014) -#define REG_UART0_BAUD_CNT (REG_BASE+0xd018) -#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C) - -/********************/ -/* UART 1 */ -/********************/ -#define UART1_BASE (REG_BASE+0xe000) -#define REG_UART1_LCON (REG_BASE+0xe000) -#define REG_UART1_CTRL (REG_BASE+0xe004) -#define REG_UART1_STAT (REG_BASE+0xe008) -#define REG_UART1_TXB (REG_BASE+0xe00c) -#define REG_UART1_RXB (REG_BASE+0xe010) -#define REG_UART1_BAUD_DIV (REG_BASE+0xe014) -#define REG_UART1_BAUD_CNT (REG_BASE+0xe018) -#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C) - -/********************/ -/* Timer Register */ -/********************/ -#define REG_TMOD (REG_BASE+0x6000) -#define REG_TDATA0 (REG_BASE+0x6004) -#define REG_TDATA1 (REG_BASE+0x6008) -#define REG_TCNT0 (REG_BASE+0x600c) -#define REG_TCNT1 (REG_BASE+0x6010) - -/**********************/ -/* I/O Port Interface */ -/**********************/ -#define REG_IOPMODE (REG_BASE+0x5000) -#define REG_IOPCON (REG_BASE+0x5004) -#define REG_IOPDATA (REG_BASE+0x5008) - -/*********************************/ -/* Interrupt Controller Register */ -/*********************************/ -#define REG_INTMODE (REG_BASE+0x4000) -#define REG_INTPEND (REG_BASE+0x4004) -#define REG_INTMASK (REG_BASE+0x4008) - -#define REG_INTPRI0 (REG_BASE+0x400c) -#define REG_INTPRI1 (REG_BASE+0x4010) -#define REG_INTPRI2 (REG_BASE+0x4014) -#define REG_INTPRI3 (REG_BASE+0x4018) -#define REG_INTPRI4 (REG_BASE+0x401c) -#define REG_INTPRI5 (REG_BASE+0x4020) -#define REG_INTOFFSET (REG_BASE+0x4024) -#define REG_INTPNDPRI (REG_BASE+0x4028) -#define REG_INTPNDTST (REG_BASE+0x402C) - -/*********************************/ -/* CACHE CONTROL MASKS */ -/*********************************/ -#define CACHE_STALL (0x00000001) -#define CACHE_ENABLE (0x00000002) -#define CACHE_WRITE_BUFF (0x00000004) -#define CACHE_MODE (0x00000030) -#define CACHE_MODE_00 (0x00000000) -#define CACHE_MODE_01 (0x00000010) -#define CACHE_MODE_10 (0x00000020) - -/*********************************/ -/* CACHE RAM BASE ADDRESSES */ -/*********************************/ -#define CACHE_SET0_RAM (0x10000000) -#define CACHE_SET1_RAM (0x10800000) -#define CACHE_TAG_RAM (0x11000000) - -/*********************************/ -/* CACHE_DISABLE MASK */ -/*********************************/ -#define CACHE_DISABLE_MASK (0x04000000) - -#define GET_REG(reg) (*((volatile u32 *)(reg))) -#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val))) -#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask)) -#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask)) -#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val))) -#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF))) -#define GET__U8(reg) (*((volatile u8 *)(reg))) - -#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF)) -#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF) -#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); } -#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); } - -/***********************************/ -/* CLOCK CONSTANTS -- 50 MHz Clock */ -/***********************************/ - -#define CLK_FREQ_MHZ (50) -#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */ -#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */ - -/*********************************************************/ -/* TIMER MODE REGISTER */ -/*********************************************************/ -#define TM0_RUN 0x01 /* Timer 0 enable */ -#define TM0_TOGGLE 0x02 /* 0, interval mode */ -#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */ -#define TM1_RUN 0x08 /* Timer 1 enable */ -#define TM1_TOGGLE 0x10 /* 0, interval mode */ -#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */ - - -/*********************************/ -/* INTERRUPT SOURCES */ -/*********************************/ -#define INT_EXTINT0 0 -#define INT_EXTINT1 1 -#define INT_EXTINT2 2 -#define INT_EXTINT3 3 -#define INT_UARTTX0 4 -#define INT_UARTRX0 5 -#define INT_UARTTX1 6 -#define INT_UARTRX1 7 -#define INT_GDMA0 8 -#define INT_GDMA1 9 -#define INT_TIMER0 10 -#define INT_TIMER1 11 -#define INT_HDLCTXA 12 -#define INT_HDLCRXA 13 -#define INT_HDLCTXB 14 -#define INT_HDLCRXB 15 -#define INT_BDMATX 16 -#define INT_BDMARX 17 -#define INT_MACTX 18 -#define INT_MACRX 19 -#define INT_IIC 20 -#define INT_GLOBAL 21 -#define N_IRQS (21) - -#ifndef __ASSEMBLER__ -struct _irq_handler { - void *m_data; - void (*m_func)( void *data); -}; - -#endif - -#endif /* __S3C4510_h */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 51af313f51..8151d2e0f4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -36,7 +36,6 @@ COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o -COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_S5P) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o diff --git a/drivers/serial/s3c4510b_uart.c b/drivers/serial/s3c4510b_uart.c deleted file mode 100644 index c460229e05..0000000000 --- a/drivers/serial/s3c4510b_uart.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * MODULE: $Id:$ - * Description: UART/Serial interface for Samsung S3C4510B SoC - * Runtime Env: ARM7TDMI - * Change History: - * 03-02-04 Create (Curt Brune) curt@cucy.com - * - */ - -#include - -#include -#include "s3c4510b_uart.h" - -DECLARE_GLOBAL_DATA_PTR; - -static UART *uart; - -/* flush serial input queue. returns 0 on success or negative error - * number otherwise - */ -static int serial_flush_input(void) -{ - volatile u32 tmp; - - /* keep on reading as long as the receiver is not empty */ - while( uart->m_stat.bf.rxReady) { - tmp = uart->m_rx; - } - - return 0; -} - - -/* flush output queue. returns 0 on success or negative error number - * otherwise - */ -static int serial_flush_output(void) -{ - /* wait until the transmitter is no longer busy */ - while( !uart->m_stat.bf.txBufEmpty); - - return 0; -} - - -static void s3c4510b_serial_setbrg(void) -{ - UART_LINE_CTRL ulctrl; - UART_CTRL uctrl; - UART_BAUD_DIV ubd; - - serial_flush_output(); - serial_flush_input(); - - /* control register */ - uctrl.ui = 0x0; - uctrl.bf.rxMode = 0x1; - uctrl.bf.rxIrq = 0x0; - uctrl.bf.txMode = 0x1; - uctrl.bf.DSR = 0x0; - uctrl.bf.sendBreak = 0x0; - uctrl.bf.loopBack = 0x0; - uart->m_ctrl.ui = uctrl.ui; - - /* line control register */ - ulctrl.ui = 0x0; - ulctrl.bf.wordLen = 0x3; /* 8 bit data */ - ulctrl.bf.nStop = 0x0; /* 1 stop bit */ - ulctrl.bf.parity = 0x0; /* no parity */ - ulctrl.bf.clk = 0x0; /* internal clock */ - ulctrl.bf.infra_red = 0x0; /* no infra_red */ - uart->m_lineCtrl.ui = ulctrl.ui; - - ubd.ui = 0x0; - - /* see table on page 10-15 in SAMSUNG S3C4510B manual */ - /* get correct divisor */ - switch(gd->baudrate) { - case 1200: ubd.bf.cnt0 = 1301; break; - case 2400: ubd.bf.cnt0 = 650; break; - case 4800: ubd.bf.cnt0 = 324; break; - case 9600: ubd.bf.cnt0 = 162; break; - case 19200: ubd.bf.cnt0 = 80; break; - case 38400: ubd.bf.cnt0 = 40; break; - case 57600: ubd.bf.cnt0 = 26; break; - case 115200: ubd.bf.cnt0 = 13; break; - } - - uart->m_baudDiv.ui = ubd.ui; - uart->m_baudCnt = 0x0; - uart->m_baudClk = 0x0; - -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int s3c4510b_serial_init(void) -{ - -#if CONFIG_SERIAL1 == 1 - uart = (UART *)UART0_BASE; -#elif CONFIG_SERIAL1 == 2 - uart = (UART *)UART1_BASE; -#else -#error CONFIG_SERIAL1 not equal to 1 or 2 -#endif - - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void s3c4510_serial_putc(const char c) -{ - /* wait for room in the transmit FIFO */ - while( !uart->m_stat.bf.txBufEmpty); - - uart->m_tx = c; - - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n') - serial_putc('\r'); -} - -/* - * Test if an input byte is ready from the serial port. Returns non-zero on - * success, 0 otherwise. - */ -static int s3c4510b_serial_tstc(void) -{ - return uart->m_stat.bf.rxReady; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c4510b_serial_getc(void) -{ - int rv; - - for(;;) { - rv = serial_tstc(); - - if (rv) { - return uart->m_rx & 0xFF; - } - } -} - -static void s3c4510b_serial_puts(const char *s) -{ - default_serial_puts(s); - - /* busy wait for tx complete */ - while (!uart->m_stat.bf.txComplete); - - /* clear break */ - uart->m_ctrl.bf.sendBreak = 0; - -} - -static struct serial_device s3c4510b_serial_drv = { - .name = "s3c4510b_serial", - .start = s3c4510b_serial_init, - .stop = NULL, - .setbrg = s3c4510b_serial_setbrg, - .putc = s3c4510b_serial_putc, - .puts = s3c4510b_serial_puts, - .getc = s3c4510b_serial_getc, - .tstc = s3c4510b_serial_tstc, -}; - -void s3c4510b_serial_initialize(void) -{ - serial_register(&s3c4510b_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &s3c4510b_serial_drv; -} diff --git a/drivers/serial/s3c4510b_uart.h b/drivers/serial/s3c4510b_uart.h deleted file mode 100644 index b06c76d84a..0000000000 --- a/drivers/serial/s3c4510b_uart.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __UART_H -#define __UART_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Description: S3C4510B UART register layout - */ - -/* UART LINE CONTROL register */ -typedef struct __BF_UART_LINE_CTRL { - u32 wordLen: 2; - u32 nStop: 1; - u32 parity: 3; - u32 clk: 1; - u32 infra_red: 1; - u32 unused:24; -} BF_UART_LINE_CTRL; - -typedef union _UART_LINE_CTRL { - u32 ui; - BF_UART_LINE_CTRL bf; -} UART_LINE_CTRL; - -/* UART CONTROL register */ -typedef struct __BF_UART_CTRL { - u32 rxMode: 2; - u32 rxIrq: 1; - u32 txMode: 2; - u32 DSR: 1; - u32 sendBreak: 1; - u32 loopBack: 1; - u32 unused:24; -} BF_UART_CTRL; - -typedef union _UART_CTRL { - u32 ui; - BF_UART_CTRL bf; -} UART_CTRL; - -/* UART STATUS register */ -typedef struct __BF_UART_STAT { - u32 overrun: 1; - u32 parity: 1; - u32 frame: 1; - u32 breakIrq: 1; - u32 DTR: 1; - u32 rxReady: 1; - u32 txBufEmpty: 1; - u32 txComplete: 1; - u32 unused:24; -} BF_UART_STAT; - -typedef union _UART_STAT { - u32 ui; - BF_UART_STAT bf; -} UART_STAT; - -/* UART BAUD_DIV register */ -typedef struct __BF_UART_BAUD_DIV { - u32 cnt1: 4; - u32 cnt0:12; - u32 unused:16; -} BF_UART_BAUD_DIV; - -typedef union _UART_BAUD_DIV { - u32 ui; - BF_UART_BAUD_DIV bf; -} UART_BAUD_DIV; - -/* UART register block */ -typedef struct __UART { - volatile UART_LINE_CTRL m_lineCtrl; - volatile UART_CTRL m_ctrl; - volatile UART_STAT m_stat; - volatile u32 m_tx; - volatile u32 m_rx; - volatile UART_BAUD_DIV m_baudDiv; - volatile u32 m_baudCnt; - volatile u32 m_baudClk; -} UART; - -#define NL 0x0A -#define CR 0x0D -#define BSP 0x08 -#define ESC 0x1B -#define CTRLZ 0x1A -#define RUBOUT 0x7F - -#endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 1d68f5568d..44bb089dee 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -96,7 +96,6 @@ serial_initfunc(lpc32xx_serial_initialize); serial_initfunc(mcf_serial_initialize); serial_initfunc(ns9750_serial_initialize); serial_initfunc(oc_serial_initialize); -serial_initfunc(s3c4510b_serial_initialize); serial_initfunc(s3c64xx_serial_initialize); serial_initfunc(sandbox_serial_initialize); serial_initfunc(clps7111_serial_initialize); @@ -193,7 +192,6 @@ void serial_initialize(void) mcf_serial_initialize(); ns9750_serial_initialize(); oc_serial_initialize(); - s3c4510b_serial_initialize(); s3c64xx_serial_initialize(); sandbox_serial_initialize(); clps7111_serial_initialize(); -- cgit v1.2.3 From b411eb30f5ccca861b5aeee6b8e5880d4e4aea6b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:10 +0000 Subject: arm: Remove support for NETARM This stuff has been rotting in the tree for a while now. Remove it. Signed-off-by: Marek Vasut --- arch/arm/cpu/arm720t/cpu.c | 9 +- arch/arm/cpu/arm720t/interrupts.c | 83 +---- arch/arm/cpu/arm720t/start.S | 75 +---- arch/arm/include/asm/arch-arm720t/hardware.h | 4 +- .../include/asm/arch-arm720t/netarm_dma_module.h | 182 ----------- .../include/asm/arch-arm720t/netarm_eni_module.h | 121 ------- .../include/asm/arch-arm720t/netarm_eth_module.h | 160 ---------- .../include/asm/arch-arm720t/netarm_gen_module.h | 186 ----------- .../include/asm/arch-arm720t/netarm_mem_module.h | 184 ----------- .../include/asm/arch-arm720t/netarm_registers.h | 96 ------ .../include/asm/arch-arm720t/netarm_ser_module.h | 347 -------------------- drivers/net/Makefile | 1 - drivers/net/netarm_eth.c | 352 --------------------- drivers/net/netarm_eth.h | 42 --- drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_netarm.c | 204 ------------ 17 files changed, 10 insertions(+), 2039 deletions(-) delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_dma_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_eni_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_eth_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_gen_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_mem_module.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_registers.h delete mode 100644 arch/arm/include/asm/arch-arm720t/netarm_ser_module.h delete mode 100644 drivers/net/netarm_eth.c delete mode 100644 drivers/net/netarm_eth.h delete mode 100644 drivers/serial/serial_netarm.c diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 864720fcdf..85c1a2c7f0 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -36,6 +36,10 @@ #include #include +#if !defined(CONFIG_INTEGRATOR) || !defined(CONFIG_ARCH_INTEGRATOR) +#error No cleanup_before_linux() defined for this CPU type +#endif + int cleanup_before_linux (void) { /* @@ -46,10 +50,7 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */ -#if defined(CONFIG_NETARM) - disable_interrupts (); - /* Nothing more needed */ -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_TEGRA) /* No cleanup before linux for tegra as yet */ diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index e3b59fef09..998efd844a 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -31,20 +31,11 @@ #include #include -#ifndef CONFIG_NETARM /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff) -#else -#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) -#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) -#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS)) -#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK -#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) -#endif - #ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) { @@ -65,18 +56,7 @@ static ulong lastdec; int timer_init (void) { -#if defined(CONFIG_NETARM) - /* disable all interrupts */ - IRQEN = 0; - - /* operate timer 2 in non-prescale mode */ - TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) | - NETARM_GEN_TCTL_ENABLE | - NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); - - /* set timer 2 counter */ - lastdec = TIMER_LOAD_VAL; -#elif defined(CONFIG_TEGRA) +#if defined(CONFIG_TEGRA) /* No timer routines for tegra as yet */ lastdec = 0; #else @@ -94,66 +74,7 @@ int timer_init (void) */ -#if defined(CONFIG_NETARM) - -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -void __udelay (unsigned long usec) -{ - ulong tmo; - - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - - tmo += get_timer (0); - - while (get_timer_masked () < tmo) -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No timer routines for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_TEGRA) /* No timer routines for tegra as yet */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 3a90e0d775..45c8f0a5ea 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -284,58 +284,7 @@ _dynsym_start_ofs: */ cpu_init_crit: -#if defined(CONFIG_NETARM) - /* - * prior to software reset : need to set pin PORTC4 to be *HRESET - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ - NETARM_GEN_PORT_DIR(0x10)) - str r1, [r0, #+NETARM_GEN_PORTC] - /* - * software reset : see HW Ref. Guide 8.2.4 : Software Service register - * for an explanation of this process - */ - ldr r0, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] - /* - * setup PLL and System Config - */ - ldr r0, =NETARM_GEN_MODULE_BASE - - ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ - NETARM_GEN_SYS_CFG_BUSFULL | \ - NETARM_GEN_SYS_CFG_USER_EN | \ - NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ - NETARM_GEN_SYS_CFG_BUSARB_INT | \ - NETARM_GEN_SYS_CFG_BUSMON_EN ) - - str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] - -#ifndef CONFIG_NETARM_PLL_BYPASS - ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ - NETARM_GEN_PLL_CTL_POLTST_DEF | \ - NETARM_GEN_PLL_CTL_INDIV(1) | \ - NETARM_GEN_PLL_CTL_ICP_DEF | \ - NETARM_GEN_PLL_CTL_OUTDIV(2) ) - str r1, [r0, #+NETARM_GEN_PLL_CONTROL] -#endif - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - mov r1, #0 - ldr r0, =NETARM_GEN_MODULE_BASE - str r1, [r0, #+NETARM_GEN_INTR_ENABLE] - -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific initialisation for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_TEGRA) /* No cpu_init_crit for tegra as yet */ @@ -533,27 +482,7 @@ fiq: #endif #endif /* CONFIG_SPL_BUILD */ -#if defined(CONFIG_NETARM) - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, =NETARM_MEM_MODULE_BASE - ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] - ldr r1, =0xFFFFF000 - and r0, r1, r0 - ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE) - add r0, r1, r0 - ldr r4, =NETARM_GEN_MODULE_BASE - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETA - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - ldr r1, =NETARM_GEN_SW_SVC_RESETB - str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] - mov pc, r0 -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_TEGRA) /* No specific reset actions for tegra as yet */ diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h index 0a357b1e0a..0a766108a6 100644 --- a/arch/arm/include/asm/arch-arm720t/hardware.h +++ b/arch/arm/include/asm/arch-arm720t/hardware.h @@ -24,9 +24,7 @@ * MA 02111-1307 USA */ -#if defined(CONFIG_NETARM) -#include -#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* include IntegratorCP/CM720T specific hardware file if there was one */ #else #error No hardware file defined for this configuration diff --git a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h deleted file mode 100644 index 328eaf0da9..0000000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h +++ /dev/null @@ -1,182 +0,0 @@ -/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * David Smith - */ - -#ifndef __NETARM_DMA_MODULE_REGISTERS_H -#define __NETARM_DMA_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_DMA_MODULE_BASE (0xFF900000) - -#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c))) - -#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00) -#define NETARM_DMA1A_CONTROL (0x10) -#define NETARM_DMA1A_STATUS (0x14) -#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20) -#define NETARM_DMA1B_CONTROL (0x30) -#define NETARM_DMA1B_STATUS (0x34) -#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40) -#define NETARM_DMA1C_CONTROL (0x50) -#define NETARM_DMA1C_STATUS (0x54) -#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60) -#define NETARM_DMA1D_CONTROL (0x70) -#define NETARM_DMA1D_STATUS (0x74) - -#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80) -#define NETARM_DMA2_CONTROL (0x90) -#define NETARM_DMA2_STATUS (0x94) - -#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0) -#define NETARM_DMA3_CONTROL (0xB0) -#define NETARM_DMA3_STATUS (0xB4) - -#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0) -#define NETARM_DMA4_CONTROL (0xD0) -#define NETARM_DMA4_STATUS (0xD4) - -#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0) -#define NETARM_DMA5_CONTROL (0xF0) -#define NETARM_DMA5_STATUS (0xF4) - -#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100) -#define NETARM_DMA6_CONTROL (0x110) -#define NETARM_DMA6_STATUS (0x114) - -#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120) -#define NETARM_DMA7_CONTROL (0x130) -#define NETARM_DMA7_STATUS (0x134) - -#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140) -#define NETARM_DMA8_CONTROL (0x150) -#define NETARM_DMA8_STATUS (0x154) - -#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160) -#define NETARM_DMA9_CONTROL (0x170) -#define NETARM_DMA9_STATUS (0x174) - -#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180) -#define NETARM_DMA10_CONTROL (0x190) -#define NETARM_DMA10_STATUS (0x194) - -/* select bitfield defintions */ - -/* DMA Control Register ( 0xFF90_0XX0 ) */ - -#define NETARM_DMA_CTL_ENABLE (0x80000000) - -#define NETARM_DMA_CTL_ABORT (0x40000000) - -#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000) -#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000) -#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000) -#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000) - -#define NETARM_DMA_CTL_BUS_MASK (0x30000000) - -#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000) -#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000) -#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000) - -#define NETARM_DMA_CTL_BURST_NONE (0x00000000) -#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000) -#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000) - -#define NETARM_DMA_CTL_BURST_MASK (0x03000000) - -#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000) - -#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000) - -/* these apply only to ext xfers on DMA 3 or 4 */ - -#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000) - -#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000) -#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000) -#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000) - -#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00) -#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF) - -/* DMA Status Register ( 0xFF90_0XX4 ) */ - -#define NETARM_DMA_STAT_NC_INTPEN (0x80000000) -#define NETARM_DMA_STAT_EC_INTPEN (0x40000000) -#define NETARM_DMA_STAT_NR_INTPEN (0x20000000) -#define NETARM_DMA_STAT_CA_INTPEN (0x10000000) -#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000) - -#define NETARM_DMA_STAT_NC_INT_EN (0x00800000) -#define NETARM_DMA_STAT_EC_INT_EN (0x00400000) -#define NETARM_DMA_STAT_NR_INT_EN (0x00200000) -#define NETARM_DMA_STAT_CA_INT_EN (0x00100000) -#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000) - -#define NETARM_DMA_STAT_WRAP (0x00080000) -#define NETARM_DMA_STAT_IDONE (0x00040000) -#define NETARM_DMA_STAT_LAST (0x00020000) -#define NETARM_DMA_STAT_FULL (0x00010000) - -#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF) - -/* DMA Buffer Descriptor Word 0 bitfields. */ - -#define NETARM_DMA_BD0_WRAP (0x80000000) -#define NETARM_DMA_BD0_IDONE (0x40000000) -#define NETARM_DMA_BD0_LAST (0x20000000) -#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF) - -/* DMA Buffer Descriptor Word 1 bitfields. */ - -#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000) -#define NETARM_DMA_BD1_FULL (0x00008000) -#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF) - -#ifndef __ASSEMBLER__ - -typedef struct __NETARM_DMA_Buff_Desc_FlyBy -{ - unsigned int word0; - unsigned int word1; -} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ; - -typedef struct __NETARM_DMA_Buff_Desc_M_to_M -{ - unsigned int word0; - unsigned int word1; - unsigned int word2; - unsigned int word3; -} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ; - -#endif - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h deleted file mode 100644 index 317b354513..0000000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_eni_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : David Smith - */ - -#ifndef __NETARM_ENI_MODULE_REGISTERS_H -#define __NETARM_ENI_MODULE_REGISTERS_H - -/* ENI unit register offsets */ - -/* #ifdef CONFIG_ARCH_NETARM */ -#define NETARM_ENI_MODULE_BASE (0xFFA00000) -/* #endif / * CONFIG_ARCH_NETARM */ - -#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c))) -#define get_eni_ctl_reg_addr(minor) \ - (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor)) - -#define NETARM_ENI_GENERAL_CONTROL (0x00) -#define NETARM_ENI_STATUS_CONTROL (0x04) -#define NETARM_ENI_FIFO_MODE_DATA (0x08) - -#define NETARM_ENI_1284_PORT1_CONTROL (0x10) -#define NETARM_ENI_1284_PORT2_CONTROL (0x14) -#define NETARM_ENI_1284_PORT3_CONTROL (0x18) -#define NETARM_ENI_1284_PORT4_CONTROL (0x1c) - -#define NETARM_ENI_1284_CHANNEL1_DATA (0x20) -#define NETARM_ENI_1284_CHANNEL2_DATA (0x24) -#define NETARM_ENI_1284_CHANNEL3_DATA (0x28) -#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c) - -#define NETARM_ENI_ENI_CONTROL (0x30) -#define NETARM_ENI_ENI_PULSED_INTR (0x34) -#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38) -#define NETARM_ENI_ENI_SHARED (0x3c) - -/* select bitfield defintions */ - -/* General Control Register (0xFFA0_0000) */ - -#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001) -#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004) -#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005) -#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006) -#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007) - -#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007) - -/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014, - 0xFFA0_0018, 0xFFA0_001c) */ - -#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000) -#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000) -#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000) -#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000) -#define NETARM_ENI_1284PC_ECP_MODE (0x08000000) -#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000) - -#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */ -#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */ -#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000) - -#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000) -#define NETARM_ENI_1284PC_FAST_MODE (0x00400000) -#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000) - -#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000) -#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000) -#define NETARM_ENI_1284PC_INIT (0x00020000) -#define NETARM_ENI_1284PC_HSELECT (0x00010000) -#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000) -#define NETARM_ENI_1284PC_EPP_MODE (0x00004000) -#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000) -#define NETARM_ENI_1284PC_IBR (0x00001000) - -#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400) -#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800) -#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00) -#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000) - -#define NETARM_ENI_1284PC_RBCC (0x00000200) -#define NETARM_ENI_1284PC_RBCT (0x00000100) -#define NETARM_ENI_1284PC_ACK (0x00000080) -#define NETARM_ENI_1284PC_FIFO_E (0x00000040) -#define NETARM_ENI_1284PC_OBE (0x00000020) -#define NETARM_ENI_1284PC_ACK_INT (0x00000010) -#define NETARM_ENI_1284PC_BUSY (0x00000008) -#define NETARM_ENI_1284PC_PE (0x00000004) -#define NETARM_ENI_1284PC_PSELECT (0x00000002) -#define NETARM_ENI_1284PC_FAULT (0x00000001) - -#endif /* __NETARM_ENI_MODULE_REGISTERS_H */ diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h deleted file mode 100644 index 8f2f36981a..0000000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_eth_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Jackie Smith Cashion - * David Smith - */ - -#ifndef __NETARM_ETH_MODULE_REGISTERS_H -#define __NETARM_ETH_MODULE_REGISTERS_H - -/* ETH unit register offsets */ - -#define NETARM_ETH_MODULE_BASE (0xFF800000) - -#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) - -#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ -#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ -#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ -#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ -#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ -#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ - -#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ -#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ -#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ -#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG - Gap Timer Reg */ -#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back - IPG Gap Timer Reg */ -#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ -#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ -#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ -#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ -#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ -#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ -#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ -#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ -#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ -#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ -#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ -#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral - Counter */ -#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ -#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address - Filter Reg */ -#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address - Reg */ -#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) -#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) -#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ -#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) -#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) -#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) - -/* select bitfield defintions */ - -/* Ethernet General Control Register (0xFF80_0000) */ - -#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ -#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ -#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ -#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ -#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water - Mark. Start transmit - when FIFO is 50% - full. */ -#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer - Descriptor Format */ - -/* Ethernet General Status Register (0xFF80_0004) */ - -#define NETARM_ETH_GST_RXFDB (0x30000000) -#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register - Ready */ -#define NETARM_ETH_GST_RXFIFOH (0x04000000) -#define NETARM_ETH_GST_RXBR (0x02000000) -#define NETARM_ETH_GST_RXSKIP (0x01000000) - -#define NETARM_ETH_GST_TXBC (0x00020000) - - -/* Ethernet Transmit Status Register (0xFF80_0010) */ - -#define NETARM_ETH_TXSTAT_TXOK (0x00008000) - - -/* Ethernet Receive Status Register (0xFF80_0014) */ - -#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) -#define NETARM_ETH_RXSTAT_RXOK (0x00002000) - - -/* PCS Configuration Register (0xFF80_0408) */ - -#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ -#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ -#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ -#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ - -/* STL Configuration Register (0xFF80_0410) */ - -#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ -#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ - -/* MAC Configuration Register (0xFF80_0400) */ - -#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit - Frame Sizes */ -#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames - to 64 Bytes */ -#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit - Frames */ - -/* MII (PHY) Command Register (0xFF80_0540) */ - -#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ - -/* MII Indicators Register (0xFF80_0550) */ - -#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with - Read/Write */ - -/* SAL Station Address Filter Register (0xFF80_05C0) */ - -#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ -#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast - Packets */ -#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets - using Hash Table */ -#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast - Packets */ - - -#endif /* __NETARM_GEN_MODULE_REGISTERS_H */ diff --git a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h deleted file mode 100644 index 13656a3ad2..0000000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_gen_module.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NETARM_GEN_MODULE_REGISTERS_H -#define __NETARM_GEN_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_GEN_MODULE_BASE (0xFFB00000) - -#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) - -#define NETARM_GEN_SYSTEM_CONTROL (0x00) -#define NETARM_GEN_STATUS_CONTROL (0x04) -#define NETARM_GEN_PLL_CONTROL (0x08) -#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) - -#define NETARM_GEN_TIMER1_CONTROL (0x10) -#define NETARM_GEN_TIMER1_STATUS (0x14) -#define NETARM_GEN_TIMER2_CONTROL (0x18) -#define NETARM_GEN_TIMER2_STATUS (0x1c) - -#define NETARM_GEN_PORTA (0x20) -#ifndef CONFIG_NETARM_NS7520 -#define NETARM_GEN_PORTB (0x24) -#endif -#define NETARM_GEN_PORTC (0x28) - -#define NETARM_GEN_INTR_ENABLE (0x30) -#define NETARM_GEN_INTR_ENABLE_SET (0x34) -#define NETARM_GEN_INTR_ENABLE_CLR (0x38) -#define NETARM_GEN_INTR_STATUS_EN (0x34) -#define NETARM_GEN_INTR_STATUS_RAW (0x38) - -#define NETARM_GEN_CACHE_CONTROL1 (0x40) -#define NETARM_GEN_CACHE_CONTROL2 (0x44) - -/* select bitfield definitions */ - -/* System Control Register ( 0xFFB0_0000 ) */ - -#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) -#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) - -#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) -#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) -#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) - -#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) - -#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) -#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) -#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) -#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) -#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) -#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) -#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) -#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) - -#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) -#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) -#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) -#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) -#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) - -#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) -#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) - -#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) -#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) - -#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) - -#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) - -#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) - -#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) - -#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) - -#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) - -/* PLL Control Register ( 0xFFB0_0008 ) */ - -#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) - -#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ - NETARM_GEN_PLL_CTL_PLLCNT_MASK) - -/* Defaults for POLTST and ICP Fields in PLL CTL */ -#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) -#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) -#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) -#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) - - -/* Software Service Register ( 0xFFB0_000C ) */ - -#define NETARM_GEN_SW_SVC_RESETA (0x123) -#define NETARM_GEN_SW_SVC_RESETB (0x321) - -/* PORT C Register ( 0xFFB0_0028 ) */ - -#ifndef CONFIG_NETARM_NS7520 -#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) -#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) -#else -#define NETARM_GEN_PORT_MODE(x) ((x)<<24) -#define NETARM_GEN_PORT_DIR(x) ((x)<<16) -#define NETARM_GEN_PORT_CSF(x) ((x)<<8) -#endif - -/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ - -#define NETARM_GEN_TCTL_ENABLE (0x80000000) -#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) - -#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) -#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) - -#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) -#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) - -#define NETARM_GEN_TSTAT_INTPEN (0x40000000) -#if ~defined(CONFIG_NETARM_NS7520) -#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) -#else -#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) -#endif - -/* prescale to msecs conversion */ - -#if !defined(CONFIG_NETARM_PLL_BYPASS) -#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ - NETARM_GEN_TSTAT_CTC_MASK ) + \ - 1 ) ) / (NETARM_XTAL_FREQ/1000) ) - -#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ - NETARM_GEN_TSTAT_CTC_MASK ) | \ - NETARM_GEN_TCTL_USE_PRESCALE ) - -#else -#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ - NETARM_GEN_TSTAT_CTC_MASK ) + \ - 1 ) ) / (NETARM_XTAL_FREQ/1000) ) - -#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ - NETARM_GEN_TSTAT_CTC_MASK ) | \ - NETARM_GEN_TCTL_USE_PRESCALE ) -#endif - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h deleted file mode 100644 index c650c3b004..0000000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * include/asm-armnommu/arch-netarm/netarm_mem_module.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NETARM_MEM_MODULE_REGISTERS_H -#define __NETARM_MEM_MODULE_REGISTERS_H - -/* GEN unit register offsets */ - -#define NETARM_MEM_MODULE_BASE (0xFFC00000) - -#define NETARM_MEM_MODULE_CONFIG (0x00) -#define NETARM_MEM_CS0_BASE_ADDR (0x10) -#define NETARM_MEM_CS0_OPTIONS (0x14) -#define NETARM_MEM_CS1_BASE_ADDR (0x20) -#define NETARM_MEM_CS1_OPTIONS (0x24) -#define NETARM_MEM_CS2_BASE_ADDR (0x30) -#define NETARM_MEM_CS2_OPTIONS (0x34) -#define NETARM_MEM_CS3_BASE_ADDR (0x40) -#define NETARM_MEM_CS3_OPTIONS (0x44) -#define NETARM_MEM_CS4_BASE_ADDR (0x50) -#define NETARM_MEM_CS4_OPTIONS (0x54) - -/* select bitfield defintions */ - -/* Module Configuration Register ( 0xFFC0_0000 ) */ - -#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000) -#define NETARM_MEM_CFG_REFRESH_EN (0x00800000) - -#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000) -#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000) -#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000) -#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000) - -#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000) - -#define NETARM_MEM_CFG_A27_ADDR (0x00080000) -#define NETARM_MEM_CFG_A27_CS0OE (0x00000000) - -#define NETARM_MEM_CFG_A26_ADDR (0x00040000) -#define NETARM_MEM_CFG_A26_CS0WE (0x00000000) - -#define NETARM_MEM_CFG_A25_ADDR (0x00020000) -#define NETARM_MEM_CFG_A25_BLAST (0x00000000) - -#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000) - - -/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ -/* the expression will round down, so make sure to reverse it to verify */ -/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */ -/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */ - -#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ - (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \ - ) - (1) ) << (24))) - -#if 0 -/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ -/* the expression will round down, so make sure to reverse it toverify */ -/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */ - -#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ - (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \ - ) - (1) ) << (24))) -#endif - -/* Base Address Registers (0xFFC0_00X0) */ - -#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000) - -/* macro to define base */ - -#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) - -#define NETARM_MEM_BAR_DRAM_FP (0x00000000) -#define NETARM_MEM_BAR_DRAM_EDO (0x00000100) -#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200) - -#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000) -#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080) - -#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000) -#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020) - -#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010) - -#define NETARM_MEM_BAR_DRAM_SEL (0x00000008) - -#define NETARM_MEM_BAR_BURST_EN (0x00000004) - -#define NETARM_MEM_BAR_WRT_PROT (0x00000002) - -#define NETARM_MEM_BAR_VALID (0x00000001) - -/* Option Registers (0xFFC0_00X4) */ - -/* macro to define which bits of the base are significant */ - -#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) - -#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00) - -#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK ) - -#define NETARM_MEM_OPT_BCYC_1 (0x00000000) -#define NETARM_MEM_OPT_BCYC_2 (0x00000040) -#define NETARM_MEM_OPT_BCYC_3 (0x00000080) -#define NETARM_MEM_OPT_BCYC_4 (0x000000C0) - -#define NETARM_MEM_OPT_BSIZE_2 (0x00000000) -#define NETARM_MEM_OPT_BSIZE_4 (0x00000010) -#define NETARM_MEM_OPT_BSIZE_8 (0x00000020) -#define NETARM_MEM_OPT_BSIZE_16 (0x00000030) - -#define NETARM_MEM_OPT_32BIT (0x00000000) -#define NETARM_MEM_OPT_16BIT (0x00000004) -#define NETARM_MEM_OPT_8BIT (0x00000008) -#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C) - -#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C) - -#define NETARM_MEM_OPT_READ_ASYNC (0x00000000) -#define NETARM_MEM_OPT_READ_SYNC (0x00000002) - -#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) -#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) - -#ifdef CONFIG_NETARM_NS7520 -/* The NS7520 has a second options register for each chip select */ -#define NETARM_MEM_CS0_OPTIONS_B (0x18) -#define NETARM_MEM_CS1_OPTIONS_B (0x28) -#define NETARM_MEM_CS2_OPTIONS_B (0x38) -#define NETARM_MEM_CS3_OPTIONS_B (0x48) -#define NETARM_MEM_CS4_OPTIONS_B (0x58) - -/* Option B Registers (0xFFC0_00x8) */ -#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) -#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) -#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) -#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) -#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) - -#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) -#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) -#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) -#endif - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h deleted file mode 100644 index fa8812879a..0000000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_registers.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * linux/include/asm-arm/arch-netarm/netarm_registers.h - * - * Copyright (C) 2005 - * Art Shipkowski, Videon Central, Inc., - * - * Copyright (C) 2000, 2001 NETsilicon, Inc. - * Copyright (C) 2000, 2001 WireSpeed Communications Corporation - * - * This software is copyrighted by WireSpeed. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall WireSpeed - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * - * Modified to support NS7520 by Art Shipkowski. - */ - -#ifndef __NET_ARM_REGISTERS_H -#define __NET_ARM_REGISTERS_H - -#include - -/* fundamental constants : */ -/* the input crystal/clock frequency ( in Hz ) */ -#define NETARM_XTAL_FREQ_25MHz (18432000) -#define NETARM_XTAL_FREQ_33MHz (23698000) -#define NETARM_XTAL_FREQ_48MHz (48000000) -#define NETARM_XTAL_FREQ_55MHz (55000000) -#define NETARM_XTAL_FREQ_EMLIN1 (20000000) - -/* the frequency of SYS_CLK */ -#if defined(CONFIG_NETARM_EMLIN) - -/* EMLIN board: 33 MHz (exp.) */ -#define NETARM_PLL_COUNT_VAL 6 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET40_REV2) - -/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ -#define NETARM_PLL_COUNT_VAL 6 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET40_REV4) - -/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with - NETARM_XTAL_FREQ_25MHz) 4 */ -#define NETARM_PLL_COUNT_VAL 4 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#elif defined(CONFIG_NETARM_NET50) - -/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ -#define NETARM_PLL_COUNT_VAL 8 -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz - -#else /* CONFIG_NETARM_NS7520 */ - -#define NETARM_PLL_COUNT_VAL 0 - -#if defined(CONFIG_BOARD_UNC20) -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz -#else -#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz -#endif - -#endif - -/* #include "arm_registers.h" */ -#include -#include -#include -#include -#include -#include - -#endif diff --git a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h deleted file mode 100644 index 6fbae11c8d..0000000000 --- a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * linux/include/asm-arm/arch-netarm/netarm_ser_module.h - * - * Copyright (C) 2000 NETsilicon, Inc. - * Copyright (C) 2000 Red Hat, Inc. - * - * This software is copyrighted by Red Hat. LICENSEE agrees that - * it will not delete this copyright notice, trademarks or protective - * notices from any copy made by LICENSEE. - * - * This software is provided "AS-IS" and any express or implied - * warranties or conditions, including but not limited to any - * implied warranties of merchantability and fitness for a particular - * purpose regarding this software. In no event shall Red Hat - * be liable for any indirect, consequential, or incidental damages, - * loss of profits or revenue, loss of use or data, or interruption - * of business, whether the alleged damages are labeled in contract, - * tort, or indemnity. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * - * author(s) : Joe deBlaquiere - * Clark Williams - */ - -#ifndef __NETARM_SER_MODULE_REGISTERS_H -#define __NETARM_SER_MODULE_REGISTERS_H - -#ifndef __ASSEMBLER__ - -/* (--sub)#include "types.h" */ - -/* serial channel control structure */ -typedef struct { - u32 ctrl_a; - u32 ctrl_b; - u32 status_a; - u32 bitrate; - u32 fifo; - u32 rx_buf_timer; - u32 rx_char_timer; - u32 rx_match; - u32 rx_match_mask; - u32 ctrl_c; - u32 status_b; - u32 status_c; - u32 fifo_last; - u32 unused[3]; -} netarm_serial_channel_t; - -#endif - -/* SER unit register offsets */ - -/* #ifdef CONFIG_ARCH_NETARM */ -#define NETARM_SER_MODULE_BASE (0xFFD00000) -/* #else */ -/* extern serial_channel_t netarm_dummy_registers[]; */ -/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */ -/* #ifndef NETARM_XTAL_FREQ */ -/* #define NETARM_XTAL_FREQ 18432000 */ -/* #endif */ -/* #endif */ - -/* calculate the sysclk value from the pll setting */ -#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \ - ( NETARM_PLL_COUNT_VAL + 3 )) - -#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c])) - -#define NETARM_SER_CH1_CTRL_A (0x00) -#define NETARM_SER_CH1_CTRL_B (0x04) -#define NETARM_SER_CH1_STATUS_A (0x08) -#define NETARM_SER_CH1_BITRATE (0x0C) -#define NETARM_SER_CH1_FIFO (0x10) -#define NETARM_SER_CH1_RX_BUF_TMR (0x14) -#define NETARM_SER_CH1_RX_CHAR_TMR (0x18) -#define NETARM_SER_CH1_RX_MATCH (0x1c) -#define NETARM_SER_CH1_RX_MATCH_MASK (0x20) -#define NETARM_SER_CH1_CTRL_C (0x24) -#define NETARM_SER_CH1_STATUS_B (0x28) -#define NETARM_SER_CH1_STATUS_C (0x2c) -#define NETARM_SER_CH1_FIFO_LAST (0x30) - -#define NETARM_SER_CH2_CTRL_A (0x40) -#define NETARM_SER_CH2_CTRL_B (0x44) -#define NETARM_SER_CH2_STATUS_A (0x48) -#define NETARM_SER_CH2_BITRATE (0x4C) -#define NETARM_SER_CH2_FIFO (0x50) -#define NETARM_SER_CH2_RX_BUF_TMR (0x54) -#define NETARM_SER_CH2_RX_CHAR_TMR (0x58) -#define NETARM_SER_CH2_RX_MATCH (0x5c) -#define NETARM_SER_CH2_RX_MATCH_MASK (0x60) -#define NETARM_SER_CH2_CTRL_C (0x64) -#define NETARM_SER_CH2_STATUS_B (0x68) -#define NETARM_SER_CH2_STATUS_C (0x6c) -#define NETARM_SER_CH2_FIFO_LAST (0x70) - -/* select bitfield defintions */ - -/* Control Register A */ - -#define NETARM_SER_CTLA_ENABLE (0x80000000) -#define NETARM_SER_CTLA_BRK (0x40000000) - -#define NETARM_SER_CTLA_STICKP (0x20000000) - -#define NETARM_SER_CTLA_P_EVEN (0x18000000) -#define NETARM_SER_CTLA_P_ODD (0x08000000) -#define NETARM_SER_CTLA_P_NONE (0x00000000) - -/* if you read the errata, you will find that the STOP bits don't work right */ -#define NETARM_SER_CTLA_2STOP (0x00000000) -#define NETARM_SER_CTLA_3STOP (0x04000000) - -#define NETARM_SER_CTLA_5BITS (0x00000000) -#define NETARM_SER_CTLA_6BITS (0x01000000) -#define NETARM_SER_CTLA_7BITS (0x02000000) -#define NETARM_SER_CTLA_8BITS (0x03000000) - -#define NETARM_SER_CTLA_CTSTX (0x00800000) -#define NETARM_SER_CTLA_RTSRX (0x00400000) - -#define NETARM_SER_CTLA_LOOP_REM (0x00200000) -#define NETARM_SER_CTLA_LOOP_LOC (0x00100000) - -#define NETARM_SER_CTLA_GPIO2 (0x00080000) -#define NETARM_SER_CTLA_GPIO1 (0x00040000) - -#define NETARM_SER_CTLA_DTR_EN (0x00020000) -#define NETARM_SER_CTLA_RTS_EN (0x00010000) - -#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000) -#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000) -#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000) -#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000) -#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800) -#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400) -#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200) -#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100) -#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080) -#define NETARM_SER_CTLA_IE_RX_RI (0x00000040) -#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020) - -#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \ - |NETARM_SER_CTLA_IE_RX_FRMERR \ - |NETARM_SER_CTLA_IE_RX_PARERR \ - |NETARM_SER_CTLA_IE_RX_OVERRUN \ - |NETARM_SER_CTLA_IE_RX_RDY \ - |NETARM_SER_CTLA_IE_RX_HALF \ - |NETARM_SER_CTLA_IE_RX_FULL \ - |NETARM_SER_CTLA_IE_RX_DMAEN \ - |NETARM_SER_CTLA_IE_RX_DCD \ - |NETARM_SER_CTLA_IE_RX_RI \ - |NETARM_SER_CTLA_IE_RX_DSR) - -#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010) -#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008) -#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004) -#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002) -#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001) - -#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \ - |NETARM_SER_CTLA_IE_TX_EMPTY \ - |NETARM_SER_CTLA_IE_TX_HALF \ - |NETARM_SER_CTLA_IE_TX_FULL \ - |NETARM_SER_CTLA_IE_TX_DMAEN) - -/* Control Register B */ - -#define NETARM_SER_CTLB_MATCH1_EN (0x80000000) -#define NETARM_SER_CTLB_MATCH2_EN (0x40000000) -#define NETARM_SER_CTLB_MATCH3_EN (0x20000000) -#define NETARM_SER_CTLB_MATCH4_EN (0x10000000) - -#define NETARM_SER_CTLB_RBGT_EN (0x08000000) -#define NETARM_SER_CTLB_RCGT_EN (0x04000000) - -#define NETARM_SER_CTLB_UART_MODE (0x00000000) -#define NETARM_SER_CTLB_HDLC_MODE (0x00100000) -#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000) -#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000) - -#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000) - -#define NETARM_SER_CTLB_MAM1 (0x00040000) -#define NETARM_SER_CTLB_MAM2 (0x00020000) - -/* Status Register A */ - -#define NETARM_SER_STATA_MATCH1 (0x80000000) -#define NETARM_SER_STATA_MATCH2 (0x40000000) -#define NETARM_SER_STATA_MATCH3 (0x20000000) -#define NETARM_SER_STATA_MATCH4 (0x10000000) - -#define NETARM_SER_STATA_BGAP (0x80000000) -#define NETARM_SER_STATA_CGAP (0x40000000) - -#define NETARM_SER_STATA_RX_1B (0x00100000) -#define NETARM_SER_STATA_RX_2B (0x00200000) -#define NETARM_SER_STATA_RX_3B (0x00300000) -#define NETARM_SER_STATA_RX_4B (0x00000000) - -/* downshifted values */ - -#define NETARM_SER_STATA_RXFDB_1BYTES (0x001) -#define NETARM_SER_STATA_RXFDB_2BYTES (0x002) -#define NETARM_SER_STATA_RXFDB_3BYTES (0x003) -#define NETARM_SER_STATA_RXFDB_4BYTES (0x000) - -#define NETARM_SER_STATA_RXFDB_MASK (0x00300000) -#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \ - >> 20) - -#define NETARM_SER_STATA_DCD (0x00080000) -#define NETARM_SER_STATA_RI (0x00040000) -#define NETARM_SER_STATA_DSR (0x00020000) -#define NETARM_SER_STATA_CTS (0x00010000) - -#define NETARM_SER_STATA_RX_BRK (0x00008000) -#define NETARM_SER_STATA_RX_FRMERR (0x00004000) -#define NETARM_SER_STATA_RX_PARERR (0x00002000) -#define NETARM_SER_STATA_RX_OVERRUN (0x00001000) -#define NETARM_SER_STATA_RX_RDY (0x00000800) -#define NETARM_SER_STATA_RX_HALF (0x00000400) -#define NETARM_SER_STATA_RX_CLOSED (0x00000200) -#define NETARM_SER_STATA_RX_FULL (0x00000100) -#define NETARM_SER_STATA_RX_DCD (0x00000080) -#define NETARM_SER_STATA_RX_RI (0x00000040) -#define NETARM_SER_STATA_RX_DSR (0x00000020) - -#define NETARM_SER_STATA_TX_CTS (0x00000010) -#define NETARM_SER_STATA_TX_RDY (0x00000008) -#define NETARM_SER_STATA_TX_HALF (0x00000004) -#define NETARM_SER_STATA_TX_FULL (0x00000002) -#define NETARM_SER_STATA_TX_DMAEN (0x00000001) - -/* you have to clear all receive signals to get the fifo to move forward */ -#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \ - NETARM_SER_STATA_RX_FRMERR | \ - NETARM_SER_STATA_RX_PARERR | \ - NETARM_SER_STATA_RX_OVERRUN | \ - NETARM_SER_STATA_RX_HALF | \ - NETARM_SER_STATA_RX_CLOSED | \ - NETARM_SER_STATA_RX_FULL | \ - NETARM_SER_STATA_RX_DCD | \ - NETARM_SER_STATA_RX_RI | \ - NETARM_SER_STATA_RX_DSR | \ - NETARM_SER_STATA_TX_CTS ) - -/* Bit Rate Registers */ - -#define NETARM_SER_BR_EN (0x80000000) -#define NETARM_SER_BR_TMODE (0x40000000) - -#define NETARM_SER_BR_RX_CLK_INT (0x00000000) -#define NETARM_SER_BR_RX_CLK_EXT (0x20000000) -#define NETARM_SER_BR_TX_CLK_INT (0x00000000) -#define NETARM_SER_BR_TX_CLK_EXT (0x10000000) - -#define NETARM_SER_BR_RX_CLK_DRV (0x08000000) -#define NETARM_SER_BR_TX_CLK_DRV (0x04000000) - -#define NETARM_SER_BR_CLK_EXT_5 (0x00000000) -#define NETARM_SER_BR_CLK_SYSTEM (0x01000000) -#define NETARM_SER_BR_CLK_OUT1A (0x02000000) -#define NETARM_SER_BR_CLK_OUT2A (0x03000000) - -#define NETARM_SER_BR_TX_CLK_INV (0x00800000) -#define NETARM_SER_BR_RX_CLK_INV (0x00400000) - -/* complete settings assuming system clock input is 18MHz */ - -#define NETARM_SER_BR_MASK (0x000007FF) - -/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */ -/* from section 7.5.4 of HW Ref Guide */ - -/* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_EXT_5 | \ - ( ( ( ( NETARM_XTAL_FREQ / \ - ( x * 10 ) ) - 1 ) / 16 ) & \ - NETARM_SER_BR_MASK ) ) -/* -#else -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_SYSTEM | \ - ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ - ( x * 2 ) ) - 1 ) / 16 ) & \ - NETARM_SER_BR_MASK ) ) -#endif -*/ - -/* Receive Buffer Gap Timer */ - -#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000) -#define NETARM_SER_RX_GAP_MASK (0x00003FFF) - -/* rx gap is a function of bit rate x */ - -/* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -/* -#else -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#endif -*/ - -#if 0 -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ - ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ - NETARM_SER_RX_GAP_MASK ) ) -#endif - -#define MIN_BAUD_RATE 600 -#define MAX_BAUD_RATE 115200 - -/* the default BAUD rate for the BOOTLOADER, there is a separate */ -/* setting in the serial driver */ -#define DEFAULT_BAUD_RATE 9600 -#define NETARM_SER_FIFO_SIZE 32 -#define MIN_GAP 0 - -#endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index e4abac7c8f..786a6567a5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -59,7 +59,6 @@ COBJS-$(CONFIG_MVGBE) += mvgbe.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o -COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o COBJS-$(CONFIG_NETCONSOLE) += netconsole.o COBJS-$(CONFIG_NS8382X) += ns8382x.o COBJS-$(CONFIG_PCNET) += pcnet.o diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c deleted file mode 100644 index 325f16c3a8..0000000000 --- a/drivers/net/netarm_eth.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (C) 2004 IMMS gGmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * author(s): Thomas Elste, - * (some parts derived from uCLinux Netarm Ethernet Driver) - */ - - -#include -#include -#include -#include "netarm_eth.h" -#include - -static int na_mii_poll_busy (void); - -static void na_get_mac_addr (void) -{ - unsigned short p[3]; - char *m_addr; - char ethaddr[20]; - - m_addr = (char *) p; - - p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1); - p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2); - p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3); - - sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - m_addr[0], m_addr[1], - m_addr[2], m_addr[3], m_addr[4], m_addr[5]); - - printf ("HW-MAC Address: %s\n", ethaddr); - - /* set env, todo: check if already an adress is set */ - setenv ("ethaddr", ethaddr); -} - -static void na_mii_write (int reg, int value) -{ - int mii_addr; - - /* Select register */ - mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; - SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); - /* Write value */ - SET_EADDR (NETARM_ETH_MII_WRITE, value); - na_mii_poll_busy (); -} - -static unsigned int na_mii_read (int reg) -{ - int mii_addr, val; - - /* Select register */ - mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; - SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); - /* do one management cycle */ - SET_EADDR (NETARM_ETH_MII_CMD, - GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT); - na_mii_poll_busy (); - /* Return read value */ - val = GET_EADDR (NETARM_ETH_MII_READ); - return val; -} - -static int na_mii_poll_busy (void) -{ - ulong start; - /* arm simple, non interrupt dependent timer */ - start = get_timer(0)); - while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) { - if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { - return 1; - } - } - printf ("na_mii_busy timeout\n"); - return (0); -} - -static int na_mii_identify_phy (void) -{ - int id_reg_a = 0; - - /* get phy id register */ - id_reg_a = na_mii_read (MII_PHY_ID); - - if (id_reg_a == 0x0043) { - /* This must be an Enable or a Lucent LU3X31 PHY chip */ - return 1; - } else if (id_reg_a == 0x0013) { - /* it is an Intel LXT971A */ - return 1; - } - return (0); -} - -static int na_mii_negotiate (void) -{ - int i = 0; - - /* Enable auto-negotiation */ - na_mii_write (MII_PHY_AUTONEGADV, 0x01e1); - /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */ - /* Restart auto-negotiation */ - na_mii_write (MII_PHY_CONTROL, 0x1200); - - /* status register is 0xffff after setting the autoneg restart bit */ - while (na_mii_read (MII_PHY_STATUS) == 0xffff) { - i++; - } - - /* na_mii_read uses the timer already, so we can't use it again for - timeout checking. - Instead we just try some times. - */ - for (i = 0; i < 40000; i++) { - if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) { - return 0; - } - } - /* - printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS)); - */ - return (1); -} - -static unsigned int na_mii_check_speed (void) -{ - unsigned int status; - - /* Read Status register */ - status = na_mii_read (MII_PHY_STATUS); - /* Check link status. If 0, default to 100 Mbps. */ - if ((status & 0x0004) == 0) { - printf ("*Warning* no link detected, set default speed to 100Mbs\n"); - return 1; - } else { - if ((na_mii_read (17) & 0x4000) != 0) { - printf ("100Mbs link detected\n"); - return 1; - } else { - printf ("10Mbs link detected\n"); - return 0; - } - } - return 0; -} - -static int reset_eth (void) -{ - int pt; - ulong start; - - na_get_mac_addr (); - pt = na_mii_identify_phy (); - - /* reset the phy */ - na_mii_write (MII_PHY_CONTROL, 0x8000); - start = get_timer(0); - while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) { - if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { - break; - } - } - if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY) - printf ("phy reset timeout\n"); - - /* set the PCS reg */ - SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M | - NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR); - - na_mii_negotiate (); - na_mii_check_speed (); - - /* Delay 10 millisecond. (Maybe this should be 1 second.) */ - udelay (10000); - - /* Turn receive on. - Enable statistics register autozero on read. - Do not insert MAC address on transmit. - Do not enable special test modes. */ - SET_EADDR (NETARM_ETH_STL_CFG, - (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN)); - - /* Set the inter-packet gap delay to 0.96us for MII. - The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG - Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG - Gap Timer Register should be set to 0x00000C12 for the MII PHY. */ - SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15); - SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12); - - /* Add CRC to end of packets. - Pad packets to minimum length of 64 bytes. - Allow unlimited length transmit packets. - Receive all broadcast packets. - NOTE: Multicast addressing is NOT enabled here currently. */ - SET_EADDR (NETARM_ETH_MAC_CFG, - (NETARM_ETH_MACC_CRCEN | - NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN)); - SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD); - - /* enable fifos */ - SET_EADDR (NETARM_ETH_GEN_CTRL, - (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX)); - - return (0); -} - - -extern int eth_init (bd_t * bd) -{ - reset_eth (); - return 0; -} - -extern void eth_halt (void) -{ - SET_EADDR (NETARM_ETH_GEN_CTRL, 0); -} - -/* Get a data block via Ethernet */ -extern int eth_rx (void) -{ - int i; - unsigned short rxlen; - unsigned int *addr; - unsigned int rxstatus, lastrxlen; - char *pa; - - /* RXBR is 1, data block was received */ - if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0) - return 0; - - /* get status register and the length of received block */ - rxstatus = GET_EADDR (NETARM_ETH_RX_STAT); - rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16; - - if (rxlen == 0) - return 0; - - /* clear RXBR to make fifo available */ - SET_EADDR (NETARM_ETH_GEN_STAT, - GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR); - - /* clear TXBC to make fifo available */ - /* According to NETARM50 data manual you just have to clear - RXBR but that has no effect. Only after clearing TXBC the - Fifo becomes readable. */ - SET_EADDR (NETARM_ETH_GEN_STAT, - GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC); - - addr = (unsigned int *) NetRxPackets[0]; - pa = (char *) NetRxPackets[0]; - - /* read the fifo */ - for (i = 0; i < rxlen / 4; i++) { - *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); - addr++; - } - - if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) { - /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ - lastrxlen = - (GET_EADDR (NETARM_ETH_GEN_STAT) & - NETARM_ETH_GST_RXFDB) >> 28; - *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); - switch (lastrxlen) { - case 1: - *addr &= 0xff000000; - break; - case 2: - *addr &= 0xffff0000; - break; - case 3: - *addr &= 0xffffff00; - break; - } - } - - /* Pass the packet up to the protocol layers. */ - NetReceive (NetRxPackets[0], rxlen); - - return rxlen; -} - -/* Send a data block via Ethernet. */ -extern int eth_send(void *packet, int length) -{ - int i, length32; - char *pa; - unsigned int *pa32, lastp = 0, rest; - - pa = (char *) packet; - pa32 = (unsigned int *) packet; - length32 = length / 4; - rest = length % 4; - - /* make sure there's no garbage in the last word */ - switch (rest) { - case 0: - lastp = pa32[length32]; - length32--; - break; - case 1: - lastp = pa32[length32] & 0x000000ff; - break; - case 2: - lastp = pa32[length32] & 0x0000ffff; - break; - case 3: - lastp = pa32[length32] & 0x00ffffff; - break; - } - - /* write to the fifo */ - for (i = 0; i < length32; i++) - SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]); - - /* the last word is written to an extra register, this - starts the transmission */ - SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp); - - /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission - went fine. But we can't use the timer for a timeout loop because - of it is used already in upper layers. So we just try some times. */ - i = 0; - while (i < 50000) { - if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK) - == NETARM_ETH_TXSTAT_TXOK) - return 0; - i++; - } - - printf ("eth_send timeout\n"); - return 1; -} diff --git a/drivers/net/netarm_eth.h b/drivers/net/netarm_eth.h deleted file mode 100644 index 8edab82da3..0000000000 --- a/drivers/net/netarm_eth.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2003 IMMS gGmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * author(s): Thomas Elste, - */ - -#include -#include - -#ifdef CONFIG_DRIVER_NETARMETH - -#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val -#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE)) - -#define NA_MII_POLL_BUSY_DELAY 900 - -/* MII negotiation timeout value - 500 jiffies = 5 seconds */ -#define NA_MII_NEGOTIATE_DELAY 30 - -/* Registers in the physical layer chip */ -#define MII_PHY_CONTROL 0 -#define MII_PHY_STATUS 1 -#define MII_PHY_ID 2 -#define MII_PHY_AUTONEGADV 4 - -#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 8151d2e0f4..b6d20f8446 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -45,7 +45,6 @@ COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MXC_UART) += serial_mxc.o -COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 44bb089dee..f5f43a6ddc 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -105,7 +105,6 @@ serial_initfunc(ks8695_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); serial_initfunc(max3100_serial_initialize); serial_initfunc(mxc_serial_initialize); -serial_initfunc(netarm_serial_initialize); serial_initfunc(pl01x_serial_initialize); serial_initfunc(s3c44b0_serial_initialize); serial_initfunc(sa1100_serial_initialize); @@ -201,7 +200,6 @@ void serial_initialize(void) lh7a40x_serial_initialize(); max3100_serial_initialize(); mxc_serial_initialize(); - netarm_serial_initialize(); pl01x_serial_initialize(); s3c44b0_serial_initialize(); sa1100_serial_initialize(); diff --git a/drivers/serial/serial_netarm.c b/drivers/serial/serial_netarm.c deleted file mode 100644 index 44d7c500c7..0000000000 --- a/drivers/serial/serial_netarm.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Serial Port stuff - taken from Linux - * - * (C) Copyright 2002 - * MAZeT GmbH - * Stephan Linz , - * - * (c) 2004 - * IMMS gGmbH - * Thomas Elste - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) -#if !defined(CONFIG_NETARM_NS7520) -#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) -#else -#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC)) -#endif - -/* wait until transmitter is ready for another character */ -#define TXWAITRDY(registers) \ -{ \ - ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \ - while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ - if (get_timer(0) > tmo) \ - break; \ - } \ -} - - -volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); -volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); - -extern void _netarm_led_FAIL1(void); - -/* - * Setup both serial i/f with given baudrate - */ -static void netarm_serial_setbrg(void) -{ - /* set 0 ... make sure pins are configured for serial */ -#if !defined(CONFIG_NETARM_NS7520) - PORTA = PORTB = - NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#else - PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); - PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); -#endif - - /* first turn em off */ - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; - - /* clear match register, we don't need it */ - serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; - - /* setup bit rate generator and rx buffer gap timer (1 byte only) */ - if ((gd->baudrate >= MIN_BAUD_RATE) - && (gd->baudrate <= MAX_BAUD_RATE)) { - serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = - NETARM_SER_BR_X16 (gd->baudrate); - serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = - 0; - serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = - NETARM_SER_RXGAP (gd->baudrate); - } else { - hang (); - } - - /* setup port mode */ - serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = - ( NETARM_SER_CTLB_RCGT_EN | - NETARM_SER_CTLB_UART_MODE); - serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = - ( NETARM_SER_CTLA_ENABLE | - NETARM_SER_CTLA_P_NONE | - /* see errata */ - NETARM_SER_CTLA_2STOP | - NETARM_SER_CTLA_8BITS | - NETARM_SER_CTLA_DTR_EN | - NETARM_SER_CTLA_RTS_EN); -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -static int netarm_serial_init(void) -{ - serial_setbrg (); - return 0; -} - - -/* - * Output a single byte to the serial port. - */ -static void netarm_serial_putc(const char c) -{ - volatile unsigned char *fifo; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); - - fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); - TXWAITRDY (serial_reg_ch1); - *fifo = c; -} - -/* - * Test of a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -static int netarm_serial_tstc(void) -{ - return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. - */ -static int netarm_serial_getc(void) -{ - unsigned int ch_uint; - volatile unsigned int *fifo; - volatile unsigned char *fifo_char = NULL; - int buf_count = 0; - - while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) - /* NOP */ ; - - fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); - fifo_char = (unsigned char *) &ch_uint; - ch_uint = *fifo; - - buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); - switch (buf_count) { - case NETARM_SER_STATA_RXFDB_4BYTES: - buf_count = 4; - break; - case NETARM_SER_STATA_RXFDB_3BYTES: - buf_count = 3; - break; - case NETARM_SER_STATA_RXFDB_2BYTES: - buf_count = 2; - break; - case NETARM_SER_STATA_RXFDB_1BYTES: - buf_count = 1; - break; - default: - /* panic, be never here */ - break; - } - - serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; - - return ch_uint & 0xff; -} - -static struct serial_device netarm_serial_drv = { - .name = "netarm_serial", - .start = netarm_serial_init, - .stop = NULL, - .setbrg = netarm_serial_setbrg, - .putc = netarm_serial_putc, - .puts = default_serial_puts, - .getc = netarm_serial_getc, - .tstc = netarm_serial_tstc, -}; - -void netarm_serial_initialize(void) -{ - serial_register(&netarm_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &netarm_serial_drv; -} -- cgit v1.2.3 From f2e0801565b7106da0f96784389c397794ce3906 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:11 +0000 Subject: stdio: Remove the CLPS7111 serial driver This driver is no longer used, remove it. Signed-off-by: Marek Vasut --- arch/arm/cpu/arm720t/cpu.c | 1 - arch/arm/cpu/arm720t/interrupts.c | 1 - drivers/serial/Makefile | 1 - drivers/serial/serial_clps7111.c | 134 ------------------ include/clps7111.h | 276 -------------------------------------- 5 files changed, 413 deletions(-) delete mode 100644 drivers/serial/serial_clps7111.c delete mode 100644 include/clps7111.h diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 85c1a2c7f0..2e2f543d0a 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -32,7 +32,6 @@ #include #include -#include #include #include diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 998efd844a..352d55dd15 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -27,7 +27,6 @@ */ #include -#include #include #include diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index b6d20f8446..5e8b64873d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -39,7 +39,6 @@ COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_S5P) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o -COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o diff --git a/drivers/serial/serial_clps7111.c b/drivers/serial/serial_clps7111.c deleted file mode 100644 index c292ed8756..0000000000 --- a/drivers/serial/serial_clps7111.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void clps7111_serial_setbrg(void) -{ - unsigned int reg = 0; - - switch (gd->baudrate) { - case 1200: reg = 191; break; - case 9600: reg = 23; break; - case 19200: reg = 11; break; - case 38400: reg = 5; break; - case 57600: reg = 3; break; - case 115200: reg = 1; break; - default: hang (); break; - } - - /* init serial serial 1,2 */ - IO_SYSCON1 = SYSCON1_UART1EN; - IO_SYSCON2 = SYSCON2_UART2EN; - - reg |= UBRLCR_WRDLEN8; - - IO_UBRLCR1 = reg; - IO_UBRLCR2 = reg; -} - - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int clps7111_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void clps7111_serial_putc(const char c) -{ - int tmo; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); - - tmo = get_timer (0) + 1 * CONFIG_SYS_HZ; - while (IO_SYSFLG1 & SYSFLG1_UTXFF) - if (get_timer (0) > tmo) - break; - - IO_UARTDR1 = c; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int clps7111_serial_tstc(void) -{ - return !(IO_SYSFLG1 & SYSFLG1_URXFE); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int clps7111_serial_getc(void) -{ - while (IO_SYSFLG1 & SYSFLG1_URXFE); - - return IO_UARTDR1 & 0xff; -} - -static struct serial_device clps7111_serial_drv = { - .name = "clps7111_serial", - .start = clps7111_serial_init, - .stop = NULL, - .setbrg = clps7111_serial_setbrg, - .putc = clps7111_serial_putc, - .puts = default_serial_puts, - .getc = clps7111_serial_getc, - .tstc = clps7111_serial_tstc, -}; - -void clps7111_serial_initialize(void) -{ - serial_register(&clps7111_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &clps7111_serial_drv; -} diff --git a/include/clps7111.h b/include/clps7111.h deleted file mode 100644 index baf600773b..0000000000 --- a/include/clps7111.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * linux/include/asm-arm/hardware/clps7111.h - * - * This file contains the hardware definitions of the CLPS7111 internal - * registers. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_HARDWARE_CLPS7111_H -#define __ASM_HARDWARE_CLPS7111_H - -#define CLPS7111_PHYS_BASE (0x80000000) - -#ifndef __ASSEMBLY__ -#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) -#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) -#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) -#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) -#endif - -#define PADR (0x0000) -#define PBDR (0x0001) -#define PDDR (0x0003) -#define PADDR (0x0040) -#define PBDDR (0x0041) -#define PDDDR (0x0043) -#define PEDR (0x0080) -#define PEDDR (0x00c0) -#define SYSCON1 (0x0100) -#define SYSFLG1 (0x0140) -#define MEMCFG1 (0x0180) -#define MEMCFG2 (0x01c0) -#define DRFPR (0x0200) -#define INTSR1 (0x0240) -#define INTMR1 (0x0280) -#define LCDCON (0x02c0) -#define TC1D (0x0300) -#define TC2D (0x0340) -#define RTCDR (0x0380) -#define RTCMR (0x03c0) -#define PMPCON (0x0400) -#define CODR (0x0440) -#define UARTDR1 (0x0480) -#define UBRLCR1 (0x04c0) -#define SYNCIO (0x0500) -#define PALLSW (0x0540) -#define PALMSW (0x0580) -#define STFCLR (0x05c0) -#define BLEOI (0x0600) -#define MCEOI (0x0640) -#define TEOI (0x0680) -#define TC1EOI (0x06c0) -#define TC2EOI (0x0700) -#define RTCEOI (0x0740) -#define UMSEOI (0x0780) -#define COEOI (0x07c0) -#define HALT (0x0800) -#define STDBY (0x0840) - -#define FBADDR (0x1000) -#define SYSCON2 (0x1100) -#define SYSFLG2 (0x1140) -#define INTSR2 (0x1240) -#define INTMR2 (0x1280) -#define UARTDR2 (0x1480) -#define UBRLCR2 (0x14c0) -#define SS2DR (0x1500) -#define SRXEOF (0x1600) -#define SS2POP (0x16c0) -#define KBDEOI (0x1700) - -/* common bits: SYSCON1 / SYSCON2 */ -#define SYSCON_UARTEN (1 << 8) - -#define SYSCON1_KBDSCAN(x) ((x) & 15) -#define SYSCON1_KBDSCANMASK (15) -#define SYSCON1_TC1M (1 << 4) -#define SYSCON1_TC1S (1 << 5) -#define SYSCON1_TC2M (1 << 6) -#define SYSCON1_TC2S (1 << 7) -#define SYSCON1_UART1EN SYSCON_UARTEN -#define SYSCON1_BZTOG (1 << 9) -#define SYSCON1_BZMOD (1 << 10) -#define SYSCON1_DBGEN (1 << 11) -#define SYSCON1_LCDEN (1 << 12) -#define SYSCON1_CDENTX (1 << 13) -#define SYSCON1_CDENRX (1 << 14) -#define SYSCON1_SIREN (1 << 15) -#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) -#define SYSCON1_ADCKSEL_MASK (3 << 16) -#define SYSCON1_EXCKEN (1 << 18) -#define SYSCON1_WAKEDIS (1 << 19) -#define SYSCON1_IRTXM (1 << 20) - -/* common bits: SYSFLG1 / SYSFLG2 */ -#define SYSFLG_UBUSY (1 << 11) -#define SYSFLG_URXFE (1 << 22) -#define SYSFLG_UTXFF (1 << 23) - -#define SYSFLG1_MCDR (1 << 0) -#define SYSFLG1_DCDET (1 << 1) -#define SYSFLG1_WUDR (1 << 2) -#define SYSFLG1_WUON (1 << 3) -#define SYSFLG1_CTS (1 << 8) -#define SYSFLG1_DSR (1 << 9) -#define SYSFLG1_DCD (1 << 10) -#define SYSFLG1_UBUSY SYSFLG_UBUSY -#define SYSFLG1_NBFLG (1 << 12) -#define SYSFLG1_RSTFLG (1 << 13) -#define SYSFLG1_PFFLG (1 << 14) -#define SYSFLG1_CLDFLG (1 << 15) -#define SYSFLG1_URXFE SYSFLG_URXFE -#define SYSFLG1_UTXFF SYSFLG_UTXFF -#define SYSFLG1_CRXFE (1 << 24) -#define SYSFLG1_CTXFF (1 << 25) -#define SYSFLG1_SSIBUSY (1 << 26) -#define SYSFLG1_ID (1 << 29) - -#define SYSFLG2_SSRXOF (1 << 0) -#define SYSFLG2_RESVAL (1 << 1) -#define SYSFLG2_RESFRM (1 << 2) -#define SYSFLG2_SS2RXFE (1 << 3) -#define SYSFLG2_SS2TXFF (1 << 4) -#define SYSFLG2_SS2TXUF (1 << 5) -#define SYSFLG2_CKMODE (1 << 6) -#define SYSFLG2_UBUSY SYSFLG_UBUSY -#define SYSFLG2_URXFE SYSFLG_URXFE -#define SYSFLG2_UTXFF SYSFLG_UTXFF - -#define LCDCON_GSEN (1 << 30) -#define LCDCON_GSMD (1 << 31) - -#define SYSCON2_SERSEL (1 << 0) -#define SYSCON2_KBD6 (1 << 1) -#define SYSCON2_DRAMZ (1 << 2) -#define SYSCON2_KBWEN (1 << 3) -#define SYSCON2_SS2TXEN (1 << 4) -#define SYSCON2_PCCARD1 (1 << 5) -#define SYSCON2_PCCARD2 (1 << 6) -#define SYSCON2_SS2RXEN (1 << 7) -#define SYSCON2_UART2EN SYSCON_UARTEN -#define SYSCON2_SS2MAEN (1 << 9) -#define SYSCON2_OSTB (1 << 12) -#define SYSCON2_CLKENSL (1 << 13) -#define SYSCON2_BUZFREQ (1 << 14) - -/* common bits: UARTDR1 / UARTDR2 */ -#define UARTDR_FRMERR (1 << 8) -#define UARTDR_PARERR (1 << 9) -#define UARTDR_OVERR (1 << 10) - -/* common bits: UBRLCR1 / UBRLCR2 */ -#define UBRLCR_BAUD_MASK ((1 << 12) - 1) -#define UBRLCR_BREAK (1 << 12) -#define UBRLCR_PRTEN (1 << 13) -#define UBRLCR_EVENPRT (1 << 14) -#define UBRLCR_XSTOP (1 << 15) -#define UBRLCR_FIFOEN (1 << 16) -#define UBRLCR_WRDLEN5 (0 << 17) -#define UBRLCR_WRDLEN6 (1 << 17) -#define UBRLCR_WRDLEN7 (2 << 17) -#define UBRLCR_WRDLEN8 (3 << 17) -#define UBRLCR_WRDLEN_MASK (3 << 17) - -#define SYNCIO_SMCKEN (1 << 13) -#define SYNCIO_TXFRMEN (1 << 14) - -#define SYSCON3 0x2200 /* System Control register 3 ----------------------- */ -#define ADCCON 0x00000001 /* ADC configuration */ -#define CLKCTL 0x00000006 /* processor clock control */ -#define CLKCTL_18 0x0 /* 18.432 MHz */ -#define CLKCTL_36 0x2 /* 36.864 MHz */ -#define CLKCTL_49 0x4 /* 49.152 MHz */ -#define CLKCTL_73 0x6 /* 73.728 MHz */ -#define MCPSEL 0x00000008 /* MCP select */ -#define ADCCKNSEN 0x000010 /* ADC clock sense */ -#define VERSN 0x000000e0 /* additional version bits */ -#define VERSN_SHIFT 5 -#define FASTWAKE 0x0000100 /* Wakeup clock select: 0=8Hz, 1=4kHz */ - -#define INTSR3 0x2240 /* Interrupt Status register 3 --------------------- */ -#define MCPINT 0x00000001 /* MCP interface interrupt (FIQ) */ - -#define INTMR3 0x2280 /* Interrupt Mask register 3 ----------------------- */ -#define LEDFLSH 0x22C0 /* LED Flash control register ---------------------- */ -#define LEDFLSH_RATE 0x03 /* flash rate */ -#define LEDFLSH_RATE_SHIFT 0 -#define LEDFLSH_DUTY 0x3c /* duty ratio */ -#define LEDFLSH_DUTY_SHIFT 2 -#define LEDFLSH_ENABLE 0x40 /* enable */ - -#define IO_START CLPS7111_PHYS_BASE - -#define IO(offset) (IO_START + (offset)) - -#define IO_BYTE(offset) (*(volatile unsigned char *)(IO_START + (offset))) -#define IO_WORD(offset) (*(volatile unsigned long *)(IO_START + (offset))) - -#define IO_PADR IO_BYTE(PADR) -#define IO_PBDR IO_BYTE(PBDR) -#define IO_PDDR IO_BYTE(PDDR) -#define IO_PADDR IO_BYTE(PADDR) -#define IO_PBDDR IO_BYTE(PBDDR) -#define IO_PDDDR IO_BYTE(PDDDR) -#define IO_PEDR IO_BYTE(PEDR) -#define IO_PEDDR IO_BYTE(PEDDR) -#define IO_SYSCON IO_WORD(SYSCON) -#define IO_SYSFLG IO_WORD(SYSFLG) -#define IO_MEMCFG1 IO_WORD(MEMCFG1) -#define IO_MEMCFG2 IO_WORD(MEMCFG2) -#define IO_DRFPR IO_WORD(DRFPR) -#define IO_INTSR IO_WORD(INTSR) -#define IO_INTMR IO_WORD(INTMR) -#define IO_LCDCON IO_WORD(LCDCON) -#define IO_TC1D IO_WORD(TC1D) -#define IO_TC2D IO_WORD(TC2D) -#define IO_RTCDR IO_WORD(RTCDR) -#define IO_RTCMR IO_WORD(RTCMR) -#define IO_PMPCON IO_WORD(PMPCON) -#define IO_CODR IO_BYTE(CODR) -#define IO_UARTDR IO_WORD(UARTDR) -#define IO_UBRLCR IO_WORD(UBRLCR) -#define IO_SYNCIO IO_WORD(SYNCIO) -#define IO_PALLSW IO_WORD(PALLSW) -#define IO_PALMSW IO_WORD(PALMSW) -#define IO_STFCLR IO_WORD(STFCLR) -#define IO_BLEOI IO_WORD(BLEOI) -#define IO_MCEOI IO_WORD(MCEOI) -#define IO_TEOI IO_WORD(TEOI) -#define IO_TC1EOI IO_WORD(TC1EOI) -#define IO_TC2EOI IO_WORD(TC2EOI) -#define IO_RTCEOI IO_WORD(RTCEOI) -#define IO_UMSEOI IO_WORD(UMSEOI) -#define IO_COEOI IO_WORD(COEOI) -#define IO_HALT IO_WORD(HALT) -#define IO_STDBY IO_WORD(STDBY) -#define IO_SYSCON1 IO_WORD(SYSCON1) -#define IO_SYSFLG1 IO_WORD(SYSFLG1) -#define IO_INTSR1 IO_WORD(INTSR1) -#define IO_INTMR1 IO_WORD(INTMR1) -#define IO_UARTDR1 IO_WORD(UARTDR1) -#define IO_UBRLCR1 IO_WORD(UBRLCR1) -#define IO_FRBADDR IO_WORD(FRBADDR) -#define IO_SYSCON2 IO_WORD(SYSCON2) -#define IO_SYSFLG2 IO_WORD(SYSFLG2) -#define IO_INTSR2 IO_WORD(INTSR2) -#define IO_INTMR2 IO_WORD(INTMR2) -#define IO_UARTDR2 IO_WORD(UARTDR2) -#define IO_UBRLCR2 IO_WORD(UBRLCR2) -#define IO_KBDEOI IO_WORD(KBDEOI) - -#define IO_MCCR IO_WORD(MCCR) -#define IO_MCDR0 IO_WORD(MCDR0) -#define IO_MCDR1 IO_WORD(MCDR1) -#define IO_MCDR2 IO_WORD(MCDR2) -#define IO_MCSR IO_WORD(MCSR) -#define IO_SYSCON3 IO_WORD(SYSCON3) -#define IO_INTSR3 IO_WORD(INTSR3) -#define IO_INTMR3 IO_WORD(INTMR3) -#define IO_LEDFLSH IO_WORD(LEDFLSH) - -#endif /* __ASM_HARDWARE_CLPS7111_H */ -- cgit v1.2.3 From a63dd62bb2e07cb7b9b9e15e917df602a3291d13 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:12 +0000 Subject: arm720: Further clean up the arm720t directory Clean up away old macros and such, so the file doesn't start piling up cruft. Signed-off-by: Marek Vasut clean --- arch/arm/cpu/arm720t/cpu.c | 32 +++++--------------------------- arch/arm/cpu/arm720t/interrupts.c | 39 ++------------------------------------- arch/arm/cpu/arm720t/start.S | 15 --------------- 3 files changed, 7 insertions(+), 79 deletions(-) diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 2e2f543d0a..820614e0ea 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -27,34 +27,12 @@ */ /* - * CPU specific code + * cleanup_before_linux() - Prepare the CPU to jump to Linux + * + * This function is called just before we call Linux, it + * prepares the processor for linux */ - -#include -#include -#include -#include - -#if !defined(CONFIG_INTEGRATOR) || !defined(CONFIG_ARCH_INTEGRATOR) -#error No cleanup_before_linux() defined for this CPU type -#endif - -int cleanup_before_linux (void) +int cleanup_before_linux(void) { - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - * and we set the CPU-speed to 73 MHz - see start.S for details - */ - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No cleanup before linux for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_TEGRA) - /* No cleanup before linux for tegra as yet */ -#else -#error No cleanup_before_linux() defined for this CPU type -#endif return 0; } diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 352d55dd15..8e763b7788 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -26,57 +26,22 @@ * MA 02111-1307 USA */ -#include -#include -#include - -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff -/* macro to read the 16 bit timer */ -#define READ_TIMER (IO_TC1D & 0xffff) - #ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) { -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No do_irq() for IntegratorAP/CM720T as yet */ -#else -#error do_irq() not defined for this CPU type -#endif } #endif -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* Use IntegratorAP routines in board/integratorap.c */ -#else - +#if defined(CONFIG_TEGRA) static ulong timestamp; static ulong lastdec; int timer_init (void) { -#if defined(CONFIG_TEGRA) /* No timer routines for tegra as yet */ lastdec = 0; -#else -#error No timer_init() defined for this CPU type -#endif timestamp = 0; - return (0); + return 0; } - -#endif /* ! IntegratorAP */ - -/* - * timer without interrupts - */ - - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No timer routines for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_TEGRA) - /* No timer routines for tegra as yet */ -#else -#error Timer routines not defined for this CPU type #endif diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 45c8f0a5ea..5d5e03e657 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -284,13 +284,6 @@ _dynsym_start_ofs: */ cpu_init_crit: -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific initialisation for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_TEGRA) - /* No cpu_init_crit for tegra as yet */ -#else -#error No cpu_init_crit() defined for current CPU type -#endif #ifdef CONFIG_ARM7_REVD /* set clock speed */ @@ -481,11 +474,3 @@ fiq: #endif #endif /* CONFIG_SPL_BUILD */ - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) - /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_TEGRA) - /* No specific reset actions for tegra as yet */ -#else -#error No reset_cpu() defined for current CPU type -#endif -- cgit v1.2.3 From 82138f4fcd09aecfe764970afeba895de379dc29 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 3 Oct 2012 08:54:13 +0000 Subject: arm720: Remove CONFIG_ARM7_REVD This is a dead code, remove it. Signed-off-by: Marek Vasut --- arch/arm/cpu/arm720t/start.S | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 5d5e03e657..c2a7763fff 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -285,17 +285,6 @@ _dynsym_start_ofs: cpu_init_crit: -#ifdef CONFIG_ARM7_REVD - /* set clock speed */ - /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */ - /* !!! not doing DRAM refresh properly! */ - ldr r0, SYSCON3 - ldr r1, [r0] - bic r1, r1, #CLKCTL - orr r1, r1, #CLKCTL_36 - str r1, [r0] -#endif - #if !defined(CONFIG_TEGRA) mov ip, lr /* -- cgit v1.2.3 From 53c41548a9fd7f0595c81c47e1ac3d9671d753e4 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Thu, 18 Oct 2012 10:15:45 +0000 Subject: arm: arm925t: remove SX1 board SX1 does not build properly by itself, is not built as part of MAKEALL arm or MAKEALL -a arm, and is only present in Makefile, not boards.cfg. As it also has no entry in MAINTAINERS, it is orphan and non-functional. Remove it. Signed-off-by: Albert ARIBAUD --- Makefile | 14 -- board/sx1/Makefile | 45 ------ board/sx1/config.mk | 19 --- board/sx1/lowlevel_init.S | 397 ---------------------------------------------- board/sx1/sx1.c | 123 -------------- doc/README.scrapyard | 3 +- include/configs/SX1.h | 189 ---------------------- 7 files changed, 2 insertions(+), 788 deletions(-) delete mode 100644 board/sx1/Makefile delete mode 100644 board/sx1/config.mk delete mode 100644 board/sx1/lowlevel_init.S delete mode 100644 board/sx1/sx1.c delete mode 100644 include/configs/SX1.h diff --git a/Makefile b/Makefile index 328347d177..d385467e8e 100644 --- a/Makefile +++ b/Makefile @@ -754,20 +754,6 @@ $(obj).boards.depend: boards.cfg lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/') ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/') -#======================================================================== -# ARM -#======================================================================== - -SX1_stdout_serial_config \ -SX1_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _stdout_serial_, $@)" ] ; then \ - echo "#undef CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \ - else \ - echo "#define CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ SX1 arm arm925t sx1 - ######################################################################### ## ARM1176 Systems ######################################################################### diff --git a/board/sx1/Makefile b/board/sx1/Makefile deleted file mode 100644 index 292459f254..0000000000 --- a/board/sx1/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2004-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sx1.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sx1/config.mk b/board/sx1/config.mk deleted file mode 100644 index 441bea2a03..0000000000 --- a/board/sx1/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, -# -# SX1 board with OMAP1510 (ARM925T) cpu -# see http://www.ti.com/ for more information on Texas Insturments -# -# SX1 has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - -CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/sx1/lowlevel_init.S b/board/sx1/lowlevel_init.S deleted file mode 100644 index c1a811aa8e..0000000000 --- a/board/sx1/lowlevel_init.S +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * - * -- Some bits of code used from rrload's head_OMAP1510.s -- - * Copyright (C) 2002 RidgeRun, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP1510) -#include <./configs/omap1510.h> -#endif - -#define OMAP1510_CLKS ((1< - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void flash__init (void); -static void ether__init (void); - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* arch number of SX1 Board */ - gd->bd->bi_arch_number = MACH_TYPE_SX1; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - -/* kk - this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ - /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ - - /* setup gpio direction to match board (no floats!) */ - /**gdir = 0xCFF9; */ - /**mdir = 0x103F; */ - - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -static void flash__init (void) -{ -#define CS0_CHIP_SELECT_REG 0xfffecc10 -#define CS3_CHIP_SELECT_REG 0xfffecc1c -#define EMIFS_GlB_Config_REG 0xfffecc0c - - unsigned int regval; - - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - regval = regval | 0x0001; /* Turn off write protection for flash devices. */ - if (regval & 0x0002) { - regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ - /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ - /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ - /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ - } - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} - - -/****************************** - Routine: - Description: -******************************/ -static void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0800000b - /* take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - */ - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); -} - - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d0f47164d7..ed779e245f 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,7 +11,8 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= -TQM85xx powerpc MPC85xx - - Stefan Roese +SX1 arm arm925t - - +TQM85xx powerpc MPC85xx d923a5d5 2012-10-04 Stefan Roese apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park tb0229 mips mips32 3f3110d 2011-12-12 rmu powerpc MPC850 fb82fd7 2011-12-07 Wolfgang Denk diff --git a/include/configs/SX1.h b/include/configs/SX1.h deleted file mode 100644 index 93d031ca85..0000000000 --- a/include/configs/SX1.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ -#define CONFIG_OMAP_SX1 1 /* a SX1 Board */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SX1 */ - -/* - * USB device configuration - */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 - -#define CONFIG_USBD_VENDORID 0x1234 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Siemens" -#define CONFIG_USBD_PRODUCT_NAME "SX1" - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP1510_I2C - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET - - -#include - -#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" -#ifdef CONFIG_STDOUT_USBTTY -#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty" -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SX1# " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. - * This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - * V1 - * PHYS_FLASH_SIZE_1 (16 << 10) 16 MB - * PHYS_FLASH_SIZE_2 (8 << 10) 8 MB - * V2 only 1 flash - * PHYS_FLASH_SIZE_1 (32 << 10) 32 MB - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, PHYS_FLASH_2 } - -/*----------------------------------------------------------------------- - * FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_SIZE_REDUND 0x20000 -#define CONFIG_ENV_OFFSET_REDUND 0x40000 - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From 522de019e566b9cbf7daafcd0a57a2d3dfdb69e6 Mon Sep 17 00:00:00 2001 From: Annamalai Lakshmanan Date: Thu, 30 Aug 2012 20:33:58 +0000 Subject: Origen: Add default clock settings for multimedia IPs Added clock settings for MFC, FIMC, FB and G3D. They are clocked to maximum respective frequencies as per datasheet. Signed-off-by: Annamalai Lakshmanan Signed-off-by: Giridhar Maruthy Signed-off-by: Inderpal Singh Signed-off-by: Tushar Behera --- board/samsung/origen/lowlevel_init.S | 37 +++++++++++++++++- board/samsung/origen/origen_setup.h | 74 ++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 1 deletion(-) diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S index 9283201201..9daa0da614 100644 --- a/board/samsung/origen/lowlevel_init.S +++ b/board/samsung/origen/lowlevel_init.S @@ -158,7 +158,22 @@ system_clock_init: ldr r2, =CLK_SRC_PERIL0_OFFSET str r1, [r0, r2] - /* FIMD0 */ + /* CAM , FIMC 0-3 */ + ldr r1, =CLK_SRC_CAM_VAL + ldr r2, =CLK_SRC_CAM_OFFSET + str r1, [r0, r2] + + /* MFC */ + ldr r1, =CLK_SRC_MFC_VAL + ldr r2, =CLK_SRC_MFC_OFFSET + str r1, [r0, r2] + + /* G3D */ + ldr r1, =CLK_SRC_G3D_VAL + ldr r2, =CLK_SRC_G3D_OFFSET + str r1, [r0, r2] + + /* LCD0 */ ldr r1, =CLK_SRC_LCD0_VAL ldr r2, =CLK_SRC_LCD0_OFFSET str r1, [r0, r2] @@ -223,6 +238,26 @@ system_clock_init: ldr r2, =CLK_DIV_PERIL0_OFFSET str r1, [r0, r2] + /* CAM, FIMC 0-3: CAM Clock Divisors */ + ldr r1, =CLK_DIV_CAM_VAL + ldr r2, =CLK_DIV_CAM_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_MFC: MFC Clock Divisors */ + ldr r1, =CLK_DIV_MFC_VAL + ldr r2, =CLK_DIV_MFC_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_G3D: G3D Clock Divisors */ + ldr r1, =CLK_DIV_G3D_VAL + ldr r2, =CLK_DIV_G3D_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_LCD0: LCD0 Clock Divisors */ + ldr r1, =CLK_DIV_LCD0_VAL + ldr r2, =CLK_DIV_LCD0_OFFSET + str r1, [r0, r2] + /* Set PLL locktime */ ldr r1, =PLL_LOCKTIME ldr r2, =APLL_LOCK_OFFSET diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h index 94cccca52c..930b948505 100644 --- a/board/samsung/origen/origen_setup.h +++ b/board/samsung/origen/origen_setup.h @@ -53,7 +53,18 @@ #define CLK_DIV_FSYS2_OFFSET 0xC548 #define CLK_DIV_FSYS3_OFFSET 0xC54C +#define CLK_SRC_CAM_OFFSET 0xC220 +#define CLK_SRC_TV_OFFSET 0xC224 +#define CLK_SRC_MFC_OFFSET 0xC228 +#define CLK_SRC_G3D_OFFSET 0xC22C +#define CLK_SRC_LCD0_OFFSET 0xC234 #define CLK_SRC_PERIL0_OFFSET 0xC250 + +#define CLK_DIV_CAM_OFFSET 0xC520 +#define CLK_DIV_TV_OFFSET 0xC524 +#define CLK_DIV_MFC_OFFSET 0xC528 +#define CLK_DIV_G3D_OFFSET 0xC52C +#define CLK_DIV_LCD0_OFFSET 0xC534 #define CLK_DIV_PERIL0_OFFSET 0xC550 #define CLK_SRC_LCD0_OFFSET 0xC234 @@ -353,6 +364,65 @@ | (UART1_RATIO << 4) \ | (UART0_RATIO << 0)) +/* Clock Source CAM/FIMC */ +/* CLK_SRC_CAM */ +#define CAM0_SEL_XUSBXTI 1 +#define CAM1_SEL_XUSBXTI 1 +#define CSIS0_SEL_XUSBXTI 1 +#define CSIS1_SEL_XUSBXTI 1 + +#define FIMC_SEL_SCLKMPLL 6 +#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL +#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL +#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL +#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL + +#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \ + | (CSIS0_SEL_XUSBXTI << 24) \ + | (CAM1_SEL_XUSBXTI << 20) \ + | (CAM0_SEL_XUSBXTI << 16) \ + | (FIMC3_LCLK_SEL << 12) \ + | (FIMC2_LCLK_SEL << 8) \ + | (FIMC1_LCLK_SEL << 4) \ + | (FIMC0_LCLK_SEL << 0)) + +/* SCLK CAM */ +/* CLK_DIV_CAM */ +#define FIMC0_LCLK_RATIO 4 +#define FIMC1_LCLK_RATIO 4 +#define FIMC2_LCLK_RATIO 4 +#define FIMC3_LCLK_RATIO 4 +#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \ + | (FIMC2_LCLK_RATIO << 8) \ + | (FIMC1_LCLK_RATIO << 4) \ + | (FIMC0_LCLK_RATIO << 0)) + +/* SCLK MFC */ +/* CLK_SRC_MFC */ +#define MFC_SEL_MPLL 0 +#define MOUTMFC_0 0 +#define MFC_SEL MOUTMFC_0 +#define MFC_0_SEL MFC_SEL_MPLL +#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL)) + + +/* CLK_DIV_MFC */ +#define MFC_RATIO 3 +#define CLK_DIV_MFC_VAL (MFC_RATIO) + +/* SCLK G3D */ +/* CLK_SRC_G3D */ +#define G3D_SEL_MPLL 0 +#define MOUTG3D_0 0 +#define G3D_SEL MOUTG3D_0 +#define G3D_0_SEL G3D_SEL_MPLL +#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) | (G3D_0_SEL)) + +/* CLK_DIV_G3D */ +#define G3D_RATIO 1 +#define CLK_DIV_G3D_VAL (G3D_RATIO) + +/* SCLK LCD0 */ /* CLK_SRC_LCD0 */ #define FIMD_SEL_SCLKMPLL 6 #define MDNIE0_SEL_XUSBXTI 1 @@ -363,6 +433,10 @@ | (MDNIE0_SEL_XUSBXTI << 4) \ | (FIMD_SEL_SCLKMPLL << 0)) +/* CLK_DIV_LCD0 */ +#define FIMD0_RATIO 4 +#define CLK_DIV_LCD0_VAL (FIMD0_RATIO) + /* Required period to generate a stable clock output */ /* PLL_LOCK_TIME */ #define PLL_LOCKTIME 0x1C20 -- cgit v1.2.3 From bff679ddfb3587df1f63a9310d2a93ce7873119d Mon Sep 17 00:00:00 2001 From: Yann Vernier Date: Fri, 5 Oct 2012 02:09:48 +0000 Subject: arm: ks8695: use defined constants for UART CONFIG_BAUDRATE and KS8695_UART_LINEC_WLEN8 used for UART registers --- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S index e9f1227dd6..1bba571077 100644 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S @@ -72,10 +72,10 @@ lowlevel_init: * enable UART for early debug trace */ ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR) - mov r2, #0xd9 - str r2, [r1] /* 115200 baud */ + mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE) + str r2, [r1] ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL) - mov r2, #0x03 + mov r2, #KS8695_UART_LINEC_WLEN8 str r2, [r1] /* 8 data bits, no parity, 1 stop */ ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) mov r2, #0x41 -- cgit v1.2.3 From b68d6712c379735e886ef9c01b946bc36f295273 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:19:32 +0000 Subject: ARM: fix u-boot.lds for -ffunction-sections/-fdata-sections When -ffunction-sections or -fdata-section are used, symbols are placed into sections such as .data.eserial1_device and .bss.serial_current. Update the linker script to explicitly include these. Without this change (at least with my gcc-4.5.3 built using crosstool-ng), I see that the sections do end up being included, but __bss_end__ gets set to the same value as __bss_start. Signed-off-by: Stephen Warren Acked-by: Allen Martin Acked-by: Simon Glass Tested-by: Simon Glass --- arch/arm/cpu/u-boot.lds | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 227aaff1e6..1996b97536 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -34,8 +34,8 @@ SECTIONS .text : { __image_copy_start = .; - CPUDIR/start.o (.text) - *(.text) + CPUDIR/start.o (.text*) + *(.text*) } . = ALIGN(4); @@ -43,7 +43,7 @@ SECTIONS . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); @@ -83,7 +83,7 @@ SECTIONS .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; - *(.bss) + *(.bss*) . = ALIGN(4); __bss_end__ = .; } -- cgit v1.2.3 From 1b0757eceddf037aad99ab59217a3a5c215e15d1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 24 Oct 2012 02:36:15 +0000 Subject: PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM) These boards have long reached EOL, and there has been no indication of any active users of such hardware for years. Get rid of the dead weight. Signed-off-by: Wolfgang Denk Cc: Wolfgang Grandegger --- MAINTAINERS | 6 - README | 4 +- arch/powerpc/cpu/mpc8xx/fec.c | 2 +- arch/powerpc/cpu/mpc8xx/scc.c | 16 +- board/c2mon/Makefile | 44 --- board/c2mon/c2mon.c | 236 ------------ board/c2mon/flash.c | 570 ---------------------------- board/c2mon/pcmcia.c | 282 -------------- board/c2mon/u-boot.lds | 106 ------ board/c2mon/u-boot.lds.debug | 137 ------- board/etx094/Makefile | 44 --- board/etx094/etx094.c | 384 ------------------- board/etx094/flash.c | 687 --------------------------------- board/etx094/u-boot.lds | 107 ------ board/lantec/Makefile | 44 --- board/lantec/flash.c | 625 ------------------------------ board/lantec/lantec.c | 208 ---------- board/lantec/u-boot.lds | 107 ------ board/lantec/u-boot.lds.debug | 137 ------- board/siemens/IAD210/IAD210.c | 299 --------------- board/siemens/IAD210/Makefile | 44 --- board/siemens/IAD210/atm.c | 652 -------------------------------- board/siemens/IAD210/atm.h | 287 -------------- board/siemens/IAD210/flash.c | 502 ------------------------- board/siemens/IAD210/u-boot.lds | 107 ------ board/siemens/SCM/Makefile | 49 --- board/siemens/SCM/flash.c | 488 ------------------------ board/siemens/SCM/fpga_scm.c | 104 ----- board/siemens/SCM/scm.c | 541 -------------------------- board/siemens/SCM/scm.h | 89 ----- board/siemens/common/README | 27 -- board/siemens/common/fpga.c | 369 ------------------ board/siemens/common/fpga.h | 53 --- board/westel/amx860/Makefile | 44 --- board/westel/amx860/amx860.c | 93 ----- board/westel/amx860/flash.c | 637 ------------------------------- board/westel/amx860/u-boot.lds | 107 ------ board/westel/amx860/u-boot.lds.debug | 138 ------- boards.cfg | 7 - doc/README.scrapyard | 6 + include/commproc.h | 131 +------ include/configs/AMX860.h | 299 --------------- include/configs/ETX094.h | 357 ------------------ include/configs/IAD210.h | 381 ------------------- include/configs/LANTEC.h | 358 ------------------ include/configs/SCM.h | 710 ----------------------------------- include/configs/c2mon.h | 417 -------------------- include/pcmcia.h | 2 - include/status_led.h | 36 -- post/cpu/mpc8xx/ether.c | 45 +-- 50 files changed, 16 insertions(+), 11109 deletions(-) delete mode 100644 board/c2mon/Makefile delete mode 100644 board/c2mon/c2mon.c delete mode 100644 board/c2mon/flash.c delete mode 100644 board/c2mon/pcmcia.c delete mode 100644 board/c2mon/u-boot.lds delete mode 100644 board/c2mon/u-boot.lds.debug delete mode 100644 board/etx094/Makefile delete mode 100644 board/etx094/etx094.c delete mode 100644 board/etx094/flash.c delete mode 100644 board/etx094/u-boot.lds delete mode 100644 board/lantec/Makefile delete mode 100644 board/lantec/flash.c delete mode 100644 board/lantec/lantec.c delete mode 100644 board/lantec/u-boot.lds delete mode 100644 board/lantec/u-boot.lds.debug delete mode 100644 board/siemens/IAD210/IAD210.c delete mode 100644 board/siemens/IAD210/Makefile delete mode 100644 board/siemens/IAD210/atm.c delete mode 100644 board/siemens/IAD210/atm.h delete mode 100644 board/siemens/IAD210/flash.c delete mode 100644 board/siemens/IAD210/u-boot.lds delete mode 100644 board/siemens/SCM/Makefile delete mode 100644 board/siemens/SCM/flash.c delete mode 100644 board/siemens/SCM/fpga_scm.c delete mode 100644 board/siemens/SCM/scm.c delete mode 100644 board/siemens/SCM/scm.h delete mode 100644 board/siemens/common/README delete mode 100644 board/siemens/common/fpga.c delete mode 100644 board/siemens/common/fpga.h delete mode 100644 board/westel/amx860/Makefile delete mode 100644 board/westel/amx860/amx860.c delete mode 100644 board/westel/amx860/flash.c delete mode 100644 board/westel/amx860/u-boot.lds delete mode 100644 board/westel/amx860/u-boot.lds.debug delete mode 100644 include/configs/AMX860.h delete mode 100644 include/configs/ETX094.h delete mode 100644 include/configs/IAD210.h delete mode 100644 include/configs/LANTEC.h delete mode 100644 include/configs/SCM.h delete mode 100644 include/configs/c2mon.h diff --git a/MAINTAINERS b/MAINTAINERS index 1b2da9421a..2daee7d2ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -104,8 +104,6 @@ Wolfgang Denk ARIA MPC5121e - AMX860 MPC860 - ETX094 MPC850 FPS850L MPC850 FPS860L MPC860 ICU862 MPC862 @@ -116,7 +114,6 @@ Wolfgang Denk IVMS8 MPC860 IVMS8_128 MPC860 IVMS8_256 MPC860 - LANTEC MPC850 LWMON MPC823 R360MPI MPC823 RRvision MPC823 @@ -128,7 +125,6 @@ Wolfgang Denk TQM855L MPC855 TQM860L MPC860 TQM860L_FEC MPC860 - c2mon MPC855 hermes MPC860 lwmon MPC823 @@ -227,7 +223,6 @@ Wolfgang Grandegger PN62 MPC8240 IPHASE4539 MPC8260 - SCM MPC8260 Anatolij Gustschin @@ -543,7 +538,6 @@ Unknown / orphaned boards: FADS850SAR MPC8xx FADS860T MPC8xx GENIETV MPC8xx - IAD210 MPC8xx MBX MPC8xx MBX860T MPC8xx NX823 MPC8xx diff --git a/README b/README index 69da2b86ba..4f16240ebd 100644 --- a/README +++ b/README @@ -2182,8 +2182,8 @@ CBFS (Coreboot Filesystem) support following board configurations are known to be "pRAM-clean": - ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL, - HERMES, IP860, RPXlite, LWMON, LANTEC, + IVMS8, IVML24, SPD8xx, TQM8xxL, + HERMES, IP860, RPXlite, LWMON, FLAGADM, TQM8260 - Error Recovery: diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index b348a98c58..d7c9090941 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -460,7 +460,7 @@ static void fec_pin_init(int fecidx) #endif /* !CONFIG_RMII */ -#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) +#elif !defined(CONFIG_ICU862) /* * Configure all of port D for MII. */ diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 2c93e24f3c..2ef77b4c14 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -473,20 +473,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) *((uint *) BCSR1) &= ~BCSR1_ETHEN; #endif /* MPC860ADS */ -#if defined(CONFIG_AMX860) - /* - * Port B is used to control the PHY,MC68160. - */ - immr->im_cpm.cp_pbdir |= - (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL); - - immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL; - immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL); - - immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN; - immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; -#endif /* AMX860 */ - #ifdef CONFIG_RPXCLASSIC *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); @@ -542,7 +528,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis) */ #if defined (CONFIG_FADS) udelay (10000); /* wait 10 ms */ -#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) +#elif defined(CONFIG_RPXCLASSIC) udelay (100000); /* wait 100 ms */ #endif diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile deleted file mode 100644 index b49f26da27..0000000000 --- a/board/c2mon/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o pcmcia.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c deleted file mode 100644 index 348dfa0af3..0000000000 --- a/board/c2mon/c2mon.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: TTTech C2MON "); - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long reg; - long int size8, size9; - long int size = 0; - - upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 the SDRAM bank 2 at physical address 0. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, - SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c deleted file mode 100644 index d33cb6ce43..0000000000 --- a/board/c2mon/flash.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c deleted file mode 100644 index 2267829039..0000000000 --- a/board/c2mon/pcmcia.c +++ /dev/null @@ -1,282 +0,0 @@ -#include -#include -#include - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "C2MON" - -static void cfg_ports (void) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - ushort sreg; - - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* - * Configure Port C for TPS2211 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - sreg = immap->im_ioport.iop_pcdat; - sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1); /* VAVPP => Hi-Z */ - sreg &= ~(TPS2211_VCCD0 | TPS2211_VCCD1); /* 3V and 5V off */ - immap->im_ioport.iop_pcdat = sreg; - - immap->im_ioport.iop_pcpar &= ~(TPS2211_OUTPUTS); - immap->im_ioport.iop_pcdir |= TPS2211_OUTPUTS; - - debug ("Set Port C: PAR: %04x DIR: %04x DAT: %04x\n", - immap->im_ioport.iop_pcpar, - immap->im_ioport.iop_pcdir, - immap->im_ioport.iop_pcdat); - - /* - * Configure Port B for TPS2211 PC-Card Power-Interface Switch - * - * Over-Current Input only - */ - cp->cp_pbpar &= ~(TPS2211_INPUTS); - cp->cp_pbdir &= ~(TPS2211_INPUTS); - - debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", - cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); -} - -int pcmcia_hardware_enable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, pipr, mask; - ushort sreg; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - immap = (immap_t *)CONFIG_SYS_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ - cfg_ports (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - sreg = immap->im_ioport.iop_pcdat; - if ((pipr & mask) == mask) { - sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ - TPS2211_VCCD1); /* 5V on */ - sreg &= ~(TPS2211_VCCD0); /* 3V off */ - puts (" 5.0V card found: "); - } else { - sreg |= (TPS2211_VPPD0 | TPS2211_VPPD1 | /* VAVPP => Hi-Z */ - TPS2211_VCCD0); /* 3V on */ - sreg &= ~(TPS2211_VCCD1); /* 5V off */ - puts (" 3.3V card found: "); - } - - debug ("\nPC DAT: %04x -> 3.3V %s 5.0V %s\n", - sreg, - ( (sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) ? "on" : "off", - (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) ? "on" : "off" - ); - - immap->im_ioport.iop_pcdat = sreg; - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if ((cp->cp_pbdat & TPS2211_OC) == 0) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - immap->im_ioport.iop_pcdat &= ~(TPS2211_VCCD0|TPS2211_VCCD1); - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - /* ALl voltages off / Hi-Z */ - immap->im_ioport.iop_pcdat |= (TPS2211_VPPD0 | TPS2211_VPPD1 | - TPS2211_VCCD0 | TPS2211_VCCD1 ); - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; - u_long reg; - ushort sreg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_ports (); /* Enables switch, but all in Hi-Z */ - - sreg = immap->im_ioport.iop_pcdat; - sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */ - - switch(vcc) { - case 0: break; /* Switch off */ - case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */ - sreg &= ~TPS2211_VCCD1; - break; - case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */ - sreg |= TPS2211_VCCD1; - break; - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - immap->im_ioport.iop_pcdat = sreg; - -#ifdef DEBUG -{ - char *s; - - if ((sreg & TPS2211_VCCD0) && !(sreg & TPS2211_VCCD1)) { - s = "at 3.3V"; - } else if (!(sreg & TPS2211_VCCD0) && (sreg & TPS2211_VCCD1)) { - s = "at 5.0V"; - } else { - s = "down"; - } - printf ("PCMCIA powered %s\n", s); -} -#endif - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds deleted file mode 100644 index b854c180c4..0000000000 --- a/board/c2mon/u-boot.lds +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - net/libnet.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug deleted file mode 100644 index 92796e6744..0000000000 --- a/board/c2mon/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/etx094/Makefile b/board/etx094/Makefile deleted file mode 100644 index 6dc495c361..0000000000 --- a/board/etx094/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c deleted file mode 100644 index abefe4a482..0000000000 --- a/board/etx094/etx094.c +++ /dev/null @@ -1,384 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static void read_hw_vers (void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - - /* single read (offset 0x00 in upm ram) */ - - 0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04, - 0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_, - - /* burst read (offset 0x08 in upm ram) */ - - 0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04, - 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00, - 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* single write (offset 0x18 in upm ram) */ - - 0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00, - 0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_, - - /* burst write (offset 0x20 in upm ram) */ - - 0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00, - 0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05, - - /* init part1 (offset 0x28 in upm ram) */ - - 0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34, - 0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* refresh (offset 0x30 in upm ram) */ - - 0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05, - - /* init part2 (offset 0x34 in upm ram) */ - - 0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34, - 0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_, - - /* exception (offset 0x3C in upm ram) */ - - 0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_, - -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test ETX ID string (ETX_xxx...) - * - * Return 1 always. - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - -#ifdef SB_ETX094 - gd->board_type = 0; /* 0 = 2SDRAM-Device */ -#else - gd->board_type = 1; /* 1 = 1SDRAM-Device */ -#endif - - if (l < 0 || strncmp(buf, "ETX_", 4)) { - puts ("### No HW ID - assuming ETX_094\n"); - read_hw_vers (); - return (0); - } - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - putc ('\n'); - - read_hw_vers (); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */ - - /* A3(SDRAM)=0 => Bursttype = Sequential - * A2-A0(SDRAM)=010 => Burst length = 4 - * A4-A6(SDRAM)=010 => CasLat=2 - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - } - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004128; /* SDRAM bank 0 (CS2) - Init Part 1 */ - memctl->memc_mcr = 0x80004734; /* SDRAM bank 0 (CS2) - Init Part 2 */ - udelay (1); - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - memctl->memc_mcr = 0x80006128; /* SDRAM bank 1 (CS3) - Init Part 1 */ - memctl->memc_mcr = 0x80006734; /* SDRAM bank 1 (CS3) - Init Part 2 */ - udelay (1); - } - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = - dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); -/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ - } else { - size_b1 = 0; - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /*DIV16 */ - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or2 = - ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b0; - } else { - unsigned long reg; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -/* HW-ID Table (Bits: 2^9;2^7;2^5) */ -#define HW_ID_0 0x0000 -#define HW_ID_1 0x0020 -#define HW_ID_2 0x0080 -#define HW_ID_3 0x00a0 -#define HW_ID_4 0x0200 -#define HW_ID_5 0x0220 -#define HW_ID_6 0x0280 -#define HW_ID_7 0x02a0 - -void read_hw_vers () -{ - unsigned short rd_msk = 0x02A0; - - /* HW-ID pin-definition */ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - immr->im_ioport.iop_pddir &= ~(rd_msk); - immr->im_ioport.iop_pdpar &= ~(rd_msk); - - /* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */ - - /* Check the HW-ID */ - printf ("HW-Version: "); - switch (immr->im_ioport.iop_pddat & rd_msk) { - case HW_ID_0: - printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n"); - break; - case HW_ID_1: - printf ("V0.9 / W50037-Q1-D6-1\n"); - break; - case HW_ID_2: - printf ("NOT USED - assuming ID#2\n"); - break; - case HW_ID_3: - printf ("NOT USED - assuming ID#3\n"); - break; - case HW_ID_4: - printf ("NOT USED - assuming ID#4\n"); - break; - case HW_ID_5: - printf ("NOT USED - assuming ID#5\n"); - break; - case HW_ID_6: - printf ("NOT USED - assuming ID#6\n"); - break; - case HW_ID_7: - printf ("NOT USED - assuming ID#7\n"); - break; - default: - printf ("###Error###\n"); - break; - } -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/etx094/flash.c b/board/etx094/flash.c deleted file mode 100644 index 0958e73d60..0000000000 --- a/board/etx094/flash.c +++ /dev/null @@ -1,687 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); -#ifdef CONFIG_FLASH_16BIT - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ -#else - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | - BR_MS_GPCM | BR_V; -#endif - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - memctl->memc_br1 = 0; /* invalidate bank 1 */ - - flash_info[0].size = size_b0; - - return size_b0; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00002000); - - return; - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ -#ifdef CONFIG_FLASH_16BIT - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000) - 0x00030000; -#else - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00020000) - 0x00060000; -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) - info->start[i] = base + i * 0x00020000; - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST200A: - printf("39xF200A (2M = 128K x 16)\n"); - break; - case FLASH_SST400A: - printf("39xF400A (4M = 256K x 16)\n"); - break; - case FLASH_SST800A: - printf("39xF800A (8M = 512K x 16)\n"); - break; - case FLASH_STM800AB: - printf("M29W800AB (8M = 512K x 16)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ -#ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short *)addr; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0090; - value = s_addr[0]; - value = value|(value<<16); -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00900090; - value = addr[0]; -#endif - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return 0; /* no or unknown flash */ - } -#ifdef CONFIG_FLASH_16BIT - value = s_addr[1]; - value = value|(value<<16); -#else - value = addr[1]; /* device ID */ -#endif - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; -#ifdef CONFIG_FLASH_16BIT - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MB */ -#else - info->sector_count = 19; - info->size = 0x00200000; /* => 2 MB */ -#endif - break; - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; -#ifdef CONFIG_FLASH_16BIT - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MB */ -#else - info->sector_count = 35; - info->size = 0x00400000; /* => 4 MB */ -#endif - - break; - case SST_ID_xF200A: - info->flash_id += FLASH_SST200A; - info->sector_count = 64; /* 39xF200A (2M = 128K x 16) */ - info->size = 0x00080000; - break; - case SST_ID_xF400A: - info->flash_id += FLASH_SST400A; - info->sector_count = 128; /* 39xF400A (4M = 256K x 16) */ - info->size = 0x00100000; - break; - case SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 256; /* 39xF800A (8M = 512K x 16) */ - info->size = 0x00200000; - break; /* => 2 MB */ - case STM_ID_x800AB: - info->flash_id += FLASH_STM800AB; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00002000); - } else { /* AMD and Fujitsu types */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ -#ifdef CONFIG_FLASH_16BIT - - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + - (i * 0x00010000) - 0x00030000; -#else - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + - (i * 0x00020000) - 0x00060000; -#endif - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) - info->start[i] = base + i * 0x00020000; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address: - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ -#ifdef CONFIG_FLASH_16BIT - s_addr = (volatile unsigned short *)(info->start[i]); - info->protect[i] = s_addr[2] & 1; -#else - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; -#endif - } - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { -#ifdef CONFIG_FLASH_16BIT - s_addr = (volatile unsigned short *)(info->start[0]); - *s_addr = 0x00F0; /* reset bank */ -#else - addr = (volatile unsigned long *)info->start[0]; - *addr = 0x00F000F0; /* reset bank */ -#endif - - } - return info->size; -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long *)(info->start[0]); - int flag, prot, sect; - ulong start, now, last; -#ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short *)addr; -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } -/*#ifndef CONFIG_FLASH_16BIT - ulong type; - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return; - } -#endif*/ - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - start = get_timer(0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ -#ifdef CONFIG_FLASH_16BIT - vu_short *s_sect_addr = (vu_short *)(info->start[sect]); -#else - vu_long *sect_addr = (vu_long *)(info->start[sect]); -#endif - /* Disable interrupts which might cause a timeout */ - flag = disable_interrupts(); - -#ifdef CONFIG_FLASH_16BIT - - /*printf("\ns_sect_addr=%x",s_sect_addr);*/ - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x0080; - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_sect_addr[0] = 0x0030; -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00800080; - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - sect_addr[0] = 0x00300030; -#endif - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - -#ifdef CONFIG_FLASH_16BIT - while ((s_sect_addr[0] & 0x0080) != 0x0080) { -#else - while ((sect_addr[0] & 0x00800080) != 0x00800080) { -#endif - now = get_timer(start); - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show every second that we're waiting */ - if ((now - last) > 1000) { - putc('.'); - last = now; - } - } - } - } - - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#ifdef CONFIG_FLASH_16BIT - s_addr[0] = 0x00F0; /* reset bank */ -#else - addr[0] = 0x00F000F0; /* reset bank */ -#endif - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return write_word(info, wp, data); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - -#ifdef CONFIG_FLASH_16BIT - vu_short high_data; - vu_short low_data; - vu_short *s_addr = (vu_short *)addr; -#endif - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return 2; - -#ifdef CONFIG_FLASH_16BIT - /* Write the 16 higher-bits */ - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - high_data = ((data>>16) & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - - *((vu_short *)dest) = high_data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - - /* Write the 16 lower-bits */ -#endif - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); -#ifdef CONFIG_FLASH_16BIT - dest += 0x2; - low_data = (data & 0x0000ffff); - - s_addr[0x5555] = 0x00AA; - s_addr[0x2AAA] = 0x0055; - s_addr[0x5555] = 0x00A0; - *((vu_short *)dest) = low_data; - -#else - addr[0x5555] = 0x00AA00AA; - addr[0x2AAA] = 0x00550055; - addr[0x5555] = 0x00A000A0; - *((vu_long *)dest) = data; -#endif - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - -#ifdef CONFIG_FLASH_16BIT - while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { -#else - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { -#endif - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - return 0; -} diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds deleted file mode 100644 index 56c3470bde..0000000000 --- a/board/etx094/u-boot.lds +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - *(.text.vsprintf) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/lantec/Makefile b/board/lantec/Makefile deleted file mode 100644 index 12e4aa6880..0000000000 --- a/board/lantec/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/lantec/flash.c b/board/lantec/flash.c deleted file mode 100644 index 97ed0542bf..0000000000 --- a/board/lantec/flash.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Derived from ../tqm8xx/flash.c - * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG] - */ - -#include -#include - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \ - BR_MS_GPCM | BR_PS_32 | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or5 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br5 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_PS_32 | BR_V; - - DEBUGF("## BR5: 0x%08x OR5: 0x%08x\n", - memctl->memc_br5, memctl->memc_or5); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_info[1].size = size_b1; - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br5 = 0; /* invalidate bank */ - memctl->memc_or5 = 0; /* invalidate bank */ - - DEBUGF("## DISABLE BR5: 0x%08x OR5: 0x%08x\n", - memctl->memc_br5, memctl->memc_or5); - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c deleted file mode 100644 index 6d3486c48a..0000000000 --- a/board/lantec/lantec.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001 - * Torsten Stevens, FHG IMS, stevens@ims.fhg.de - * Bruno Achauer, Exet AG, bruno@exet-ag.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Derived from ../tqm8xx/tqm8xx.c - */ - -#include -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Return 1 for "L" type, 0 else. - */ - -int checkboard (void) -{ - printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - /* initialize memory address register */ - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ - udelay (200); /* 0x80006105 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05); - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - udelay (1); /* 0x80006130 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30); - - udelay (1); /* 0x80006106 */ - memctl->memc_mcr = - MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06); - - memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */ - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE3_PRELIM; - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - */ - size_b0 = dram_size (CONFIG_SYS_MAMR_8COL, - (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE; - - /* - * Final mapping: - */ - - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - udelay (1000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds deleted file mode 100644 index 94118024bd..0000000000 --- a/board/lantec/u-boot.lds +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - net/libnet.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - drivers/rtc/librtc.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug deleted file mode 100644 index e788f5c170..0000000000 --- a/board/lantec/u-boot.lds.debug +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c deleted file mode 100644 index 7325a93647..0000000000 --- a/board/siemens/IAD210/IAD210.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2001 - * Paul Geerinckx - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include "atm.h" -#include - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -/* used PLD registers */ -# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0) -# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10) -# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11) -# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12) -# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13) - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */ - _NOT_USED_, - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0xFFFAF834, 0xFFE5B435, /* last */ - _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00, - 0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF1AAF804, 0xFFA5F447, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84, - 0xFFAFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * MRS sequence (Offset 38 in UPMA RAM) - */ - 0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */ - _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0xFFAFFC04, 0xFFAFFC05, /* last */ - _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile iop8xx_t *iop = &immap->im_ioport; - volatile fec_t *fecp = &immap->im_cpm.cp_fec; - long int size; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM precharge */ - udelay (1); - memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */ - udelay (1); - memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - */ - size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - - memctl->memc_mamr = CONFIG_SYS_MAMR; - udelay (1000); - - /* - * Final mapping - */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); - - udelay (10000); - - /* prepare pin multiplexing for fast ethernet */ - - atmLoad (); - fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ - iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ - - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - return (0); -} - -void board_serial_init (void) -{ - ; /* nothing to do here */ -} - -void board_ether_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8xx_t *iop = &immap->im_ioport; - volatile fec_t *fecp = &immap->im_cpm.cp_fec; - - atmLoad (); - fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ - iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ -} - -int board_early_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile iop8xx_t *iop = &immap->im_ioport; - - /* configure the LED timing output pins - port A pin 4 */ - iop->iop_papar = 0x0800; - iop->iop_padir = 0x0800; - - /* start timer 2 for the 4hz LED blink rate */ - timers->cpmt_tmr2 = 0xff2c; /* 4HZ for 64MHz */ - timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */ - timers->cpmt_tgcr = 0x00000810; /* run timer 2 */ - - /* chip select for PLD access */ - memctl->memc_br6 = 0x10000401; - memctl->memc_or6 = 0xFC000908; - - /* PLD initial values ( set LEDs, remove reset on LXT) */ - - *PLD_GCR1_REG = 0x06; - *PLD_EXT_RES = 0xC0; - *PLD_EXT_FETH = 0x40; - *PLD_EXT_LED = 0xFF; - *PLD_EXT_X21 = 0x04; - return 0; -} - -static void board_get_enetaddr(uchar *addr) -{ - int i; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cpm = &immap->im_cpm; - unsigned int rccrtmp; - - char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 }; - - for (i = 0; i < 6; i++) - addr[i] = default_mac_addr[i]; - - printf ("There is an error in the i2c driver .. /n"); - printf ("You need to fix it first....../n"); - - rccrtmp = cpm->cp_rccr; - cpm->cp_rccr |= 0x0020; - - i2c_reg_read (0xa0, 0); - printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n", - i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0), - i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0), - i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0)); - - cpm->cp_rccr = rccrtmp; -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} diff --git a/board/siemens/IAD210/Makefile b/board/siemens/IAD210/Makefile deleted file mode 100644 index bb81507815..0000000000 --- a/board/siemens/IAD210/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o atm.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c deleted file mode 100644 index 40aad0ac26..0000000000 --- a/board/siemens/IAD210/atm.c +++ /dev/null @@ -1,652 +0,0 @@ -#include -#include -#include - -#include "atm.h" -#include - -#define SYNC __asm__("sync") -#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) - -#define FALSE 1 -#define TRUE 0 -#define OK 0 -#define ERROR -1 - -struct atm_connection_t g_conn[NUM_CONNECTIONS] = -{ - { NULL, 10, NULL, 10, NULL, NULL, NULL, NULL }, /* OAM */ -}; - -struct atm_driver_t g_atm = -{ - FALSE, /* loaded */ - FALSE, /* started */ - NULL, /* csram */ - 0, /* csram_size */ - NULL, /* am_top */ - NULL, /* ap_top */ - NULL, /* int_reload_ptr */ - NULL, /* int_serv_ptr */ - NULL, /* rbd_base_ptr */ - NULL, /* tbd_base_ptr */ - 0 /* linerate */ -}; - -char csram[1024]; /* more than enough for doing nothing*/ - -int atmLoad(void); -void atmUnload(void); -int atmMemInit(void); -void atmIntInit(void); -void atmApcInit(void); -void atmAmtInit(void); -void atmCpmInit(void); -void atmUtpInit(void); - -/***************************************************************************** - * - * FUNCTION NAME: atmLoad - * - * DESCRIPTION: Basic ATM initialization. - * - * PARAMETERS: none - * - * RETURNS: OK or ERROR - * - ****************************************************************************/ -int atmLoad() -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; - volatile iop8xx_t *iop = &immap->im_ioport; - - timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ - immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ - iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ - - if ( atmMemInit() != OK ) return ERROR; - - atmIntInit(); - atmApcInit(); - atmAmtInit(); - atmCpmInit(); - atmUtpInit(); - - g_atm.loaded = TRUE; - - return OK; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmUnload - * - * DESCRIPTION: Disables ATM and UTOPIA. - * - * PARAMETERS: none - * - * RETURNS: void - * - ****************************************************************************/ -void atmUnload() -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; - volatile iop8xx_t *iop = &immap->im_ioport; - - timers->cpmt_tgcr &= 0x0FFF; SYNC; /* Disable Timer 4 */ - immap->im_cpm.cp_scc[3].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */ - iop->iop_pdpar &= 0x3FFF; SYNC; /* Disable SAR and UTOPIA */ - g_atm.loaded = FALSE; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmMemInit - * - * DESCRIPTION: - * - * The ATM driver uses the following resources: - * - * A. Memory in DPRAM to hold - * - * 1/ CT = Connection Table ( RCT & TCT ) - * 2/ TCTE = Transmit Connection Table Extension - * 3/ MPHYPT = Multi-PHY Pointing Table - * 4/ APCP = APC Parameter Table - * 5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 ) - * 6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR ) - * 7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR ) - * 8/ TQ = Transmit Queue - * 9/ AM = Address Matching Table - * 10/ AP = Address Pointing Table - * - * B. Memory in cache safe RAM to hold - * - * 1/ INT = Interrupt Queue - * 2/ RBD = Receive Buffer Descriptors - * 3/ TBD = Transmit Buffer Descriptors - * - * This function - * 1. clears the ATM DPRAM area, - * 2. Allocates and clears cache safe memory, - * 3. Initializes 'g_conn'. - * - * PARAMETERS: none - * - * RETURNS: OK or ERROR - * - ****************************************************************************/ -int atmMemInit() -{ - int i; - unsigned immr = CONFIG_SYS_IMMR; - int total_num_rbd = 0; - int total_num_tbd = 0; - - memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); - - g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY; - - for ( i = 0; i < NUM_CONNECTIONS; ++i ) { - total_num_rbd += g_conn[i].num_rbd; - total_num_tbd += g_conn[i].num_tbd; - } - - g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4; - - g_atm.csram = &csram[0]; - memset(&(g_atm.csram), 0x00, g_atm.csram_size); - - g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4); - g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES); - g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd); - - g_conn[0].rbd_ptr = g_atm.rbd_base_ptr; - g_conn[0].tbd_ptr = g_atm.tbd_base_ptr; - g_conn[0].ct_ptr = CT_PTR(immr); - g_conn[0].tcte_ptr = TCTE_PTR(immr); - - return OK; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmIntInit - * - * DESCRIPTION: - * - * Initialization of the MPC860 ESAR Interrupt Queue. - * This function - * - clears all entries in the INT, - * - sets the WRAP bit of the last INT entry, - * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure - * to the first INT entry. - * - * PARAMETERS: none - * - * RETURNS: void - * - * REMARKS: - * - * - The INT resides in external cache safe memory. - * - The base address of the INT is stored in g_atm.int_reload_ptr. - * - The number of entries in the INT is given by NUM_INT_ENTRIES. - * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit(). - * - ****************************************************************************/ -void atmIntInit() -{ - int i; - for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0; - g_atm.int_reload_ptr[i] = INT_WRAP; - g_atm.int_serv_ptr = g_atm.int_reload_ptr; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmApcInit - * - * DESCRIPTION: - * - * This function initializes the following ATM Pace Controller related - * data structures: - * - * - 1 MPHY Pointing Table (contains only one entry) - * - 3 APC Parameter Tables (one PHY with 3 priorities) - * - 3 APC Tables (one table for each priority) - * - 1 Transmit Queue (one transmit queue per PHY) - * - * PARAMETERS: none - * - * RETURNS: void - * - ****************************************************************************/ -void atmApcInit() -{ - int i; - /* unsigned immr = CONFIG_SYS_IMMR; */ - uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR); - struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR); - uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR); - uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR); - /***************************************************/ - /* Initialize MPHY Pointing Table (only one entry) */ - /***************************************************/ - *mphypt_ptr = APCP_BASE; - - /********************************************/ - /* Initialize APC parameters for priority 1 */ - /********************************************/ - apcp_ptr->apct_base1 = APCT_PRIO_1_BASE; - apcp_ptr->apct_end1 = APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2; - apcp_ptr->apct_ptr1 = APCT_PRIO_1_BASE; - apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE; - apcp_ptr->etqbase = TQ_BASE; - apcp_ptr->etqend = TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2; - apcp_ptr->etqaptr = TQ_BASE; - apcp_ptr->etqtptr = TQ_BASE; - apcp_ptr->apc_mi = 8; - apcp_ptr->ncits = 0x0100; /* NCITS = 1 */ - apcp_ptr->apcnt = 0; - apcp_ptr->reserved1 = 0; - apcp_ptr->eapcst = 0x2009; /* LAST, ESAR, MPHY */ - apcp_ptr->ptp_counter = 0; - apcp_ptr->ptp_txch = 0; - apcp_ptr->reserved2 = 0; - - - /***************************************************/ - /* Initialize APC Tables with empty slots (0xFFFF) */ - /***************************************************/ - for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF; - - /************************/ - /* Clear Transmit Queue */ - /************************/ - for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmAmtInit - * - * DESCRIPTION: - * - * This function clears the first entry in the Address Matching Table and - * lets the first entry in the Address Pointing table point to the first - * entry in the TCT table (i.e. the raw cell channel). - * - * PARAMETERS: none - * - * RETURNS: void - * - * REMARKS: - * - * The values for the AMBASE, AMEND and APBASE registers in SAR parameter - * RAM are initialized by atmCpmInit(). - * - ****************************************************************************/ -void atmAmtInit() -{ - unsigned immr = CONFIG_SYS_IMMR; - - g_atm.am_top = AM_PTR(immr); - g_atm.ap_top = AP_PTR(immr); - - *(g_atm.ap_top--) = CT_BASE; - *(g_atm.am_top--) = 0; -} - -/***************************************************************************** - * - * FUNCTION NAME: atmCpmInit - * - * DESCRIPTION: - * - * This function initializes the Utopia Interface Parameter RAM Map - * (SCC4, ATM Protocol) of the Communication Processor Modudule. - * - * PARAMETERS: none - * - * RETURNS: void - * - ****************************************************************************/ -void atmCpmInit() -{ - unsigned immr = CONFIG_SYS_IMMR; - - memset((char *)immr + 0x3F00, 0x00, 0xC0); - - /*-----------------------------------------------------------------*/ - /* RBDBASE - Receive buffer descriptors base address */ - /* The RBDs reside in cache safe external memory. */ - /*-----------------------------------------------------------------*/ - *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr; - - /*-----------------------------------------------------------------*/ - /* SRFCR - SAR receive function code */ - /* 0-2 rsvd = 000 */ - /* 3-4 BO = 11 Byte ordering (big endian). */ - /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ - /* when the SDMA channel accesses memory. */ - /*-----------------------------------------------------------------*/ - *SRFCR(immr) = 0x18; - - /*-----------------------------------------------------------------*/ - /* SRSTATE - SAR receive status */ - /* 0 EXT = 0 Extended mode off. */ - /* 1 ACP = 0 Valid only if EXT = 1. */ - /* 2 EC = 0 Standard 53-byte ATM cell. */ - /* 3 SNC = 0 In sync. Must be set to 0 during initialization. */ - /* 4 ESAR = 1 Enhanced SAR functionality enabled. */ - /* 5 MCF = 1 Management Cell Filter active. */ - /* 6 SER = 0 UTOPIA mode. */ - /* 7 MPY = 1 Multiple PHY mode. */ - /*-----------------------------------------------------------------*/ - *SRSTATE(immr) = 0x0D; - - /*-----------------------------------------------------------------*/ - /* MRBLR - Maximum receive buffer length register. */ - /* Must be cleared for ATM operation (see also SMRBLR). */ - /*-----------------------------------------------------------------*/ - *MRBLR(immr) = 0; - - /*-----------------------------------------------------------------*/ - /* RSTATE - SCC internal receive state parameters */ - /* The first byte must be initialized with the value of SRFCR. */ - /*-----------------------------------------------------------------*/ - *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24; - - /*-----------------------------------------------------------------*/ - /* STFCR - SAR transmit function code */ - /* 0-2 rsvd = 000 */ - /* 3-4 BO = 11 Byte ordering (big endian). */ - /* 5-7 FC = 000 Value driven on the address type signals AT[1-3] */ - /* when the SDMA channel accesses memory. */ - /*-----------------------------------------------------------------*/ - *STFCR(immr) = 0x18; - - /*-----------------------------------------------------------------*/ - /* SRSTATE - SAR transmit status */ - /* 0 EXT = 0 : Extended mode off */ - /* 1 rsvd = 0 : */ - /* 2 EC = 0 : Standard 53-byte ATM cell */ - /* 3 rsvd = 0 : */ - /* 4 ESAR = 1 : Enhanced SAR functionality enabled */ - /* 5 rsvd = 0 : */ - /* 6 SER = 0 : UTOPIA mode */ - /* 7 MPY = 1 : Multiple PHY mode */ - /*-----------------------------------------------------------------*/ - *STSTATE(immr) = 0x09; - - /*-----------------------------------------------------------------*/ - /* TBDBASE - Transmit buffer descriptors base address */ - /* The TBDs reside in cache safe external memory. */ - /*-----------------------------------------------------------------*/ - *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr; - - /*-----------------------------------------------------------------*/ - /* TSTATE - SCC internal transmit state parameters */ - /* The first byte must be initialized with the value of STFCR. */ - /*-----------------------------------------------------------------*/ - *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24; - - /*-----------------------------------------------------------------*/ - /* CTBASE - Connection table base address */ - /* Offset from the beginning of DPRAM (64-byte aligned). */ - /*-----------------------------------------------------------------*/ - *CTBASE(immr) = CT_BASE; - - /*-----------------------------------------------------------------*/ - /* INTBASE - Interrupt queue base pointer. */ - /* The interrupt queue resides in cache safe external memory. */ - /*-----------------------------------------------------------------*/ - *INTBASE(immr) = (uint32)g_atm.int_reload_ptr; - - /*-----------------------------------------------------------------*/ - /* INTPTR - Pointer into interrupt queue. */ - /* Initialize to INTBASE. */ - /*-----------------------------------------------------------------*/ - *INTPTR(immr) = *INTBASE(immr); - - /*-----------------------------------------------------------------*/ - /* C_MASK - Constant mask for CRC32 */ - /* Must be initialized to 0xDEBB20E3. */ - /*-----------------------------------------------------------------*/ - *C_MASK(immr) = 0xDEBB20E3; - - /*-----------------------------------------------------------------*/ - /* INT_ICNT - Interrupt threshold value */ - /*-----------------------------------------------------------------*/ - *INT_ICNT(immr) = 1; - - /*-----------------------------------------------------------------*/ - /* INT_CNT - Interrupt counter */ - /* Initalize to INT_ICNT. Decremented for each interrupt entry */ - /* reported in the interrupt queue. On zero an interrupt is */ - /* signaled to the host by setting the GINT bit in the event */ - /* register. The counter is reinitialized with INT_ICNT. */ - /*-----------------------------------------------------------------*/ - *INT_CNT(immr) = *INT_ICNT(immr); - - /*-----------------------------------------------------------------*/ - /* SMRBLR - SAR maximum receive buffer length register. */ - /* Must be a multiple of 48 bytes. Common for all ATM connections. */ - /*-----------------------------------------------------------------*/ - *SMRBLR(immr) = SAR_RXB_SIZE; - - /*-----------------------------------------------------------------*/ - /* APCST - APC status register. */ - /* 0 rsvd 0 */ - /* 1-2 CSER 11 Initialize with the same value as NSER. */ - /* 3-4 NSER 11 Next serial or UTOPIA channel. */ - /* 5-7 rsvd 000 */ - /* 8-10 rsvd 000 */ - /* 11 rsvd 0 */ - /* 12 ESAR 1 UTOPIA Level 2 MPHY enabled. */ - /* 13 DIS 0 APC disable. Must be initiazed to 0. */ - /* 14 PL2 0 Not used. */ - /* 15 MPY 1 Multiple PHY mode on. */ - /*-----------------------------------------------------------------*/ - *APCST(immr) = 0x7809; - - /*-----------------------------------------------------------------*/ - /* APCPTR - Pointer to the APC parameter table */ - /* In MPHY master mode this parameter points to the MPHY pointing */ - /* table. 2-byte aligned. */ - /*-----------------------------------------------------------------*/ - *APCPTR(immr) = MPHYPT_BASE; - - /*-----------------------------------------------------------------*/ - /* HMASK - Header mask */ - /* Each incoming cell is masked with HMASK before being compared */ - /* to the entries in the address matching table. */ - /*-----------------------------------------------------------------*/ - *HMASK(immr) = AM_HMASK; - - /*-----------------------------------------------------------------*/ - /* AMBASE - Address matching table base address */ - /*-----------------------------------------------------------------*/ - *AMBASE(immr) = AM_BASE; - - /*-----------------------------------------------------------------*/ - /* AMEND - Address matching table end address */ - /*-----------------------------------------------------------------*/ - *AMEND(immr) = AM_BASE; - - /*-----------------------------------------------------------------*/ - /* APBASE - Address pointing table base address */ - /*-----------------------------------------------------------------*/ - *APBASE(immr) = AP_BASE; - - /*-----------------------------------------------------------------*/ - /* MPHYST - MPHY status register */ - /* 0-1 rsvd 00 */ - /* 2-6 NMPHY 00000 1 PHY */ - /* 7-9 rsvd 000 */ - /* 10-14 CMPHY 00000 Initialize with same value as NMPHY */ - /*-----------------------------------------------------------------*/ - *MPHYST(immr) = 0x0000; - - /*-----------------------------------------------------------------*/ - /* TCTEBASE - Transmit connection table extension base address */ - /* Offset from the beginning of DPRAM (32-byte aligned). */ - /*-----------------------------------------------------------------*/ - *TCTEBASE(immr) = TCTE_BASE; - - /*-----------------------------------------------------------------*/ - /* Clear not used registers. */ - /*-----------------------------------------------------------------*/ -} - -/***************************************************************************** - * - * FUNCTION NAME: atmUtpInit - * - * DESCRIPTION: - * - * This function initializes the ATM interface for - * - * - UTOPIA mode - * - muxed bus - * - master operation - * - multi PHY (because of a bug in the MPC860P rev. E.0) - * - internal clock = SYSCLK / 2 - * - * EXTERNAL EFFECTS: - * - * After calling this function, the MPC860ESAR UTOPIA bus is - * active and uses the following ports/pins: - * - * Port Pin Signal Description - * ------ --- ------- ------------------------------------------- - * PB[15] R17 TxClav Transmit cell available input/output signal - * PC[15] D16 RxClav Receive cell available input/output signal - * PD[15] U17 UTPB[0] UTOPIA bus bit 0 input/output signal - * PD[14] V19 UTPB[1] UTOPIA bus bit 1 input/output signal - * PD[13] V18 UTPB[2] UTOPIA bus bit 2 input/output signal - * PD[12] R16 UTPB[3] UTOPIA bus bit 3 input/output signal - * PD[11] T16 RXENB Receive enable input/output signal - * PD[10] W18 TXENB Transmit enable input/output signal - * PD[9] V17 UTPCLK UTOPIA clock input/output signal - * PD[7] T15 UTPB[4] UTOPIA bus bit 4 input/output signal - * PD[6] V16 UTPB[5] UTOPIA bus bit 5 input/output signal - * PD[5] U15 UTPB[6] UTOPIA bus bit 6 input/output signal - * PD[4] U16 UTPB[7] UTOPIA bus bit 7 input/output signal - * PD[3] W16 SOC Start of cell input/output signal - * - * PARAMETERS: none - * - * RETURNS: void - * - * REMARK: - * - * The ATM parameters and data structures must be configured before - * initializing the UTOPIA port. The UTOPIA port activates immediately - * upon initialization, and if its associated data structures are not - * initialized, the CPM will lock up. - * - ****************************************************************************/ -void atmUtpInit() -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile iop8xx_t *iop = &immap->im_ioport; - volatile car8xx_t *car = &immap->im_clkrst; - volatile cpm8xx_t *cpm = &immap->im_cpm; - int flag; - - flag = disable_interrupts(); - - /*-----------------------------------------------------------------*/ - /* SCCR - System Clock Control Register */ - /* */ - /* The UTOPIA clock can be selected to be internal clock or */ - /* external clock (selected by the UTOPIA mode register). */ - /* In case of internal clock, the UTOPIA clock is derived from */ - /* the system frequency divided by two dividers. */ - /* Bits 27-31 of the SCCR register are defined to control the */ - /* UTOPIA clock. */ - /* */ - /* SCCR[27:29] DFUTP Division factor. Divide the system clock */ - /* by 2^DFUTP. */ - /* SCCR[30:31] DFAUTP Additional division factor. Divide the */ - /* system clock by the following value: */ - /* 00 = divide by 1 */ - /* 00 = divide by 3 */ - /* 10 = divide by 5 */ - /* 11 = divide by 7 */ - /* */ - /* Note that the UTOPIA clock must be programmed as to operate */ - /* within the range SYSCLK/10 .. 50MHz. */ - /*-----------------------------------------------------------------*/ - car->car_sccr &= 0xFFFFFFE0; - car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */ - - /*-----------------------------------------------------------------*/ - /* RCCR - RISC Controller Configuration Register */ - /* */ - /* RCCR[8] DR1M IDMA Request 0 Mode */ - /* 0 = edge sensitive */ - /* 1 = level sensitive */ - /* RCCR[9] DR0M IDMA Request 0 Mode */ - /* 0 = edge sensitive */ - /* 1 = level sensitive */ - /* RCCR[10:11] DRQP IDMA Request Priority */ - /* 00 = IDMA req. have more prio. than SCCs */ - /* 01 = IDMA req. have less prio. then SCCs */ - /* 10 = IDMA requests have the lowest prio. */ - /* 11 = reserved */ - /* */ - /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */ - /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */ - /* higher priority. */ - /*-----------------------------------------------------------------*/ - cpm->cp_rccr &= 0xFF0F; - cpm->cp_rccr |= 0x00D0; - - /*-----------------------------------------------------------------*/ - /* Port B - TxClav Signal */ - /*-----------------------------------------------------------------*/ - cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */ - cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */ - - /*-----------------------------------------------------------------*/ - /* UTOPIA Mode Register */ - /* */ - /* - muxed bus (master operation only) */ - /* - multi PHY (because of a bug in the MPC860P rev.E.0) */ - /* - internal clock */ - /* - no loopback */ - /* - do no activate statistical counters */ - /*-----------------------------------------------------------------*/ - iop->utmode = 0x00000004; SYNC; - - /*-----------------------------------------------------------------*/ - /* Port D - UTOPIA Data and Control Signals */ - /* */ - /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals */ - /* 11 RXENB UTOPIA receive enable input/output signal */ - /* 10 TXENB UTOPIA transmit enable input/output signal */ - /* 9 TUPCLK UTOPIA clock input/output signal */ - /* 8 MII-MDC Used by MII in simult. MII and UTOPIA operation */ - /* 7-4 UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals */ - /* 3 SOC UTOPIA Start of cell input/output signal */ - /* 2 Reserved */ - /* 1 Enable UTOPIA mode */ - /* 0 Enable SAR */ - /*-----------------------------------------------------------------*/ - iop->iop_pdpar |= 0xDF7F; SYNC; - iop->iop_pddir &= 0x2080; SYNC; - - /*-----------------------------------------------------------------*/ - /* Port C - RxClav Signal */ - /*-----------------------------------------------------------------*/ - iop->iop_pcpar |= 0x0001; /* PCPAR[15] = 1 */ - iop->iop_pcdir &= 0xFFFE; /* PCDIR[15] = 0 */ - iop->iop_pcso &= 0xFFFE; /* PCSO[15] = 0 */ - - if (flag) - enable_interrupts(); -} diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h deleted file mode 100644 index cd5b45e869..0000000000 --- a/board/siemens/IAD210/atm.h +++ /dev/null @@ -1,287 +0,0 @@ -typedef unsigned char uint8; -typedef unsigned short uint16; -typedef unsigned int uint32; -typedef volatile unsigned char vuint8; -typedef volatile unsigned short vuint16; -typedef volatile unsigned int vuint32; - - -#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000 - -#define ATM_DPRAM_BEGIN (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000) -#define NUM_CONNECTIONS 1 -#define SAR_RXB_SIZE 1584 -#define AM_HMASK 0x0FFFFFF0 - -#define NUM_CT_ENTRIES (NUM_CONNECTIONS) -#define NUM_TCTE_ENTRIES (NUM_CONNECTIONS) -#define NUM_AM_ENTRIES (NUM_CONNECTIONS+1) -#define NUM_AP_ENTRIES (NUM_CONNECTIONS+1) -#define NUM_MPHYPT_ENTRIES 1 -#define NUM_APCP_ENTRIES 1 -#define NUM_APCT_PRIO_1_ENTRIES 146 /* Determines minimum rate */ -#define NUM_TQ_ENTRIES 12 - -#define SIZE_OF_CT_ENTRY 64 -#define SIZE_OF_TCTE_ENTRY 32 -#define SIZE_OF_AM_ENTRY 4 -#define SIZE_OF_AP_ENTRY 2 -#define SIZE_OF_MPHYPT_ENTRY 2 -#define SIZE_OF_APCP_ENTRY 32 -#define SIZE_OF_APCT_ENTRY 2 -#define SIZE_OF_TQ_ENTRY 2 - -#define CT_BASE ((ATM_DPRAM_BEGIN + 63) & 0xFFC0) /*64 */ -#define TCTE_BASE (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY) /*32 */ -#define APCP_BASE (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY) /*32 */ -#define AM_BEGIN (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY) /*4 */ -#define AM_BASE (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY) -#define AP_BEGIN (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY) /*2 */ -#define AP_BASE (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY) -#define MPHYPT_BASE (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY) /*2 */ -#define APCT_PRIO_1_BASE (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY) /*2 */ -#define TQ_BASE (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY) /*2 */ -#define ATM_DPRAM_SIZE ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN) - -#define CT_PTR(base) ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE)) -#define TCTE_PTR(base) ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE)) -#define AM_PTR(base) ((uint32 *)((char *)(base) + 0x2000 + AM_BASE)) -#define AP_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + AP_BASE)) -#define MPHYPT_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE)) -#define APCP_PTR(base) ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE)) -#define APCT1_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE)) -#define APCT2_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE)) -#define APCT3_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE)) -#define TQ_PTR(base) ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE)) - -/* SAR registers */ -#define RBDBASE(base) ((vuint32 *)(base + 0x3F00)) /* Base address of RxBD-List */ -#define SRFCR(base) ((vuint8 *)(base + 0x3F04)) /* DMA Receive function code */ -#define SRSTATE(base) ((vuint8 *)(base + 0x3F05)) /* DMA Receive status */ -#define MRBLR(base) ((vuint16 *)(base + 0x3F06)) /* Init to 0 for ATM */ -#define RSTATE(base) ((vuint32 *)(base + 0x3F08)) /* Do not write to */ -#define R_CNT(base) ((vuint16 *)(base + 0x3F10)) /* Do not write to */ -#define STFCR(base) ((vuint8 *)(base + 0x3F12)) /* DMA Transmit function code */ -#define STSTATE(base) ((vuint8 *)(base + 0x3F13)) /* DMA Transmit status */ -#define TBDBASE(base) ((vuint32 *)(base + 0x3F14)) /* Base address of TxBD-List */ -#define TSTATE(base) ((vuint32 *)(base + 0x3F18)) /* Do not write to */ -#define COMM_CH(base) ((vuint16 *)(base + 0x3F1C)) /* Command channel */ -#define STCHNUM(base) ((vuint16 *)(base + 0x3F1E)) /* Do not write to */ -#define T_CNT(base) ((vuint16 *)(base + 0x3F20)) /* Do not write to */ -#define CTBASE(base) ((vuint16 *)(base + 0x3F22)) /* Base address of Connection-table */ -#define ECTBASE(base) ((vuint32 *)(base + 0x3F24)) /* Valid only for external Conn.-table */ -#define INTBASE(base) ((vuint32 *)(base + 0x3F28)) /* Base address of Interrupt-table */ -#define INTPTR(base) ((vuint32 *)(base + 0x3F2C)) /* Pointer to Interrupt-queue */ -#define C_MASK(base) ((vuint32 *)(base + 0x3F30)) /* CRC-mask */ -#define SRCHNUM(base) ((vuint16 *)(base + 0x3F34)) /* Do not write to */ -#define INT_CNT(base) ((vuint16 *)(base + 0x3F36)) /* Interrupt-Counter */ -#define INT_ICNT(base) ((vuint16 *)(base + 0x3F38)) /* Interrupt threshold */ -#define TSTA(base) ((vuint16 *)(base + 0x3F3A)) /* Time-stamp-address */ -#define OLDLEN(base) ((vuint16 *)(base + 0x3F3C)) /* Do not write to */ -#define SMRBLR(base) ((vuint16 *)(base + 0x3F3E)) /* SAR max RXBuffer length */ -#define EHEAD(base) ((vuint32 *)(base + 0x3F40)) /* Valid for serial mode */ -#define EPAYLOAD(base) ((vuint32 *)(base + 0x3F44)) /* Valid for serial mode */ -#define TQBASE(base) ((vuint16 *)(base + 0x3F48)) /* Base address of Tx queue */ -#define TQEND(base) ((vuint16 *)(base + 0x3F4A)) /* End address of Tx queue */ -#define TQAPTR(base) ((vuint16 *)(base + 0x3F4C)) /* TQ APC pointer */ -#define TQTPTR(base) ((vuint16 *)(base + 0x3F4E)) /* TQ Tx pointer */ -#define APCST(base) ((vuint16 *)(base + 0x3F50)) /* APC status */ -#define APCPTR(base) ((vuint16 *)(base + 0x3F52)) /* APC parameter pointer */ -#define HMASK(base) ((vuint32 *)(base + 0x3F54)) /* Header mask */ -#define AMBASE(base) ((vuint16 *)(base + 0x3F58)) /* Address match table base */ -#define AMEND(base) ((vuint16 *)(base + 0x3F5A)) /* Address match table end */ -#define APBASE(base) ((vuint16 *)(base + 0x3F5C)) /* Address match parameter */ -#define FLBASE(base) ((vuint32 *)(base + 0x3F54)) /* First-level table base */ -#define SLBASE(base) ((vuint32 *)(base + 0x3F58)) /* Second-level table base */ -#define FLMASK(base) ((vuint16 *)(base + 0x3F5C)) /* First-level mask */ -#define ECSIZE(base) ((vuint16 *)(base + 0x3F5E)) /* Valid for extended mode */ -#define APCT_REAL(base) ((vuint32 *)(base + 0x3F60)) /* APC 32 bit counter */ -#define R_PTR(base) ((vuint32 *)(base + 0x3F64)) /* Do not write to */ -#define RTEMP(base) ((vuint32 *)(base + 0x3F68)) /* Do not write to */ -#define T_PTR(base) ((vuint32 *)(base + 0x3F6C)) /* Do not write to */ -#define TTEMP(base) ((vuint32 *)(base + 0x3F70)) /* Do not write to */ - -/* ESAR registers */ -#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80)) /* Perf.Mon.Timestamp */ -#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84)) /* Perf.Mon.Template */ -#define PMPTR(base) ((vuint16 *)(base + 0x3F88)) /* Perf.Mon.Table */ -#define PMCHANNEL(base) ((vuint16 *)(base + 0x3F8A)) /* Perf.Mon.Channel */ -#define MPHYST(base) ((vuint16 *)(base + 0x3F90)) /* Multi-PHY Status */ -#define TCTEBASE(base) ((vuint16 *)(base + 0x3F92)) /* Internal TCT Extension Base */ -#define ETCTEBASE(base) ((vuint32 *)(base + 0x3F94)) /* External TCT Extension Base */ -#define COMM_CH2(base) ((vuint32 *)(base + 0x3F98)) /* 2nd command channel word */ -#define STATBASE(base) ((vuint16 *)(base + 0x3F9C)) /* Statistics table pointer */ - -/* UTOPIA Mode Register */ -#define UTMODE(base) (CAST(vuint32 *)(base + 0x0978)) - -/* SAR commands */ -#define TRANSMIT_CHANNEL_ACTIVATE_CMD 0x0FC1 -#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1 -#define STOP_TRANSMIT_CMD 0x2FC1 -#define RESTART_TRANSMIT_CMD 0x3FC1 -#define STOP_RECEIVE_CMD 0x4FC1 -#define RESTART_RECEIVE_CMD 0x5FC1 -#define APC_BYPASS_CMD 0x6FC1 -#define MEM_WRITE_CMD 0x7FC1 -#define CPCR_FLG 0x0001 - -/* INT flags */ -#define INT_VALID 0x80000000 -#define INT_WRAP 0x40000000 -#define INT_APCO 0x00800000 -#define INT_TQF 0x00200000 -#define INT_RXF 0x00080000 -#define INT_BSY 0x00040000 -#define INT_TXB 0x00020000 -#define INT_RXB 0x00010000 - -#define NUM_INT_ENTRIES 80 -#define SIZE_OF_INT_ENTRY 4 - -struct apc_params_t { - vuint16 apct_base1; /* APC Table - First Priority Base pointer */ - vuint16 apct_end1; /* First APC Table - Length */ - vuint16 apct_ptr1; /* First APC Table Pointer */ - vuint16 apct_sptr1; /* APC Table First Priority Service pointer */ - vuint16 etqbase; /* Enhanced Transmit Queue Base pointer */ - vuint16 etqend; /* Enhanced Transmit Queue End pointer */ - vuint16 etqaptr; /* Enhanced Transmit Queue APC pointer */ - vuint16 etqtptr; /* Enhanced Transmit Queue Transmitter pointer */ - vuint16 apc_mi; /* APC - Max Iteration */ - vuint16 ncits; /* Number of Cells In TimeSlot */ - vuint16 apcnt; /* APC - N Timer */ - vuint16 reserved1; /* reserved */ - vuint16 eapcst; /* APC status */ - vuint16 ptp_counter; /* PTP queue length */ - vuint16 ptp_txch; /* PTP channel */ - vuint16 reserved2; /* reserved */ -}; - -struct ct_entry_t { - /* RCT */ - unsigned fhnt:1; - unsigned pm_rct:1; - unsigned reserved0:6; - unsigned hec:1; - unsigned clp:1; - unsigned cng_ncrc:1; - unsigned inf_rct:1; - unsigned cngi_ptp:1; - unsigned cdis_rct:1; - unsigned aal_rct:2; - uint16 rbalen; - uint32 rcrc; - uint32 rb_ptr; - uint16 rtmlen; - uint16 rbd_ptr; - uint16 rbase; - uint16 tstamp; - uint16 imask; - unsigned ft:2; - unsigned nim:1; - unsigned reserved1:2; - unsigned rpmt:6; - unsigned reserved2:5; - uint8 reserved3[8]; - /* TCT */ - unsigned reserved4:1; - unsigned pm_tct:1; - unsigned reserved5:6; - unsigned pc:1; - unsigned reserved6:2; - unsigned inf_tct:1; - unsigned cr10:1; - unsigned cdis_tct:1; - unsigned aal_tct:2; - uint16 tbalen; - uint32 tcrc; - uint32 tb_ptr; - uint16 ttmlen; - uint16 tbd_ptr; - uint16 tbase; - unsigned reserved7:5; - unsigned tpmt:6; - unsigned reserved8:3; - unsigned avcf:1; - unsigned act:1; - uint32 chead; - uint16 apcl; - uint16 apcpr; - unsigned out:1; - unsigned bnr:1; - unsigned tservice:2; - unsigned apcp:12; - uint16 apcpf; -}; - -struct tcte_entry_t { - unsigned res1:4; - unsigned scr:12; - uint16 scrf; - uint16 bt; - uint16 buptrh; - uint32 buptrl; - unsigned vbr2:1; - unsigned res2:15; - uint16 oobr; - uint16 res3[8]; -}; - -#define SIZE_OF_RBD 12 -#define SIZE_OF_TBD 12 - -struct atm_bd_t { - vuint16 flags; - vuint16 length; - unsigned char *buffer_ptr; - vuint16 cpcs_uu_cpi; - vuint16 reserved; -}; - -/* BD flags */ -#define EMPTY 0x8000 -#define READY 0x8000 -#define WRAP 0x2000 -#define INTERRUPT 0x1000 -#define LAST 0x0800 -#define FIRST 0x0400 -#define OAM 0x0400 -#define CONTINUOUS 0x0200 -#define HEC_ERROR 0x0080 -#define CELL_LOSS 0x0040 -#define CONGESTION 0x0020 -#define ABORT 0x0010 -#define LEN_ERROR 0x0002 -#define CRC_ERROR 0x0001 - -struct atm_connection_t { - struct atm_bd_t *rbd_ptr; - int num_rbd; - struct atm_bd_t *tbd_ptr; - int num_tbd; - struct ct_entry_t *ct_ptr; - struct tcte_entry_t *tcte_ptr; - void *drv; - void (*notify) (void *drv, int event); -}; - -struct atm_driver_t { - int loaded; - int started; - char *csram; - int csram_size; - uint32 *am_top; - uint16 *ap_top; - uint32 *int_reload_ptr; - uint32 *int_serv_ptr; - struct atm_bd_t *rbd_base_ptr; - struct atm_bd_t *tbd_base_ptr; - unsigned linerate_in_bps; -}; - -extern struct atm_connection_t g_conn[NUM_CONNECTIONS]; -extern struct atm_driver_t g_atm; - -extern int atmLoad (void); -extern void atmUnload (void); diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c deleted file mode 100644 index c262e0f836..0000000000 --- a/board/siemens/IAD210/flash.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; imemc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - - return (size); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds deleted file mode 100644 index c0f107319e..0000000000 --- a/board/siemens/IAD210/u-boot.lds +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - net/libnet.o (.text*) - drivers/rtc/librtc.o (.text*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile deleted file mode 100644 index 07db9d44e5..0000000000 --- a/board/siemens/SCM/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common $(obj)../../tqc/tqm8xx) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \ - ../../tqc/tqm8xx/load_sernum_ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c deleted file mode 100644 index 4a6d5382be..0000000000 --- a/board/siemens/SCM/flash.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD devices on the TQM8260 board - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset (void) -{ - if (flash_info[0].flash_id != FLASH_UNKNOWN) { - V_ULONG (flash_info[0].start[0]) = 0x00F000F0; - V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG (baseaddr + 4); - - switch ((int) flashtest_h) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG (baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - } else { - switch (flashtest_h) { - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x02000000; - break; /* 4 * 8 MB = 32 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* no or unknown flash */ - } - } - - if (flashtest_h == AMD_ID_LV640U) { - - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - - } else if (info->flash_id & FLASH_BTYPE) { - - /* set up sector start adress table (bottom sector type) */ - info->start[0] = baseaddr + 0x00000000; - info->start[1] = baseaddr + 0x00010000; - info->start[2] = baseaddr + 0x00018000; - info->start[3] = baseaddr + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; - } - - } else { - - /* set up sector start adress table (top sector type) */ - i = info->sector_count - 1; - info->start[i--] = baseaddr + info->size - 0x00010000; - info->start[i--] = baseaddr + info->size - 0x00018000; - info->start[i--] = baseaddr + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = baseaddr + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG (info->start[i] + 16) & 0x00010001) || - (V_ULONG (info->start[i] + 20) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset (); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - printf ("29LV800T (8 M, top sector)\n"); - break; - case FLASH_AM800B: - printf ("29LV800T (8 M, bottom sector)\n"); - break; - case FLASH_AM160T: - printf ("29LV160T (16 M, top sector)\n"); - break; - case FLASH_AM160B: - printf ("29LV160B (16 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: - printf ("29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: - printf ("29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: - printf ("29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: - printf ("29LV640D (64 M, uniform sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG (info->start[sect]) = 0x00300030; - V_ULONG (info->start[sect] + 4) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || - (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) - { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; - if ((rc = write_dword (info, dp, bb)) != 0) { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword (info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); - } - return (write_dword (info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) -{ - ulong start, cl, ch; - int flag, i; - - for (ch = 0, i = 0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl = 0, i = 0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & ch) != ch - || (*((vu_long *) (dest + 4)) & cl) != cl) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest) = ch; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest + 4) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c deleted file mode 100644 index acd9c1570f..0000000000 --- a/board/siemens/SCM/fpga_scm.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include "../common/fpga.h" - -fpga_t fpga_list[] = { - {"FIOX", CONFIG_SYS_FIOX_BASE, - CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE} - , - {"FDOHM", CONFIG_SYS_FDOHM_BASE, - CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE} -}; -int fpga_count = sizeof (fpga_list) / sizeof (fpga_t); - - -ulong fpga_control (fpga_t * fpga, int cmd) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - switch (cmd) { - case FPGA_INIT_IS_HIGH: - immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */ - return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0; - - case FPGA_INIT_SET_LOW: - immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pdatd &= ~fpga->init_mask; - break; - - case FPGA_INIT_SET_HIGH: - immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pdatd |= fpga->init_mask; - break; - - case FPGA_PROG_SET_LOW: - immr->im_ioport.iop_pdatd &= ~fpga->prog_mask; - break; - - case FPGA_PROG_SET_HIGH: - immr->im_ioport.iop_pdatd |= fpga->prog_mask; - break; - - case FPGA_DONE_IS_HIGH: - return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0; - - case FPGA_READ_MODE: - break; - - case FPGA_LOAD_MODE: - break; - - case FPGA_GET_ID: - if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) { - ulong ver = - *(volatile ulong *) (fpga->conf_base + 0x10); - return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0); - } else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) { - return (*(volatile ushort *) fpga->conf_base) & 0xff; - } else { - return *(volatile ulong *) fpga->conf_base; - } - - case FPGA_INIT_PORTS: - immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */ - immr->im_ioport.iop_psord &= ~fpga->init_mask; - immr->im_ioport.iop_pdird &= ~fpga->init_mask; - - immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */ - immr->im_ioport.iop_psord &= ~fpga->prog_mask; - immr->im_ioport.iop_pdird |= fpga->prog_mask; - - immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */ - immr->im_ioport.iop_psord &= ~fpga->done_mask; - immr->im_ioport.iop_pdird &= ~fpga->done_mask; - - break; - - } - return 0; -} diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c deleted file mode 100644 index 461b56e3ff..0000000000 --- a/board/siemens/SCM/scm.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#include "scm.h" - -DECLARE_GLOBAL_DATA_PTR; - -static void config_scoh_cs(void); -extern int fpga_init(void); - -#if 0 -#define DEBUGF(fmt,args...) printf (fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, - /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */ - /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */ - /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */ - /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */ - /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */ - /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */ - /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */ - /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, - /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */ - /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */ - /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */ - /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, - /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */ - /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */ - /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */ - /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */ - /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */ - /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */ - /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */ - /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */ - /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */ - /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */ - /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */ - /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC19 */ { 0, 1, 0, 0, 0, 0 }, - /* PC18 */ { 0, 1, 0, 0, 0, 0 }, - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, - /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */ - /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */ - }, - - /* Port D configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, - /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */ - /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */ - /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */ - /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */ - /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */ - /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */ - /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */ -#if defined(CONFIG_SOFT_I2C) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */ - /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */ - /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */ - /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, - /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */ - /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "TQM8260", 7)) { - puts ("### No HW ID - assuming TQM8260\n"); - return (0); - } - - puts (str); - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -/* - * Test Power-On-Reset. - */ -int power_on_reset (void) -{ - /* Test Reset Status Register */ - return gd->reset_status & RSR_CSRS ? 0 : 1; -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize, lsize; - - psize = 16 * 1024 * 1024; - lsize = 0; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#if 0 /* Just for debugging */ -#define prt_br_or(brX,orX) do { \ - ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ - ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ - printf ("\n" \ - #brX " 0x%08x " #orX " 0x%08x " \ - "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ - memctl->memc_ ## brX, memctl->memc_ ## orX, \ - start, start+sizem, (sizem+1)>>20); \ - } while (0) - prt_br_or (br0, or0); - prt_br_or (br1, or1); - prt_br_or (br2, or2); - prt_br_or (br3, or3); -#endif - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - - /* Local SDRAM setup: - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CONFIG_SYS_LSRT; - size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) SDRAM_BASE2_PRELIM); - - if (size8 < size9) { - lsize = size9; - printf ("Local:9COL - %ld MB) using ", lsize >> 20); - } else { - lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - printf ("Local:8COL - %ld MB) using ", lsize >> 20); - } - -#if 0 - /* Set up BR2 so that the local SDRAM goes - * right after the 60x SDRAM - */ - memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | - (CONFIG_SYS_SDRAM_BASE + psize); -#endif -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - config_scoh_cs (); - - return (psize); -} - -/* ------------------------------------------------------------------------- */ - -static void config_scoh_cs (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE; - __maybe_unused volatile uint tmp, i; - - /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ - memctl->memc_or3 = CONFIG_SYS_CAN0_OR3; - memctl->memc_br3 = CONFIG_SYS_CAN0_BR3; - /* Initialize OR4 / BR4 for CAN Bus Controller 1 */ - memctl->memc_or4 = CONFIG_SYS_CAN1_OR4; - memctl->memc_br4 = CONFIG_SYS_CAN1_BR4; - - /* Initialize MAMR to write in the array at address 0x0 */ - memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS; - - /* Initialize UPMA for CAN: single read */ - memctl->memc_mdr = 0xcffeec00; - udelay (1); /* Necessary to have the data correct in the UPM array!!!! */ - /* The read on the CAN controller write the data of mdr in UPMA array. */ - /* The index to the array will be incremented automatically - through this read */ - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcfc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x0ffcfc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0xfffdec07; - udelay (1); - tmp = can->cpu_interface; - - - /* Initialize MAMR to write in the array at address 0x18 */ - memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS; - - /* Initialize UPMA for CAN: single write */ - memctl->memc_mdr = 0xfcffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00ffec00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00fffc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x00fffc00; - udelay (1); - tmp = can->cpu_interface; - - memctl->memc_mdr = 0x30ffec07; - udelay (1); - tmp = can->cpu_interface; - - /* Initialize MAMR */ - memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */ - - - /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */ - memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5; - memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5; - /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */ - memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6; - memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6; - - /* Initialize OR7 / BR7 for the Glue Logic */ - memctl->memc_or7 = CONFIG_SYS_FIOX_OR7; - memctl->memc_br7 = CONFIG_SYS_FIOX_BR7; - - /* Initialize OR8 / BR8 for the DOH Logic */ - memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8; - memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8; - - DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0); - DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1); - DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2); - DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3); - DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4); - DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5); - DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6); - DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7); - DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8); - - DEBUGF ("UPMA addr 0x0\n"); - memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS; - for (i = 0; i < 0x8; i++) { - tmp = can->cpu_interface; - udelay (1); - DEBUGF (" %08x ", memctl->memc_mdr); - } - DEBUGF ("\nUPMA addr 0x18\n"); - memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS; - for (i = 0; i < 0x8; i++) { - tmp = can->cpu_interface; - udelay (1); - DEBUGF (" %08x ", memctl->memc_mdr); - } - DEBUGF ("\n"); - memctl->memc_mamr = MxMR_GPL_x4DIS; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - fpga_init (); - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/SCM/scm.h b/board/siemens/SCM/scm.h deleted file mode 100644 index cb5e03e581..0000000000 --- a/board/siemens/SCM/scm.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SCM_H -#define __SCM_H - -/*----------------*/ -/* CAN Structures */ -/*----------------*/ - -/* Message */ -struct can_msg { - uchar ctrl_0; - uchar ctrl_1; - uchar arbit_0; - uchar arbit_1; - uchar arbit_2; - uchar arbit_3; - uchar config; - uchar data[8]; -} __attribute__ ((packed)); - -typedef struct can_msg can_msg_t; - -/* CAN Register */ -typedef struct can_reg { - uchar ctrl; - uchar status; - uchar cpu_interface; - uchar resv0; - ushort high_speed_rd; - ushort gbl_mask_std; - uint gbl_mask_extd; - uint msg15_mask; - can_msg_t msg1; - uchar clkout; - can_msg_t msg2; - uchar bus_config; - can_msg_t msg3; - uchar bit_timing_0; - can_msg_t msg4; - uchar bit_timing_1; - can_msg_t msg5; - uchar interrupt; - can_msg_t msg6; - uchar resv1; - can_msg_t msg7; - uchar resv2; - can_msg_t msg8; - uchar resv3; - can_msg_t msg9; - uchar p1conf; - can_msg_t msg10; - uchar p2conf; - can_msg_t msg11; - uchar p1in; - can_msg_t msg12; - uchar p2in; - can_msg_t msg13; - uchar p1out; - can_msg_t msg14; - uchar p2out; - can_msg_t msg15; - uchar ser_res_addr; - uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */ -} can_reg_t; - - -#endif /* __SCM_H */ diff --git a/board/siemens/common/README b/board/siemens/common/README deleted file mode 100644 index 7f1c8cd62d..0000000000 --- a/board/siemens/common/README +++ /dev/null @@ -1,27 +0,0 @@ -CCM/SCM-Ergaenzungen fuer U-Boot und Linux: -------------------------------------------- - -Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs: - - => help fpga - fpga fpga status [name] - print FPGA status - fpga reset [name] - reset FPGA - fpga load [name] addr - load FPGA configuration data - -Der Name kann beim CCM-Module auch weggelassen werden. -Die Laengenangabe und damit "puma_len" ist nicht mehr -noetig: - - => fpga load puma 40600000 - FPGA load PUMA: addr 40600000: (00000005)... done - -Die MTD-Partitionierung kann nun mittels "bootargs" ueber- -geben werden: - - => printenv addmtd - addmtd=setenv bootargs ${bootargs} - mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2) - -Die Portierung auf SMC ist natuerlich noch nicht getestet. - -Wolfgang Grandegger (04.06.2002) diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c deleted file mode 100644 index ef8bfde7f1..0000000000 --- a/board/siemens/common/fpga.c +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include - -#include "fpga.h" - -int power_on_reset(void); - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - - -static int fpga_get_version(fpga_t* fpga, char* name) -{ - char vname[12]; - /* - * Net-list string format: - * "vvvvvvvvddddddddn...". - * Version Date Name - * "0000000322042002PUMA" = PUMA version 3 from 22.04.2002. - */ - if (strlen(name) < (16 + strlen(fpga->name))) - goto failure; - /* Check FPGA name */ - if (strcmp(&name[16], fpga->name) != 0) - goto failure; - /* Get version number */ - memcpy(vname, name, 8); - vname[8] = '\0'; - return simple_strtoul(vname, NULL, 16); - - failure: - printf("Image name %s is invalid\n", name); - return -1; -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static fpga_t* fpga_get(char* fpga_name) -{ - char name[FPGA_NAME_LEN]; - int i; - - if (strlen(fpga_name) >= FPGA_NAME_LEN) - goto failure; - for (i = 0; i < strlen(fpga_name); i++) - name[i] = toupper(fpga_name[i]); - name[i] = '\0'; - for (i = 0; i < fpga_count; i++) { - if (strcmp(name, fpga_list[i].name) == 0) - return &fpga_list[i]; - } - failure: - printf("FPGA: name %s is invalid\n", fpga_name); - return NULL; -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void fpga_status (fpga_t* fpga) -{ - /* Check state */ - if (fpga_control(fpga, FPGA_DONE_IS_HIGH)) - printf ("%s is loaded (%08lx)\n", - fpga->name, fpga_control(fpga, FPGA_GET_ID)); - else - printf ("%s is NOT loaded\n", fpga->name); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */ - -static int fpga_reset (fpga_t* fpga) -{ - int i; - - /* Set PROG to low and wait til INIT goes low */ - fpga_control(fpga, FPGA_PROG_SET_LOW); - for (i = 0; i < FPGA_RESET_TIMEOUT; i++) { - udelay (100); - if (!fpga_control(fpga, FPGA_INIT_IS_HIGH)) - break; - } - if (i == FPGA_RESET_TIMEOUT) - goto failure; - - /* Set PROG to high and wait til INIT goes high */ - fpga_control(fpga, FPGA_PROG_SET_HIGH); - for (i = 0; i < FPGA_RESET_TIMEOUT; i++) { - udelay (100); - if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) - break; - } - if (i == FPGA_RESET_TIMEOUT) - goto failure; - - return 0; - failure: - return 1; -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */ - -static int fpga_load (fpga_t* fpga, ulong addr, int checkall) -{ - volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base; - image_header_t *hdr = (image_header_t *)addr; - ulong len; - uchar *data; - char msg[32]; - int verify, i; - -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* - * Check the image header and data of the net-list - */ - if (!image_check_magic (hdr)) { - strcpy (msg, "Bad Image Magic Number"); - goto failure; - } - - if (!image_check_hcrc (hdr)) { - strcpy (msg, "Bad Image Header CRC"); - goto failure; - } - - data = (uchar*)image_get_data (hdr); - len = image_get_data_size (hdr); - - verify = getenv_yesno ("verify"); - if (verify) { - if (!image_check_dcrc (hdr)) { - strcpy (msg, "Bad Image Data CRC"); - goto failure; - } - } - - if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0) - return 1; - - /* align length */ - if (len & 1) - ++len; - - /* - * Reset FPGA and wait for completion - */ - if (fpga_reset(fpga)) { - strcpy (msg, "Reset Timeout"); - goto failure; - } - - printf ("(%s)... ", image_get_name (hdr)); - /* - * Copy data to FPGA - */ - fpga_control (fpga, FPGA_LOAD_MODE); - while (len--) { - *fpga_addr = *data++; - } - fpga_control (fpga, FPGA_READ_MODE); - - /* - * Wait for completion and check error status if timeout - */ - for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) { - udelay (100); - if (fpga_control (fpga, FPGA_DONE_IS_HIGH)) - break; - } - if (i == FPGA_LOAD_TIMEOUT) { - if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) - strcpy(msg, "Invalid Size"); - else - strcpy(msg, "CRC Error"); - goto failure; - } - - printf("done\n"); - return 0; - - failure: - - printf("ERROR: %s\n", msg); - return 1; -} - -#if defined(CONFIG_CMD_BSP) - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr = 0; - int i; - fpga_t* fpga; - - if (argc < 2) - goto failure; - - if (strncmp(argv[1], "stat", 4) == 0) { /* status */ - if (argc == 2) { - for (i = 0; i < fpga_count; i++) { - fpga_status (&fpga_list[i]); - } - } - else if (argc == 3) { - if ((fpga = fpga_get(argv[2])) == 0) - goto failure; - fpga_status (fpga); - } - else - goto failure; - } - else if (strcmp(argv[1],"load") == 0) { /* load */ - if (argc == 3 && fpga_count == 1) { - fpga = &fpga_list[0]; - } - else if (argc == 4) { - if ((fpga = fpga_get(argv[2])) == 0) - goto failure; - } - else - goto failure; - - addr = simple_strtoul(argv[argc-1], NULL, 16); - - printf ("FPGA load %s: addr %08lx: ", - fpga->name, addr); - fpga_load (fpga, addr, 1); - - } - else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */ - if (argc == 2 && fpga_count == 1) { - fpga = &fpga_list[0]; - } - else if (argc == 3) { - if ((fpga = fpga_get(argv[2])) == 0) - goto failure; - } - else - goto failure; - - printf ("FPGA reset %s: ", fpga->name); - if (fpga_reset(fpga)) - printf ("ERROR: Timeout\n"); - else - printf ("done\n"); - } - else - goto failure; - - return 0; - - failure: - return cmd_usage(cmdtp); -} - -U_BOOT_CMD( - fpga, 4, 1, do_fpga, - "access FPGA(s)", - "fpga status [name] - print FPGA status\n" - "fpga reset [name] - reset FPGA\n" - "fpga load [name] addr - load FPGA configuration data" -); - -#endif - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -int fpga_init (void) -{ - ulong addr; - ulong new_id, old_id = 0; - image_header_t *hdr; - fpga_t* fpga; - int do_load, i, j; - char name[16], *s; - - /* - * Port setup for FPGA control - */ - for (i = 0; i < fpga_count; i++) { - fpga_control(&fpga_list[i], FPGA_INIT_PORTS); - } - - /* - * Load FPGA(s): a new net-list is loaded if the FPGA is - * empty, Power-on-Reset or the old one is not up-to-date - */ - for (i = 0; i < fpga_count; i++) { - fpga = &fpga_list[i]; - printf ("%s: ", fpga->name); - - for (j = 0; j < strlen(fpga->name); j++) - name[j] = tolower(fpga->name[j]); - name[j] = '\0'; - sprintf(name, "%s_addr", name); - addr = 0; - if ((s = getenv(name)) != NULL) - addr = simple_strtoul(s, NULL, 16); - - if (!addr) { - printf ("env. variable %s undefined\n", name); - return 1; - } - - hdr = (image_header_t *)addr; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1) - return 1; - - do_load = 1; - - if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) { - old_id = fpga_control(fpga, FPGA_GET_ID); - if (new_id == old_id) - do_load = 0; - } - - if (do_load) { - printf ("loading "); - fpga_load (fpga, addr, 0); - } else { - printf ("loaded (%08lx)\n", old_id); - } - } - - return 0; -} diff --git a/board/siemens/common/fpga.h b/board/siemens/common/fpga.h deleted file mode 100644 index 2de25b0146..0000000000 --- a/board/siemens/common/fpga.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#ifndef _FPGA_H_ -#define _FPGA_H_ - -#define FPGA_INIT_IS_HIGH 0 -#define FPGA_INIT_SET_HIGH 1 -#define FPGA_INIT_SET_LOW 2 -#define FPGA_PROG_SET_HIGH 3 -#define FPGA_PROG_SET_LOW 4 -#define FPGA_DONE_IS_HIGH 5 -#define FPGA_READ_MODE 6 -#define FPGA_LOAD_MODE 7 -#define FPGA_GET_ID 8 -#define FPGA_INIT_PORTS 9 - -#define FPGA_NAME_LEN 8 -typedef struct { - char name[FPGA_NAME_LEN]; - ulong conf_base; - uint init_mask; - uint prog_mask; - uint done_mask; -} fpga_t; - -extern fpga_t fpga_list[]; -extern int fpga_count; - -ulong fpga_control (fpga_t* fpga, int cmd); - -#endif /* _FPGA_H_ */ diff --git a/board/westel/amx860/Makefile b/board/westel/amx860/Makefile deleted file mode 100644 index 12e4aa6880..0000000000 --- a/board/westel/amx860/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c deleted file mode 100644 index 91dcc0dcb3..0000000000 --- a/board/westel/amx860/amx860.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint edo_60ns[] = -{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, - 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_, - 0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08, - 0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48, - 0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, - 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, - 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ }; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: AMX860\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */ - - upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint)); - -#ifndef CONFIG_AMX_RAM_EXT - memctl->memc_mptpr = 0x0400; /* divide by 16 */ -#else - memctl->memc_mptpr = 0x0200; -#endif - - memctl->memc_mamr = 0x30a21114; - memctl->memc_or2 = 0xffc00800; -#ifndef CONFIG_AMX_RAM_EXT - memctl->memc_br2 = 0x81; - - return (4 << 20); -#else - memctl->memc_or1 = 0xff000800; - memctl->memc_br1 = 0x00000081; - memctl->memc_br2 = 0x01000081; - - return (20 << 20); -#endif -} diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c deleted file mode 100644 index fe8bce412b..0000000000 --- a/board/westel/amx860/flash.c +++ /dev/null @@ -1,637 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } -#else - size_b1 = 0; -#endif /* FLASH_BASE1_PRELIM */ - - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - DEBUGF("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_info[1].size = size_b1; - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -# endif - -# ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - } else { -#ifndef CONFIG_AMX_RAM_EXT - memctl->memc_br1 = 0; /* invalidate bank */ - memctl->memc_or1 = 0; /* invalidate bank */ -#endif - - DEBUGF("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - } - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00040000); - } - } else if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds deleted file mode 100644 index 9b69d3d1e6..0000000000 --- a/board/westel/amx860/u-boot.lds +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - net/libnet.o (.text*) - board/westel/amx860/libamx860.o (.text*) - *(.text.*printf) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug deleted file mode 100644 index 3e075a85bd..0000000000 --- a/board/westel/amx860/u-boot.lds.debug +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - #include - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end__ = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index 4c63789041..0ecd1b8ea1 100644 --- a/boards.cfg +++ b/boards.cfg @@ -625,7 +625,6 @@ PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freesca VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz mgcoge powerpc mpc8260 km82xx keymile - km82xx:MGCOGE mgcoge3ne powerpc mpc8260 km82xx keymile - km82xx:MGCOGE3NE -SCM powerpc mpc8260 - siemens TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz TQM8260_AB powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x @@ -861,11 +860,8 @@ Adder87x powerpc mpc8xx adder - AdderII powerpc mpc8xx adder - - Adder:MPC852T AdderUSB powerpc mpc8xx adder - - Adder ADS860 powerpc mpc8xx fads -c2mon powerpc mpc8xx cogent_mpc8xx powerpc mpc8xx cogent -EP88x powerpc mpc8xx ep88x ESTEEM192E powerpc mpc8xx esteem192e -ETX094 powerpc mpc8xx etx094 FADS823 powerpc mpc8xx fads FADS850SAR powerpc mpc8xx fads FADS860T powerpc mpc8xx fads @@ -883,7 +879,6 @@ IVML24_256 powerpc mpc8xx ivm - IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M -LANTEC powerpc mpc8xx lantec lwmon powerpc mpc8xx MBX powerpc mpc8xx mbx8xx MBX860T powerpc mpc8xx mbx8xx @@ -930,7 +925,6 @@ KUP4K powerpc mpc8xx kup4k kup KUP4X powerpc mpc8xx kup4x kup ELPT860 powerpc mpc8xx elpt860 LEOX uc100 powerpc mpc8xx - manroland -IAD210 powerpc mpc8xx - siemens QS823 powerpc mpc8xx qs850 snmc QS850 powerpc mpc8xx qs850 snmc QS860T powerpc mpc8xx qs860t snmc @@ -956,7 +950,6 @@ TQM885D powerpc mpc8xx tqm8xx tqc TTTech powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ104V7DS01 virtlab2 powerpc mpc8xx tqm8xx tqc wtk powerpc mpc8xx tqm8xx tqc - TQM823L:LCD,SHARP_LQ065T9DR51U -AMX860 powerpc mpc8xx amx860 westel csb272 powerpc ppc4xx csb472 powerpc ppc4xx G2000 powerpc ppc4xx g2000 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index ed779e245f..2b868e6515 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,12 @@ easily if here is something they might want to dig for... Board Arch CPU removed Commit last known maintainer/contact ============================================================================= +AMX860 powerpc mpc860 - - Wolfgang Denk +c2mon powerpc mpc855 - - Wolfgang Denk +ETX094 powerpc mpc850 - - Wolfgang Denk +IAD210 powerpc mpc860 - - - +LANTEC powerpc mpc850 - - Wolfgang Denk +SCM powerpc mpc8260 - - Wolfgang Grandegger SX1 arm arm925t - - TQM85xx powerpc MPC85xx d923a5d5 2012-10-04 Stefan Roese apollon arm omap24xx 535c74f 2012-09-18 Kyungmin Park diff --git a/include/commproc.h b/include/commproc.h index 8b8cc45dad..7ca28c8369 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -466,39 +466,6 @@ typedef struct scc_enet { #endif /* MPC860ADS */ -/*** AMX860 **********************************************/ - -#if defined(CONFIG_AMX860) - -/* This ENET stuff is for the AMX860 with ethernet on SCC1. - */ - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0800) - -#define PB_ENET_TENA ((uint)0x00001000) - -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003e) - -/* 68160 PHY control */ - -#define PB_ENET_ETHLOOP ((uint)0x00020000) -#define PB_ENET_TPFLDL ((uint)0x00010000) -#define PB_ENET_TPSQEL ((uint)0x00008000) -#define PD_ENET_ETH_EN ((ushort)0x0004) - -#endif /* CONFIG_AMX860 */ - /*** BSEIP **********************************************************/ #ifdef CONFIG_BSEIP @@ -547,38 +514,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00003400) #endif /* CONFIG_FLAGADM */ -/*** C2MON **********************************************************/ - -#ifdef CONFIG_C2MON - -# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */ -# error "Ethernet on SCC not supported on C2MON Board!" -# else /* Use FEC for Fast Ethernet */ - -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_C2MON */ - -/*********************************************************************/ - /*** ELPT860 *********************************************************/ #ifdef CONFIG_ELPT860 @@ -828,33 +763,6 @@ typedef struct scc_enet { #endif /* CONFIG_HERMES */ -/*** IAD210 **********************************************************/ - -/* The IAD210 uses the FEC on a MPC860P for Ethernet */ - -#if defined(CONFIG_IAD210) - -# define FEC_ENET /* use FEC for Ethernet */ -# undef SCC_ENET - -# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */ -# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */ -# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */ -# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */ -# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */ -# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */ -# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */ -# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */ -# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */ -# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */ -# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */ -# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */ -# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */ - -# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */ - -#endif /* CONFIG_IAD210 */ - /*** ICU862 **********************************************************/ #if defined(CONFIG_ICU862) @@ -954,34 +862,6 @@ typedef struct scc_enet { #endif /* CONFIG_KUP4K */ - -/*** LANTEC *********************************************************/ - -#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2 -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000FF00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) -#endif /* CONFIG_LANTEC v2 */ - /*** LWMON **********************************************************/ #if defined(CONFIG_LWMON) @@ -1373,15 +1253,14 @@ typedef struct scc_enet { #endif /* CONFIG_SXNI855T */ -/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ +/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ - defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ - defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ - defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ - (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) + defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \ + defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ + defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \ + defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h deleted file mode 100644 index e7a6c80f62..0000000000 --- a/include/configs/AMX860.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_AMX860 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */ -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_SCC2 1 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 10 /* Multiply by 10 */ -#define MPC8XX_XIN 5000000 /* 5 MHz in */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" /* autoboot command */ - -#undef CONFIG_BOOTARGS - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * U-Boot for AMX board supports two types of memory extension - * modules: one that provides 4 MB flash memory, and another one with - * 16 MB EDO DRAM. - * - * The flash module swaps the CS0 and CS1 signals: if the module is - * installed, CS0 is connected to Flash on the module and CS1 is - * connected to the on-board Flash. This means that you must intall - * U-Boot when the Flash module is plugged in, if you plan to use - * it. - * - * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT - * must be defined. The DRAM module uses CS1. - * - * Only one of these modules may be installed at a time. If U-Boot - * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not - * work if the Flash extension module is installed instead of the - * DRAM module. - */ -#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - * - * Use 4 MB for without and 8 MB with 16 MB DRAM extension module - * (CONFIG_AMX_RAM_EXT) - */ -#ifdef CONFIG_AMX_RAM_EXT -# define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#else -# define CONFIG_SYS_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */ -#endif -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#ifndef CONFIG_AMX_RAM_EXT -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ -#endif - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_SYS_OR0_PRELIM 0xFFC00954 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ - -#ifndef CONFIG_AMX_RAM_EXT -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM 0xFFC00954 /* Real values for the board */ -#define CONFIG_SYS_BR1_PRELIM 0x60000001 /* Real values for the board */ -#endif - -/* DSP ("Glue") Xilinx */ -#define CONFIG_SYS_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */ -#define CONFIG_SYS_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h deleted file mode 100644 index 2703625677..0000000000 --- a/include/configs/ETX094.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_ETX094 1 /* ...on a ETX_094 board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 57600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ -#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ -#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ - -#define CONFIG_ETHADDR 08:00:06:00:00:00 - -#ifdef CONFIG_ETHADDR -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */ -#endif - -#undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \ - "U-Boot_version=U-Boot-1.0.x-Date " \ - "panic=1 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#define CONFIG_NFSBOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#ifdef DEBUG -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#ifdef CONFIG_FLASH_16BIT -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ -#else -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ - OR_SCY_2_CLK | OR_TRLX ) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) -#else /* 32 bit data port */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) -#endif /* CONFIG_FLASH_16BIT */ - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 23 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h deleted file mode 100644 index 94b05dce41..0000000000 --- a/include/configs/IAD210.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - -# ifdef DEBUG -# warning DEBUG Defined -# endif /* DEBUG */ - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_IAD210 1 /* ...on a IAD210 module */ -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_SYS_TEXT_BASE 0x08000000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#undef CONFIG_8xx_CONS_SMC1 -#undef CONFIG_8xx_CONS_SMC2 -#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 - - -# define MPC8XX_FACT 16 -# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */ -# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#if 0 -# define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -/* using this define saves us updating another source file */ -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R - -#undef CONFIG_BOOTARGS -/* #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" -*/ - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs" \ - "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -# define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -# define CONFIG_MII 1 -# define CONFIG_SYS_DISCOVER_PHY 1 -# define CONFIG_FEC_UTOPIA 1 -# define CONFIG_ETHADDR 08:00:06:26:A2:6D -# define CONFIG_IPADDR 192.168.28.128 -# define CONFIG_SERVERIP 139.10.137.138 -# define CONFIG_SYS_DISCOVER_PHY 1 - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -# define CONFIG_SYS_I2C_SPEED 50000 -# define CONFIG_SYS_I2C_SLAVE 0xDD -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if defined(DEBUG) -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif - -# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CONFIG_SYS_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0xF8000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xF8000000 /* OR addr mask */ - -/* FLASH timing: - TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ - OR_SCY_3_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 124 /* start with divider for 64 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X) - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h deleted file mode 100644 index c3855c332c..0000000000 --- a/include/configs/LANTEC.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) Copyright 2001 - * Torsten Stevens, FHG IMS, stevens@ims.fhg.de - * Bruno Achauer, Exet AG, bruno@exet-ag.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - * [derived from config_TQM850L.h] - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -/* - * Port assignments (CONFIG_LANTEC == 1): - * - SMC1: J11 (MDB) ? - * - SMC2: J6 (Feature connector) - * - SCC2: J9 (RJ45) - * - SCC3: J8 (Sub-D9) - * - * Port assignments (CONFIG_LANTEC == 2): TBD - */ - - -#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ -#define CONFIG_8xx_CONS_SCC3 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_XIMG - -#if !(CONFIG_LANTEC >= 2) - #undef CONFIG_CMD_DATE - #undef CONFIG_CMD_NET -#endif - - -#if CONFIG_LANTEC >= 2 -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK) - -/*----------------------------------------------------------------------- - * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX] - *----------------------------------------------------------------------- - */ -#define CONFIG_8xx_GCLK_FREQ 33000000 - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ - /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 - /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/5 and OR0/5 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ - OR_SCY_5_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR5_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM) - -#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * Memory Periodic Timer Prescaler - */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL \ - ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h deleted file mode 100644 index 87d52babe6..0000000000 --- a/include/configs/SCM.h +++ /dev/null @@ -1,710 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#define CONFIG_SCM 1 /* ...on a System Controller Module */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#if (CONFIG_TQM8260 <= 100) -# error "TQM8260 module revison not supported" -#endif - -/* We use a TQM8260 module with a 300MHz CPU */ -#define CONFIG_300MHz - -/* Define 60x busmode only if your TQM8260 has L2 cache! */ -#ifdef CONFIG_L2_CACHE -# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ -#else -# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ -#endif - -/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ -#ifdef CONFIG_300MHz -# define CONFIG_BUSMODE_60x -#endif - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK12 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifndef CONFIG_300MHz -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 83333000 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_BSP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#define CONFIG_SYS_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 2048 -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if defined(CONFIG_266MHz) -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0111) -#elif defined(CONFIG_300MHz) -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0110) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#define CONFIG_SYS_CAN0_BASE 0xc0000000 -#define CONFIG_SYS_CAN1_BASE 0xc0008000 -#define CONFIG_SYS_FIOX_BASE 0xc0010000 -#define CONFIG_SYS_FDOHM_BASE 0xc0018000 -#define CONFIG_SYS_EXTPROM_BASE 0xc2000000 - -#define CONFIG_SYS_CAN_SIZE 0x00000100 -#define CONFIG_SYS_FIOX_SIZE 0x00000020 -#define CONFIG_SYS_FDOHM_SIZE 0x00002000 -#define CONFIG_SYS_EXTPROM_BANK_SIZE 0x01000000 - -#define EXT_EEPROM_MAX_FLASH_BANKS 0x02 - -/* CS3 - CAN 0 - */ -#define CONFIG_SYS_CAN0_BR3 ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CONFIG_SYS_CAN0_OR3 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_4IDLE) - -/* CS4 - CAN 1 - */ -#define CONFIG_SYS_CAN1_BR4 ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) - -#define CONFIG_SYS_CAN1_OR4 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_4IDLE) - -/* CS5 - Extended PROM (16MB optional) - */ -#define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS6 - Extended PROM (16MB optional) - */ -#define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \ - CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS7 - FPGA FIOX: Glue Logic - */ -#define CONFIG_SYS_FIOX_BR7 ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_FIOX_OR7 (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE) |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -/* CS8 - FPGA DOH Master - */ -#define CONFIG_SYS_FDOHM_BR8 ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_FDOHM_OR8 (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE) |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - - -/* FPGA configuration */ -#define CONFIG_SYS_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ -#define CONFIG_SYS_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ -#define CONFIG_SYS_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ - -#define CONFIG_SYS_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ -#define CONFIG_SYS_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ -#define CONFIG_SYS_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h deleted file mode 100644 index 41ff00847a..0000000000 --- a/include/configs/c2mon.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_C2MON 1 /* ...on a C2MON module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_PLPRCR \ - ( (5-1)<im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | SCC_PSMR_NIB22 | SCC_PSMR_LPB; -#if 0 - /* - * Configure Ethernet TENA Signal - */ - -#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) - immr->im_ioport.iop_pcpar |= PC_ENET_TENA; - immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; -#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) - immr->im_cpm.cp_pbpar |= PB_ENET_TENA; - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; -#else -#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined -#endif - -#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) - /* - * Port C is used to control the PHY,MC68160. - */ - immr->im_ioport.iop_pcdir |= - (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); - - immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; - immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif /* MPC860ADS */ - -#if defined(CONFIG_AMX860) - /* - * Port B is used to control the PHY,MC68160. - */ - immr->im_cpm.cp_pbdir |= - (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL); - - immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL; - immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL); - - immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN; - immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; -#endif /* AMX860 */ - -#endif /* 0 */ - #ifdef CONFIG_RPXCLASSIC *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); @@ -449,7 +406,7 @@ static void scc_init (int scc_index) */ #if defined (CONFIG_FADS) udelay (10000); /* wait 10 ms */ -#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) +#elif defined(CONFIG_RPXCLASSIC) udelay (100000); /* wait 100 ms */ #endif } -- cgit v1.2.3 From 461d3800b476e34dee0924c4bd5bf490bf36784e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 24 Oct 2012 02:36:16 +0000 Subject: TQM8xx: adjust linker script to grown code size Once more, some of the previous changes caused the code to grow, which causes errors like u-boot.lds:80 cannot move location counter backwards (from 400082a4 to 40008000) when building with some older tool chains (like ELDK 4.2). Adjust the linker script to make fit again. Signed-off-by: Wolfgang Denk --- board/tqc/tqm8xx/u-boot.lds | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 7cc41cd521..e1e1ccd482 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2012 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -41,8 +41,6 @@ SECTIONS drivers/net/libnet.o (.text*) drivers/pcmcia/libpcmcia.o (.text.pcmcia_on) drivers/pcmcia/libpcmcia.o (.text.pcmcia_hardware_enable) - drivers/rtc/librtc.o (.text*) - drivers/misc/libmisc.o (.text*) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv*) -- cgit v1.2.3 From 28aa27b608bddf20a655e10c09412f93d2f83a5a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 24 Oct 2012 02:36:17 +0000 Subject: ESTEEM192E: adjust linker script to grown code size Once more, some of the previous changes caused the code to grow, which causes errors like u-boot.lds:74 cannot move location counter backwards (from 40008384 to 40008000) when building with some older tool chains (like ELDK 4.2). Adjust the linker script to make fit again. Signed-off-by: Wolfgang Denk Cc: Conn Clark --- board/esteem192e/u-boot.lds | 1 - 1 file changed, 1 deletion(-) diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 69f15000db..fe5cf095fc 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -36,7 +36,6 @@ SECTIONS arch/powerpc/cpu/mpc8xx/traps.o (.text*) net/libnet.o (.text*) board/esteem192e/libesteem192e.o (.text*) - *(.text.*printf) . = env_offset; common/env_embedded.o (.text*) -- cgit v1.2.3 From f9a2d79337c27bee516dfbadea8a72773c81a5b7 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Thu, 25 Oct 2012 14:51:42 +0800 Subject: ColdFire: Update the lds file for M54418TWR board. The M54418TWR lds file need to update since commit: 8b493a52367623f36e628e4ab2cf8ee082b655e0 common: Discard the __u_boot_cmd section The command declaration now uses the new LG-array method to generate list of commands. Thus the __u_boot_cmd section is now superseded and redundant and therefore can be removed. Also, remove externed symbols associated with this section from include/command.h . Signed-off-by: Jason Jin --- board/freescale/m54418twr/u-boot.lds | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds index f341449346..36a4c264b9 100644 --- a/board/freescale/m54418twr/u-boot.lds +++ b/board/freescale/m54418twr/u-boot.lds @@ -66,9 +66,11 @@ SECTIONS PROVIDE (edata = .); . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + + . = ALIGN(4); + .u_boot_list : { + #include + } . = .; __start___ex_table = .; -- cgit v1.2.3 From b765fce95c58b5a7da44b89eb754e66880ecd7f1 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Thu, 25 Oct 2012 15:27:37 +0800 Subject: ColdFire: Remove save env in NAND support for M54418TWR board. This patch remove the env saving in NAND as so far the NAND driver is not ported to the M54418TWR platform. Signed-off-by: Jason Jin --- include/configs/M54418TWR.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 6c96111a7e..3be2f8ef33 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -350,7 +350,7 @@ #endif #if defined(CONFIG_SYS_NAND_BOOT) #define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_OFFSET 0x80000 #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 -- cgit v1.2.3 From 73286d8729c0a2325911719492218477caa2c58e Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Wed, 3 Oct 2012 04:26:28 +0000 Subject: tegra: move common features to a common makefile For Non-Nvidia boards to include newly added features (like emc clock scaling) it would be necessary to add each feature to their own board Makefile. This is because currently the top Makefile automaticly includes these features only for Nvidia boards. This patch adds a simple Makefile include so all new features become available for non-Nvidia board vendors. Cc: Stephen Warren Cc: Tom Warren Cc: Thierry Reding Cc: Lucas Stach Signed-off-by: Marc Dietrich Acked-by: Stephen Warren Acked-by: Thierry Reding Signed-off-by: Tom Warren --- board/avionic-design/medcom-wide/Makefile | 6 ++++-- board/avionic-design/plutux/Makefile | 6 ++++-- board/avionic-design/tec/Makefile | 6 ++++-- board/compal/paz00/Makefile | 6 ++++-- board/compulab/trimslice/Makefile | 6 ++++-- board/nvidia/common/Makefile | 4 +--- board/nvidia/common/common.mk | 4 ++++ 7 files changed, 25 insertions(+), 13 deletions(-) create mode 100644 board/nvidia/common/common.mk diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile index 864bc0ec01..e8c1e8b287 100644 --- a/board/avionic-design/medcom-wide/Makefile +++ b/board/avionic-design/medcom-wide/Makefile @@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) LIB = $(obj)lib$(BOARD).o -COBJS := ../../nvidia/common/board.o -COBJS += ../common/tamonten.o +COBJS-y := ../common/tamonten.o +include ../../nvidia/common/common.mk + +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index 864bc0ec01..e8c1e8b287 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) LIB = $(obj)lib$(BOARD).o -COBJS := ../../nvidia/common/board.o -COBJS += ../common/tamonten.o +COBJS-y := ../common/tamonten.o +include ../../nvidia/common/common.mk + +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index 864bc0ec01..e8c1e8b287 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -29,9 +29,11 @@ $(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) LIB = $(obj)lib$(BOARD).o -COBJS := ../../nvidia/common/board.o -COBJS += ../common/tamonten.o +COBJS-y := ../common/tamonten.o +include ../../nvidia/common/common.mk + +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index 7f7287ee9a..fa5c510340 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -20,9 +20,11 @@ $(shell mkdir -p $(obj)../../nvidia/common) LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o -COBJS += ../../nvidia/common/board.o +COBJS-y := $(BOARD).o +include ../../nvidia/common/common.mk + +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index ff0787967d..cc844d2e07 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -28,9 +28,11 @@ $(shell mkdir -p $(obj)../../nvidia/common) LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o -COBJS += ../../nvidia/common/board.o +COBJS-y := $(BOARD).o +include ../../nvidia/common/common.mk + +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile index a93d4583e7..f6f419e0ce 100644 --- a/board/nvidia/common/Makefile +++ b/board/nvidia/common/Makefile @@ -25,9 +25,7 @@ endif LIB = $(obj)lib$(VENDOR).o -COBJS-y += board.o -COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o -COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +include common.mk COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk new file mode 100644 index 0000000000..bd6202c299 --- /dev/null +++ b/board/nvidia/common/common.mk @@ -0,0 +1,4 @@ +# common options for all tegra boards +COBJS-y += ../../nvidia/common/board.o +COBJS-$(CONFIG_SPI_UART_SWITCH) += ../../nvidia/common/uart-spi-switch.o +COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o -- cgit v1.2.3 From 6bbda88384948808dd4050624a6c27d6d63265a1 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 7 Oct 2012 11:36:06 +0000 Subject: tegra: add Colibri T20 board support This adds board support for the Toradex Colibri T20 module. Working functions: - SD card boot - USB boot - Network - NAND environment Signed-off-by: Lucas Stach Signed-off-by: Tom Warren --- MAINTAINERS | 4 ++ .../colibri_t20-common/colibri_t20-common.c | 44 ++++++++++++ .../colibri_t20-common/colibri_t20-common.h | 16 +++++ board/toradex/colibri_t20_iris/Makefile | 40 +++++++++++ board/toradex/colibri_t20_iris/colibri_t20_iris.c | 46 ++++++++++++ board/toradex/dts/tegra20-colibri_t20_iris.dts | 38 ++++++++++ boards.cfg | 1 + include/configs/colibri_t20_iris.h | 83 ++++++++++++++++++++++ 8 files changed, 272 insertions(+) create mode 100644 board/toradex/colibri_t20-common/colibri_t20-common.c create mode 100644 board/toradex/colibri_t20-common/colibri_t20-common.h create mode 100644 board/toradex/colibri_t20_iris/Makefile create mode 100644 board/toradex/colibri_t20_iris/colibri_t20_iris.c create mode 100644 board/toradex/dts/tegra20-colibri_t20_iris.dts create mode 100644 include/configs/colibri_t20_iris.h diff --git a/MAINTAINERS b/MAINTAINERS index 1b2da9421a..5a500c5a24 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -902,6 +902,10 @@ Michal Simek zynq ARM ARMV7 (Zynq SoC) +Lucas Stach + + colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core) + Nick Thompson da830evm ARM926EJS (DA830/OMAP-L137) diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20-common/colibri_t20-common.c new file mode 100644 index 0000000000..6d5e47d38e --- /dev/null +++ b/board/toradex/colibri_t20-common/colibri_t20-common.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Lucas Stach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#include "colibri_t20-common.h" + +#ifdef CONFIG_USB_EHCI_TEGRA +void colibri_t20_common_pin_mux_usb(void) +{ + /* module internal USB bus to connect ethernet chipset */ + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + /* ULPI reference clock output */ + pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PINGRP_CDEV2); + /* PHY reset GPIO */ + pinmux_tristate_disable(PINGRP_UAC); + /* VBus GPIO */ + pinmux_tristate_disable(PINGRP_DTE); +} +#endif + +#ifdef CONFIG_TEGRA_NAND +void pin_mux_nand(void) +{ + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); +} +#endif diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.h b/board/toradex/colibri_t20-common/colibri_t20-common.h new file mode 100644 index 0000000000..76dc8608d5 --- /dev/null +++ b/board/toradex/colibri_t20-common/colibri_t20-common.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2012 Lucas Stach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +void colibri_t20_common_pin_mux_usb(void); diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile new file mode 100644 index 0000000000..c138729a48 --- /dev/null +++ b/board/toradex/colibri_t20_iris/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2012 Lucas Stach +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# + +include $(TOPDIR)/config.mk + +$(shell mkdir -p $(obj)../../nvidia/common) +$(shell mkdir -p $(obj)../colibri_t20-common) + +LIB = $(obj)lib$(BOARD).o + +COBJS := ../../nvidia/common/board.o +COBJS += ../colibri_t20-common/colibri_t20-common.o +COBJS += $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c new file mode 100644 index 0000000000..e40a98609f --- /dev/null +++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2012 Lucas Stach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../colibri_t20-common/colibri_t20-common.h" + +#ifdef CONFIG_USB_EHCI_TEGRA +void pin_mux_usb(void) +{ + colibri_t20_common_pin_mux_usb(); + + /* USB 1 aka Tegra USB port 3 VBus*/ + pinmux_tristate_disable(PINGRP_SPIG); +} +#endif + +#ifdef CONFIG_TEGRA_MMC +int board_mmc_init(bd_t *bd) +{ + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + pinmux_tristate_disable(PINGRP_GMB); + + tegra_mmc_init(0, 4, -1, GPIO_PC7); + + return 0; +} +#endif diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts new file mode 100644 index 0000000000..c29b43a0ef --- /dev/null +++ b/board/toradex/dts/tegra20-colibri_t20_iris.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Toradex Colibri T20"; + compatible = "toradex,t20", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + usb2 = "/usb@c5004000"; + }; + + usb@c5000000 { + dr_mode = "otg"; + }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */ + nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */ + }; + + usb@c5008000 { + nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */ + }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */ + nvidia,width = <8>; + nvidia,timing = <15 100 25 80 25 10 15 10 100>; + + nand@0 { + reg = <0>; + compatible = "nand-flash"; + }; + }; +}; diff --git a/boards.cfg b/boards.cfg index 4c63789041..c45556e8fd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -278,6 +278,7 @@ harmony arm armv7:arm720t harmony nvidia seaboard arm armv7:arm720t seaboard nvidia tegra20 ventana arm armv7:arm720t ventana nvidia tegra20 whistler arm armv7:arm720t whistler nvidia tegra20 +colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 snowball arm armv7 snowball st-ericsson u8500 kzm9g arm armv7 kzm9g kmc rmobile diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h new file mode 100644 index 0000000000..0e5f281b25 --- /dev/null +++ b/include/configs/colibri_t20_iris.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2012 Lucas Stach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* Enable FDT support */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra20-colibri_t20_iris +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra20 (Colibri) # " +#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_SDIO1 +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* SD/MMC support */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* File system support */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* USB host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_2M) +#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */ +#define CONFIG_ENV_SIZE (SZ_64K) + +/* Debug commands */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CACHE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 7f1b767aea949d954e75fa635968a9d315d2e7ff Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 20 Sep 2012 09:29:03 +0000 Subject: ARM: tegra: define CONFIG_SYS_BOOTMAPSZ This define indicates the size of the memory region where it is safe to place data passed to the Linux kernel (ATAGs, DTB, initrd). The value needs to be: a) Less than or equal to RAM size. b) Small enough that the area is not within the kernel's highmem region, since the kernel cannot access ATAGs/DTB/initrd from highmem. c) Large enough to hold the kernel+DTB+initrd. 256M seems large enough for (c) in most circumstances, and small enough to satisfy (a) and (b) across any possible Tegra board. Note that the user can override this value via environment variable "bootm_mapsize" if needed. The advantage of defining BOOTMAPSZ is that we no longer need to define variable fdt_high in the default environment. Previously, we defined this to prevent the DTB from being relocated to the very end of RAM, which on most Tegra systems is within highmem, and hence which would cause boot failures. A user can still define this variable themselves if they want the FDT to be either left in-place wherever loaded, or copied to some other specific location. Similarly, there should no longer be a strict requirement for the user to define initrd_high if using an initrd. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 1 - include/configs/tegra20-common.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 9698c23dad..5d1d3ddcb7 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -143,7 +143,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ "fdt_load=0x01000000\0" \ - "fdt_high=01100000\0" \ BOOTCMDS_COMMON /* overrides for SPL build here */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index dc7444d1cc..70c5cfbba8 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -171,6 +171,8 @@ #define CONFIG_SYS_TEXT_BASE 0x0010c000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ + #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ -- cgit v1.2.3 From 938176a48274361c0b86b237ff6c0953a08233b3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 2 Oct 2012 09:26:51 +0000 Subject: ARM: tegra: use standard variables to define load addresses Currently, Tegra's default environment uses non-standard variables to define where boot scripts should load the kernel, FDT, and initrd. This change both changes the variable names to match those described in U-Boot's README, and shuffles their values around a little so that the values make a little more sense; see comments in the patch for rationale behind the values chosen. Note that this patch does remove the old non-standard variable "fdt_load" from the default environment, so this patch requires people to change their boot scripts. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 5d1d3ddcb7..6835155d11 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -95,8 +95,6 @@ #endif #define BOOTCMDS_COMMON \ - "scriptaddr=0x400000\0" \ - \ "rootpart=1\0" \ \ "script_boot=" \ @@ -140,9 +138,36 @@ #endif +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x10000000\0" \ + "kernel_addr_r=0x01000000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ - "fdt_load=0x01000000\0" \ + MEM_LAYOUT_ENV_SETTINGS \ BOOTCMDS_COMMON /* overrides for SPL build here */ -- cgit v1.2.3 From 699c40e8789cfbb5c3ca4ef2849a4bd051ff79bb Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 12 Oct 2012 09:45:48 +0000 Subject: ARM: tegra: Harmony: enable ULPI USB port The ULPI port is routed onto pins on the mini PCI Express connector. A standard breakout board may be used to access the port. * Add required DT entries to configure the ULPI port. * Setup up the ULPI pinmux in the board code. * Enable multiple USB controller and ULPI support in the board config. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- board/nvidia/dts/tegra20-harmony.dts | 3 ++- board/nvidia/harmony/harmony.c | 9 +++++++++ include/configs/harmony.h | 3 +++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index ca5facb7fe..5645a8d477 100644 --- a/board/nvidia/dts/tegra20-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + usb1 = "/usb@c5004000"; }; memory { @@ -52,7 +53,7 @@ }; usb@c5004000 { - status = "disabled"; + nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; nand-controller@70008000 { diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 32ed9bb7d1..c7590ac6cf 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -75,3 +75,12 @@ int board_mmc_init(bd_t *bd) return 0; } #endif + +void pin_mux_usb(void) +{ + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PINGRP_CDEV2); + /* USB2 PHY reset GPIO */ + pinmux_tristate_disable(PINGRP_UAC); +} diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d582ae1ab6..040bfe48eb 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -72,8 +72,11 @@ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ /* USB Host support */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB -- cgit v1.2.3 From e73c7cdd1ea152f35f6cf2bc850362cd859f36b6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 12 Oct 2012 09:45:49 +0000 Subject: ARM: tegra: Seaboard: enable multiple USB ports The device tree already contains the required configuration for both the USB1 and USB3 ports. Enable the required configuration options to enable both these ports, which in turn allows the USB1 port to be used. Note that on a true Seaboard, this port is typically used as a device port hosting Tegra's USB recovery protocol. However, on the Springbank derivative, this port is the only external USB port, so we enable it as a host port so that USB peripherals may be used. Enabling this port in U-Boot as a host port doesn't prevent the port from reverting to a device port when the CPU is reset into recovery mode. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/seaboard.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 0727a4c6f8..74d3b94887 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -81,6 +81,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_STORAGE -- cgit v1.2.3 From 56f42f85f5a14040fb0e74fd6cad3910643830d6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 12 Oct 2012 09:45:50 +0000 Subject: ARM: tegra: Whistler: remove unused USB alias Port USB1 on Whistler is intended as a device port for USB recovery. Whistler's DT currently contains an alias for this USB port, even though Whistler's config doesn't enable multiple USB controllers, so the alias is unused. Remove the unused alias for consistency for now. Similar, explicitly disable the port in the device tree too. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- board/nvidia/dts/tegra20-whistler.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts index 38599bd67d..f830cf3995 100644 --- a/board/nvidia/dts/tegra20-whistler.dts +++ b/board/nvidia/dts/tegra20-whistler.dts @@ -9,7 +9,6 @@ aliases { i2c0 = "/i2c@7000d000"; usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; }; memory { @@ -61,6 +60,10 @@ }; }; + usb@c5000000 { + status = "disabled"; + }; + usb@c5004000 { status = "disabled"; }; -- cgit v1.2.3 From a833b95039a08cd52980f95564b567c8b3138cfe Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sun, 7 Oct 2012 11:29:38 +0000 Subject: tegra: nand: make ONFI detection work Add the missing bits to the Tegra NAND driver to make ONFI detection work properly. Also add it to the Tegra default config, as it seems to be a reasonable thing to have it available on all boards that use any kind of NAND. Signed-off-by: Lucas Stach Acked-by: Scott Wood Signed-off-by: Tom Warren --- drivers/mtd/nand/tegra_nand.c | 36 ++++++++++++++++++++++++++++++++++++ include/configs/tegra20-common.h | 1 + 2 files changed, 37 insertions(+) diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index 5408c51ffb..4d94cc6f56 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -218,6 +218,34 @@ static uint8_t read_byte(struct mtd_info *mtd) return (uint8_t)dword_read; } +/** + * Read len bytes from the chip into a buffer + * + * @param mtd MTD device structure + * @param buf buffer to store data to + * @param len number of bytes to read + * + * Read function for 8bit bus-width + */ +static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i, s; + unsigned int reg; + struct nand_chip *chip = mtd->priv; + struct nand_drv *info = (struct nand_drv *)chip->priv; + + for (i = 0; i < len; i += 4) { + s = (len - i) > 4 ? 4 : len - i; + writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 | + ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO, + &info->reg->command); + if (!nand_waitfor_cmd_completion(info->reg)) + puts("Command timeout during read_buf\n"); + reg = readl(&info->reg->resp); + memcpy(buf + i, ®, s); + } +} + /** * Check NAND status to see if it is ready or not * @@ -317,6 +345,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, switch (command) { case NAND_CMD_READID: writel(NAND_CMD_READID, &info->reg->cmd_reg1); + writel(column & 0xFF, &info->reg->addr_reg1); writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO | CMD_RX | ((4 - 1) << CMD_TRANS_SIZE_SHIFT) @@ -324,6 +353,12 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, &info->reg->command); info->pio_byte_index = 0; break; + case NAND_CMD_PARAM: + writel(NAND_CMD_PARAM, &info->reg->cmd_reg1); + writel(column & 0xFF, &info->reg->addr_reg1); + writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0, + &info->reg->command); + break; case NAND_CMD_READ0: writel(NAND_CMD_READ0, &info->reg->cmd_reg1); writel(NAND_CMD_READSTART, &info->reg->cmd_reg2); @@ -976,6 +1011,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) nand->options = LP_OPTIONS; nand->cmdfunc = nand_command; nand->read_byte = read_byte; + nand->read_buf = read_buf; nand->ecc.read_page = nand_read_page_hwecc; nand->ecc.write_page = nand_write_page_hwecc; nand->ecc.read_page_raw = nand_read_page_raw; diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 70c5cfbba8..272c46e06b 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -200,5 +200,6 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" #define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION #endif /* __TEGRA20_COMMON_H */ -- cgit v1.2.3 From 2b7818d49f00ec185eb97650fc1b306c0c6e4565 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:19:33 +0000 Subject: ARM: enhance u-boot.lds to detect over-sized SPL Add an ASSERT() to u-boot.lds to detect an SPL that doesn't fit within SPL_TEXT_BASE..SPL_MAX_SIZE. Different .lds files implement this check in two possible ways: 1) An ASSERT() like this 2) Defining a MEMORY region of size SPL_MAX_SIZE, and re-directing all linker output into that region. Since u-boot.lds is used for both SPL and main U-Boot, this would entail only sometimes defining a MEMORY region, and only sometimes performing that redirection, and hence option (1) was deemed much simpler, and hence implemented. Note that this causes build failures at least for NVIDIA Tegra Seaboard and Ventana. However, these are legitimate; the SPL doesn't fit within the required space, and this does cause runtime issues. Signed-off-by: Stephen Warren Acked-by: Simon Glass Acked-by: Allen Martin Acked-by: Tom Rini Tested-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/cpu/u-boot.lds | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 1996b97536..e6b202bd14 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -94,3 +94,7 @@ SECTIONS /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } } + +#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE) +ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big"); +#endif -- cgit v1.2.3 From 644a69ec85a73b4d24c3a7b0369da76e2c336bce Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:19:34 +0000 Subject: ARM: tegra: derive CONFIG_SPL_MAX_SIZE instead of hard-coding it For Tegra, the SPL and main U-Boot are concatenated together to form a single memory image. Hence, the maximum SPL size is the different in TEXT_BASE for SPL and main U-Boot. Instead of manually calculating SPL_MAX_SIZE based on those two TEXT_BASE, which can lead to errors if one TEXT_BASE is changed without updating SPL_MAX_SIZE, simply perform the calculation automatically. Signed-off-by: Stephen Warren Acked-by: Simon Glass Acked-by: Allen Martin Tested-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra20-common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 272c46e06b..5b048e0094 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -188,7 +188,8 @@ #define CONFIG_SPL #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x00108000 -#define CONFIG_SPL_MAX_SIZE 0x00004000 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \ + CONFIG_SPL_TEXT_BASE) #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 #define CONFIG_SPL_STACK 0x000ffffc -- cgit v1.2.3 From da1f735272aaccf201b7d289c86fe8c6ff848f4f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:19:35 +0000 Subject: ARM: tegra: select between Seaboard/Ventana at compile time Seaboard and Ventana are very similar boards, and so share the seaboard.c board file. The one difference needed so far is detected at run-time by calling machine_is_ventana(). This bloats the Ventana build with code that is never used. Switch to detecting Ventana at compile time to remove bloat. This shaves ~5K off the SPL size on Ventana, and makes the SPL fit within the max size. Signed-off-by: Stephen Warren Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Tom Warren --- board/nvidia/seaboard/seaboard.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 4e8a183b8b..ea431e9f62 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -34,7 +34,7 @@ #endif /* TODO: Remove this code when the SPI switch is working */ -#ifndef CONFIG_SPI_UART_SWITCH +#if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) /* * Routine: gpio_config_uart_seaboard * Description: Force GPIO_PI3 low on Seaboard so UART4 works. @@ -48,8 +48,6 @@ static void gpio_config_uart_seaboard(void) void gpio_early_init_uart(void) { - if (machine_is_ventana()) - return; gpio_config_uart_seaboard(); } #endif -- cgit v1.2.3 From a2ab6b7d320423ab4d925d75c588c2a13fce61c6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:19:36 +0000 Subject: ARM: tegra: don't request GPIO from Seaboard's SPL Seaboard has a GPIO that switches an external mux between Tegra's debug UART and SPI flash. This is initialized from the SPL so that SPL debug output can be seen. Simplify the code that does this, and don't actually request the GPIO in the SPL; just program it. This saves ~4.5K from the size of the SPL, mostly BSS due to the large gpio_names[] table that is no longer required. This makes Seaboard's SPL fit within the current max size. Signed-off-by: Stephen Warren Acked-by: Simon Glass Acked-by: Allen Martin Tested-by: Simon Glass Signed-off-by: Tom Warren --- board/nvidia/seaboard/seaboard.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index ea431e9f62..c412c077da 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -35,21 +36,14 @@ /* TODO: Remove this code when the SPI switch is working */ #if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) -/* - * Routine: gpio_config_uart_seaboard - * Description: Force GPIO_PI3 low on Seaboard so UART4 works. - */ -static void gpio_config_uart_seaboard(void) +void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ +#ifndef CONFIG_SPL_BUILD gpio_request(GPIO_PI3, NULL); +#endif gpio_direction_output(GPIO_PI3, 0); } - -void gpio_early_init_uart(void) -{ - gpio_config_uart_seaboard(); -} #endif #ifdef CONFIG_TEGRA_MMC -- cgit v1.2.3 From a759f1e0db7be05ab562e060cf024af262920426 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 19 Oct 2012 21:08:22 +0000 Subject: SPL: make jump_to_image_no_args a weak symbol Change jump_to_image_no_args() to a weak symbol to allow override by SoC specific code. This is required by tegra because the SPL runs on a different CPU from the image it is loading, so tegra specific initialization is required to start the host CPU. Pass in spl_image as a parameter for the same reason. Signed-off-by: Allen Martin Acked-by: Tom Rini Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Tom Warren --- common/spl/spl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index 0d829c0f12..f068abd8f8 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -113,13 +113,13 @@ void spl_parse_image_header(const struct image_header *header) } } -static void __noreturn jump_to_image_no_args(void) +__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(u32 *); image_entry_noargs_t image_entry = - (image_entry_noargs_t) spl_image.entry_point; + (image_entry_noargs_t) spl_image->entry_point; - debug("image entry point: 0x%X\n", spl_image.entry_point); + debug("image entry point: 0x%X\n", spl_image->entry_point); /* Pass the saved boot_params from rom code */ #if defined(CONFIG_VIRTIO) || defined(CONFIG_ZEBU) image_entry = (image_entry_noargs_t)0x80100000; @@ -223,7 +223,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) default: debug("Unsupported OS image.. Jumping nevertheless..\n"); } - jump_to_image_no_args(); + jump_to_image_no_args(&spl_image); } /* -- cgit v1.2.3 From b2f9893826c48f2653d4a1ffaff8623fdec22303 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 19 Oct 2012 21:08:23 +0000 Subject: tegra: move to common SPL framework Change tegra SPL to use common SPL framework. Any tegra specific initialization is now done in spl_board_init() instead of board_init_f()/board_init_r(). Only one SPL boot target is supported on tegra, which is boot to RAM image. jump_to_image_no_args() must be overridden on tegra so the host CPU can be initialized. Signed-off-by: Allen Martin Acked-by: Stephen Warren Tested-by: Stephen Warren Tested-by: Lucas Stach Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/cpu/arm720t/tegra-common/spl.c | 91 +++++---------------------------- arch/arm/include/asm/arch-tegra20/spl.h | 28 ++++++++++ include/configs/tegra20-common.h | 4 ++ 3 files changed, 46 insertions(+), 77 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra20/spl.h diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 0d37ce83c8..c280ab7d0f 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -23,105 +23,42 @@ * MA 02111-1307 USA */ #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include "cpu.h" +#include #include #include #include #include #include -#include -#include -#include -#include +#include -DECLARE_GLOBAL_DATA_PTR; -/* Define global data structure pointer to it*/ -static gd_t gdata __attribute__ ((section(".data"))); -static bd_t bdata __attribute__ ((section(".data"))); - -inline void hang(void) +void spl_board_init(void) { - puts("### ERROR ### Please RESET the board ###\n"); - for (;;) - ; -} + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + + /* enable JTAG */ + writel(0xC0, &pmt->pmt_cfg_ctl); -void board_init_f(ulong dummy) -{ board_init_uart_f(); /* Initialize periph GPIOs */ gpio_early_init_uart(); - /* - * We call relocate_code() with relocation target same as the - * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting - * skipped. Instead, only .bss initialization will happen. That's - * all we need - */ - debug(">>board_init_f()\n"); - relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE); + clock_early_init(); + preloader_console_init(); } -/* This requires UART clocks to be enabled */ -static void preloader_console_init(void) +u32 spl_boot_device(void) { - const char *u_boot_rev = U_BOOT_VERSION; - - gd = &gdata; - gd->bd = &bdata; - gd->flags |= GD_FLG_RELOC; - gd->baudrate = CONFIG_BAUDRATE; - - serial_init(); /* serial communications setup */ - - gd->have_console = 1; - - /* Avoid a second "U-Boot" coming from this string */ - u_boot_rev = &u_boot_rev[7]; - - printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, - U_BOOT_TIME); + return BOOT_DEVICE_RAM; } -void board_init_r(gd_t *id, ulong dummy) +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; - - /* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); - - debug(">>spl:board_init_r()\n"); - - mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, - CONFIG_SYS_SPL_MALLOC_SIZE); - -#ifdef CONFIG_SPL_BOARD_INIT - spl_board_init(); -#endif + debug("image entry point: 0x%X\n", spl_image->entry_point); - clock_early_init(); - serial_init(); - preloader_console_init(); - - start_cpu((u32)CONFIG_SYS_TEXT_BASE); + start_cpu((u32)spl_image->entry_point); halt_avp(); - /* not reached */ -} - -int board_usb_init(const void *blob) -{ - return 0; } diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h new file mode 100644 index 0000000000..5e453c5cc7 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/spl.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2012 + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 5b048e0094..15bd9bb146 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -169,6 +169,7 @@ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_TEXT_BASE 0x0010c000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ @@ -186,6 +187,9 @@ /* Defines for SPL */ #define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x00108000 #define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \ -- cgit v1.2.3 From ee2e185f62d7b9962fa295acbb55688fbace4ad4 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Fri, 19 Oct 2012 21:18:03 +0000 Subject: tegra20: initialize variable to avoid compiler warning Initialize this variable to avoid a compiler warning about possible use of uninitialized variable with gcc 4.4.6. Signed-off-by: Allen Martin Acked-by: Stephen Warren Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/cpu/tegra20-common/emc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c index 97420d7066..90edf00a5e 100644 --- a/arch/arm/cpu/tegra20-common/emc.c +++ b/arch/arm/cpu/tegra20-common/emc.c @@ -257,7 +257,7 @@ static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp, int tegra_set_emc(const void *blob, unsigned rate) { struct emc_ctlr *emc; - const u32 *table; + const u32 *table = NULL; int err, i; err = decode_emc(blob, rate, &emc, &table); -- cgit v1.2.3 From e4ec9346735fdccce4d9b75a5896affe224a38be Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 16 Oct 2012 11:50:07 +0000 Subject: ARM: tegra: combine duplicate Makefile rules The rules to generate u-boot-{no,}dtb-tegra.bin were almost identical. Combine them into a single paremeterized rule. This will allow the next patch to edit a single rule, rather than being cut/paste twice. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- Makefile | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/Makefile b/Makefile index d385467e8e..216ad02e05 100644 --- a/Makefile +++ b/Makefile @@ -515,17 +515,18 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin ifeq ($(SOC),tegra20) ifeq ($(CONFIG_OF_SEPARATE),y) -$(obj)u-boot-dtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(obj)u-boot.dtb - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(obj)u-boot.dtb > $@ - rm $(obj)spl/u-boot-spl-pad.bin +nodtb=dtb +dtbfile=$(obj)u-boot.dtb else -$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin +nodtb=nodtb +dtbfile= +endif + +$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile) $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ + cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@ rm $(obj)spl/u-boot-spl-pad.bin endif -endif ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ -- cgit v1.2.3 From 0f8998022294ea744b5e2db0faacb96cddba2018 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Thu, 25 Oct 2012 13:30:14 +0000 Subject: serial: remove calls to serial_assign() Remove calls to serial_assign() that are failing now that it returns a proper error code. This calls were not actually doing anything because they passed the name of a stdio_dev when a serial_device name is exptectd. Signed-off-by: Allen Martin Acked-by: Joe Hershberger Acked-by: Marek Vasut Acked-by: Simon Glass Tested-by: Simon Glass Tested-by: Stephen Warren Signed-off-by: Tom Warren --- common/cmd_nvedit.c | 3 --- common/iomux.c | 10 ---------- 2 files changed, 13 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 1f9c674260..68c38f4e5c 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -238,9 +238,6 @@ int env_check_apply(const char *name, const char *oldval, /* Try assigning specified device */ if (console_assign(console, newval) < 0) return 1; - - if (serial_assign(newval) < 0) - return 1; #endif /* CONFIG_CONSOLE_MUX */ } diff --git a/common/iomux.c b/common/iomux.c index dbc231250c..6a757041f6 100644 --- a/common/iomux.c +++ b/common/iomux.c @@ -135,16 +135,6 @@ int iomux_doenv(const int console, const char *arg) */ if (console_assign(console, start[j]) < 0) continue; - /* - * This was taken from common/cmd_nvedit.c. - * This will never work because serial_assign() returns - * 1 upon error, not -1. - * This would almost always return an error anyway because - * serial_assign() expects the name of a serial device, like - * serial_smc, but the user generally only wants to set serial. - */ - if (serial_assign(start[j]) < 0) - continue; cons_set[cs_idx++] = dev; } free(console_args); -- cgit v1.2.3 From d598e0fe739e5a75db74cc144beabd09e3c51433 Mon Sep 17 00:00:00 2001 From: Allen Martin Date: Mon, 29 Oct 2012 10:47:43 +0000 Subject: arm720t: add back common.h include Add back common.h header that was removed in previous patch so that CONFIG_TEGRA can be evaluated correctly. Signed-off-by: Allen Martin Signed-off-by: Tom Warren --- arch/arm/cpu/arm720t/interrupts.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 8e763b7788..623a24b651 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -26,6 +26,8 @@ * MA 02111-1307 USA */ +#include + #ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) { -- cgit v1.2.3 From 672ee2110c478d04bd95111bb6c9d5bcacf4b7aa Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:43:49 +0000 Subject: fs: delete unused Makefile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fs/Makefile is unused. The top-level Makefile sets LIBS-y += fs/xxx and hence causes make to directly descend two directory levels into each individual filesystem, and it never descends into fs/ itself. So, delete this useless file. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau Acked-by: Simon Glass --- fs/Makefile | 43 ------------------------------------------- 1 file changed, 43 deletions(-) delete mode 100644 fs/Makefile diff --git a/fs/Makefile b/fs/Makefile deleted file mode 100644 index b4db606236..0000000000 --- a/fs/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# - -subdirs-$(CONFIG_CMD_CBFS) += cbfs -subdirs-$(CONFIG_CMD_CRAMFS) := cramfs -subdirs-$(CONFIG_CMD_EXT4) += ext4 -ifndef CONFIG_CMD_EXT4 -subdirs-$(CONFIG_CMD_EXT2) += ext4 -endif -subdirs-$(CONFIG_CMD_FAT) += fat -subdirs-$(CONFIG_CMD_FDOS) += fdos -subdirs-$(CONFIG_CMD_JFFS2) += jffs2 -subdirs-$(CONFIG_CMD_REISER) += reiserfs -subdirs-$(CONFIG_YAFFS2) += yaffs2 -subdirs-$(CONFIG_CMD_UBIFS) += ubifs -subdirs-$(CONFIG_CMD_ZFS) += zfs - -SUBDIRS := $(subdirs-y) - -$(obj).depend all: - @for dir in $(SUBDIRS) ; do \ - $(MAKE) -C $$dir $@ ; done -- cgit v1.2.3 From 03e2ecf6b83e43803f7eed9547d0973b7eb1c8fc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:43:50 +0000 Subject: fs: separate CONFIG_FS_{FAT, EXT4} from CONFIG_CMD_{FAT, EXT*} MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the FAT and ext4 filesystem implementations build if CONFIG_FS_{FAT,EXT4} are defined, rather than basing the build on whether CONFIG_CMD_{FAT,EXT*} are defined. This will allow the filesystems to be built separately from the filesystem-specific commands that use them. This paves the way for the creation of filesystem-generic commands that used the filesystems, without requiring the filesystem- specific commands. Minor documentation changes are made for this change. The new config options are automatically selected by the old config options to retain backwards-compatibility. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- README | 4 +++- doc/README.ext4 | 13 +++++++++++++ fs/ext4/Makefile | 7 ++----- fs/ext4/ext4_common.c | 2 +- fs/ext4/ext4_common.h | 4 ++-- fs/ext4/ext4fs.c | 2 +- fs/fat/Makefile | 4 ++-- include/config_fallbacks.h | 13 +++++++++++++ include/ext4fs.h | 2 +- 9 files changed, 38 insertions(+), 13 deletions(-) diff --git a/README b/README index 4f16240ebd..22fd6b761e 100644 --- a/README +++ b/README @@ -807,9 +807,11 @@ The following options need to be configured: CONFIG_CMD_EEPROM * EEPROM read/write support CONFIG_CMD_ELF * bootelf, bootvx CONFIG_CMD_EXPORTENV * export the environment + CONFIG_CMD_EXT2 * ext2 command support + CONFIG_CMD_EXT4 * ext4 command support CONFIG_CMD_SAVEENV saveenv CONFIG_CMD_FDC * Floppy Disk Support - CONFIG_CMD_FAT * FAT partition support + CONFIG_CMD_FAT * FAT command support CONFIG_CMD_FDOS * Dos diskette Support CONFIG_CMD_FLASH flinfo, erase, protect CONFIG_CMD_FPGA FPGA device initialization support diff --git a/doc/README.ext4 b/doc/README.ext4 index b3ea8b776d..b7d0ad3930 100644 --- a/doc/README.ext4 +++ b/doc/README.ext4 @@ -1,15 +1,28 @@ This patch series adds support for ext4 ls,load and write features in uboot Journaling is supported for write feature. +To enable support for the ext4 (and ext2) filesystem implementation, +#define CONFIG_FS_EXT4 + +If you want write support, +#define CONFIG_EXT4_WRITE + To Enable ext2 ls and load commands, modify the board specific config file with #define CONFIG_CMD_EXT2 +This automatically defines CONFIG_FS_EXT4 for you. To Enable ext4 ls and load commands, modify the board specific config file with #define CONFIG_CMD_EXT4 +This automatically defines CONFIG_FS_EXT4 for you. To enable ext4 write command, modify the board specific config file with #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE +These automatically define CONFIG_FS_EXT4 and CONFIG_EXT4_WRITE for you. + +Also relevant are the generic filesystem commands, +#define CONFIG_CMD_FS_GENERIC +This does not automatically enable EXT4 support for you. Steps to test: diff --git a/fs/ext4/Makefile b/fs/ext4/Makefile index 82cd9ae16a..bb801f9054 100644 --- a/fs/ext4/Makefile +++ b/fs/ext4/Makefile @@ -30,11 +30,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)libext4fs.o AOBJS = -COBJS-$(CONFIG_CMD_EXT4) := ext4fs.o ext4_common.o dev.o -ifndef CONFIG_CMD_EXT4 -COBJS-$(CONFIG_CMD_EXT2) := ext4fs.o ext4_common.o dev.o -endif -COBJS-$(CONFIG_CMD_EXT4_WRITE) += ext4_journal.o crc16.o +COBJS-$(CONFIG_FS_EXT4) := ext4fs.o ext4_common.o dev.o +COBJS-$(CONFIG_EXT4_WRITE) += ext4_journal.o crc16.o SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y)) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index d6d55b9fff..323875fa94 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -56,7 +56,7 @@ int ext4fs_indir3_blkno = -1; struct ext2_inode *g_parent_inode; static int symlinknest; -#if defined(CONFIG_CMD_EXT4_WRITE) +#if defined(CONFIG_EXT4_WRITE) uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n) { uint32_t res = size / n; diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h index f728134186..87cab168ee 100644 --- a/fs/ext4/ext4_common.h +++ b/fs/ext4/ext4_common.h @@ -37,7 +37,7 @@ #include #include #include -#if defined(CONFIG_CMD_EXT4_WRITE) +#if defined(CONFIG_EXT4_WRITE) #include "ext4_journal.h" #include "crc16.h" #endif @@ -71,7 +71,7 @@ int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode, int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, struct ext2fs_node **fnode, int *ftype); -#if defined(CONFIG_CMD_EXT4_WRITE) +#if defined(CONFIG_EXT4_WRITE) uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n); int ext4fs_checksum_update(unsigned int i); int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags); diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 3a5ef20a4b..06536baf62 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -196,7 +196,7 @@ int ext4fs_read(char *buf, unsigned len) return ext4fs_read_file(ext4fs_file, 0, len, buf); } -#if defined(CONFIG_CMD_EXT4_WRITE) +#if defined(CONFIG_EXT4_WRITE) static void ext4fs_update(void) { short i; diff --git a/fs/fat/Makefile b/fs/fat/Makefile index 02e6881670..969715bf9c 100644 --- a/fs/fat/Makefile +++ b/fs/fat/Makefile @@ -24,11 +24,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)libfat.o AOBJS = -COBJS-$(CONFIG_CMD_FAT) := fat.o +COBJS-$(CONFIG_FS_FAT) := fat.o COBJS-$(CONFIG_FAT_WRITE):= fat_write.o ifndef CONFIG_SPL_BUILD -COBJS-$(CONFIG_CMD_FAT) += file.o +COBJS-$(CONFIG_FS_FAT) += file.o endif SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 430890c3fb..bfb9680d68 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -13,4 +13,17 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif +#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT) +#define CONFIG_FS_FAT +#endif + +#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \ + !defined(CONFIG_FS_EXT4) +#define CONFIG_FS_EXT4 +#endif + +#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE) +#define CONFIG_EXT4_WRITE +#endif + #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/ext4fs.h b/include/ext4fs.h index 23298fcd7d..3b59d15aab 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -116,7 +116,7 @@ struct ext_filesystem { extern struct ext2_data *ext4fs_root; extern struct ext2fs_node *ext4fs_file; -#if defined(CONFIG_CMD_EXT4_WRITE) +#if defined(CONFIG_EXT4_WRITE) extern struct ext2_inode *g_parent_inode; extern int gd_index; extern int gindex; -- cgit v1.2.3 From 045fa1e1142552799ad3203e9e0bc22a11e866ea Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 Oct 2012 06:43:51 +0000 Subject: fs: add filesystem switch libary, implement ls and fsload commands Implement "ls" and "fsload" commands that act like {fat,ext2}{ls,load}, and transparently handle either file-system. This scheme could easily be extended to other filesystem types; I only didn't do it for zfs because I don't have any filesystems of that type to test with. Replace the implementation of {fat,ext[24]}{ls,load} with this new code too. Signed-off-by: Stephen Warren --- Makefile | 3 +- common/Makefile | 6 +- common/cmd_ext2.c | 13 +- common/cmd_ext4.c | 12 +- common/cmd_ext_common.c | 197 ------------------------------- common/cmd_fat.c | 76 +----------- common/cmd_fs.c | 51 ++++++++ fs/Makefile | 47 ++++++++ fs/fs.c | 308 ++++++++++++++++++++++++++++++++++++++++++++++++ include/ext_common.h | 3 - include/fs.h | 65 ++++++++++ 11 files changed, 483 insertions(+), 298 deletions(-) delete mode 100644 common/cmd_ext_common.c create mode 100644 common/cmd_fs.c create mode 100644 fs/Makefile create mode 100644 fs/fs.c create mode 100644 include/fs.h diff --git a/Makefile b/Makefile index d385467e8e..2fe149045b 100644 --- a/Makefile +++ b/Makefile @@ -260,7 +260,8 @@ LIBS-y += drivers/net/npe/libnpe.o endif LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o -LIBS-y += fs/cbfs/libcbfs.o \ +LIBS-y += fs/libfs.o \ + fs/cbfs/libcbfs.o \ fs/cramfs/libcramfs.o \ fs/ext4/libext4fs.o \ fs/fat/libfat.o \ diff --git a/common/Makefile b/common/Makefile index eac63605ce..9e43322211 100644 --- a/common/Makefile +++ b/common/Makefile @@ -90,11 +90,6 @@ COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o COBJS-$(CONFIG_CMD_EXT4) += cmd_ext4.o COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o -ifdef CONFIG_CMD_EXT4 -COBJS-y += cmd_ext_common.o -else -COBJS-$(CONFIG_CMD_EXT2) += cmd_ext_common.o -endif COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o @@ -104,6 +99,7 @@ COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o ifdef CONFIG_FPGA COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o endif +COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index c27d9c7ede..06d0234a47 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -37,15 +37,11 @@ /* * Ext2fs support */ -#include -#include +#include int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - if (do_ext_ls(cmdtp, flag, argc, argv)) - return -1; - - return 0; + return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EXT); } /****************************************************************************** @@ -53,10 +49,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - if (do_ext_load(cmdtp, flag, argc, argv)) - return -1; - - return 0; + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT); } U_BOOT_CMD( diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index ca4656184c..237bc198ae 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -47,10 +47,10 @@ #include #include #include -#include #include #include #include +#include #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) #include @@ -59,18 +59,12 @@ int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - if (do_ext_load(cmdtp, flag, argc, argv)) - return -1; - - return 0; + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT); } int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - if (do_ext_ls(cmdtp, flag, argc, argv)) - return -1; - - return 0; + return do_ls(cmdtp, flag, argc, argv, FS_TYPE_EXT); } #if defined(CONFIG_CMD_EXT4_WRITE) diff --git a/common/cmd_ext_common.c b/common/cmd_ext_common.c deleted file mode 100644 index 1952f4d1e1..0000000000 --- a/common/cmd_ext_common.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2011 - 2012 Samsung Electronics - * EXT2/4 filesystem implementation in Uboot by - * Uma Shankar - * Manjunatha C Achar - * - * Ext4fs support - * made from existing cmd_ext2.c file of Uboot - * - * (C) Copyright 2004 - * esd gmbh - * Reinhard Arlt - * - * made from cmd_reiserfs by - * - * (C) Copyright 2003 - 2004 - * Sysgo Real-Time Solutions, AG - * Pavel Bartusek - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * Changelog: - * 0.1 - Newly created file for ext4fs support. Taken from cmd_ext2.c - * file in uboot. Added ext4fs ls load and write support. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) -#include -#endif - -#if !defined(CONFIG_DOS_PARTITION) && !defined(CONFIG_EFI_PARTITION) -#error DOS or EFI partition support must be selected -#endif - -#define DOS_PART_MAGIC_OFFSET 0x1fe -#define DOS_FS_TYPE_OFFSET 0x36 -#define DOS_FS32_TYPE_OFFSET 0x52 - -int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) -{ - char *filename = NULL; - int dev, part; - ulong addr = 0; - int filelen; - disk_partition_t info; - block_dev_desc_t *dev_desc; - char buf[12]; - unsigned long count; - const char *addr_str; - - count = 0; - addr = simple_strtoul(argv[3], NULL, 16); - filename = getenv("bootfile"); - switch (argc) { - case 3: - addr_str = getenv("loadaddr"); - if (addr_str != NULL) - addr = simple_strtoul(addr_str, NULL, 16); - else - addr = CONFIG_SYS_LOAD_ADDR; - - break; - case 4: - break; - case 5: - filename = argv[4]; - break; - case 6: - filename = argv[4]; - count = simple_strtoul(argv[5], NULL, 16); - break; - - default: - return cmd_usage(cmdtp); - } - - if (!filename) { - puts("** No boot file defined **\n"); - return 1; - } - - part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); - if (part < 0) - return 1; - - dev = dev_desc->dev; - printf("Loading file \"%s\" from %s device %d%c%c\n", - filename, argv[1], dev, - part ? ':' : ' ', part ? part + '0' : ' '); - - ext4fs_set_blk_dev(dev_desc, &info); - - if (!ext4fs_mount(info.size)) { - printf("** Bad ext2 partition or disk - %s %d:%d **\n", - argv[1], dev, part); - ext4fs_close(); - goto fail; - } - - filelen = ext4fs_open(filename); - if (filelen < 0) { - printf("** File not found %s\n", filename); - ext4fs_close(); - goto fail; - } - if ((count < filelen) && (count != 0)) - filelen = count; - - if (ext4fs_read((char *)addr, filelen) != filelen) { - printf("** Unable to read \"%s\" from %s %d:%d **\n", - filename, argv[1], dev, part); - ext4fs_close(); - goto fail; - } - - ext4fs_close(); - /* Loading ok, update default load address */ - load_addr = addr; - - printf("%d bytes read\n", filelen); - sprintf(buf, "%X", filelen); - setenv("filesize", buf); - - return 0; -fail: - return 1; -} - -int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - const char *filename = "/"; - int dev; - int part; - block_dev_desc_t *dev_desc; - disk_partition_t info; - - if (argc < 2) - return cmd_usage(cmdtp); - - part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); - if (part < 0) - return 1; - - if (argc == 4) - filename = argv[3]; - - dev = dev_desc->dev; - ext4fs_set_blk_dev(dev_desc, &info); - - if (!ext4fs_mount(info.size)) { - printf("** Bad ext2 partition or disk - %s %d:%d **\n", - argv[1], dev, part); - ext4fs_close(); - goto fail; - } - - if (ext4fs_ls(filename)) { - printf("** Error extfs_ls() **\n"); - ext4fs_close(); - goto fail; - }; - - ext4fs_close(); - return 0; - -fail: - return 1; -} diff --git a/common/cmd_fat.c b/common/cmd_fat.c index c38302d447..c865d6d8a2 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -31,54 +31,11 @@ #include #include #include - +#include int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - long size; - unsigned long offset; - unsigned long count = 0; - unsigned long pos = 0; - char buf [12]; - block_dev_desc_t *dev_desc=NULL; - disk_partition_t info; - int part, dev; - - if (argc < 5) { - printf("usage: fatload [] " - " [bytes [pos]]\n"); - return 1; - } - - part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); - if (part < 0) - return 1; - - dev = dev_desc->dev; - if (fat_set_blk_dev(dev_desc, &info) != 0) { - printf("\n** Unable to use %s %d:%d for fatload **\n", - argv[1], dev, part); - return 1; - } - offset = simple_strtoul(argv[3], NULL, 16); - if (argc >= 6) - count = simple_strtoul(argv[5], NULL, 16); - if (argc >= 7) - pos = simple_strtoul(argv[6], NULL, 16); - size = file_fat_read_at(argv[4], pos, (unsigned char *)offset, count); - - if(size==-1) { - printf("\n** Unable to read \"%s\" from %s %d:%d **\n", - argv[4], argv[1], dev, part); - return 1; - } - - printf("\n%ld bytes read\n", size); - - sprintf(buf, "%lX", size); - setenv("filesize", buf); - - return 0; + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_FAT); } @@ -96,34 +53,7 @@ U_BOOT_CMD( int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *filename = "/"; - int ret, dev, part; - block_dev_desc_t *dev_desc=NULL; - disk_partition_t info; - - if (argc < 2) { - printf("usage: fatls [] [directory]\n"); - return 0; - } - - part = get_device_and_partition(argv[1], argv[2], &dev_desc, &info, 1); - if (part < 0) - return 1; - - dev = dev_desc->dev; - if (fat_set_blk_dev(dev_desc, &info) != 0) { - printf("\n** Unable to use %s %d:%d for fatls **\n", - argv[1], dev, part); - return 1; - } - if (argc == 4) - ret = file_fat_ls(argv[3]); - else - ret = file_fat_ls(filename); - - if(ret!=0) - printf("No Fat FS detected\n"); - return ret; + return do_ls(cmdtp, flag, argc, argv, FS_TYPE_FAT); } U_BOOT_CMD( diff --git a/common/cmd_fs.c b/common/cmd_fs.c new file mode 100644 index 0000000000..296124b995 --- /dev/null +++ b/common/cmd_fs.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Inspired by cmd_ext_common.c, cmd_fat.c. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +int do_fsload_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_ANY); +} + +U_BOOT_CMD( + fsload, 7, 0, do_fsload_wrapper, + "load binary file from a filesystem", + " [ [ [ [bytes [pos]]]]]\n" + " - Load binary file 'filename' from partition 'part' on device\n" + " type 'interface' instance 'dev' to address 'addr' in memory.\n" + " 'bytes' gives the size to load in bytes.\n" + " If 'bytes' is 0 or omitted, the file is read until the end.\n" + " 'pos' gives the file byte position to start reading from.\n" + " If 'pos' is 0 or omitted, the file is read from the start." +); + +int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return do_ls(cmdtp, flag, argc, argv, FS_TYPE_ANY); +} + +U_BOOT_CMD( + ls, 4, 1, do_ls_wrapper, + "list files in a directory (default /)", + " [ [directory]]\n" + " - List files in directory 'directory' of partition 'part' on\n" + " device type 'interface' instance 'dev'." +); diff --git a/fs/Makefile b/fs/Makefile new file mode 100644 index 0000000000..d0ab3aec56 --- /dev/null +++ b/fs/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)libfs.o + +COBJS-y += fs.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/fs/fs.c b/fs/fs.c new file mode 100644 index 0000000000..23ffa25f0d --- /dev/null +++ b/fs/fs.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +static block_dev_desc_t *fs_dev_desc; +static disk_partition_t fs_partition; +static int fs_type = FS_TYPE_ANY; + +static inline int fs_ls_unsupported(const char *dirname) +{ + printf("** Unrecognized filesystem type **\n"); + return -1; +} + +static inline int fs_read_unsupported(const char *filename, ulong addr, + int offset, int len) +{ + printf("** Unrecognized filesystem type **\n"); + return -1; +} + +#ifdef CONFIG_FS_FAT +static int fs_probe_fat(void) +{ + return fat_set_blk_dev(fs_dev_desc, &fs_partition); +} + +static void fs_close_fat(void) +{ +} + +#define fs_ls_fat file_fat_ls + +static int fs_read_fat(const char *filename, ulong addr, int offset, int len) +{ + int len_read; + + len_read = file_fat_read_at(filename, offset, + (unsigned char *)addr, len); + if (len_read == -1) { + printf("** Unable to read file %s **\n", filename); + return -1; + } + + return len_read; +} +#else +static inline int fs_probe_fat(void) +{ + return -1; +} + +static inline void fs_close_fat(void) +{ +} + +#define fs_ls_fat fs_ls_unsupported +#define fs_read_fat fs_read_unsupported +#endif + +#ifdef CONFIG_FS_EXT4 +static int fs_probe_ext(void) +{ + ext4fs_set_blk_dev(fs_dev_desc, &fs_partition); + + if (!ext4fs_mount(fs_partition.size)) { + ext4fs_close(); + return -1; + } + + return 0; +} + +static void fs_close_ext(void) +{ + ext4fs_close(); +} + +#define fs_ls_ext ext4fs_ls + +static int fs_read_ext(const char *filename, ulong addr, int offset, int len) +{ + int file_len; + int len_read; + + if (offset != 0) { + printf("** Cannot support non-zero offset **\n"); + return -1; + } + + file_len = ext4fs_open(filename); + if (file_len < 0) { + printf("** File not found %s **\n", filename); + ext4fs_close(); + return -1; + } + + if (len == 0) + len = file_len; + + len_read = ext4fs_read((char *)addr, len); + ext4fs_close(); + + if (len_read != len) { + printf("** Unable to read file %s **\n", filename); + return -1; + } + + return len_read; +} +#else +static inline int fs_probe_ext(void) +{ + return -1; +} + +static inline void fs_close_ext(void) +{ +} + +#define fs_ls_ext fs_ls_unsupported +#define fs_read_ext fs_read_unsupported +#endif + +static const struct { + int fstype; + int (*probe)(void); +} fstypes[] = { + { + .fstype = FS_TYPE_FAT, + .probe = fs_probe_fat, + }, + { + .fstype = FS_TYPE_EXT, + .probe = fs_probe_ext, + }, +}; + +int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) +{ + int part, i; + + part = get_device_and_partition(ifname, dev_part_str, &fs_dev_desc, + &fs_partition, 1); + if (part < 0) + return -1; + + for (i = 0; i < ARRAY_SIZE(fstypes); i++) { + if ((fstype != FS_TYPE_ANY) && (fstype != fstypes[i].fstype)) + continue; + + if (!fstypes[i].probe()) { + fs_type = fstypes[i].fstype; + return 0; + } + } + + printf("** Unrecognized filesystem type **\n"); + return -1; +} + +static void fs_close(void) +{ + switch (fs_type) { + case FS_TYPE_FAT: + fs_close_fat(); + break; + case FS_TYPE_EXT: + fs_close_ext(); + break; + default: + break; + } + + fs_type = FS_TYPE_ANY; +} + +int fs_ls(const char *dirname) +{ + int ret; + + switch (fs_type) { + case FS_TYPE_FAT: + ret = fs_ls_fat(dirname); + break; + case FS_TYPE_EXT: + ret = fs_ls_ext(dirname); + break; + default: + ret = fs_ls_unsupported(dirname); + break; + } + + fs_close(); + + return ret; +} + +int fs_read(const char *filename, ulong addr, int offset, int len) +{ + int ret; + + switch (fs_type) { + case FS_TYPE_FAT: + ret = fs_read_fat(filename, addr, offset, len); + break; + case FS_TYPE_EXT: + ret = fs_read_ext(filename, addr, offset, len); + break; + default: + ret = fs_read_unsupported(filename, addr, offset, len); + break; + } + + fs_close(); + + return ret; +} + +int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype) +{ + unsigned long addr; + const char *addr_str; + const char *filename; + unsigned long bytes; + unsigned long pos; + int len_read; + char buf[12]; + + if (argc < 5) + return CMD_RET_USAGE; + + if (fs_set_blk_dev(argv[1], argv[2], fstype)) + return 1; + + if (argc >= 4) { + addr = simple_strtoul(argv[3], NULL, 0); + } else { + addr_str = getenv("loadaddr"); + if (addr_str != NULL) + addr = simple_strtoul(addr_str, NULL, 16); + else + addr = CONFIG_SYS_LOAD_ADDR; + } + if (argc >= 5) { + filename = argv[4]; + } else { + filename = getenv("bootfile"); + if (!filename) { + puts("** No boot file defined **\n"); + return 1; + } + } + if (argc >= 6) + bytes = simple_strtoul(argv[5], NULL, 0); + else + bytes = 0; + if (argc >= 7) + pos = simple_strtoul(argv[6], NULL, 0); + else + pos = 0; + + len_read = fs_read(filename, addr, pos, bytes); + if (len_read <= 0) + return 1; + + printf("%d bytes read\n", len_read); + + sprintf(buf, "0x%x", len_read); + setenv("filesize", buf); + + return 0; +} + +int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype) +{ + if (argc < 2) + return CMD_RET_USAGE; + + if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype)) + return 1; + + if (fs_ls(argc == 4 ? argv[3] : "/")) + return 1; + + return 0; +} diff --git a/include/ext_common.h b/include/ext_common.h index ce73857f8d..86373a6e50 100644 --- a/include/ext_common.h +++ b/include/ext_common.h @@ -195,7 +195,4 @@ int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); -int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]); -int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); #endif diff --git a/include/fs.h b/include/fs.h new file mode 100644 index 0000000000..f396d8492a --- /dev/null +++ b/include/fs.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef _FS_H +#define _FS_H + +#include + +#define FS_TYPE_ANY 0 +#define FS_TYPE_FAT 1 +#define FS_TYPE_EXT 2 + +/* + * Tell the fs layer which block device an partition to use for future + * commands. This also internally identifies the filesystem that is present + * within the partition. The identification process may be limited to a + * specific filesystem type by passing FS_* in the fstype parameter. + * + * Returns 0 on success. + * Returns non-zero if there is an error accessing the disk or partition, or + * no known filesystem type could be recognized on it. + */ +int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype); + +/* + * Print the list of files on the partition previously set by fs_set_blk_dev(), + * in directory "dirname". + * + * Returns 0 on success. Returns non-zero on error. + */ +int fs_ls(const char *dirname); + +/* + * Read file "filename" from the partition previously set by fs_set_blk_dev(), + * to address "addr", starting at byte offset "offset", and reading "len" + * bytes. "offset" may be 0 to read from the start of the file. "len" may be + * 0 to read the entire file. Note that not all filesystem types support + * either/both offset!=0 or len!=0. + * + * Returns number of bytes read on success. Returns <= 0 on error. + */ +int fs_read(const char *filename, ulong addr, int offset, int len); + +/* + * Common implementation for various filesystem commands, optionally limited + * to a specific filesystem type via the fstype parameter. + */ +int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); +int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], + int fstype); + +#endif /* _FS_H */ -- cgit v1.2.3 From a99c040c337753a7141263b36e91209f504191f1 Mon Sep 17 00:00:00 2001 From: Stephan Gatzka Date: Mon, 22 Oct 2012 23:11:41 +0000 Subject: FPGA: Cyclon II: Correctly reset the FPGA before configuration Deassert the CONFIG pin before asserting it again. This assures that the FPGA will be resetted and therefore configuration will be correctly enabled. This is also already done on other FPGA's, e.g. Stratix. Signed-off-by: Stephan Gatzka Signed-off-by: Stefan Roese --- drivers/fpga/cyclon2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 26494a3f89..0773e731eb 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -144,6 +144,8 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ + (*fn->config) (FALSE, TRUE, cookie); /* De-assert nCONFIG */ + udelay(100); (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ udelay(2); /* T_cfg > 2us */ -- cgit v1.2.3 From b9dc49412d592a4ce8e5c3a297dc6eb0110646c6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 23 Oct 2012 13:49:25 +0000 Subject: ext4: Fix printf() format string error Fix the following error in the ext4 command: cmd_ext4.c:110:3: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'int' [-Werror=format] Signed-off-by: Simon Glass --- common/cmd_ext4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index 237bc198ae..e193f29c47 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -101,7 +101,7 @@ int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, /* mount the filesystem */ if (!ext4fs_mount(info.size)) { - printf("Bad ext4 partition %s %d:%lu\n", argv[1], dev, part); + printf("Bad ext4 partition %s %d:%d\n", argv[1], dev, part); goto fail; } -- cgit v1.2.3 From ed296d206a1840c0a0b6c1322379c950f9996905 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 25 Oct 2012 08:53:14 +0000 Subject: MAKEALL: Add -s to '${MAKE} tidy' section When BUILD_NBUILDS is > 1 we run the tidy command. With the addition of DocBook this now includes a -C doc/DocBook and a 'entering/leaving' pair of messages happen. Since we don't want to see what's being cleaned here, we can just invoke make -s like we do when building. Signed-off-by: Tom Rini --- MAKEALL | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index 63f8bef6ca..84a5c92cf3 100755 --- a/MAKEALL +++ b/MAKEALL @@ -640,7 +640,7 @@ build_target() { fi if [ $BUILD_MANY == 1 ] ; then - ${MAKE} tidy + ${MAKE} -s tidy if [ -s ${LOG_DIR}/${target}.ERR ] ; then cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target} -- cgit v1.2.3 From 89e6f13849fa583a475aa2bd733021d850098bf4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 19 Oct 2012 02:00:04 +0000 Subject: arm bootm: Allow to pass board specified atags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Board can implement function setup_board_tags which is used for adding atags Signed-off-by: Pali Rohár --- arch/arm/include/asm/setup.h | 5 +++++ arch/arm/lib/bootm.c | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 89df4dc708..78a7facfc3 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -267,3 +267,8 @@ struct meminfo { extern struct meminfo meminfo; #endif + +/* + * Board specified tags + */ +void setup_board_tags(struct tag **in_params); diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 37476cc90d..1bd2730856 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -34,6 +34,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -269,6 +270,8 @@ static int create_fdt(bootm_headers_t *images) } #endif +__weak void setup_board_tags(struct tag **in_params) {} + /* Subcommand: PREP */ static void boot_prep_linux(bootm_headers_t *images) { @@ -310,6 +313,7 @@ static void boot_prep_linux(bootm_headers_t *images) setup_initrd_tag(gd->bd, images->rd_start, images->rd_end); #endif + setup_board_tags(¶ms); setup_end_tag(gd->bd); #else /* all tags */ printf("FDT and ATAGS support not compiled in - hanging\n"); -- cgit v1.2.3 From 318e70e2447d2706b27e7d3b66a6dbc54ec01e7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 19 Oct 2012 02:00:06 +0000 Subject: Add power bus message definitions in twl4030.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Code copied from linux kernel 3.0.0 from file include/linux/i2c/twl.h * commit 6523b148b44be38d89c2ee9865d34da30d9f5f1c Signed-off-by: Pali Rohár --- include/twl4030.h | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/include/twl4030.h b/include/twl4030.h index 9cd32ab45a..0c17f5929b 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -151,6 +151,103 @@ #define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1) #define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0) +/* Power bus message definitions */ + +/* The TWL4030/5030 splits its power-management resources (the various + * regulators, clock and reset lines) into 3 processor groups - P1, P2 and + * P3. These groups can then be configured to transition between sleep, wait-on + * and active states by sending messages to the power bus. See Section 5.4.2 + * Power Resources of TWL4030 TRM + */ + +/* Processor groups */ +#define DEV_GRP_NULL 0x0 +#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ +#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ +#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ + +/* Resource groups */ +#define RES_GRP_RES 0x0 /* Reserved */ +#define RES_GRP_PP 0x1 /* Power providers */ +#define RES_GRP_RC 0x2 /* Reset and control */ +#define RES_GRP_PP_RC 0x3 +#define RES_GRP_PR 0x4 /* Power references */ +#define RES_GRP_PP_PR 0x5 +#define RES_GRP_RC_PR 0x6 +#define RES_GRP_ALL 0x7 /* All resource groups */ + +#define RES_TYPE2_R0 0x0 + +#define RES_TYPE_ALL 0x7 + +/* Resource states */ +#define RES_STATE_WRST 0xF +#define RES_STATE_ACTIVE 0xE +#define RES_STATE_SLEEP 0x8 +#define RES_STATE_OFF 0x0 + +/* Power resources */ + +/* Power providers */ +#define RES_VAUX1 1 +#define RES_VAUX2 2 +#define RES_VAUX3 3 +#define RES_VAUX4 4 +#define RES_VMMC1 5 +#define RES_VMMC2 6 +#define RES_VPLL1 7 +#define RES_VPLL2 8 +#define RES_VSIM 9 +#define RES_VDAC 10 +#define RES_VINTANA1 11 +#define RES_VINTANA2 12 +#define RES_VINTDIG 13 +#define RES_VIO 14 +#define RES_VDD1 15 +#define RES_VDD2 16 +#define RES_VUSB_1V5 17 +#define RES_VUSB_1V8 18 +#define RES_VUSB_3V1 19 +#define RES_VUSBCP 20 +#define RES_REGEN 21 +/* Reset and control */ +#define RES_NRES_PWRON 22 +#define RES_CLKEN 23 +#define RES_SYSEN 24 +#define RES_HFCLKOUT 25 +#define RES_32KCLKOUT 26 +#define RES_RESET 27 +/* Power Reference */ +#define RES_Main_Ref 28 + +#define TOTAL_RESOURCES 28 +/* + * Power Bus Message Format ... these can be sent individually by Linux, + * but are usually part of downloaded scripts that are run when various + * power events are triggered. + * + * Broadcast Message (16 Bits): + * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] + * RES_STATE[3:0] + * + * Singular Message (16 Bits): + * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] + */ + +#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ + ((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ + | (type) << 4 | (state)) + +#define MSG_SINGULAR(devgrp, id, state) \ + ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) + +#define MSG_BROADCAST_ALL(devgrp, state) \ + ((devgrp) << 5 | (state)) + +#define MSG_BROADCAST_REF MSG_BROADCAST_ALL +#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL +#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL + /* Power Managment Receiver */ #define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B #define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C @@ -311,6 +408,7 @@ #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03 +#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03 /* Device Selection in PM Receiver Module */ #define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20 -- cgit v1.2.3 From 33a35bbbe09a9b63b46e86a97d5dfbdae5481401 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 19 Oct 2012 13:30:09 +0000 Subject: cfb_console: Add support for some ANSI terminal escape codes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add optional support for some ANSI escape sequences to the cfb_console driver. Define CONFIG_CFB_CONSOLE_ANSI to enable cursor moving, color reverting and clearing the cfb console via ANSI escape codes. Signed-off-by: Pali Rohár Signed-off-by: Anatolij Gustschin --- README | 4 + drivers/video/cfb_console.c | 328 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 323 insertions(+), 9 deletions(-) diff --git a/README b/README index df4aed14e4..61e2e1ffc7 100644 --- a/README +++ b/README @@ -655,6 +655,10 @@ The following options need to be configured: additional board info beside the logo + When CONFIG_CFB_CONSOLE_ANSI is defined, console will support + a limited number of ANSI escape sequences (cursor control, + erase functions and limited graphics rendition control). + When CONFIG_CFB_CONSOLE is defined, video console is default i/o. Serial console can be forced with environment 'console=serial'. diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 9f7794fe53..9c67b63bf4 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -385,6 +385,13 @@ static u32 eorx, fgx, bgx; /* color pats */ static int cfb_do_flush_cache; +#ifdef CONFIG_CFB_CONSOLE_ANSI +static char ansi_buf[10]; +static int ansi_buf_size; +static int ansi_colors_need_revert; +static int ansi_cursor_hidden; +#endif + static const int video_font_draw_table8[] = { 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, @@ -768,9 +775,97 @@ static void console_back(void) } } -static void console_newline(void) +#ifdef CONFIG_CFB_CONSOLE_ANSI + +static void console_clear(void) +{ +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + video_logo_height, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS, /* frame height */ + bgx /* fill color */ + ); +#else + memsetl(CONSOLE_ROW_FIRST, CONSOLE_SIZE, bgx); +#endif +} + +static void console_cursor_fix(void) +{ + if (console_row < 0) + console_row = 0; + if (console_row >= CONSOLE_ROWS) + console_row = CONSOLE_ROWS - 1; + if (console_col < 0) + console_col = 0; + if (console_col >= CONSOLE_COLS) + console_col = CONSOLE_COLS - 1; +} + +static void console_cursor_up(int n) +{ + console_row -= n; + console_cursor_fix(); +} + +static void console_cursor_down(int n) +{ + console_row += n; + console_cursor_fix(); +} + +static void console_cursor_left(int n) +{ + console_col -= n; + console_cursor_fix(); +} + +static void console_cursor_right(int n) +{ + console_col += n; + console_cursor_fix(); +} + +static void console_cursor_set_position(int row, int col) +{ + if (console_row != -1) + console_row = row; + if (console_col != -1) + console_col = col; + console_cursor_fix(); +} + +static void console_previousline(int n) { - console_row++; + /* FIXME: also scroll terminal ? */ + console_row -= n; + console_cursor_fix(); +} + +static void console_swap_colors(void) +{ + eorx = fgx; + fgx = bgx; + bgx = eorx; + eorx = fgx ^ bgx; +} + +static inline int console_cursor_is_visible(void) +{ + return !ansi_cursor_hidden; +} +#else +static inline int console_cursor_is_visible(void) +{ + return 1; +} +#endif + +static void console_newline(int n) +{ + console_row += n; console_col = 0; /* Check if we need to scroll the terminal */ @@ -779,7 +874,7 @@ static void console_newline(void) console_scrollup(); /* Decrement row number */ - console_row--; + console_row = CONSOLE_ROWS - 1; } } @@ -788,11 +883,12 @@ static void console_cr(void) console_col = 0; } -void video_putc(const char c) +static void parse_putc(const char c) { static int nl = 1; - CURSOR_OFF; + if (console_cursor_is_visible()) + CURSOR_OFF; switch (c) { case 13: /* back to first column */ @@ -801,7 +897,7 @@ void video_putc(const char c) case '\n': /* next line */ if (console_col || (!console_col && nl)) - console_newline(); + console_newline(1); nl = 1; break; @@ -810,7 +906,7 @@ void video_putc(const char c) console_col &= ~0x0007; if (console_col >= CONSOLE_COLS) - console_newline(); + console_newline(1); break; case 8: /* backspace */ @@ -827,11 +923,225 @@ void video_putc(const char c) /* check for newline */ if (console_col >= CONSOLE_COLS) { - console_newline(); + console_newline(1); nl = 0; } } - CURSOR_SET; + + if (console_cursor_is_visible()) + CURSOR_SET; +} + +void video_putc(const char c) +{ +#ifdef CONFIG_CFB_CONSOLE_ANSI + int i; + + if (c == 27) { + for (i = 0; i < ansi_buf_size; ++i) + parse_putc(ansi_buf[i]); + ansi_buf[0] = 27; + ansi_buf_size = 1; + return; + } + + if (ansi_buf_size > 0) { + /* + * 0 - ESC + * 1 - [ + * 2 - num1 + * 3 - .. + * 4 - ; + * 5 - num2 + * 6 - .. + * - cchar + */ + int next = 0; + + int flush = 0; + int fail = 0; + + int num1 = 0; + int num2 = 0; + int cchar = 0; + + ansi_buf[ansi_buf_size++] = c; + + if (ansi_buf_size >= sizeof(ansi_buf)) + fail = 1; + + for (i = 0; i < ansi_buf_size; ++i) { + if (fail) + break; + + switch (next) { + case 0: + if (ansi_buf[i] == 27) + next = 1; + else + fail = 1; + break; + + case 1: + if (ansi_buf[i] == '[') + next = 2; + else + fail = 1; + break; + + case 2: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num1 = ansi_buf[i]-'0'; + next = 3; + } else if (ansi_buf[i] != '?') { + --i; + num1 = 1; + next = 4; + } + break; + + case 3: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num1 *= 10; + num1 += ansi_buf[i]-'0'; + } else { + --i; + next = 4; + } + break; + + case 4: + if (ansi_buf[i] != ';') { + --i; + next = 7; + } else + next = 5; + break; + + case 5: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num2 = ansi_buf[i]-'0'; + next = 6; + } else + fail = 1; + break; + + case 6: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num2 *= 10; + num2 += ansi_buf[i]-'0'; + } else { + --i; + next = 7; + } + break; + + case 7: + if ((ansi_buf[i] >= 'A' && ansi_buf[i] <= 'H') + || ansi_buf[i] == 'J' + || ansi_buf[i] == 'K' + || ansi_buf[i] == 'h' + || ansi_buf[i] == 'l' + || ansi_buf[i] == 'm') { + cchar = ansi_buf[i]; + flush = 1; + } else + fail = 1; + break; + } + } + + if (fail) { + for (i = 0; i < ansi_buf_size; ++i) + parse_putc(ansi_buf[i]); + ansi_buf_size = 0; + return; + } + + if (flush) { + if (!ansi_cursor_hidden) + CURSOR_OFF; + ansi_buf_size = 0; + switch (cchar) { + case 'A': + /* move cursor num1 rows up */ + console_cursor_up(num1); + break; + case 'B': + /* move cursor num1 rows down */ + console_cursor_down(num1); + break; + case 'C': + /* move cursor num1 columns forward */ + console_cursor_right(num1); + break; + case 'D': + /* move cursor num1 columns back */ + console_cursor_left(num1); + break; + case 'E': + /* move cursor num1 rows up at begin of row */ + console_previousline(num1); + break; + case 'F': + /* move cursor num1 rows down at begin of row */ + console_newline(num1); + break; + case 'G': + /* move cursor to column num1 */ + console_cursor_set_position(-1, num1-1); + break; + case 'H': + /* move cursor to row num1, column num2 */ + console_cursor_set_position(num1-1, num2-1); + break; + case 'J': + /* clear console and move cursor to 0, 0 */ + console_clear(); + console_cursor_set_position(0, 0); + break; + case 'K': + /* clear line */ + if (num1 == 0) + console_clear_line(console_row, + console_col, + CONSOLE_COLS-1); + else if (num1 == 1) + console_clear_line(console_row, + 0, console_col); + else + console_clear_line(console_row, + 0, CONSOLE_COLS-1); + break; + case 'h': + ansi_cursor_hidden = 0; + break; + case 'l': + ansi_cursor_hidden = 1; + break; + case 'm': + if (num1 == 0) { /* reset swapped colors */ + if (ansi_colors_need_revert) { + console_swap_colors(); + ansi_colors_need_revert = 0; + } + } else if (num1 == 7) { /* once swap colors */ + if (!ansi_colors_need_revert) { + console_swap_colors(); + ansi_colors_need_revert = 1; + } + } + break; + } + if (!ansi_cursor_hidden) + CURSOR_SET; + } + } else { + parse_putc(c); + } +#else + parse_putc(c); +#endif } void video_puts(const char *s) -- cgit v1.2.3 From ed407be53e1e8f0be90d5723ca71ab1c37e2eed8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 29 Oct 2012 07:54:01 +0000 Subject: New board support: Nokia RX-51 aka N900 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on previous work by: Alistair Buxton Signed-off-by: Pali Rohár Cc: Ивайло Димитров --- MAINTAINERS | 4 + board/nokia/rx51/Makefile | 46 +++ board/nokia/rx51/lowlevel_init.S | 209 ++++++++++++ board/nokia/rx51/rx51.c | 677 +++++++++++++++++++++++++++++++++++++++ board/nokia/rx51/rx51.h | 389 ++++++++++++++++++++++ board/nokia/rx51/tag_omap.h | 311 ++++++++++++++++++ boards.cfg | 1 + doc/README.nokia_rx51 | 104 ++++++ include/configs/nokia_rx51.h | 452 ++++++++++++++++++++++++++ 9 files changed, 2193 insertions(+) create mode 100644 board/nokia/rx51/Makefile create mode 100644 board/nokia/rx51/lowlevel_init.S create mode 100644 board/nokia/rx51/rx51.c create mode 100644 board/nokia/rx51/rx51.h create mode 100644 board/nokia/rx51/tag_omap.h create mode 100644 doc/README.nokia_rx51 create mode 100644 include/configs/nokia_rx51.h diff --git a/MAINTAINERS b/MAINTAINERS index c0fff0e40c..d4c511783f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1013,6 +1013,10 @@ Nobuhiro Iwamatsu armadillo-800eva R8A7740 (RMOBILE SoC) +Pali Rohár + + nokia_rx51 ARM ARMV7 (OMAP34xx SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/nokia/rx51/Makefile b/board/nokia/rx51/Makefile new file mode 100644 index 0000000000..86fb48cc99 --- /dev/null +++ b/board/nokia/rx51/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o +SOBJS-y := lowlevel_init.o + +COBJS := $(sort $(COBJS-y)) +SOBJS := $(sort $(SOBJS-y)) +SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S) +OBJS := $(addprefix $(obj),$(COBJS)) $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S new file mode 100644 index 0000000000..055b1038d1 --- /dev/null +++ b/board/nokia/rx51/lowlevel_init.S @@ -0,0 +1,209 @@ +/* + * (C) Copyright 2011-2012 + * Pali Rohár + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +relocaddr: /* address of this relocaddr section after coping */ + .word . /* address of section (calculated at compile time) */ + +startaddr: /* address of u-boot after copying */ + .word CONFIG_SYS_TEXT_BASE + +kernaddr: /* address of kernel after copying */ + .word KERNEL_ADDRESS + +kernsize: /* maximal size of kernel image */ + .word KERNEL_MAXSIZE + +kernoffs: /* offset of kernel image in loaded u-boot */ + .word KERNEL_OFFSET + +imagesize: /* maximal size of image */ + .word IMAGE_MAXSIZE + +ih_magic: /* IH_MAGIC in big endian from include/image.h */ + .word 0x56190527 + +/* + * Routine: save_boot_params (called after reset from start.S) + * Description: Copy attached kernel to address KERNEL_ADDRESS + * Copy u-boot to address CONFIG_SYS_TEXT_BASE + * Return to copied u-boot address + */ + +.global save_boot_params +save_boot_params: + + +/* Copy valid attached kernel to address KERNEL_ADDRESS */ + +copy_kernel_start: + adr r0, relocaddr /* r0 - address of section relocaddr */ + ldr r1, relocaddr /* r1 - address of relocaddr after relocation */ + cmp r0, r1 + + /* r4 - calculated offset */ + subhi r4, r0, r1 + sublo r4, r1, r0 + + /* r0 - start of kernel before */ + ldr r0, startaddr + addhi r0, r0, r4 + sublo r0, r0, r4 + ldr r1, kernoffs + add r0, r0, r1 + + /* r3 - start of kernel after */ + ldr r3, kernaddr + + /* r2 - end of kernel after */ + ldr r1, kernsize + add r2, r3, r1 + + /* r1 - end of kernel before */ + add r1, r0, r1 + + /* remove header in target kernel */ + mov r5, #0 + str r5, [r3] + + /* check for valid kernel uImage */ + ldr r4, [r0] /* r4 - 4 bytes header of kernel */ + ldr r5, ih_magic /* r5 - IH_MAGIC */ + cmp r4, r5 + bne copy_kernel_end /* skip if invalid image */ + +copy_kernel_loop: + ldmdb r1!, {r3 - r10} + stmdb r2!, {r3 - r10} + cmp r1, r0 + bhi copy_kernel_loop + +copy_kernel_end: + mov r5, #0 + str r5, [r0] /* remove 4 bytes header of kernel */ + + +/* Fix u-boot code */ + +fix_start: + adr r0, relocaddr /* r0 - address of section relocaddr */ + ldr r1, relocaddr /* r1 - address of relocaddr after relocation */ + cmp r0, r1 + + beq copy_uboot_end /* skip if u-boot is on correct address */ + + /* r5 - calculated offset */ + subhi r5, r0, r1 + sublo r5, r1, r0 + + /* r6 - maximal u-boot size */ + ldr r6, imagesize + + /* fix return address */ + subhi lr, lr, r5 + addlo lr, lr, r5 + + /* r1 - start of u-boot after */ + ldr r1, startaddr + + /* r0 - start of u-boot before */ + addhi r0, r1, r5 + sublo r0, r1, r5 + + /* check if we need to move uboot copy code before calling it */ + cmp r5, r6 + bhi copy_uboot_start /* now coping u-boot code directly is safe */ + + +copy_code_start: + /* r0 - start of u-boot before */ + /* r1 - start of u-boot after */ + /* r6 - maximal u-boot size */ + + /* r7 - maximal kernel size */ + ldr r7, kernsize + + /* r4 - end of kernel before */ + add r4, r0, r6 + add r4, r4, r7 + + /* r5 - end of u-boot after */ + ldr r5, startaddr + add r5, r5, r6 + + /* r2 - start of loop code after */ + cmp r4, r5 /* higher address (r4 or r5) */ + movhs r2, r4 + movlo r2, r5 + + /* r3 - end of loop code before */ + adr r3, end + + /* r4 - end of loop code after */ + adr r4, copy_uboot_start + sub r4, r3, r4 + add r4, r2, r4 + +copy_code_loop: + ldmdb r3!, {r7 - r10} + stmdb r4!, {r7 - r10} + cmp r4, r2 + bhi copy_code_loop + +copy_code_end: + mov pc, r2 + + +/* Copy u-boot to address CONFIG_SYS_TEXT_BASE */ + +copy_uboot_start: + /* r0 - start of u-boot before */ + /* r1 - start of u-boot after */ + /* r6 - maximal u-boot size */ + + /* r2 - end of u-boot after */ + add r2, r1, r6 + + /* condition for copying from left to right */ + cmp r0, r1 + addlo r1, r0, r6 /* r1 - end of u-boot before */ + blo copy_uboot_loop_right + +copy_uboot_loop_left: + ldmia r0!, {r3 - r10} + stmia r1!, {r3 - r10} + cmp r1, r2 + blo copy_uboot_loop_left + b copy_uboot_end + +copy_uboot_loop_right: + ldmdb r1!, {r3 - r10} + stmdb r2!, {r3 - r10} + cmp r1, r0 + bhi copy_uboot_loop_right + +copy_uboot_end: + bx lr + +end: diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c new file mode 100644 index 0000000000..b2fe1c531a --- /dev/null +++ b/board/nokia/rx51/rx51.c @@ -0,0 +1,677 @@ +/* + * (C) Copyright 2012 + * Ивайло Димитров + * + * (C) Copyright 2011-2012 + * Pali Rohár + * + * (C) Copyright 2010 + * Alistair Buxton + * + * Derived from Beagle Board and 3430 SDP code: + * (C) Copyright 2004-2008 + * Texas Instruments, + * + * Author : + * Sunil Kumar + * Shashi Ranjan + * + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rx51.h" +#include "tag_omap.h" + +DECLARE_GLOBAL_DATA_PTR; + +GraphicDevice gdev; + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "Nokia RX-51", + "OneNAND" +}; + +/* This structure contains default omap tags needed for booting Maemo 5 */ +static struct tag_omap omap[] = { + OMAP_TAG_UART_CONFIG(0x04), + OMAP_TAG_SERIAL_CONSOLE_CONFIG(0x03, 0x01C200), + OMAP_TAG_LCD_CONFIG("acx565akm", "internal", 90, 0x18), + OMAP_TAG_GPIO_SWITCH_CONFIG("cam_focus", 0x44, 0x1, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cam_launch", 0x45, 0x1, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cam_shutter", 0x6e, 0x1, 0x0, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_apeslpx", 0x46, 0x2, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_bsi", 0x9d, 0x2, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_en", 0x4a, 0x2, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst", 0x4b, 0x6, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst_rq", 0x49, 0x6, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_wddis", 0x0d, 0x2, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("headphone", 0xb1, 0x1, 0x1, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("kb_lock", 0x71, 0x1, 0x0, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("proximity", 0x59, 0x0, 0x0, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0), + OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0), + OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1), + OMAP_TAG_PARTITION_CONFIG(PART1_NAME, PART1_SIZE * PART1_MULL, + PART1_OFFS, PART1_MASK), + OMAP_TAG_PARTITION_CONFIG(PART2_NAME, PART2_SIZE * PART2_MULL, + PART2_OFFS, PART2_MASK), + OMAP_TAG_PARTITION_CONFIG(PART3_NAME, PART3_SIZE * PART3_MULL, + PART3_OFFS, PART3_MASK), + OMAP_TAG_PARTITION_CONFIG(PART4_NAME, PART4_SIZE * PART4_MULL, + PART4_OFFS, PART4_MASK), + OMAP_TAG_PARTITION_CONFIG(PART5_NAME, PART5_SIZE * PART5_MULL, + PART5_OFFS, PART5_MASK), + OMAP_TAG_PARTITION_CONFIG(PART6_NAME, PART6_SIZE * PART6_MULL, + PART6_OFFS, PART6_MASK), + OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"), + OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"), + OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"), + OMAP_TAG_VERSION_STR_CONFIG("nolo", "1.4.14"), + OMAP_TAG_VERSION_STR_CONFIG("boot-mode", "normal"), + { } +}; + +static char *boot_reason_ptr; +static char *hw_build_ptr; +static char *nolo_version_ptr; +static char *boot_mode_ptr; + +/* + * Routine: init_omap_tags + * Description: Initialize pointers to values in tag_omap + */ +static void init_omap_tags(void) +{ + char *component; + char *version; + int i = 0; + while (omap[i].hdr.tag) { + switch (omap[i].hdr.tag) { + case OMAP_TAG_BOOT_REASON: + boot_reason_ptr = omap[i].u.boot_reason.reason_str; + break; + case OMAP_TAG_VERSION_STR: + component = omap[i].u.version.component; + version = omap[i].u.version.version; + if (strcmp(component, "hw-build") == 0) + hw_build_ptr = version; + else if (strcmp(component, "nolo") == 0) + nolo_version_ptr = version; + else if (strcmp(component, "boot-mode") == 0) + boot_mode_ptr = version; + break; + default: + break; + } + i++; + } +} + +static void reuse_omap_atags(struct tag_omap *t) +{ + char *component; + char *version; + while (t->hdr.tag) { + switch (t->hdr.tag) { + case OMAP_TAG_BOOT_REASON: + memset(boot_reason_ptr, 0, 12); + strcpy(boot_reason_ptr, t->u.boot_reason.reason_str); + break; + case OMAP_TAG_VERSION_STR: + component = t->u.version.component; + version = t->u.version.version; + if (strcmp(component, "hw-build") == 0) { + memset(hw_build_ptr, 0, 12); + strcpy(hw_build_ptr, version); + } else if (strcmp(component, "nolo") == 0) { + memset(nolo_version_ptr, 0, 12); + strcpy(nolo_version_ptr, version); + } else if (strcmp(component, "boot-mode") == 0) { + memset(boot_mode_ptr, 0, 12); + strcpy(boot_mode_ptr, version); + } + break; + default: + break; + } + t = tag_omap_next(t); + } +} + +/* + * Routine: reuse_atags + * Description: Reuse atags from previous bootloader. + * Reuse only only HW build, boot reason, boot mode and nolo + */ +static void reuse_atags(void) +{ + struct tag *t = (struct tag *)gd->bd->bi_boot_params; + + /* First tag must be ATAG_CORE */ + if (t->hdr.tag != ATAG_CORE) + return; + + if (!boot_reason_ptr || !hw_build_ptr) + return; + + /* Last tag must be ATAG_NONE */ + while (t->hdr.tag != ATAG_NONE) { + switch (t->hdr.tag) { + case ATAG_REVISION: + memset(hw_build_ptr, 0, 12); + sprintf(hw_build_ptr, "%x", t->u.revision.rev); + break; + case ATAG_BOARD: + reuse_omap_atags((struct tag_omap *)&t->u); + break; + default: + break; + } + t = tag_next(t); + } +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + /* in SRAM or SDRAM, finish GPMC */ + gpmc_init(); + /* boot param addr */ + gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100; + return 0; +} + +/* + * Routine: get_board_revision + * Description: Return board revision. + */ +u32 get_board_rev(void) +{ + return simple_strtol(hw_build_ptr, NULL, 16); +} + +/* + * Routine: setup_board_tags + * Description: Append board specific boot tags. + */ +void setup_board_tags(struct tag **in_params) +{ + int setup_console_atag; + char *setup_boot_reason_atag; + char *setup_boot_mode_atag; + char *str; + int i; + int size; + int total_size; + struct tag *params; + struct tag_omap *t; + + params = (struct tag *)gd->bd->bi_boot_params; + + params->u.core.flags = 0x0; + params->u.core.pagesize = 0x1000; + params->u.core.rootdev = 0x0; + + /* append omap atag only if env setup_omap_atag is set to 1 */ + str = getenv("setup_omap_atag"); + if (!str || str[0] != '1') + return; + + str = getenv("setup_console_atag"); + if (str && str[0] == '1') + setup_console_atag = 1; + else + setup_console_atag = 0; + + setup_boot_reason_atag = getenv("setup_boot_reason_atag"); + setup_boot_mode_atag = getenv("setup_boot_mode_atag"); + + params = *in_params; + t = (struct tag_omap *)¶ms->u; + total_size = sizeof(struct tag_header); + + for (i = 0; omap[i].hdr.tag; i++) { + + /* skip serial console tag */ + if (!setup_console_atag && + omap[i].hdr.tag == OMAP_TAG_SERIAL_CONSOLE) + continue; + + size = omap[i].hdr.size + sizeof(struct tag_omap_header); + memcpy(t, &omap[i], size); + + /* set uart tag to 0 - disable serial console */ + if (!setup_console_atag && omap[i].hdr.tag == OMAP_TAG_UART) + t->u.uart.enabled_uarts = 0; + + /* change boot reason */ + if (setup_boot_reason_atag && + omap[i].hdr.tag == OMAP_TAG_BOOT_REASON) { + memset(t->u.boot_reason.reason_str, 0, 12); + strcpy(t->u.boot_reason.reason_str, + setup_boot_reason_atag); + } + + /* change boot mode */ + if (setup_boot_mode_atag && + omap[i].hdr.tag == OMAP_TAG_VERSION_STR && + strcmp(omap[i].u.version.component, "boot-mode") == 0) { + memset(t->u.version.version, 0, 12); + strcpy(t->u.version.version, setup_boot_mode_atag); + } + + total_size += size; + t = tag_omap_next(t); + + } + + params->hdr.tag = ATAG_BOARD; + params->hdr.size = total_size >> 2; + params = tag_next(params); + + *in_params = params; +} + +/* + * Routine: video_hw_init + * Description: Set up the GraphicDevice depending on sys_boot. + */ +void *video_hw_init(void) +{ + /* fill in Graphic Device */ + gdev.frameAdrs = 0x8f9c0000; + gdev.winSizeX = 800; + gdev.winSizeY = 480; + gdev.gdfBytesPP = 2; + gdev.gdfIndex = GDF_16BIT_565RGB; + memset((void *)gdev.frameAdrs, 0, 0xbb800); + return (void *) &gdev; +} + +/* + * Routine: twl4030_regulator_set_mode + * Description: Set twl4030 regulator mode over i2c powerbus. + */ +static void twl4030_regulator_set_mode(u8 id, u8 mode) +{ + u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg >> 8, + TWL4030_PM_MASTER_PB_WORD_MSB); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, msg & 0xff, + TWL4030_PM_MASTER_PB_WORD_LSB); +} + +static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) +{ + u32 i, num_params = *parameters; + u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; + + /* + * copy the parameters to an un-cached area to avoid coherency + * issues + */ + for (i = 0; i < num_params; i++) { + __raw_writel(*parameters, sram_scratch_space); + parameters++; + sram_scratch_space++; + } + + /* Now make the PPA call */ + do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); +} + +/* + * Routine: omap3_update_aux_cr_secure_rx51 + * Description: Modify the contents Auxiliary Control Register. + * Parameters: + * set_bits - bits to set in ACR + * clr_bits - bits to clear in ACR + */ +static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits) +{ + struct emu_hal_params_rx51 emu_romcode_params = { 0, }; + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + emu_romcode_params.num_params = 2; + emu_romcode_params.param1 = acr; + + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts. + */ +int misc_init_r(void) +{ + char buf[12]; + u8 state; + + /* reset lp5523 led */ + i2c_set_bus_num(1); + state = 0xff; + i2c_write(0x32, 0x3d, 1, &state, 1); + i2c_set_bus_num(0); + + /* initialize twl4030 power managment */ + twl4030_power_init(); + + /* set VSIM to 1.8V */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED, + TWL4030_PM_RECEIVER_VSIM_VSEL_18, + TWL4030_PM_RECEIVER_VSIM_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + /* store I2C access state */ + twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &state, + TWL4030_PM_MASTER_PB_CFG); + + /* enable I2C access to powerbus (needed for twl4030 regulator) */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x02, + TWL4030_PM_MASTER_PB_CFG); + + /* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */ + twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE); + twl4030_regulator_set_mode(RES_VSIM, RES_STATE_ACTIVE); + twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE); + + /* restore I2C access state */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, state, + TWL4030_PM_MASTER_PB_CFG); + + /* set env variable attkernaddr for relocated kernel */ + sprintf(buf, "%#x", KERNEL_ADDRESS); + setenv("attkernaddr", buf); + + /* initialize omap tags */ + init_omap_tags(); + + /* reuse atags from previous bootloader */ + reuse_atags(); + + dieid_num_r(); + print_cpuinfo(); + + /* + * Cortex-A8(r1p0..r1p2) errata 430973 workaround + * Set IBE bit in Auxiliary Control Register + */ + omap3_update_aux_cr_secure_rx51(1 << 6, 0); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_RX51(); +} + +static unsigned long int twl_wd_time; /* last time of watchdog reset */ +static unsigned long int twl_i2c_lock; + +/* + * Routine: hw_watchdog_reset + * Description: Reset timeout of twl4030 watchdog. + */ +void hw_watchdog_reset(void) +{ + u8 timeout = 0; + + /* do not reset watchdog too often - max every 4s */ + if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ) + return; + + /* localy lock twl4030 i2c bus */ + if (test_and_set_bit(0, &twl_i2c_lock)) + return; + + /* read actual watchdog timeout */ + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &timeout, + TWL4030_PM_RECEIVER_WATCHDOG_CFG); + + /* timeout 0 means watchdog is disabled */ + /* reset watchdog timeout to 31s (maximum) */ + if (timeout != 0) + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 31, + TWL4030_PM_RECEIVER_WATCHDOG_CFG); + + /* store last watchdog reset time */ + twl_wd_time = get_timer(0); + + /* localy unlock twl4030 i2c bus */ + test_and_clear_bit(0, &twl_i2c_lock); +} + +/* + * TWL4030 keypad handler for cfb_console + */ + +static const char keymap[] = { + /* normal */ + 'q', 'o', 'p', ',', '\b', 0, 'a', 's', + 'w', 'd', 'f', 'g', 'h', 'j', 'k', 'l', + 'e', '.', 0, '\r', 0, 'z', 'x', 'c', + 'r', 'v', 'b', 'n', 'm', ' ', ' ', 0, + 't', 0, 0, 0, 0, 0, 0, 0, + 'y', 0, 0, 0, 0, 0, 0, 0, + 'u', 0, 0, 0, 0, 0, 0, 0, + 'i', 5, 6, 0, 0, 0, 0, 0, + /* fn */ + '1', '9', '0', '=', '\b', 0, '*', '+', + '2', '#', '-', '_', '(', ')', '&', '!', + '3', '?', '^', '\r', 0, 156, '$', 238, + '4', '/', '\\', '"', '\'', '@', 0, '<', + '5', '|', '>', 0, 0, 0, 0, 0, + '6', 0, 0, 0, 0, 0, 0, 0, + '7', 0, 0, 0, 0, 0, 0, 0, + '8', 16, 17, 0, 0, 0, 0, 0, +}; + +static u8 keys[8]; +static u8 old_keys[8] = {0, 0, 0, 0, 0, 0, 0, 0}; +#define KEYBUF_SIZE 32 +static u8 keybuf[KEYBUF_SIZE]; +static u8 keybuf_head; +static u8 keybuf_tail; + +/* + * Routine: rx51_kp_init + * Description: Initialize HW keyboard. + */ +int rx51_kp_init(void) +{ + int ret = 0; + u8 ctrl; + ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, + TWL4030_KEYPAD_KEYP_CTRL_REG); + + if (ret) + return ret; + + /* turn on keyboard and use hardware scanning */ + ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON; + ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST; + ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN; + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, + TWL4030_KEYPAD_KEYP_CTRL_REG); + /* enable key event status */ + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0xfe, + TWL4030_KEYPAD_KEYP_IMR1); + /* enable interrupt generation on rising and falling */ + /* this is a workaround for qemu twl4030 emulation */ + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x57, + TWL4030_KEYPAD_KEYP_EDR); + /* enable ISR clear on read */ + ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, 0x05, + TWL4030_KEYPAD_KEYP_SIH_CTRL); + return 0; +} + +static void rx51_kp_fill(u8 k, u8 mods) +{ + /* check if some cursor key without meta fn key was pressed */ + if (!(mods & 2) && (k == 18 || k == 31 || k == 33 || k == 34)) { + keybuf[keybuf_tail++] = '\e'; + keybuf_tail %= KEYBUF_SIZE; + keybuf[keybuf_tail++] = '['; + keybuf_tail %= KEYBUF_SIZE; + if (k == 18) /* up */ + keybuf[keybuf_tail++] = 'A'; + else if (k == 31) /* left */ + keybuf[keybuf_tail++] = 'D'; + else if (k == 33) /* down */ + keybuf[keybuf_tail++] = 'B'; + else if (k == 34) /* right */ + keybuf[keybuf_tail++] = 'C'; + keybuf_tail %= KEYBUF_SIZE; + return; + } + + if (mods & 2) { /* fn meta key was pressed */ + k = keymap[k+64]; + } else { + k = keymap[k]; + if (mods & 1) { /* ctrl key was pressed */ + if (k >= 'a' && k <= 'z') + k -= 'a' - 1; + } + if (mods & 4) { /* shift key was pressed */ + if (k >= 'a' && k <= 'z') + k += 'A' - 'a'; + else if (k == '.') + k = ':'; + else if (k == ',') + k = ';'; + } + } + keybuf[keybuf_tail++] = k; + keybuf_tail %= KEYBUF_SIZE; +} + +/* + * Routine: rx51_kp_tstc + * Description: Test if key was pressed (from buffer). + */ +int rx51_kp_tstc(void) +{ + u8 c, r, dk, i; + u8 intr; + u8 mods; + + /* localy lock twl4030 i2c bus */ + if (test_and_set_bit(0, &twl_i2c_lock)) + return 0; + + /* twl4030 remembers up to 2 events */ + for (i = 0; i < 2; i++) { + + /* check interrupt register for events */ + twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &intr, + TWL4030_KEYPAD_KEYP_ISR1+(2*i)); + + /* no event */ + if (!(intr&1)) + continue; + + /* read the key state */ + i2c_read(TWL4030_CHIP_KEYPAD, + TWL4030_KEYPAD_FULL_CODE_7_0, 1, keys, 8); + + /* cut out modifier keys from the keystate */ + mods = keys[4] >> 4; + keys[4] &= 0x0f; + + for (c = 0; c < 8; c++) { + + /* get newly pressed keys only */ + dk = ((keys[c] ^ old_keys[c])&keys[c]); + old_keys[c] = keys[c]; + + /* fill the keybuf */ + for (r = 0; r < 8; r++) { + if (dk&1) + rx51_kp_fill((c*8)+r, mods); + dk = dk >> 1; + } + + } + + } + + /* localy unlock twl4030 i2c bus */ + test_and_clear_bit(0, &twl_i2c_lock); + + return (KEYBUF_SIZE + keybuf_tail - keybuf_head)%KEYBUF_SIZE; +} + +/* + * Routine: rx51_kp_getc + * Description: Get last pressed key (from buffer). + */ +int rx51_kp_getc(void) +{ + keybuf_head %= KEYBUF_SIZE; + while (!rx51_kp_tstc()) + WATCHDOG_RESET(); + return keybuf[keybuf_head++]; +} + +/* + * Routine: board_mmc_init + * Description: Initialize mmc devices. + */ +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0); + omap_mmc_init(1, 0, 0); + return 0; +} diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h new file mode 100644 index 0000000000..e66e241488 --- /dev/null +++ b/board/nokia/rx51/rx51.h @@ -0,0 +1,389 @@ +/* + * (C) Copyright 2012 + * Ивайло Димитров + * + * (C) Copyright 2011-2012 + * Pali Rohár + * + * (C) Copyright 2008 + * Dirk Behme + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _RX51_H_ +#define _RX51_H_ + +/* Needed for ROM SMC call */ +struct emu_hal_params_rx51 { + u32 num_params; + u32 param1; + u32 param2; + u32 param3; + u32 param4; +}; + +int print_cpuinfo(void); + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_RX51() \ +/* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ +/* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*nDMA_REQ2*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ +/* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ +/* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS*/\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS*/\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ +/* Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLK*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ +/* Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ +/* Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ +/* Bluetooth */\ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ +/* Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT*/\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG*/\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ +/* Serial Interface */\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOM*/\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ +/* USB EHCI (port 2) */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA1*/\ +/* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*MMC1_WP*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MD*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA0*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA1*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA2*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA7*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA4*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA5*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA6*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA3*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26m*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespw*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswa*/\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9ni*/\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmare0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmare1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmare2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmare3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrs*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtc*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeu*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlere*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleac*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusfl*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusfl*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ + +#define MUX_RX51_C() \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ + +#endif diff --git a/board/nokia/rx51/tag_omap.h b/board/nokia/rx51/tag_omap.h new file mode 100644 index 0000000000..60fa26f3e1 --- /dev/null +++ b/board/nokia/rx51/tag_omap.h @@ -0,0 +1,311 @@ +/* + * (C) Copyright 2011-2012 + * Pali Rohár + * + * (C) Copyright 2011 + * marcel@mesa.nl, Mesa Consulting B.V. + * + * (C) Copyright 2004-2005 + * Nokia Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +/* + * Code copied from maemo kernel 2.6.28 file + * arch/arm/plat-omap/include/mach/board.h + * + * Information structures for board-specific data + * + * Copyright (C) 2004 Nokia Corporation + * Written by Juha Yrjölä + */ + +/* Different peripheral ids */ +#define OMAP_TAG_CLOCK 0x4f01 +#define OMAP_TAG_SERIAL_CONSOLE 0x4f03 +#define OMAP_TAG_USB 0x4f04 +#define OMAP_TAG_LCD 0x4f05 +#define OMAP_TAG_GPIO_SWITCH 0x4f06 +#define OMAP_TAG_UART 0x4f07 +#define OMAP_TAG_FBMEM 0x4f08 +#define OMAP_TAG_STI_CONSOLE 0x4f09 +#define OMAP_TAG_CAMERA_SENSOR 0x4f0a +#define OMAP_TAG_PARTITION 0x4f0b +#define OMAP_TAG_TEA5761 0x4f10 +#define OMAP_TAG_TMP105 0x4f11 + +#define OMAP_TAG_BOOT_REASON 0x4f80 +#define OMAP_TAG_FLASH_PART_STR 0x4f81 +#define OMAP_TAG_VERSION_STR 0x4f82 + +#define OMAP_TAG_NOKIA_BT 0x4e01 +#define OMAP_TAG_WLAN_CX3110X 0x4e02 +#define OMAP_TAG_CBUS 0x4e03 +#define OMAP_TAG_EM_ASIC_BB5 0x4e04 + + +struct omap_clock_config { + /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ + u8 system_clock_type; +}; + +struct omap_serial_console_config { + u8 console_uart; + u32 console_speed; +}; + +struct omap_sti_console_config { + unsigned enable:1; + u8 channel; +}; + +struct omap_usb_config { + /* Configure drivers according to the connectors on your board: + * - "A" connector (rectagular) + * ... for host/OHCI use, set "register_host". + * - "B" connector (squarish) or "Mini-B" + * ... for device/gadget use, set "register_dev". + * - "Mini-AB" connector (very similar to Mini-B) + * ... for OTG use as device OR host, initialize "otg" + */ + unsigned register_host:1; + unsigned register_dev:1; + u8 otg; /* port number, 1-based: usb1 == 2 */ + + u8 hmc_mode; + + /* implicitly true if otg: host supports remote wakeup? */ + u8 rwc; + + /* signaling pins used to talk to transceiver on usbN: + * 0 == usbN unused + * 2 == usb0-only, using internal transceiver + * 3 == 3 wire bidirectional + * 4 == 4 wire bidirectional + * 6 == 6 wire unidirectional (or TLL) + */ + u8 pins[3]; +}; + +struct omap_lcd_config { + char panel_name[16]; + char ctrl_name[16]; + s16 nreset_gpio; + u8 data_lines; +}; + +struct omap_fbmem_config { + u32 start; + u32 size; +}; + +struct omap_gpio_switch_config { + char name[12]; + u16 gpio; + u8 flags:4; + u8 type:4; + unsigned int key_code:24; /* Linux key code */ +}; + +struct omap_uart_config { + /* Bit field of UARTs present; bit 0 --> UART1 */ + unsigned int enabled_uarts; +}; + +struct omap_tea5761_config { + u16 enable_gpio; +}; + +struct omap_partition_config { + char name[16]; + unsigned int size; + unsigned int offset; + /* same as in include/linux/mtd/partitions.h */ + unsigned int mask_flags; +}; + +struct omap_flash_part_str_config { + char part_table[0]; +}; + +struct omap_boot_reason_config { + char reason_str[12]; +}; + +struct omap_version_config { + char component[12]; + char version[12]; +}; + +/* + * Code copied from maemo kernel 2.6.28 file + * arch/arm/plat-omap/include/mach/board-nokia.h + * + * Information structures for Nokia-specific board config data + * + * Copyright (C) 2005 Nokia Corporation + */ + +struct omap_bluetooth_config { + u8 chip_type; + u8 bt_wakeup_gpio; + u8 host_wakeup_gpio; + u8 reset_gpio; + u8 bt_uart; + u8 bd_addr[6]; + u8 bt_sysclk; +}; + +struct omap_wlan_cx3110x_config { + u8 chip_type; + u8 reserverd; + s16 power_gpio; + s16 irq_gpio; + s16 spi_cs_gpio; +}; + +struct omap_cbus_config { + s16 clk_gpio; + s16 dat_gpio; + s16 sel_gpio; +}; + +struct omap_em_asic_bb5_config { + s16 retu_irq_gpio; + s16 tahvo_irq_gpio; +}; + +/* + * omap_tag handling + * + * processing omap tag structures + * + * Copyright (C) 2011 marcel@mesa.nl, Mesa Consulting B.V. + * Copyright (C) 2012 Pali Rohár + */ + +/* TI OMAP specific information */ +#define ATAG_BOARD 0x414f4d50 + +struct tag_omap_header { + u16 tag; + u16 size; +}; + +struct tag_omap { + struct tag_omap_header hdr; + union { + struct omap_clock_config clock; + struct omap_serial_console_config serial_console; + struct omap_sti_console_config sti_console; + struct omap_usb_config usb; + struct omap_lcd_config lcd; + struct omap_fbmem_config fbmem; + struct omap_gpio_switch_config gpio_switch; + struct omap_uart_config uart; + struct omap_tea5761_config tea5761; + struct omap_partition_config partition; + struct omap_flash_part_str_config flash_part_str; + struct omap_boot_reason_config boot_reason; + struct omap_version_config version; + struct omap_bluetooth_config bluetooth; + struct omap_wlan_cx3110x_config wlan_cx3110x; + struct omap_cbus_config cbus; + struct omap_em_asic_bb5_config em_asic_bb5; + } u; +}; + +#define tag_omap_next(t) ((struct tag_omap *)((u8 *)(t) + \ + (t)->hdr.size + sizeof(struct tag_omap_header))) + +#define OMAP_TAG_HEADER_CONFIG(config, type) \ + .hdr.tag = config, \ + .hdr.size = sizeof(struct type) + +#define OMAP_TAG_UART_CONFIG(p1) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_UART, omap_uart_config), \ + .u.uart.enabled_uarts = p1, \ + } + +#define OMAP_TAG_SERIAL_CONSOLE_CONFIG(p1, p2) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_SERIAL_CONSOLE, \ + omap_serial_console_config), \ + .u.serial_console.console_uart = p1, \ + .u.serial_console.console_speed = p2, \ + } + +#define OMAP_TAG_LCD_CONFIG(p1, p2, p3, p4) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_LCD, omap_lcd_config), \ + .u.lcd.panel_name = p1, \ + .u.lcd.ctrl_name = p2, \ + .u.lcd.nreset_gpio = p3, \ + .u.lcd.data_lines = p4, \ + } + +#define OMAP_TAG_GPIO_SWITCH_CONFIG(p1, p2, p3, p4, p5) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_GPIO_SWITCH, \ + omap_gpio_switch_config), \ + .u.gpio_switch.name = p1, \ + .u.gpio_switch.gpio = p2, \ + .u.gpio_switch.flags = p3, \ + .u.gpio_switch.type = p4, \ + .u.gpio_switch.key_code = p5, \ + } + +#define OMAP_TAG_WLAN_CX3110X_CONFIG(p1, p2, p3, p4, p5) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_WLAN_CX3110X, \ + omap_wlan_cx3110x_config), \ + .u.wlan_cx3110x.chip_type = p1, \ + .u.wlan_cx3110x.reserverd = p2, \ + .u.wlan_cx3110x.power_gpio = p3, \ + .u.wlan_cx3110x.irq_gpio = p4, \ + .u.wlan_cx3110x.spi_cs_gpio = p5, \ + } + +#define OMAP_TAG_PARTITION_CONFIG(p1, p2, p3, p4) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_PARTITION, \ + omap_partition_config), \ + .u.partition.name = p1, \ + .u.partition.size = p2, \ + .u.partition.offset = p3, \ + .u.partition.mask_flags = p4, \ + } + +#define OMAP_TAG_BOOT_REASON_CONFIG(p1) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_BOOT_REASON, \ + omap_boot_reason_config), \ + .u.boot_reason.reason_str = p1, \ + } + +#define OMAP_TAG_VERSION_STR_CONFIG(p1, p2) \ + { \ + OMAP_TAG_HEADER_CONFIG(OMAP_TAG_VERSION_STR, \ + omap_version_config), \ + .u.version.component = p1, \ + .u.version.version = p2, \ + } diff --git a/boards.cfg b/boards.cfg index a1bae069c2..92eb778d56 100644 --- a/boards.cfg +++ b/boards.cfg @@ -269,6 +269,7 @@ devkit8000 arm armv7 devkit8000 timll mcx arm armv7 mcx htkw omap3 tricorder arm armv7 tricorder corscience omap3 twister arm armv7 twister technexion omap3 +nokia_rx51 arm armv7 rx51 nokia omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 diff --git a/doc/README.nokia_rx51 b/doc/README.nokia_rx51 new file mode 100644 index 0000000000..a8fdfcd372 --- /dev/null +++ b/doc/README.nokia_rx51 @@ -0,0 +1,104 @@ +Board: Nokia RX-51 aka N900 + +This board definition results in a u-boot.bin which can be chainloaded +from NOLO in qemu or on a real N900. It does very little hardware config +because NOLO has already configured the board. Only needed is enabling +internal eMMC memory via twl4030 regulator which is not enabled by NOLO. + +NOLO is expecting a kernel image and will treat any image it finds in +onenand as such. This u-boot is intended to be flashed to the N900 like +a kernel. In order to transparently boot the original kernel, it will be +appended to u-boot.bin at 0x40000. NOLO will load the entire image into +(random) memory and execute u-boot, which saves hw revision, boot reason +and boot mode ATAGs set by NOLO. Then the bootscripts will attempt to load +uImage or boot.scr from a fat, ext2/ext3 or ext4 filesystem in external +SD card or internal eMMC memory. If this fails or keyboard is closed then +the appended kernel image will be booted using some generated and some +stored ATAGs (see boot order). + +There is support for hardware watchdog. Hardware watchdog is started by +NOLO so u-boot must kick watchdog to prevent reboot device (but not very +often, max every 2 seconds). There is also support for framebuffer display +output with ANSI espace codes and the N900 HW keyboard input. USB tty works +but is disabled because it prevents the current Maemo kernel from booting. + +When U-Boot is starting it enable IBE bit in Auxiliary Control Register, +which is needed for Thumb-2 ISA support. It is workaround for errata 430973. + +Default boot order: + + * 0. if keyboard is closed boot automatically attached kernel image + * 1. try boot from external SD card + * 2. try boot from internal eMMC memory + * 3. try boot from attached kernel image + +Boot from SD or eMMC in this order: + + * 1. + * 1.1 find boot.scr on first fat partition + * 1.2 find uImage on first fat parition + * 1.3 same order for 2. - 4. fat partition + * 2. same as 1. but for ext2/3 partition + * 3. same as 1. but for ext4 partition + + +Available additional commands/variables: + + * run sercon - Use serial port for control + * run usbcon - Use usbtty for control + * run vgacon - Use framebuffer and HW keyboard for control (default) + + * run sdboot - Boot from external SD card (see boot order) + * run emmcboot - Boot from internal eMMC memory (see boot order) + * run attachboot - Boot attached kernel image (attached to U-Boot binary) + + * run scriptload - Load boot script ${mmcscriptfile} + * run scriptboot - Run loaded boot script + * run kernload - Load kernel image ${mmckernfile} + * run initrdload - Load initrd image ${mmcinitrdfile} + * run kernboot - Boot loaded kernel image + * run kerninitrdboot - Boot loaded kernel image with loaded initrd image + + * run trymmcscriptboot - Try to load and boot script ${mmcscriptfile} + * run trymmckernboot - Try to load and boot kernel image ${mmckernfile} + * run trymmckerninitrdboot - Try to load and boot kernel image ${mmckernfile} + with initrd image ${mmcinitrdfile} + +Additional variables for loading files from mmc: + + * mmc ${mmcnum} (0 - external, 1 - internal) + * partition number ${mmcpart} (1 - 4) + * parition type ${mmctype} (fat, ext2) + +Additional varuables for booting kernel: + + * setup_omap_atag - Add OMAP table into atags structure (needs maemo kernel) + * setup_console_atag - Enable serial console in OMAP table + * setup_boot_reason_atag - Change boot reason in OMAP table + * setup_boot_mode_atag - Change boot mode in OMAP table + +USB TTY: + + Maemo kernel 2.6.28 will crash if u-boot enable usb tty. So USB TTY is disabled. + For enabling USB TTY just add this line to file include/configs/nokia_rx51.h + + #define CONFIG_USB_TTY + + +ONENAND support: + + ONENAND support is disabled because not working yet and cause linux kernel to + crash or no access to mtd. For enabling ONENAND support add this line at begin + of file include/configs/nokia_rx51.h + + #define ONENAND_SUPPORT + + +UBIFS support: + + UBIFS support is disabled, because U-Boot image is too big and cannot be + flashed with attached zImage to RX-51 kernel nand area. For enabling UBIFS + support first enable ONENAND support and then add this line at begin of file + include/configs/nokia_rx51.h + + #define UBIFS_SUPPORT diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h new file mode 100644 index 0000000000..8506604a76 --- /dev/null +++ b/include/configs/nokia_rx51.h @@ -0,0 +1,452 @@ +/* + * (C) Copyright 2011-2012 + * Pali Rohár + * + * (C) Copyright 2010 + * Alistair Buxton + * + * Derived from Beagle Board code: + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * Configuration settings for the Nokia RX-51 aka N900. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ + +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3430 /* which is in a 3430 */ +#define CONFIG_OMAP3_RX51 /* working with RX51 */ +#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ + +#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 + +/* + * Nokia X-Loader loading secondary image to address 0x80400000 + * NOLO loading boot image to random place, so it doesn't really + * matter what we set this to. We have to copy u-boot to this address + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include /* get chip and board defs */ +#include +#include +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R +#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ + +#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */ +#define CONFIG_INITRD_TAG /* enable passing initrd */ +#define CONFIG_REVISION_TAG /* enable passing revision tag*/ +#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_UBI_SIZE (512 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on RX-51 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_MUSB_UDC +#define CONFIG_MUSB_HDC +#define CONFIG_USB_OMAP3 +#define CONFIG_TWL4030_USB + +/* USB device configuration */ +#define CONFIG_USB_DEVICE +#define CONFIG_USBD_VENDORID 0x0421 +#define CONFIG_USBD_PRODUCTID 0x01c8 +#define CONFIG_USBD_MANUFACTURER "Nokia" +#define CONFIG_USBD_PRODUCT_NAME "N900" + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_NO_FLASH + +/* commands to include */ +#include + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_EXT4 /* EXT4 Support */ +#define CONFIG_CMD_FAT /* FAT support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_GPIO /* Enable gpio command */ + +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +#define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */ + +#ifdef ONENAND_SUPPORT + +#define CONFIG_CMD_ONENAND /* ONENAND support */ +#define CONFIG_CMD_MTDPARTS /* mtd parts support */ + +#ifdef UBIFS_SUPPORT +#define CONFIG_CMD_UBI /* UBI Support */ +#define CONFIG_CMD_UBIFS /* UBIFS Support */ +#endif + +#endif + +/* commands not needed from config_cmd_default.h */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ +#undef CONFIG_CMD_SAVEENV /* saveenv */ +#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ + +#define CONFIG_OMAP3_SPI +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED +#define CONFIG_TWL4030_KEYPAD + +#define CONFIG_OMAP_GPIO +#define GPIO_SLIDE 71 + +/* + * Board ONENAND Info. + */ + +#define PART1_NAME "bootloader" +#define PART1_SIZE 128 +#define PART1_MULL 1024 +#define PART1_SUFF "k" +#define PART1_OFFS 0x00000000 +#define PART1_MASK 0x00000003 + +#define PART2_NAME "config" +#define PART2_SIZE 384 +#define PART2_MULL 1024 +#define PART2_SUFF "k" +#define PART2_OFFS 0x00020000 +#define PART2_MASK 0x00000000 + +#define PART3_NAME "log" +#define PART3_SIZE 256 +#define PART3_MULL 1024 +#define PART3_SUFF "k" +#define PART3_OFFS 0x00080000 +#define PART3_MASK 0x00000000 + +#define PART4_NAME "kernel" +#define PART4_SIZE 2 +#define PART4_MULL 1024*1024 +#define PART4_SUFF "m" +#define PART4_OFFS 0x000c0000 +#define PART4_MASK 0x00000000 + +#define PART5_NAME "initfs" +#define PART5_SIZE 2 +#define PART5_MULL 1024*1024 +#define PART5_SUFF "m" +#define PART5_OFFS 0x002c0000 +#define PART5_MASK 0x00000000 + +#define PART6_NAME "rootfs" +#define PART6_SIZE 257280 +#define PART6_MULL 1024 +#define PART6_SUFF "k" +#define PART6_OFFS 0x004c0000 +#define PART6_MASK 0x00000000 + +#ifdef ONENAND_SUPPORT + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#ifdef UBIFS_SUPPORT +#define CONFIG_RBTREE +#define CONFIG_LZO +#endif + +#define MTDIDS_DEFAULT "onenand0=onenand" +#define MTDPARTS_DEFAULT "mtdparts=onenand:" \ + __stringify(PART1_SIZE) PART1_SUFF "(" PART1_NAME ")ro," \ + __stringify(PART2_SIZE) PART2_SUFF "(" PART2_NAME ")," \ + __stringify(PART3_SIZE) PART3_SUFF "(" PART3_NAME ")," \ + __stringify(PART4_SIZE) PART4_SUFF "(" PART4_NAME ")," \ + __stringify(PART5_SIZE) PART5_SUFF "(" PART5_NAME ")," \ + "-(" PART6_NAME ")" + +#endif + +/* Watchdog support */ +#define CONFIG_HW_WATCHDOG + +/* + * Framebuffer + */ +/* Video console */ +#define CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_CFB_CONSOLE_ANSI /* Enable ANSI escape codes in framebuffer */ +#define CONFIG_VIDEO_LOGO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN + +/* functions for cfb_console */ +#define VIDEO_KBD_INIT_FCT rx51_kp_init() +#define VIDEO_TSTC_FCT rx51_kp_tstc +#define VIDEO_GETC_FCT rx51_kp_getc +#ifndef __ASSEMBLY__ +int rx51_kp_init(void); +int rx51_kp_tstc(void); +int rx51_kp_getc(void); +#endif + +#ifndef MTDPARTS_DEFAULT +#define MTDPARTS_DEFAULT +#endif + +/* Environment information */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "usbtty=cdc_acm\0" \ + "stdin=vga\0" \ + "stdout=vga\0" \ + "stderr=vga\0" \ + "setcon=setenv stdin ${con};" \ + "setenv stdout ${con};" \ + "setenv stderr ${con}\0" \ + "sercon=setenv con serial; run setcon\0" \ + "usbcon=setenv con usbtty; run setcon\0" \ + "vgacon=setenv con vga; run setcon\0" \ + "slide=gpio input " __stringify(GPIO_SLIDE) "\0" \ + "switchmmc=mmc dev ${mmcnum}\0" \ + "kernaddr=0x82008000\0" \ + "initrdaddr=0x84008000\0" \ + "scriptaddr=0x86008000\0" \ + "fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \ + "${loadaddr} ${mmcfile}\0" \ + "kernload=setenv loadaddr ${kernaddr};" \ + "setenv mmcfile ${mmckernfile};" \ + "run fileload\0" \ + "initrdload=setenv loadaddr ${initrdaddr};" \ + "setenv mmcfile ${mmcinitrdfile};" \ + "run fileload\0" \ + "scriptload=setenv loadaddr ${scriptaddr};" \ + "setenv mmcfile ${mmcscriptfile};" \ + "run fileload\0" \ + "scriptboot=echo Running ${mmcscriptfile} from mmc " \ + "${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \ + "kernboot=echo Booting ${mmckernfile} from mmc " \ + "${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \ + "kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\ + "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \ + "attachboot=echo Booting attached kernel image ...;" \ + "setenv setup_omap_atag 1;" \ + "bootm ${attkernaddr};" \ + "setenv setup_omap_atag\0" \ + "trymmcscriptboot=if run switchmmc; then " \ + "if run scriptload; then " \ + "run scriptboot;" \ + "fi;" \ + "fi\0" \ + "trymmckernboot=if run switchmmc; then " \ + "if run kernload; then " \ + "run kernboot;" \ + "fi;" \ + "fi\0" \ + "trymmckerninitrdboot=if run switchmmc; then " \ + "if run initrdload; then " \ + "if run kernload; then " \ + "run kerninitrdboot;" \ + "fi;" \ + "fi; " \ + "fi\0" \ + "trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \ + "setenv mmckernfile uImage; run trymmckernboot\0" \ + "trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \ + "setenv mmcpart 2; run trymmcpartboot;" \ + "setenv mmcpart 3; run trymmcpartboot;" \ + "setenv mmcpart 4; run trymmcpartboot\0" \ + "trymmcboot=if run switchmmc; then " \ + "setenv mmctype fat;" \ + "run trymmcallpartboot;" \ + "setenv mmctype ext2;" \ + "run trymmcallpartboot;" \ + "setenv mmctype ext4;" \ + "run trymmcallpartboot;" \ + "fi\0" \ + "emmcboot=setenv mmcnum 1; run trymmcboot\0" \ + "sdboot=setenv mmcnum 0; run trymmcboot\0" \ + "" + +#define CONFIG_PREBOOT \ + "if run slide; then true; else run attachboot; fi;" \ + "echo Extra commands:;" \ + "echo run sercon - Use serial port for control.;" \ + "echo run usbcon - Use usbtty for control.;" \ + "echo run vgacon - Use framebuffer/keyboard.;" \ + "echo run sdboot - Boot from SD card slot.;" \ + "echo run emmcboot - Boot internal eMMC memory.;" \ + "echo run attachboot - Boot attached kernel image.;" \ + "echo" + +#define CONFIG_BOOTCOMMAND \ + "run sdboot;" \ + "run emmcboot;" \ + "run attachboot;" \ + "echo" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Nokia RX-51 # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/ + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 + +/* + * FLASH and environment organization + */ + +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * Attached kernel image + */ + +#define SDRAM_SIZE 0x10000000 /* 256 MB */ +#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) + +#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ +#define KERNEL_OFFSET 0x40000 /* 256 kB */ +#define KERNEL_MAXSIZE (IMAGE_MAXSIZE-KERNEL_OFFSET) +#define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE) + +/* Reserve protected RAM for attached kernel */ +#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1) + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 843a7ee8c4b1e47fae41268d6b95306f7e6408f5 Mon Sep 17 00:00:00 2001 From: Raphael Assenat Date: Mon, 22 Oct 2012 05:23:46 +0000 Subject: eco5pk: Add new board and default config Signed-off-by: Raphael Assenat [trini: Squash boards.cfg / MAINTAINERS change into main patch] Signed-off-by: Tom Rini --- MAINTAINERS | 4 + board/8dtech/eco5pk/Makefile | 43 +++++ board/8dtech/eco5pk/eco5pk.c | 61 +++++++ board/8dtech/eco5pk/eco5pk.h | 404 +++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/eco5pk.h | 81 +++++++++ 6 files changed, 594 insertions(+) create mode 100644 board/8dtech/eco5pk/Makefile create mode 100644 board/8dtech/eco5pk/eco5pk.c create mode 100644 board/8dtech/eco5pk/eco5pk.h create mode 100644 include/configs/eco5pk.h diff --git a/MAINTAINERS b/MAINTAINERS index d4c511783f..f4625c3f05 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -573,6 +573,10 @@ Albert ARIBAUD edminiv2 ARM926EJS (Orion5x SoC) +Raphael Assenat + + eco5pk ARM ARMV7 (AM35x SoC) + Stefano Babic ea20 davinci diff --git a/board/8dtech/eco5pk/Makefile b/board/8dtech/eco5pk/Makefile new file mode 100644 index 0000000000..befe60aac0 --- /dev/null +++ b/board/8dtech/eco5pk/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Adapted from ti/evm/Makefile +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := eco5pk.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/8dtech/eco5pk/eco5pk.c b/board/8dtech/eco5pk/eco5pk.c new file mode 100644 index 0000000000..cdb5b6f67d --- /dev/null +++ b/board/8dtech/eco5pk/eco5pk.c @@ -0,0 +1,61 @@ +/* + * eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board + * + * Based on am3517evm.c + * + * Copyright (C) 2011-2012 8D Technologies inc. + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "eco5pk.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + gpio_request(30, "RESOUT"); + gpio_direction_output(30, 1); + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_ECO5_PK(); +} diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h new file mode 100644 index 0000000000..d289e2bf1d --- /dev/null +++ b/board/8dtech/eco5pk/eco5pk.h @@ -0,0 +1,404 @@ +/* + * eco5.h - Header file for the 8D Technologies ECO5 board. + * + * Based on am3517evm.h + * Based on ti/evm/evm.h + * + * Copyright (C) 2011 8D Technologies inc. + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _ECO5PK_H__ +#define _ECO5PK_H__ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "ECO5 Board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_ECO5_PK() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ + /* - ETH_nRESET*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + /* - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \ + \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ + /* - LCD_INI*/\ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ + /* - LCD_ENVDD */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ + /* - LCD_QVGA/nVGA */\ + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ + /* - LCD_RESB */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ + /* - LAN_INTR*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ + /* LCD_EN_BACKLIGHT */\ + MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + /* SYS_nRESWARM */\ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + /* - GPIO30 */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ + /* - PEN_IRQ */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) + +#endif diff --git a/boards.cfg b/boards.cfg index 92eb778d56..36415a79b2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -245,6 +245,7 @@ mx6qarm2 arm armv7 mx6qarm2 freesca mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +eco5pk arm armv7 eco5pk 8dtech omap3 cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h new file mode 100644 index 0000000000..b9ebf6a2a8 --- /dev/null +++ b/include/configs/eco5pk.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2012 8D Technologies inc. + * Based on mt_ventoux.h, original banner below: + * + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2009 TechNexion Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tam3517-common.h" + +#undef CONFIG_USB_EHCI +#undef CONFIG_USB_EHCI_OMAP +#undef CONFIG_USB_OMAP3 +#undef CONFIG_CMD_USB + +/* Our console port is port3 */ +#undef CONFIG_CONS_INDEX +#undef CONFIG_SYS_NS16550_COM1 +#undef CONFIG_SERIAL1 + +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 + +#define MACH_TYPE_ECO5_PK 4017 +#define CONFIG_MACH_TYPE MACH_TYPE_ECO5_PK + +#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "ECO5-PK # " +#define CONFIG_SYS_PROMPT V_PROMPT + +/* + * Set its own mtdparts, different from common + */ +#undef MTDIDS_DEFAULT +#undef MTDPARTS_DEFAULT +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader-nand)," \ + "1024k(uboot-nand),256k(params-nand)," \ + "5120k(kernel),-(ubifs)" + +/* + * The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten. + */ +#undef CONFIG_ENV_OFFSET_REDUND +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_SYS_ENV_SECT_SIZE) + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ + "install_kernel=if dhcp $bootfile; then nand erase kernel;" \ + "nand write $fileaddr kernel; fi\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" \ + "serverip=192.168.142.60\0" + + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 9cd7b4cdca2500608b218fb4de215eddd8e66111 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Tue, 23 Oct 2012 01:56:40 +0000 Subject: am335x: add mux config for DDR3 version of beaglebone This fixes the following boothang in SPL: Unknown board, cannot configure pinmux.### ERROR ### Please RESET the board ### Future commits will add pinmuxes for more on-board peripherals. Signed-off-by: Koen Kooi --- board/ti/am335x/mux.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 6a5f23a551..acb8ff3e5c 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -256,6 +256,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux_sk_evm); + } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) { + /* Beaglebone LT pinmux */ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mmc1_pin_mux); } else { puts("Unknown board, cannot configure pinmux."); hang(); -- cgit v1.2.3 From 57f588be60eac8135cdfb366237fbf6e6dc2d316 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 30 Oct 2012 22:23:28 -0700 Subject: omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFF When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings currently. Re-order functions so that we don't have that anymore. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap3/board.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9cee1d9b49..f3cd81ad98 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; static void omap3_setup_aux_cr(void); +#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); +#endif static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } } -static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); -} - static void omap3_setup_aux_cr(void) { /* Workaround for Cortex-A8 errata: #454179 #430973 @@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void) } #ifndef CONFIG_SYS_L2CACHE_OFF +static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + /* Write ACR - affects non-secure banked bits */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); +} + /* Invalidate the entire L2 cache from secure mode */ static void omap3_invalidate_l2_cache_secure(void) { -- cgit v1.2.3 From 60607c9de01afb53cb284cede3481d0167fc9df0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Wed, 17 Oct 2012 00:00:48 +0000 Subject: avr32: allow multi block mmc access for all boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 1db7377a70a8d931c32648e717695133120d5456 fixes the gen_atmel_mci driver to be able to use multi block access for avr32. Therefore remove the setting which forces single block access. This also adds a huge performace gain for mmc access: ---8<--- Loading file "/boot/uImage" from mmc device 0:1 1830666 bytes read in 1293 ms (1.3 MiB/s) --->8--- vs. ---8<--- Loading file "/boot/uImage" from mmc device 0:1 1830666 bytes read in 237 ms (7.4 MiB/s) --->8--- Signed-off-by: Andreas Bießmann Cc: haavard.skinnemoen@atmel.com Cc: hans-christian.egtvedt@atmel.com Cc: mpfj@mimc.co.uk Cc: alex.raimondi@miromico.ch Cc: julien.may@miromico.ch Cc: egtvedt@samfundet.no Cc: havard@skinnemoen.net --- include/configs/atngw100.h | 1 - include/configs/atngw100mkii.h | 1 - include/configs/atstk1002.h | 1 - include/configs/atstk1003.h | 1 - include/configs/atstk1004.h | 1 - include/configs/atstk1006.h | 1 - include/configs/favr-32-ezkit.h | 1 - include/configs/hammerhead.h | 1 - include/configs/mimc200.h | 1 - 9 files changed, 9 deletions(-) diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 5e3155dffc..6bd1397dcd 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -130,7 +130,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_ATMEL_SPI #define CONFIG_SPI_FLASH diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index f85374f882..998cb97a55 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -154,7 +154,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_ATMEL_SPI #define CONFIG_SPI_FLASH diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index bb426f1edb..c6b129aff9 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -153,7 +153,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 817d94373e..67ff39bfd9 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -137,7 +137,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 5134b7ffa5..a1d593b5cf 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -137,7 +137,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 29fdd126a7..280ecbccc8 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -153,7 +153,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 71d2473a90..1c8da9f91a 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -152,7 +152,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index 532feb2f6c..5570bdb468 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -126,7 +126,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index d5797cb2e6..8031a05fc8 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -131,7 +131,6 @@ #define CONFIG_MMC #define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1 #if defined(CONFIG_LCD) #define CONFIG_CMD_BMP -- cgit v1.2.3 From a956bdcb3ff759f753e3f0c5e40e58f4c3056e22 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 2 Nov 2012 03:35:59 +0000 Subject: am335x: add initial AM335x IDK board support This patch extends the am335x_evm board for the AM335x IDK. The IDK board uses MII for the ethernet phy (same as Beaglebone board) and MMC0 for storage (but without card detect line). The IDK uses UART3 for console. So u-boot must be build with CONFIG_SERIAL4 and CONFIG_CONS_INDEX=4 or for the am335x_evm_uart3 board configuration as introduced by Andrew Bradfords recent patch series "am33xx: Enable UART {1,2,3,4,5}...". When using the IDK with console on UART0, those patches are not required. In this case the board slightly needs to be modified. Signed-off-by: Matthias Fuchs --- board/ti/am335x/board.c | 7 ++++++- board/ti/am335x/mux.c | 20 ++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 013ad881f0..e5ad76e9a0 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -68,6 +68,11 @@ static inline int board_is_evm_sk(void) return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); } +static inline int board_is_idk(void) +{ + return !strncmp(header.config, "SKU#02", 6); +} + /* * Read header information from EEPROM into global structure. */ @@ -378,7 +383,7 @@ int board_eth_init(bd_t *bis) return -1; } - if (board_is_bone() || board_is_bone_lt()) { + if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index acb8ff3e5c..8437ef515a 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -69,6 +69,17 @@ static struct module_pin_mux mmc0_pin_mux[] = { {-1}, }; +static struct module_pin_mux mmc0_no_cd_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {-1}, +}; + static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ @@ -250,6 +261,15 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } + } else if (!strncmp(header->config, "SKU#02", 6)) { + /* + * Industrial Motor Control (IDK) + * note: IDK console is on UART3 by default. + * So u-boot mus be build with CONFIG_SERIAL4 and + * CONFIG_CONS_INDEX=4 + */ + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(mmc0_no_cd_pin_mux); } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); -- cgit v1.2.3 From a1b231cef634d8aaa002bcb848332785803127c8 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 30 Oct 2012 07:50:47 +0000 Subject: fs: handle CONFIG_NEEDS_MANUAL_RELOC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without this, fstypes[].probe points at the wrong place, so calling the function results in undefined behaviour. Signed-off-by: Stephen Warren Tested-by: Andreas Bießmann --- fs/fs.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/fs/fs.c b/fs/fs.c index 23ffa25f0d..e148a07406 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -21,6 +21,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static block_dev_desc_t *fs_dev_desc; static disk_partition_t fs_partition; static int fs_type = FS_TYPE_ANY; @@ -141,7 +143,7 @@ static inline void fs_close_ext(void) #define fs_read_ext fs_read_unsupported #endif -static const struct { +static struct { int fstype; int (*probe)(void); } fstypes[] = { @@ -158,6 +160,15 @@ static const struct { int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) { int part, i; +#ifdef CONFIG_NEEDS_MANUAL_RELOC + static int relocated; + + if (!relocated) { + for (i = 0; i < ARRAY_SIZE(fstypes); i++) + fstypes[i].probe += gd->reloc_off; + relocated = 1; + } +#endif part = get_device_and_partition(ifname, dev_part_str, &fs_dev_desc, &fs_partition, 1); -- cgit v1.2.3 From 085b9c3a1dfa3f29cf2bb34f434be318ba313f57 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 29 Oct 2012 14:53:18 +0000 Subject: cmd_fdt.c: Use %p when printing pointers When putting pointers into a format string use %p to ensure that they are printed correctly regardless of bitsize. This fixes warnings on sandbox on 64bit systems. Cc: Joe Hershberger Cc: Gerald Van Baren Signed-off-by: Tom Rini Acked-by: Joe Hershberger --- common/cmd_fdt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index a5e2cfcbfa..f9acfc19ce 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -375,7 +375,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) /* Get address */ char buf[11]; - sprintf(buf, "0x%08X", (uint32_t)nodep); + sprintf(buf, "0x%p", nodep); setenv(var, buf); } else if (subcmd[0] == 's') { /* Get size */ @@ -816,7 +816,7 @@ static void print_data(const void *data, int len) if ((len %4) == 0) { if (len > CONFIG_CMD_FDT_MAX_DUMP) - printf("* 0x%08x [0x%08x]", (unsigned int)data, len); + printf("* 0x%p [0x%08x]", data, len); else { const u32 *p; @@ -828,7 +828,7 @@ static void print_data(const void *data, int len) } } else { /* anything else... hexdump */ if (len > CONFIG_CMD_FDT_MAX_DUMP) - printf("* 0x%08x [0x%08x]", (unsigned int)data, len); + printf("* 0x%p [0x%08x]", data, len); else { const u8 *s; -- cgit v1.2.3 From d266f669252a5ebd7e9b940743ec7d05cdbd4061 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 30 Oct 2012 09:19:52 +0000 Subject: lib/vsprintf.c: don't special-case pointers to address null The %p format of printf() would print a pointer to address null as "(null)". This makes sense in a real OS where a NULL pointer must never be dereferenced, but this is a bootloader, and there are cases where accessing the data at address null makes perfect sense. Remove the special case in lib/vsprintf.c using "#if 0" with a comment to make clear this was an intentional change and to stop re-adding this code. Signed-off-by: Wolfgang Denk Acked-by: Joe Hershberger --- lib/vsprintf.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/vsprintf.c b/lib/vsprintf.c index d7627632d0..dd13bca5a7 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -495,9 +495,15 @@ static char *ip4_addr_string(char *buf, char *end, u8 *addr, int field_width, static char *pointer(const char *fmt, char *buf, char *end, void *ptr, int field_width, int precision, int flags) { + /* + * Being a boot loader, we explicitly allow pointers to + * (physical) address null. + */ +#if 0 if (!ptr) return string(buf, end, "(null)", field_width, precision, flags); +#endif #ifdef CONFIG_CMD_NET switch (*fmt) { -- cgit v1.2.3 From b4a2e43570f335cf91b8cbeb8f74c49701217c1b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 31 Oct 2012 12:41:49 +0000 Subject: git-mailrc: Change x86 maintainer to Simon Grame is still listed since he has agreed to continue with some review. Also add an alias to shorten things. Signed-off-by: Simon Glass --- doc/git-mailrc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/doc/git-mailrc b/doc/git-mailrc index 7f60ef134a..6600c150dc 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -30,6 +30,7 @@ alias rbohmer Remy Bohmer alias reinhardm Reinhard Meyer alias sbabic Stefano Babic alias scottwood Scott Wood +alias sjg Simon Glass alias smcnutt Scott McNutt alias stroese Stefan Roese alias vapier Mike Frysinger @@ -50,7 +51,7 @@ alias rmobile uboot, iwamatsu alias s3c samsung alias s5pc samsung alias samsung uboot, prom -alias tegra uboot, Simon Glass , Tom Warren , Stephen Warren +alias tegra uboot, sjg, Tom Warren , Stephen Warren alias tegra2 tegra alias ti uboot, Tom Rini @@ -84,7 +85,7 @@ alias ppc4xx uboot, stroese alias ppc7xx uboot, wd alias ppc74xx uboot, wd -alias sandbox Simon Glass +alias sandbox sjg alias sb sandbox alias sparc uboot, Daniel Hellstrom @@ -92,7 +93,7 @@ alias sparc uboot, Daniel Hellstrom alias superh uboot, iwamatsu alias sh superh -alias x86 uboot, gruss +alias x86 uboot, sjg, gruss # Subsystem aliases alias cfi uboot, stroese -- cgit v1.2.3 From 7e27f89fdfbe4acbaea2821073f90fa7e82b94ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 24 Oct 2012 07:28:16 +0000 Subject: README: Document CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG This option is intended to be set by boards which will set the board_name and board_rev environment variables. These are to be used when the U-Boot binary can support more than one board type at run-time and the user needs an easy way (for example for scripting to determine what device tree to load) to determine what board they are on. Signed-off-by: Tom Rini --- README | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README b/README index 22fd6b761e..06c1b15e98 100644 --- a/README +++ b/README @@ -2311,6 +2311,12 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_VENDOR - CONFIG_SYS_SOC + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + + Define this in order to add variables describing certain + run-time determined information about the hardware to the + environment. These will be named board_name, board_rev. + - DataFlash Support: CONFIG_HAS_DATAFLASH -- cgit v1.2.3 From 418b7f3aff3bf4c508b2a57ffc6dc7ca10f811aa Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 31 Oct 2012 11:17:28 +0000 Subject: Add board_name to CONFIG_ENV_VARS_UBOOT_CONFIG CONFIG_ENV_VARS_UBOOT_CONFIG creates environment variables indicating which configuration U-Boot was built for. Some U-Boot binaries run on multiple boards, and hence this information may not uniquley describe the HW that U-Boot is actually running on. Another patch introduces environment variable board_name to represent that. In order to avoid scripts having to check $board_name, use it if set, and then fall back to using $board, make CONFIG_ENV_VARS_UBOOT_CONFIG also set a default value for board_name, so that variable is always available. Signed-off-by: Stephen Warren Acked-by: Joe Hershberger --- include/env_default.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/env_default.h b/include/env_default.h index 375e5ca15c..a1db73a2c5 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -118,6 +118,7 @@ const uchar default_environment[] = { "arch=" CONFIG_SYS_ARCH "\0" "cpu=" CONFIG_SYS_CPU "\0" "board=" CONFIG_SYS_BOARD "\0" + "board_name=" CONFIG_SYS_BOARD "\0" #ifdef CONFIG_SYS_VENDOR "vendor=" CONFIG_SYS_VENDOR "\0" #endif -- cgit v1.2.3 From 044fc14bcbcd2a344a2e63c083852fb4af82b96d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 24 Oct 2012 07:28:17 +0000 Subject: am335x_evm: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support We add CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT to set the variables and then fdtfile and findfdt to make us of this. It is now possible to do 'run findfdt' to have fdtfile be set to the value of the dtb file to load for the board we are running on. Signed-off-by: Tom Rini --- board/ti/am335x/board.c | 20 ++++++++++++++++++++ include/configs/am335x_evm.h | 11 +++++++++++ 2 files changed, 31 insertions(+) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 5d279ecdbc..1f0b1a72d1 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -299,6 +299,26 @@ int board_init(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + char safe_string[HDR_NAME_LEN + 1]; + + /* Now set variables based on the header. */ + strncpy(safe_string, (char *)header.name, sizeof(header.name)); + safe_string[sizeof(header.name)] = 0; + setenv("board_name", safe_string); + + strncpy(safe_string, (char *)header.version, sizeof(header.version)); + safe_string[sizeof(header.version)] = 0; + setenv("board_rev", safe_string); +#endif + + return 0; +} +#endif + #ifdef CONFIG_DRIVER_TI_CPSW static void cpsw_control(int enabled) { diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 58d62d0c7d..6e9aada53a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -29,6 +29,7 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_NO_FLASH #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM @@ -46,11 +47,14 @@ /* set to negative value for no autoboot */ #define CONFIG_BOOTDELAY 1 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ "rdaddr=0x81000000\0" \ "bootfile=/boot/uImage\0" \ + "fdtfile=\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ "mmcdev=0\0" \ @@ -79,6 +83,13 @@ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ + "findfdt="\ + "if test $board_name = A335BONE; then " \ + "setenv fdtfile am335x-bone.dtb; fi; " \ + "if test $board_name = A33515BB; then " \ + "setenv fdtfile am335x-evm.dtb; fi; " \ + "if test $board_name = A335X_SK; then " \ + "setenv fdtfile am335x-evmsk.dtb; fi\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ -- cgit v1.2.3 From af8d1d3f71d27aafadab43e85076a9d0389d3d1b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 26 Oct 2012 04:24:00 +0000 Subject: ZFS: Fix compile warning in cmd_zfs.c (GCC 4.6.4 from ELDK 5.2.1) This patch fixes the following compile warnings: cmd_zfs.c:177:1: warning: initialization from incompatible pointer type [enabled by default] cmd_zfs.c:177:1: warning: (near initialization for '_u_boot_list_cmd_zfsls.cmd') [enabled by default] cmd_zfs.c:182:1: warning: initialization from incompatible pointer type [enabled by default] cmd_zfs.c:182:1: warning: (near initialization for '_u_boot_list_cmd_zfsload.cmd') [enabled by default] Signed-off-by: Stefan Roese Cc: Jorgen Lundman --- common/cmd_zfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_zfs.c b/common/cmd_zfs.c index d580f7bca0..1df0c4d72a 100644 --- a/common/cmd_zfs.c +++ b/common/cmd_zfs.c @@ -46,7 +46,7 @@ #define DOS_FS_TYPE_OFFSET 0x36 #define DOS_FS32_TYPE_OFFSET 0x52 -static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_zfs_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *filename = NULL; int dev; @@ -146,7 +146,7 @@ int zfs_print(const char *entry, const struct zfs_dirhook_info *data) -static int do_zfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int do_zfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { const char *filename = "/"; int part; -- cgit v1.2.3 From e08ebf468784668155fd889b9eaf7868f283fe87 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 26 Oct 2012 04:24:01 +0000 Subject: ZFS: Fix compile warning in fs/zfs/zfs.c (GCC 4.6.4 from ELDK 5.2.1) This patch fixes the following compile warning: zfs.c:2006:1: warning: 'zfs_label' defined but not used [-Wunused-function] zfs.c:2029:1: warning: 'zfs_uuid' defined but not used [-Wunused-function] Signed-off-by: Stefan Roese Cc: Jorgen Lundman --- fs/zfs/zfs.c | 51 --------------------------------------------------- 1 file changed, 51 deletions(-) diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index 360f723c84..2db45b1928 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -2002,49 +2002,6 @@ zfs_fetch_nvlist(device_t dev, char **nvlist) return err; } -static int -zfs_label(device_t device, char **label) -{ - char *nvlist; - int err; - struct zfs_data *data; - - data = zfs_mount(device); - if (!data) - return ZFS_ERR_BAD_FS; - - err = int_zfs_fetch_nvlist(data, &nvlist); - if (err) { - zfs_unmount(data); - return err; - } - - *label = zfs_nvlist_lookup_string(nvlist, ZPOOL_CONFIG_POOL_NAME); - free(nvlist); - zfs_unmount(data); - return ZFS_ERR_NONE; -} - -static int -zfs_uuid(device_t device, char **uuid) -{ - struct zfs_data *data; - - data = zfs_mount(device); - if (!data) - return ZFS_ERR_BAD_FS; - - *uuid = malloc(17); /* %016llx + nil */ - if (!*uuid) - return ZFS_ERR_OUT_OF_MEMORY; - - /* *uuid = xasprintf ("%016llx", (long long unsigned) data->pool_guid);*/ - snprintf(*uuid, 17, "%016llx", (long long unsigned) data->pool_guid); - zfs_unmount(data); - - return ZFS_ERR_NONE; -} - /* * zfs_open() locates a file in the rootpool by following the * MOS and places the dnode of the file in the memory address DNODE. @@ -2325,14 +2282,6 @@ zfs_ls(device_t device, const char *path, struct zfs_data *data; int err; int isfs; -#if 0 - char *label = NULL; - - zfs_label(device, &label); - if (label) - printf("ZPOOL label '%s'\n", - label); -#endif data = zfs_mount(device); if (!data) -- cgit v1.2.3 From 284231e49a2b4ee00647db592c54c3efd1ac7d35 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Mon, 29 Oct 2012 05:23:44 +0000 Subject: ahci: Support splitting of read transactions into multiple chunks With an Intel AHCI controller, the driver does not operate properly if the requested amount of blocks to read exceeds 255. It is probably possible to specify 0 as the block count and the driver will read 256 blocks, but it was decided to limit the number of blocks read at once to 128 (it should be a power of 2 for the optimal performance of solid state drives). Signed-off-by: Vadim Bendebury Signed-off-by: Simon Glass --- drivers/block/ahci.c | 98 ++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 69 insertions(+), 29 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 7b2ec505e1..d94da1f05a 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -42,6 +42,14 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) +/* + * Some controllers limit number of blocks they can read at once. Contemporary + * SSD devices work much faster if the read size is aligned to a power of 2. + * Let's set default to 128 and allowing to be overwritten if needed. + */ +#ifndef MAX_SATA_BLOCKS_READ +#define MAX_SATA_BLOCKS_READ 0x80 +#endif static inline u32 ahci_port_base(u32 base, u32 port) { @@ -88,6 +96,8 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) int i, j; volatile u8 *port_mmio; + debug("ahci_host_init: start\n"); + cap_save = readl(mmio + HOST_CAP); cap_save &= ((1 << 28) | (1 << 17)); cap_save |= (1 << 27); @@ -129,6 +139,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) debug("cap 0x%x port_map 0x%x n_ports %d\n", probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); + if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) + probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; + for (i = 0; i < probe_ent->n_ports; i++) { probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); port_mmio = (u8 *) probe_ent->port[i].port_mmio; @@ -277,8 +290,8 @@ static int ahci_init_one(pci_dev_t pdev) probe_ent->pio_mask = 0x1f; probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR, - PCI_REGION_MEM); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); + debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); /* Take from kernel: * JMicron-specific fixup: @@ -398,7 +411,7 @@ static int ahci_port_start(u8 port) * 32 bytes each in size */ pp->cmd_slot = (struct ahci_cmd_hdr *)mem; - debug("cmd_slot = %p\n", pp->cmd_slot); + debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); mem += (AHCI_CMD_SLOT_SZ + 224); /* @@ -561,42 +574,69 @@ static int ata_scsiop_inquiry(ccb *pccb) */ static int ata_scsiop_read10(ccb * pccb) { - u32 len = 0; + u32 lba = 0; + u16 blocks = 0; u8 fis[20]; + u8 *user_buffer = pccb->pdata; + u32 user_buffer_size = pccb->datalen; - len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]); + /* Retrieve the base LBA number from the ccb structure. */ + memcpy(&lba, pccb->cmd + 2, sizeof(lba)); + lba = be32_to_cpu(lba); - /* For 10-byte and 16-byte SCSI R/W commands, transfer + /* + * And the number of blocks. + * + * For 10-byte and 16-byte SCSI R/W commands, transfer * length 0 means transfer 0 block of data. * However, for ATA R/W commands, sector count 0 means * 256 or 65536 sectors, not 0 sectors as in SCSI. * * WARNING: one or two older ATA drives treat 0 as 0... */ - if (!len) - return 0; + blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); + + debug("scsi_ahci: read %d blocks starting from lba 0x%x\n", + (unsigned)lba, blocks); + + /* Preset the FIS */ memset(fis, 0, 20); + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ - /* Construct the FIS */ - fis[0] = 0x27; /* Host to device FIS. */ - fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ - - /* LBA address, only support LBA28 in this driver */ - fis[4] = pccb->cmd[5]; - fis[5] = pccb->cmd[4]; - fis[6] = pccb->cmd[3]; - fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0; - - /* Sector Count */ - fis[12] = pccb->cmd[8]; - fis[13] = pccb->cmd[7]; - - /* Read from ahci */ - if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20, - pccb->pdata, pccb->datalen)) { - debug("scsi_ahci: SCSI READ10 command failure.\n"); - return -EIO; + while (blocks) { + u16 now_blocks; /* number of blocks per iteration */ + u32 transfer_size; /* number of bytes per iteration */ + + now_blocks = min(MAX_SATA_BLOCKS_READ, blocks); + + transfer_size = ATA_BLOCKSIZE * now_blocks; + if (transfer_size > user_buffer_size) { + printf("scsi_ahci: Error: buffer too small.\n"); + return -EIO; + } + + /* LBA address, only support LBA28 in this driver */ + fis[4] = (lba >> 0) & 0xff; + fis[5] = (lba >> 8) & 0xff; + fis[6] = (lba >> 16) & 0xff; + fis[7] = ((lba >> 24) & 0xf) | 0xe0; + + /* Block (sector) count */ + fis[12] = (now_blocks >> 0) & 0xff; + fis[13] = (now_blocks >> 8) & 0xff; + + /* Read from ahci */ + if (get_ahci_device_data(pccb->target, (u8 *) &fis, sizeof(fis), + user_buffer, user_buffer_size)) { + debug("scsi_ahci: SCSI READ10 command failure.\n"); + return -EIO; + } + user_buffer += transfer_size; + user_buffer_size -= transfer_size; + blocks -= now_blocks; + lba += now_blocks; } return 0; @@ -617,7 +657,7 @@ static int ata_scsiop_read_capacity10(ccb *pccb) return -EPERM; } - cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); + cap = be32_to_cpu(ataid[pccb->target]->lba_capacity); memcpy(pccb->pdata, &cap, sizeof(cap)); pccb->pdata[4] = pccb->pdata[5] = 0; -- cgit v1.2.3 From 4ae5eb7c5bb8b393ffeec456329a331a786bba47 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Mon, 29 Oct 2012 05:23:45 +0000 Subject: scsi: Provide support for a list of AHCI controllers. Many AHCI controllers are identical, the main (and often the only) difference being the PCI Vendor ID/Device ID combination reported by the device. This change allows the config file to define a list of PCI vendor ID/device ID pairs. The driver would scan the list and initialize the first device it finds. No actual multiple device list is introduced yet, this change just add the framework. Signed-off-by: Vadim Bendebury Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- common/cmd_scsi.c | 40 +++++++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 22d0119814..50eb239aaf 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -34,6 +34,9 @@ #include #include +#ifdef CONFIG_SCSI_DEV_LIST +#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST +#else #ifdef CONFIG_SCSI_SYM53C8XX #define SCSI_VEND_ID 0x1000 #ifndef CONFIG_SCSI_DEV_ID @@ -49,8 +52,12 @@ #elif !defined(CONFIG_SCSI_AHCI_PLAT) #error no scsi device defined #endif +#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#endif - +#ifdef CONFIG_PCI +const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST }; +#endif static ccb tempccb; /* temporary scsi command buffer */ static unsigned char tempbuff[512]; /* temporary data buffer */ @@ -178,15 +185,38 @@ removable: void scsi_init(void) { int busdevfunc; + int i; + /* + * Find a device from the list, this driver will support a single + * controller. + */ + for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) { + /* get PCI Device ID */ + busdevfunc = pci_find_device(scsi_device_list[i].vendor, + scsi_device_list[i].device, + 0); + if (busdevfunc != -1) + break; + } - busdevfunc=pci_find_device(SCSI_VEND_ID,SCSI_DEV_ID,0); /* get PCI Device ID */ - if(busdevfunc==-1) { - printf("Error SCSI Controller (%04X,%04X) not found\n",SCSI_VEND_ID,SCSI_DEV_ID); + if (busdevfunc == -1) { + printf("Error: SCSI Controller(s) "); + for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) { + printf("%04X:%04X ", + scsi_device_list[i].vendor, + scsi_device_list[i].device); + } + printf("not found\n"); return; } #ifdef DEBUG else { - printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",SCSI_VEND_ID,SCSI_DEV_ID,(busdevfunc>>16)&0xFF,(busdevfunc>>11)&0x1F,(busdevfunc>>8)&0x7); + printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n", + scsi_device_list[i].vendor, + scsi_device_list[i].device, + (busdevfunc >> 16) & 0xFF, + (busdevfunc >> 11) & 0x1F, + (busdevfunc >> 8) & 0x7); } #endif scsi_low_level_init(busdevfunc); -- cgit v1.2.3 From 758c9e69545b2f233ba98750aa3b4f57211b5c5a Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Mon, 29 Oct 2012 05:23:46 +0000 Subject: scsi: Add scsi_write to SCSI driver Implement write functionality in the scsi layer. A ''scsi write' command is also added to console for testing. Signed-off-by: Hung-Te Lin Signed-off-by: Simon Glass --- common/cmd_scsi.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 108 insertions(+), 7 deletions(-) diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 50eb239aaf..31ea78845c 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -75,11 +75,15 @@ void scsi_setup_test_unit_ready(ccb * pccb); void scsi_setup_read_capacity(ccb * pccb); void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks); void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks); +static void scsi_setup_write_ext(ccb *pccb, unsigned long start, + unsigned short blocks); void scsi_setup_inquiry(ccb * pccb); void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); -ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer); +static ulong scsi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer); +static ulong scsi_write(int device, ulong blknr, + lbaint_t blkcnt, const void *buffer); /********************************************************************************* @@ -109,6 +113,7 @@ void scsi_scan(int mode) scsi_dev_desc[i].dev=i; scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN; scsi_dev_desc[i].block_read=scsi_read; + scsi_dev_desc[i].block_write = scsi_write; } scsi_max_devs=0; for(i=0;ipdata=(unsigned char *)buf_addr; if(blks>SCSI_MAX_READ_BLK) { @@ -376,7 +397,9 @@ ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer) start+=blks; blks=0; } - debug ("scsi_read_ext: startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr); + debug("scsi_read_ext: startblk " LBAF + ", blccnt %x buffer %lx\n", + start, smallblks, buf_addr); if(scsi_exec(pccb)!=TRUE) { scsi_print_error(pccb); blkcnt-=blks; @@ -384,10 +407,65 @@ ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer) } buf_addr+=pccb->datalen; } while(blks!=0); - debug ("scsi_read_ext: end startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr); + debug("scsi_read_ext: end startblk " LBAF + ", blccnt %x buffer %lx\n", start, smallblks, buf_addr); return(blkcnt); } +/******************************************************************************* + * scsi_write + */ + +/* Almost the maximum amount of the scsi_ext command.. */ +#define SCSI_MAX_WRITE_BLK 0xFFFF + +static ulong scsi_write(int device, ulong blknr, + lbaint_t blkcnt, const void *buffer) +{ + lbaint_t start, blks; + uintptr_t buf_addr; + unsigned short smallblks; + ccb* pccb = (ccb *)&tempccb; + device &= 0xff; + /* Setup device + */ + pccb->target = scsi_dev_desc[device].target; + pccb->lun = scsi_dev_desc[device].lun; + buf_addr = (unsigned long)buffer; + start = blknr; + blks = blkcnt; + debug("\n%s: dev %d startblk " LBAF ", blccnt " LBAF " buffer %lx\n", + __func__, device, start, blks, (unsigned long)buffer); + do { + pccb->pdata = (unsigned char *)buf_addr; + if (blks > SCSI_MAX_WRITE_BLK) { + pccb->datalen = (scsi_dev_desc[device].blksz * + SCSI_MAX_WRITE_BLK); + smallblks = SCSI_MAX_WRITE_BLK; + scsi_setup_write_ext(pccb, start, smallblks); + start += SCSI_MAX_WRITE_BLK; + blks -= SCSI_MAX_WRITE_BLK; + } else { + pccb->datalen = scsi_dev_desc[device].blksz * blks; + smallblks = (unsigned short)blks; + scsi_setup_write_ext(pccb, start, smallblks); + start += blks; + blks = 0; + } + debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n", + __func__, start, smallblks, buf_addr); + if (scsi_exec(pccb) != TRUE) { + scsi_print_error(pccb); + blkcnt -= blks; + break; + } + buf_addr += pccb->datalen; + } while (blks != 0); + debug("%s: end startblk " LBAF ", blccnt %x buffer %lx\n", + __func__, start, smallblks, buf_addr); + return blkcnt; +} + /* copy src to dest, skipping leading and trailing blanks * and null terminate the string */ @@ -481,6 +559,27 @@ void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks) pccb->cmd[7],pccb->cmd[8]); } +void scsi_setup_write_ext(ccb *pccb, unsigned long start, unsigned short blocks) +{ + pccb->cmd[0] = SCSI_WRITE10; + pccb->cmd[1] = pccb->lun << 5; + pccb->cmd[2] = ((unsigned char) (start>>24)) & 0xff; + pccb->cmd[3] = ((unsigned char) (start>>16)) & 0xff; + pccb->cmd[4] = ((unsigned char) (start>>8)) & 0xff; + pccb->cmd[5] = ((unsigned char) (start)) & 0xff; + pccb->cmd[6] = 0; + pccb->cmd[7] = ((unsigned char) (blocks>>8)) & 0xff; + pccb->cmd[8] = (unsigned char)blocks & 0xff; + pccb->cmd[9] = 0; + pccb->cmdlen = 10; + pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ + debug("%s: cmd: %02X %02X startblk %02X%02X%02X%02X blccnt %02X%02X\n", + __func__, + pccb->cmd[0], pccb->cmd[1], + pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5], + pccb->cmd[7], pccb->cmd[8]); +} + void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks) { pccb->cmd[0]=SCSI_READ6; @@ -522,7 +621,9 @@ U_BOOT_CMD( "scsi device [dev] - show or set current device\n" "scsi part [dev] - print partition table of one or all SCSI devices\n" "scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n" - " to memory address `addr'" + " to memory address `addr'\n" + "scsi write addr blk# cnt - write `cnt' blocks starting at block\n" + " `blk#' from memory address `addr'" ); U_BOOT_CMD( -- cgit v1.2.3 From c4fa493d3a822757af8fbcdc516e12bb7f72d071 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 Oct 2012 05:23:47 +0000 Subject: Support setenv_ulong() and setenv_addr() for powerpc This includes were outside an #ifdef CONFIG_PPC, but there is not reason to exclude powerpc from using them. Move the declaration outside the #ifdef. Signed-off-by: Simon Glass --- include/common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/common.h b/include/common.h index b23e90b025..12b3e039a0 100644 --- a/include/common.h +++ b/include/common.h @@ -345,9 +345,9 @@ int saveenv (void); int inline setenv (const char *, const char *); #else int setenv (const char *, const char *); +#endif /* CONFIG_PPC */ int setenv_ulong(const char *varname, ulong value); int setenv_addr(const char *varname, const void *addr); -#endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include # include -- cgit v1.2.3 From 447c031ba4b6b306bb3f77690af06f5d2ad0691b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 29 Oct 2012 05:23:48 +0000 Subject: scsi: Add function and env var to report number of scsi drives Add a new function to find out the number of available SCSI disks. Also set the 'scsidevs' environment variable after each scan. Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- README | 3 +++ common/cmd_scsi.c | 8 ++++++++ include/scsi.h | 2 ++ 3 files changed, 13 insertions(+) diff --git a/README b/README index 06c1b15e98..8141068e4f 100644 --- a/README +++ b/README @@ -1041,6 +1041,9 @@ The following options need to be configured: devices. CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) + The environment variable 'scsidevs' is set to the number of + SCSI devices found during the last scan. + - NETWORK Support (PCI): CONFIG_E1000 Support for Intel 8254x/8257x gigabit chips. diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 31ea78845c..9bd8ec9ecb 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -184,6 +184,14 @@ removable: scsi_curr_dev=0; else scsi_curr_dev = -1; + + printf("Found %d device(s).\n", scsi_max_devs); + setenv_ulong("scsidevs", scsi_max_devs); +} + +int scsi_get_disk_count(void) +{ + return scsi_max_devs; } #ifdef CONFIG_PCI diff --git a/include/scsi.h b/include/scsi.h index 89ae45f8e8..9681d198df 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -189,6 +189,8 @@ void scsi_low_level_init(int busdevfunc); void scsi_init(void); void scsi_scan(int mode); +/** @return the number of scsi disks */ +int scsi_get_disk_count(void); #define SCSI_IDENTIFY 0xC0 /* not used */ -- cgit v1.2.3 From 9a65b8754c57e8640e208b9743272b9c74527e0e Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 29 Oct 2012 05:23:49 +0000 Subject: ahci: Optimise AHCI controller reset and start-up The existing code waits a whole second for the AHCI controller to reset. Instead, let's poll the status register to see if the reset has succeeded and return earlier if possible. This brings down the time for AHCI probing from 1s to 20ms. Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- drivers/block/ahci.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index d94da1f05a..ad397dcb6a 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -110,13 +110,15 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) /* reset must complete within 1 second, or * the hardware should be considered fried. */ - ssleep(1); - - tmp = readl(mmio + HOST_CTL); - if (tmp & HOST_RESET) { - debug("controller reset failed (0x%x)\n", tmp); - return -1; - } + i = 1000; + do { + udelay(1000); + tmp = readl(mmio + HOST_CTL); + if (!i--) { + debug("controller reset failed (0x%x)\n", tmp); + return -1; + } + } while (tmp & HOST_RESET); writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); writel(cap_save, mmio + HOST_CAP); @@ -164,13 +166,17 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); j = 0; - while (j < 100) { - msleep(10); + while (j < 1000) { tmp = readl(port_mmio + PORT_SCR_STAT); if ((tmp & 0xf) == 0x3) break; + udelay(1000); j++; } + if (j == 1000) + debug("timeout.\n"); + else + debug("ok.\n"); tmp = readl(port_mmio + PORT_SCR_ERR); debug("PORT_SCR_ERR 0x%x\n", tmp); -- cgit v1.2.3 From 7ba7917c91b875d1cd54dadfcca07d839b75e2a5 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 29 Oct 2012 05:23:50 +0000 Subject: ahci: Improve AHCI debugging - remove unused ssleep macro - add some useful debugging information Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- drivers/block/ahci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index ad397dcb6a..af31c97533 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -68,7 +68,6 @@ static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, #define msleep(a) udelay(a * 1000) -#define ssleep(a) msleep(a * 1000) static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, @@ -153,6 +152,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) tmp = readl(port_mmio + PORT_CMD); if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | PORT_CMD_FIS_RX | PORT_CMD_START)) { + debug("Port %d is active. Deactivating.\n", i); tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | PORT_CMD_FIS_RX | PORT_CMD_START); writel_with_flush(tmp, port_mmio + PORT_CMD); @@ -163,6 +163,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) msleep(500); } + debug("Spinning up port %d... ", i); writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); j = 0; -- cgit v1.2.3 From 4e422bce8a51749ff3c67eec2c8caa6377cc35ee Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 29 Oct 2012 05:23:51 +0000 Subject: ahci: cosmetics and cleanup - print the correct speed - print all the AHCI capability flags (information taken from Linux kernel driver) - clean up some comments For example, this might show the following string: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode Signed-off-by: Stefan Reinauer Commit-Ready: Stefan Reinauer Signed-off-by: Simon Glass Tested-by: Stefan Reinauer --- drivers/block/ahci.c | 25 ++++++++++++++++++------- include/ahci.h | 1 + 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index af31c97533..0a7ad81650 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -194,7 +194,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) /* set irq mask (enables interrupts) */ writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); - /*register linkup ports */ + /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); debug("Port %d status: 0x%x\n", i, tmp); if ((tmp & 0xf) == 0x03) @@ -222,12 +222,13 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) u16 cc; #endif volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; - u32 vers, cap, impl, speed; + u32 vers, cap, cap2, impl, speed; const char *speed_s; const char *scc_s; vers = readl(mmio + HOST_VERSION); cap = probe_ent->cap; + cap2 = readl(mmio + HOST_CAP2); impl = probe_ent->port_map; speed = (cap >> 20) & 0xf; @@ -235,6 +236,8 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) speed_s = "1.5"; else if (speed == 2) speed_s = "3"; + else if (speed == 3) + speed_s = "6"; else speed_s = "?"; @@ -260,8 +263,9 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); printf("flags: " - "%s%s%s%s%s%s" - "%s%s%s%s%s%s%s\n", + "%s%s%s%s%s%s%s" + "%s%s%s%s%s%s%s" + "%s%s%s%s%s%s\n", cap & (1 << 31) ? "64bit " : "", cap & (1 << 30) ? "ncq " : "", cap & (1 << 28) ? "ilck " : "", @@ -272,9 +276,16 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) cap & (1 << 19) ? "nz " : "", cap & (1 << 18) ? "only " : "", cap & (1 << 17) ? "pmp " : "", + cap & (1 << 16) ? "fbss " : "", cap & (1 << 15) ? "pio " : "", cap & (1 << 14) ? "slum " : "", - cap & (1 << 13) ? "part " : ""); + cap & (1 << 13) ? "part " : "", + cap & (1 << 7) ? "ccc " : "", + cap & (1 << 6) ? "ems " : "", + cap & (1 << 5) ? "sxs " : "", + cap2 & (1 << 2) ? "apst " : "", + cap2 & (1 << 1) ? "nvmp " : "", + cap2 & (1 << 0) ? "boh " : ""); } #ifndef CONFIG_SCSI_AHCI_PLAT @@ -369,7 +380,7 @@ static void ahci_set_feature(u8 port) u32 cmd_fis_len = 5; /* five dwords */ u8 fis[20]; - /*set feature */ + /* set feature */ memset(fis, 0, 20); fis[0] = 0x27; fis[1] = 1 << 7; @@ -383,7 +394,7 @@ static void ahci_set_feature(u8 port) readl(port_mmio + PORT_CMD_ISSUE); if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { - printf("set feature error!\n"); + printf("set feature error on port %d!\n", port); } } diff --git a/include/ahci.h b/include/ahci.h index c4fb9e79a5..babbdc656f 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -51,6 +51,7 @@ #define HOST_IRQ_STAT 0x08 /* interrupt status */ #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ +#define HOST_CAP2 0x24 /* host capabilities, extended */ /* HOST_CTL bits */ #define HOST_RESET (1 << 0) /* reset controller; self-clear */ -- cgit v1.2.3 From e81058c05b762e6da012a7a3c22ee25c6c0bf71e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Oct 2012 05:23:52 +0000 Subject: ahci: Make sending the SETFEATURES_XFER command optional This command doesn't really do anything when talking to a SATA device, and sending it confuses some of them. This change makes sending the command optional, and defaults to not. The situations where it should be sent are not the common case. With the standard SSD in the machine, here are some times with the option turned off: 1. 8277 2. 8273 3. 8050 And turned on: 1. 8303 2. 8155 3. 8276 Sending that command seems to have no meaningful effect on performance. This fixes problems with an SSD marked Toshiba NV6424, Taiwan 11159AE P and TC58NVG5D2FTA10. Signed-off-by: Gabe Black Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- drivers/block/ahci.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 0a7ad81650..22363211b3 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -373,6 +373,7 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) } +#ifdef CONFIG_AHCI_SETFEATURES_XFER static void ahci_set_feature(u8 port) { struct ahci_ioports *pp = &(probe_ent->port[port]); @@ -397,6 +398,7 @@ static void ahci_set_feature(u8 port) printf("set feature error on port %d!\n", port); } } +#endif static int ahci_port_start(u8 port) @@ -743,7 +745,9 @@ void scsi_low_level_init(int busdevfunc) printf("Can not start port %d\n", i); continue; } +#ifdef CONFIG_AHCI_SETFEATURES_XFER ahci_set_feature((u8) i); +#endif } } } @@ -784,7 +788,9 @@ int ahci_init(u32 base) printf("Can not start port %d\n", i); continue; } +#ifdef CONFIG_AHCI_SETFEATURES_XFER ahci_set_feature((u8) i); +#endif } } err_out: -- cgit v1.2.3 From b7a21b70d0d3f94d7ab3ed84fbf68d2e2b7488bf Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Mon, 29 Oct 2012 05:23:53 +0000 Subject: ahci: support scsi writing in AHCI driver The "scsi write" command requires support from underlying driver. This CL enables SCSI_WRITE10 in AHCI driver. Tested in U-Boot console, try to i/o with sector #64: scsi read 1000 40 1 md.b 1000 200 # check if things are not 0xcc mw.b 1000 cc 200 # try to fill with 0xcc scsi write 1000 40 1 mw.b 1000 0 200 # fill with zero md.b 1000 200 # should be all 0 scsi read 1000 40 1 md.b 1000 200 # should be all 0xcc Signed-off-by: Hung-Te Lin Signed-off-by: Simon Glass --- drivers/block/ahci.c | 54 +++++++++++++++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 22363211b3..5092352758 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -43,12 +43,13 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) /* - * Some controllers limit number of blocks they can read at once. Contemporary - * SSD devices work much faster if the read size is aligned to a power of 2. - * Let's set default to 128 and allowing to be overwritten if needed. + * Some controllers limit number of blocks they can read/write at once. + * Contemporary SSD devices work much faster if the read/write size is aligned + * to a power of 2. Let's set default to 128 and allowing to be overwritten if + * needed. */ -#ifndef MAX_SATA_BLOCKS_READ -#define MAX_SATA_BLOCKS_READ 0x80 +#ifndef MAX_SATA_BLOCKS_READ_WRITE +#define MAX_SATA_BLOCKS_READ_WRITE 0x80 #endif static inline u32 ahci_port_base(u32 base, u32 port) @@ -464,8 +465,8 @@ static int ahci_port_start(u8 port) } -static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, - int buf_len) +static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, + int buf_len, u8 is_write) { struct ahci_ioports *pp = &(probe_ent->port[port]); @@ -474,7 +475,7 @@ static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, u32 port_status; int sg_count; - debug("Enter get_ahci_device_data: for port %d\n", port); + debug("Enter %s: for port %d\n", __func__, port); if (port > probe_ent->n_ports) { printf("Invaild port number %d\n", port); @@ -490,7 +491,7 @@ static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); sg_count = ahci_fill_sg(port, buf, buf_len); - opts = (fis_len >> 2) | (sg_count << 16); + opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); ahci_fill_cmd_slot(pp, opts); writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); @@ -499,8 +500,7 @@ static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf, printf("timeout exit!\n"); return -1; } - debug("get_ahci_device_data: %d byte transferred.\n", - pp->cmd_slot->status); + debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); return 0; } @@ -570,8 +570,8 @@ static int ata_scsiop_inquiry(ccb *pccb) if (!(tmpid = malloc(sizeof(hd_driveid_t)))) return -ENOMEM; - if (get_ahci_device_data(port, (u8 *) & fis, 20, - tmpid, sizeof(hd_driveid_t))) { + if (ahci_device_data_io(port, (u8 *) &fis, 20, tmpid, + sizeof(hd_driveid_t), 0)) { debug("scsi_ahci: SCSI inquiry command failure.\n"); return -EIO; } @@ -590,9 +590,9 @@ static int ata_scsiop_inquiry(ccb *pccb) /* - * SCSI READ10 command operation. + * SCSI READ10/WRITE10 command operation. */ -static int ata_scsiop_read10(ccb * pccb) +static int ata_scsiop_read_write(ccb *pccb, u8 is_write) { u32 lba = 0; u16 blocks = 0; @@ -616,20 +616,21 @@ static int ata_scsiop_read10(ccb * pccb) */ blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); - debug("scsi_ahci: read %d blocks starting from lba 0x%x\n", - (unsigned)lba, blocks); + debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", + is_write ? "write" : "read", (unsigned)lba, blocks); /* Preset the FIS */ memset(fis, 0, 20); fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_RD_DMA; /* Command byte. */ + /* Command byte (read/write). */ + fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA; while (blocks) { u16 now_blocks; /* number of blocks per iteration */ u32 transfer_size; /* number of bytes per iteration */ - now_blocks = min(MAX_SATA_BLOCKS_READ, blocks); + now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); transfer_size = ATA_BLOCKSIZE * now_blocks; if (transfer_size > user_buffer_size) { @@ -647,10 +648,12 @@ static int ata_scsiop_read10(ccb * pccb) fis[12] = (now_blocks >> 0) & 0xff; fis[13] = (now_blocks >> 8) & 0xff; - /* Read from ahci */ - if (get_ahci_device_data(pccb->target, (u8 *) &fis, sizeof(fis), - user_buffer, user_buffer_size)) { - debug("scsi_ahci: SCSI READ10 command failure.\n"); + /* Read/Write from ahci */ + if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), + user_buffer, user_buffer_size, + is_write)) { + debug("scsi_ahci: SCSI %s10 command failure.\n", + is_write ? "WRITE" : "READ"); return -EIO; } user_buffer += transfer_size; @@ -703,7 +706,10 @@ int scsi_exec(ccb *pccb) switch (pccb->cmd[0]) { case SCSI_READ10: - ret = ata_scsiop_read10(pccb); + ret = ata_scsiop_read_write(pccb, 0); + break; + case SCSI_WRITE10: + ret = ata_scsiop_read_write(pccb, 1); break; case SCSI_RD_CAPAC: ret = ata_scsiop_read_capacity10(pccb); -- cgit v1.2.3 From 19d1d41e844ea8525f527fd5301aba9eb3006241 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Oct 2012 05:23:54 +0000 Subject: ahci: Make the AHCI code find the capacity of disks > 128 GB properly In the structure returned by the ATA identify device command, there are two fields which describe the device capacity. One is a 32 bit data type which reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs, the small value is the only value with the correct size. If it supports more, if the number of sectors is small enough to fit into 28 bits, both fields reflect the correct value. If it's too large, the smaller field has 28 bits of 1s, 0xfffffff, and the other field has the correct value. The AHCI driver is implemented by attaching to the generic SCSI code and translating on the fly between SCSI binary data structures and AHCI data structures. It responds to requests to execute specific SCSI commands by executing the equivalent AHCI commands and then crafting a response which matches what a SCSI disk would send. The AHCI driver now considers both fields and chooses the correct one when implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- drivers/block/ahci.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++----- include/scsi.h | 2 ++ 2 files changed, 52 insertions(+), 5 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 5092352758..c16e8bae6f 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -672,6 +672,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) static int ata_scsiop_read_capacity10(ccb *pccb) { u32 cap; + u32 block_size; if (!ataid[pccb->target]) { printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " @@ -680,12 +681,53 @@ static int ata_scsiop_read_capacity10(ccb *pccb) return -EPERM; } - cap = be32_to_cpu(ataid[pccb->target]->lba_capacity); + cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); + if (cap == 0xfffffff) { + unsigned short *cap48 = ataid[pccb->target]->lba48_capacity; + if (cap48[2] || cap48[3]) { + cap = 0xffffffff; + } else { + cap = (le16_to_cpu(cap48[1]) << 16) | + (le16_to_cpu(cap48[0])); + } + } + + cap = cpu_to_be32(cap); memcpy(pccb->pdata, &cap, sizeof(cap)); - pccb->pdata[4] = pccb->pdata[5] = 0; - pccb->pdata[6] = 512 >> 8; - pccb->pdata[7] = 512 & 0xff; + block_size = cpu_to_be32((u32)512); + memcpy(&pccb->pdata[4], &block_size, 4); + + return 0; +} + + +/* + * SCSI READ CAPACITY16 command operation. + */ +static int ata_scsiop_read_capacity16(ccb *pccb) +{ + u64 cap; + u64 block_size; + + if (!ataid[pccb->target]) { + printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " + "\tNo ATA info!\n" + "\tPlease run SCSI commmand INQUIRY firstly!\n"); + return -EPERM; + } + + cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); + if (cap == 0xfffffff) { + memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap)); + cap = le64_to_cpu(cap); + } + + cap = cpu_to_be64(cap); + memcpy(pccb->pdata, &cap, sizeof(cap)); + + block_size = cpu_to_be64((u64)512); + memcpy(&pccb->pdata[8], &block_size, 8); return 0; } @@ -711,9 +753,12 @@ int scsi_exec(ccb *pccb) case SCSI_WRITE10: ret = ata_scsiop_read_write(pccb, 1); break; - case SCSI_RD_CAPAC: + case SCSI_RD_CAPAC10: ret = ata_scsiop_read_capacity10(pccb); break; + case SCSI_RD_CAPAC16: + ret = ata_scsiop_read_capacity16(pccb); + break; case SCSI_TST_U_RDY: ret = ata_scsiop_test_unit_ready(pccb); break; diff --git a/include/scsi.h b/include/scsi.h index 9681d198df..9da764bdcf 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -150,6 +150,8 @@ typedef struct SCSI_cmd_block{ #define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */ #define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */ #define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */ +#define SCSI_RD_CAPAC10 SCSI_RD_CAPAC /* Read Capacity (10) */ +#define SCSI_RD_CAPAC16 0x9e /* Read Capacity (16) */ #define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */ #define SCSI_READ_LONG 0x3E /* Read Long (O) */ #define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */ -- cgit v1.2.3 From c8731115656132b4b449f4e32a867ec48e47c84b Mon Sep 17 00:00:00 2001 From: Taylor Hutt Date: Mon, 29 Oct 2012 05:23:55 +0000 Subject: ahci: Use sizeof(fis) instead of hardcoding '20' This cleanup replaces the hardcoded use of '20', which represents the number of bytes in the FIS, with sizeof(fis). Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- drivers/block/ahci.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index c16e8bae6f..10fae88ecb 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -383,14 +383,14 @@ static void ahci_set_feature(u8 port) u8 fis[20]; /* set feature */ - memset(fis, 0, 20); + memset(fis, 0, sizeof(fis)); fis[0] = 0x27; fis[1] = 1 << 7; fis[2] = ATA_CMD_SETF; fis[3] = SETFEATURES_XFER; fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; - memcpy((unsigned char *)pp->cmd_tbl, fis, 20); + memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); ahci_fill_cmd_slot(pp, cmd_fis_len); writel(1, port_mmio + PORT_CMD_ISSUE); readl(port_mmio + PORT_CMD_ISSUE); @@ -559,7 +559,7 @@ static int ata_scsiop_inquiry(ccb *pccb) if (pccb->datalen <= 35) return 0; - memset(fis, 0, 20); + memset(fis, 0, sizeof(fis)); /* Construct the FIS */ fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ @@ -570,7 +570,7 @@ static int ata_scsiop_inquiry(ccb *pccb) if (!(tmpid = malloc(sizeof(hd_driveid_t)))) return -ENOMEM; - if (ahci_device_data_io(port, (u8 *) &fis, 20, tmpid, + if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid, sizeof(hd_driveid_t), 0)) { debug("scsi_ahci: SCSI inquiry command failure.\n"); return -EIO; @@ -620,7 +620,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) is_write ? "write" : "read", (unsigned)lba, blocks); /* Preset the FIS */ - memset(fis, 0, 20); + memset(fis, 0, sizeof(fis)); fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ /* Command byte (read/write). */ -- cgit v1.2.3 From 5a2b77f47daa5c87ef45a1c71c72cbc16ede77f8 Mon Sep 17 00:00:00 2001 From: Taylor Hutt Date: Mon, 29 Oct 2012 05:23:56 +0000 Subject: ahci: Fix 'Invaild' typo This fixes a spelling error in a message which can be output to the console. Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- drivers/block/ahci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 10fae88ecb..20c5336263 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -478,7 +478,7 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, debug("Enter %s: for port %d\n", __func__, port); if (port > probe_ent->n_ports) { - printf("Invaild port number %d\n", port); + printf("Invalid port number %d\n", port); return -1; } -- cgit v1.2.3 From b4c5bbce49a081f5d05837ba13ee76afeff72d91 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 29 Oct 2012 05:23:57 +0000 Subject: ahci: Support 64-bit LBA option when reading capacity Capacity needs to allow for a 64-bit value. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- common/cmd_scsi.c | 92 +++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 66 insertions(+), 26 deletions(-) diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 9bd8ec9ecb..266bfa6905 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -72,7 +72,6 @@ static block_dev_desc_t scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE]; * forward declerations of some Setup Routines */ void scsi_setup_test_unit_ready(ccb * pccb); -void scsi_setup_read_capacity(ccb * pccb); void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks); void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks); static void scsi_setup_write_ext(ccb *pccb, unsigned long start, @@ -81,6 +80,8 @@ void scsi_setup_inquiry(ccb * pccb); void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); +static int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, + unsigned long *blksz); static ulong scsi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer); static ulong scsi_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer); @@ -93,7 +94,8 @@ static ulong scsi_write(int device, ulong blknr, void scsi_scan(int mode) { unsigned char i,perq,modi,lun; - unsigned long capacity,blksz; + lbaint_t capacity; + unsigned long blksz; ccb* pccb=(ccb *)&tempccb; if(mode==1) { @@ -158,16 +160,10 @@ void scsi_scan(int mode) scsi_print_error(pccb); continue; } - pccb->datalen=8; - scsi_setup_read_capacity(pccb); - if(scsi_exec(pccb)!=TRUE) { + if (scsi_read_capacity(pccb, &capacity, &blksz)) { scsi_print_error(pccb); continue; } - capacity=((unsigned long)tempbuff[0]<<24)|((unsigned long)tempbuff[1]<<16)| - ((unsigned long)tempbuff[2]<<8)|((unsigned long)tempbuff[3]); - blksz=((unsigned long)tempbuff[4]<<24)|((unsigned long)tempbuff[5]<<16)| - ((unsigned long)tempbuff[6]<<8)|((unsigned long)tempbuff[7]); scsi_dev_desc[scsi_max_devs].lba=capacity; scsi_dev_desc[scsi_max_devs].blksz=blksz; scsi_dev_desc[scsi_max_devs].type=perq; @@ -514,6 +510,67 @@ void scsi_trim_trail (unsigned char *str, unsigned int len) } } +int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz) +{ + *capacity = 0; + + memset(pccb->cmd, 0, sizeof(pccb->cmd)); + pccb->cmd[0] = SCSI_RD_CAPAC10; + pccb->cmd[1] = pccb->lun << 5; + pccb->cmdlen = 10; + pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ + + pccb->datalen = 8; + if (scsi_exec(pccb) != TRUE) + return 1; + + *capacity = ((lbaint_t)pccb->pdata[0] << 24) | + ((lbaint_t)pccb->pdata[1] << 16) | + ((lbaint_t)pccb->pdata[2] << 8) | + ((lbaint_t)pccb->pdata[3]); + + if (*capacity != 0xffffffff) { + /* Read capacity (10) was sufficient for this drive. */ + *blksz = ((unsigned long)pccb->pdata[4] << 24) | + ((unsigned long)pccb->pdata[5] << 16) | + ((unsigned long)pccb->pdata[6] << 8) | + ((unsigned long)pccb->pdata[7]); + return 0; + } + + /* Read capacity (10) was insufficient. Use read capacity (16). */ + + memset(pccb->cmd, 0, sizeof(pccb->cmd)); + pccb->cmd[0] = SCSI_RD_CAPAC16; + pccb->cmd[1] = 0x10; + pccb->cmdlen = 16; + pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ + + pccb->datalen = 16; + if (scsi_exec(pccb) != TRUE) + return 1; + + *capacity = ((uint64_t)pccb->pdata[0] << 56) | + ((uint64_t)pccb->pdata[1] << 48) | + ((uint64_t)pccb->pdata[2] << 40) | + ((uint64_t)pccb->pdata[3] << 32) | + ((uint64_t)pccb->pdata[4] << 24) | + ((uint64_t)pccb->pdata[5] << 16) | + ((uint64_t)pccb->pdata[6] << 8) | + ((uint64_t)pccb->pdata[7]); + + *blksz = ((uint64_t)pccb->pdata[8] << 56) | + ((uint64_t)pccb->pdata[9] << 48) | + ((uint64_t)pccb->pdata[10] << 40) | + ((uint64_t)pccb->pdata[11] << 32) | + ((uint64_t)pccb->pdata[12] << 24) | + ((uint64_t)pccb->pdata[13] << 16) | + ((uint64_t)pccb->pdata[14] << 8) | + ((uint64_t)pccb->pdata[15]); + + return 0; +} + /************************************************************************************ * Some setup (fill-in) routines @@ -530,23 +587,6 @@ void scsi_setup_test_unit_ready(ccb * pccb) pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ } -void scsi_setup_read_capacity(ccb * pccb) -{ - pccb->cmd[0]=SCSI_RD_CAPAC; - pccb->cmd[1]=pccb->lun<<5; - pccb->cmd[2]=0; - pccb->cmd[3]=0; - pccb->cmd[4]=0; - pccb->cmd[5]=0; - pccb->cmd[6]=0; - pccb->cmd[7]=0; - pccb->cmd[8]=0; - pccb->cmd[9]=0; - pccb->cmdlen=10; - pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ - -} - void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks) { pccb->cmd[0]=SCSI_READ10; -- cgit v1.2.3 From 64738e8ae89214030061f62d6598e837664916c3 Mon Sep 17 00:00:00 2001 From: Taylor Hutt Date: Mon, 29 Oct 2012 05:23:58 +0000 Subject: ahci: Use virt_to_phys() to denote physical addresses for DMA Update the assignment of various physical memory buffers used by the SATA controller to explicitly be denoted as physical addresses. The memory is identity-mapped, so these function calls are a nop, but they provide good semantic documentation for any maintainers. The return value of virt_to_phys() is 'unsigned long'. On machines where sizeof(unsigned long) != sizeof(pointer), a cast through (uintptr_t) is needed to appease the compiler due to the potential of losing the upper 32 bits of the address. In compilation this scenario, a physical address could be 64-bits, yet the C pointer environment only allows 32-bit addresses; the constraint is that pointers cannot address more than 4Gb of memory and if virt_to_phys() ever returns an out-of-range value for the physical address, there are issues with emmory mapping which must be solved. However, since the memory is identify mappeed, there is no problem introducing the cast: the original pointer will reside in 32-bits, so the physical address will also be within in 32-bits. Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- drivers/block/ahci.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 20c5336263..00de0868a3 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -431,25 +431,27 @@ static int ahci_port_start(u8 port) * First item in chunk of DMA memory: 32-slot command table, * 32 bytes each in size */ - pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + pp->cmd_slot = + (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); mem += (AHCI_CMD_SLOT_SZ + 224); /* * Second item: Received-FIS area */ - pp->rx_fis = mem; + pp->rx_fis = virt_to_phys((void *)mem); mem += AHCI_RX_FIS_SZ; /* * Third item: data area for storing a single command * and its scatter-gather table */ - pp->cmd_tbl = mem; + pp->cmd_tbl = virt_to_phys((void *)mem); debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); mem += AHCI_CMD_TBL_HDR; - pp->cmd_tbl_sg = (struct ahci_sg *)mem; + pp->cmd_tbl_sg = + (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); -- cgit v1.2.3 From 90b276f6a2a9e197eadce297fd593d85397bc430 Mon Sep 17 00:00:00 2001 From: Taylor Hutt Date: Mon, 29 Oct 2012 05:23:59 +0000 Subject: ahci: flush / invalidate dcache around SATA commands Exynos5 automatically performs DMA when the SATA controller executes commands. This adds the necessary dcache-to-memory flush & invalidation calls to allow the DMA to properly function. Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- drivers/block/ahci.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 00de0868a3..a05d9cfd76 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -70,6 +70,39 @@ static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, #define msleep(a) udelay(a * 1000) +static void ahci_dcache_flush_range(unsigned begin, unsigned len) +{ + const unsigned long start = begin; + const unsigned long end = start + len; + + debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); + flush_dcache_range(start, end); +} + +/* + * SATA controller DMAs to physical RAM. Ensure data from the + * controller is invalidated from dcache; next access comes from + * physical RAM. + */ +static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) +{ + const unsigned long start = begin; + const unsigned long end = start + len; + + debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); + invalidate_dcache_range(start, end); +} + +/* + * Ensure data for SATA controller is flushed out of dcache and + * written to physical memory. + */ +static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) +{ + ahci_dcache_flush_range((unsigned long)pp->cmd_slot, + AHCI_PORT_PRIV_DMA_SZ); +} + static int waiting_for_cmd_completed(volatile u8 *offset, int timeout_msec, u32 sign) @@ -392,6 +425,7 @@ static void ahci_set_feature(u8 port) memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); ahci_fill_cmd_slot(pp, cmd_fis_len); + ahci_dcache_flush_sata_cmd(pp); writel(1, port_mmio + PORT_CMD_ISSUE); readl(port_mmio + PORT_CMD_ISSUE); @@ -496,12 +530,17 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); ahci_fill_cmd_slot(pp, opts); + ahci_dcache_flush_sata_cmd(pp); + ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { printf("timeout exit!\n"); return -1; } + + ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); return 0; -- cgit v1.2.3 From 57847660bb9ddba1d4bc9c1dc551730f71c097a7 Mon Sep 17 00:00:00 2001 From: Walter Murphy Date: Mon, 29 Oct 2012 05:24:00 +0000 Subject: ahci: Adjust SATA timeouts for hard disk (spinup delay & command timeout) Note: These are timeout values and not delay values, so the event being timed out will complete whenever it is actually ready, with a measurement granularity of 1 millisecond, up till the timeout value. Therefore, there is no effect on SSD booting. The values were determined by instrumenting the code and measuring the actual time taken by several different models of HDD for each of the parameters and then adding 50% more for the spinup value and just doubling the command timeout value. Signed-off-by: Walter Murphy Signed-off-by: Simon Glass --- drivers/block/ahci.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index a05d9cfd76..719574f220 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -52,6 +52,10 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; #define MAX_SATA_BLOCKS_READ_WRITE 0x80 #endif +/* Maximum timeouts for each event */ +#define WAIT_MS_DATAIO 5000 +#define WAIT_MS_LINKUP 4 + static inline u32 ahci_port_base(u32 base, u32 port) { return base + 0x100 + (port * 0x80); @@ -201,14 +205,14 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); j = 0; - while (j < 1000) { + while (j < WAIT_MS_LINKUP) { tmp = readl(port_mmio + PORT_SCR_STAT); if ((tmp & 0xf) == 0x3) break; udelay(1000); j++; } - if (j == 1000) + if (j == WAIT_MS_LINKUP) debug("timeout.\n"); else debug("ok.\n"); @@ -429,7 +433,8 @@ static void ahci_set_feature(u8 port) writel(1, port_mmio + PORT_CMD_ISSUE); readl(port_mmio + PORT_CMD_ISSUE); - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, + WAIT_MS_DATAIO, 0x1)) { printf("set feature error on port %d!\n", port); } } @@ -535,7 +540,8 @@ static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); - if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) { + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, + WAIT_MS_DATAIO, 0x1)) { printf("timeout exit!\n"); return -1; } -- cgit v1.2.3 From 2a0c61d401732a2c21b0dc7fe6d1aeec79da8c05 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 29 Oct 2012 05:24:01 +0000 Subject: ahci: Support spin-up and link-up separately Add HDD handling to the SSD-only AHCI driver, by separately dealing with spin-up and link-up. Signed-off-by: Marc Jones Signed-off-by: Simon Glass --- drivers/block/ahci.c | 45 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 719574f220..19c5f137f8 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -53,6 +53,7 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; #endif /* Maximum timeouts for each event */ +#define WAIT_MS_SPINUP 10000 #define WAIT_MS_DATAIO 5000 #define WAIT_MS_LINKUP 4 @@ -129,7 +130,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) unsigned short vendor; #endif volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; - u32 tmp, cap_save; + u32 tmp, cap_save, cmd; int i, j; volatile u8 *port_mmio; @@ -137,7 +138,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) cap_save = readl(mmio + HOST_CAP); cap_save &= ((1 << 28) | (1 << 17)); - cap_save |= (1 << 27); + cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ /* global controller reset */ tmp = readl(mmio + HOST_CTL); @@ -201,9 +202,18 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) msleep(500); } - debug("Spinning up port %d... ", i); - writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); - + /* Add the spinup command to whatever mode bits may + * already be on in the command register. + */ + cmd = readl(port_mmio + PORT_CMD); + cmd |= PORT_CMD_FIS_RX; + cmd |= PORT_CMD_SPIN_UP; + writel_with_flush(cmd, port_mmio + PORT_CMD); + + /* Bring up SATA link. + * SATA link bringup time is usually less than 1 ms; only very + * rarely has it taken between 1-2 ms. Never seen it above 2 ms. + */ j = 0; while (j < WAIT_MS_LINKUP) { tmp = readl(port_mmio + PORT_SCR_STAT); @@ -212,7 +222,30 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) udelay(1000); j++; } - if (j == WAIT_MS_LINKUP) + if (j == WAIT_MS_LINKUP) { + printf("SATA link %d timeout.\n", i); + continue; + } else { + debug("SATA link ok.\n"); + } + + /* Clear error status */ + tmp = readl(port_mmio + PORT_SCR_ERR); + if (tmp) + writel(tmp, port_mmio + PORT_SCR_ERR); + + debug("Spinning up device on SATA port %d... ", i); + + j = 0; + while (j < WAIT_MS_SPINUP) { + tmp = readl(port_mmio + PORT_TFDATA); + if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ))) + break; + udelay(1000); + j++; + } + printf("Target spinup took %d ms.\n", j); + if (j == WAIT_MS_SPINUP) debug("timeout.\n"); else debug("ok.\n"); -- cgit v1.2.3 From 766b16fe180087d8c59a79a4f6a92d1a500fa524 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 29 Oct 2012 05:24:02 +0000 Subject: ahci: Perform SATA flush after disk write. Writes in u-boot are so rare, and the logic to know when is the last write and do a flush only there is sufficiently difficult. Just do a flush after every write. This incurs, usually, one extra flush when the rare writes do happen. Signed-off-by: Marc Jones Signed-off-by: Simon Glass --- drivers/block/ahci.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++++++- include/ata.h | 3 +++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 19c5f137f8..963efec4e1 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -37,6 +37,8 @@ #include #include +static int ata_io_flush(u8 port); + struct ahci_probe_ent *probe_ent = NULL; hd_driveid_t *ataid[AHCI_MAX_PORTS]; @@ -55,6 +57,7 @@ hd_driveid_t *ataid[AHCI_MAX_PORTS]; /* Maximum timeouts for each event */ #define WAIT_MS_SPINUP 10000 #define WAIT_MS_DATAIO 5000 +#define WAIT_MS_FLUSH 5000 #define WAIT_MS_LINKUP 4 static inline u32 ahci_port_base(u32 base, u32 port) @@ -267,7 +270,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent) /* register linkup ports */ tmp = readl(port_mmio + PORT_SCR_STAT); - debug("Port %d status: 0x%x\n", i, tmp); + debug("SATA port %d status: 0x%x\n", i, tmp); if ((tmp & 0xf) == 0x03) probe_ent->link_port_map |= (0x01 << i); } @@ -736,6 +739,17 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) is_write ? "WRITE" : "READ"); return -EIO; } + + /* If this transaction is a write, do a following flush. + * Writes in u-boot are so rare, and the logic to know when is + * the last write and do a flush only there is sufficiently + * difficult. Just do a flush after every write. This incurs, + * usually, one extra flush when the rare writes do happen. + */ + if (is_write) { + if (-EIO == ata_io_flush(pccb->target)) + return -EIO; + } user_buffer += transfer_size; user_buffer_size -= transfer_size; blocks -= now_blocks; @@ -929,6 +943,42 @@ err_out: } #endif +/* + * In the general case of generic rotating media it makes sense to have a + * flush capability. It probably even makes sense in the case of SSDs because + * one cannot always know for sure what kind of internal cache/flush mechanism + * is embodied therein. At first it was planned to invoke this after the last + * write to disk and before rebooting. In practice, knowing, a priori, which + * is the last write is difficult. Because writing to the disk in u-boot is + * very rare, this flush command will be invoked after every block write. + */ +static int ata_io_flush(u8 port) +{ + u8 fis[20]; + struct ahci_ioports *pp = &(probe_ent->port[port]); + volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; + u32 cmd_fis_len = 5; /* five dwords */ + + /* Preset the FIS */ + memset(fis, 0, 20); + fis[0] = 0x27; /* Host to device FIS. */ + fis[1] = 1 << 7; /* Command FIS. */ + fis[2] = ATA_CMD_FLUSH; + + memcpy((unsigned char *)pp->cmd_tbl, fis, 20); + ahci_fill_cmd_slot(pp, cmd_fis_len); + writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); + + if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, + WAIT_MS_FLUSH, 0x1)) { + debug("scsi_ahci: flush command timeout on port %d.\n", port); + return -EIO; + } + + return 0; +} + + void scsi_bus_reset(void) { /*Not implement*/ diff --git a/include/ata.h b/include/ata.h index 3b2d737e61..a614724b8e 100644 --- a/include/ata.h +++ b/include/ata.h @@ -114,6 +114,9 @@ #define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */ #define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */ +#define ATA_CMD_FLUSH 0xE7 /* Flush drive cache */ +#define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */ + /* * ATAPI Commands */ -- cgit v1.2.3 From fe1f808ce79de0caa4674340958f02780b2f81f9 Mon Sep 17 00:00:00 2001 From: Walter Murphy Date: Mon, 29 Oct 2012 05:24:03 +0000 Subject: ahci: Expand HDD Logical Block addressability up to 32 bits Currently, this driver uses a 28bit interface to AHCI, this limits the number of blocks addressable to 2^28, or the max disk size to 512(2^28) or about 137GB. This change allows supporting drives up to about 2TB. Testing this is a bit difficult. There is test code that can be inserted into U-Boot that will write test patterns into certain unused blocks. These patterns can be manually checked using 'dd' after boot. Another way is to confirm the original error that exposed this bug is fixed. IOW: see if AU (Auto Update) will now work on the drive. Also, check that there are no warning messages from the 'cgpt' utility. Signed-off-by: Walter Murphy Signed-off-by: Simon Glass --- drivers/block/ahci.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 963efec4e1..8c785ae923 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -707,7 +707,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ /* Command byte (read/write). */ - fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA; + fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; while (blocks) { u16 now_blocks; /* number of blocks per iteration */ @@ -721,11 +721,15 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) return -EIO; } - /* LBA address, only support LBA28 in this driver */ + /* LBA48 SATA command but only use 32bit address range within + * that. The next smaller command range (28bit) is too small. + */ fis[4] = (lba >> 0) & 0xff; fis[5] = (lba >> 8) & 0xff; fis[6] = (lba >> 16) & 0xff; - fis[7] = ((lba >> 24) & 0xf) | 0xe0; + fis[7] = 1 << 6; /* device reg: set LBA mode */ + fis[8] = ((lba >> 24) & 0xff); + fis[3] = 0xe0; /* features */ /* Block (sector) count */ fis[12] = (now_blocks >> 0) & 0xff; @@ -963,7 +967,7 @@ static int ata_io_flush(u8 port) memset(fis, 0, 20); fis[0] = 0x27; /* Host to device FIS. */ fis[1] = 1 << 7; /* Command FIS. */ - fis[2] = ATA_CMD_FLUSH; + fis[2] = ATA_CMD_FLUSH_EXT; memcpy((unsigned char *)pp->cmd_tbl, fis, 20); ahci_fill_cmd_slot(pp, cmd_fis_len); -- cgit v1.2.3 From b6458d38d6dcdb00a70d12a8a48a2c0ca7eacbf7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 Oct 2012 05:24:04 +0000 Subject: ide: Correct function signatures for ide_read/write() The prototypes in the header were changed by commit 4ac8f8e0 but the functions no longer match. Correct this. It seems odd that block devices take an lbaint_t for the block count, but an unsigned long for the blknr. Surely we should promote blknr to lbaint_t also? Signed-off-by: Simon Glass Reviewed-by: Tom Rini --- common/cmd_ide.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/common/cmd_ide.c b/common/cmd_ide.c index d508e9f75b..0105bdbb7f 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -96,7 +96,8 @@ static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len #ifdef CONFIG_ATAPI static void atapi_inquiry(block_dev_desc_t *dev_desc); -ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer); +static ulong atapi_read(int device, ulong blknr, lbaint_t blkcnt, + void *buffer); #endif @@ -826,7 +827,7 @@ static void ide_ident(block_dev_desc_t *dev_desc) /* ------------------------------------------------------------------------- */ -ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer) +ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer) { ulong n = 0; unsigned char c; @@ -840,7 +841,7 @@ ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer) lba48 = 1; } #endif - debug("ide_read dev %d start %lX, blocks %lX buffer at %lX\n", + debug("ide_read dev %d start %lX, blocks " LBAF " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer); ide_led(DEVICE_LED(device), 1); /* LED on */ @@ -930,13 +931,8 @@ ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer) if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) != ATA_STAT_DRQ) { -#if defined(CONFIG_SYS_64BIT_LBA) - printf("Error (no IRQ) dev %d blk %lld: status 0x%02x\n", + printf("Error (no IRQ) dev %d blk %ld: status %#02x\n", device, blknr, c); -#else - printf("Error (no IRQ) dev %d blk %ld: status 0x%02x\n", - device, (ulong) blknr, c); -#endif break; } @@ -955,7 +951,7 @@ IDE_READ_E: /* ------------------------------------------------------------------------- */ -ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer) +ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer) { ulong n = 0; unsigned char c; @@ -1023,13 +1019,8 @@ ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer) if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) != ATA_STAT_DRQ) { -#if defined(CONFIG_SYS_64BIT_LBA) - printf("Error (no IRQ) dev %d blk %lld: status 0x%02x\n", + printf("Error (no IRQ) dev %d blk %ld: status %#02x\n", device, blknr, c); -#else - printf("Error (no IRQ) dev %d blk %ld: status 0x%02x\n", - device, (ulong) blknr, c); -#endif goto WR_OUT; } @@ -1518,13 +1509,13 @@ static void atapi_inquiry(block_dev_desc_t *dev_desc) #define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */ #define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE) -ulong atapi_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer) +ulong atapi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer) { ulong n = 0; unsigned char ccb[12]; /* Command descriptor block */ ulong cnt; - debug("atapi_read dev %d start %lX, blocks %lX buffer at %lX\n", + debug("atapi_read dev %d start %lX, blocks " LBAF " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer); do { -- cgit v1.2.3 From 51bdad67cb6738c5d0e78084cf3e3baa216f4d2f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 29 Oct 2012 05:24:05 +0000 Subject: x86: config: Enable AHCI support for coreboot Enable AHCI driver for Intel SATA devices. Signed-off-by: Simon Glass --- include/configs/coreboot.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 3df085be51..cc95e2be98 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -45,6 +45,28 @@ #undef CONFIG_WATCHDOG #undef CONFIG_HW_WATCHDOG +/* SATA AHCI storage */ + +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SYS_64BIT_LBA +#define CONFIG_SATA_INTEL 1 +#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ + {PCI_VENDOR_ID_INTEL, \ + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + /*----------------------------------------------------------------------- * Real Time Clock Configuration */ -- cgit v1.2.3 From cc69cc002714422cbb551e3d6ebf7e2723c0c6de Mon Sep 17 00:00:00 2001 From: "Jens Scharsig (BuS Elektronik)" Date: Thu, 18 Oct 2012 21:41:10 +0000 Subject: arm: atmel: cpux9k2: add missing cache configs * add CONFIG_SYS_CACHELINE_SIZE to eb_cpux9k2 board config header * dissable dcache (CONFIG_SYS_DCACHE_OFF) for eb_cpux9k2 Signed-off-by: Jens Scharsig (BuS Elektronik) --- include/configs/eb_cpux9k2.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 9371ec31f3..3be4929fc2 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -43,6 +43,10 @@ #define MACH_TYPE_EB_CPUX9K2 1977 #define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2 + +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_DCACHE_OFF + /*--------------------------------------------------------------------------*/ #ifndef CONFIG_RAMBOOT #define CONFIG_SYS_TEXT_BASE 0x00000000 @@ -56,7 +60,6 @@ #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */ - #define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_CMDLINE_EDITING -- cgit v1.2.3 From 7ae534cef9393bd60d261aedff87872a319aa769 Mon Sep 17 00:00:00 2001 From: Vikram Narayanan Date: Tue, 23 Oct 2012 00:21:16 +0000 Subject: socfpga/spl: Remove timer_init from spl_board_init Timer is initialized already in board_init_r function in (common/spl/spl.c) No need to initialize it again Signed-off-by: Vikram Narayanan Cc: Dinh Nguyen --- arch/arm/cpu/armv7/socfpga/spl.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 944238bad1..23053fd90f 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -37,9 +37,6 @@ u32 spl_boot_device(void) */ void spl_board_init(void) { - /* init timer for enabling delay function */ - timer_init(); - /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); -- cgit v1.2.3 From 46d626d3926cf6b9f9c477782c5a0ee620a424cd Mon Sep 17 00:00:00 2001 From: Vikram Narayanan Date: Tue, 23 Oct 2012 00:22:53 +0000 Subject: socfpga/spl: Remove malloc.h Remove unused header Signed-off-by: Vikram Narayanan --- arch/arm/cpu/armv7/socfpga/spl.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 23053fd90f..84216eb1ef 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3 From e9b0f99e8243e3146f3b5f4ef91f4b6c8f4452c0 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 30 Oct 2012 12:04:17 +0000 Subject: fs: fix do_fsload() handling of optional arguments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most arguments to the shell command do_fsload() implements are optional. Fix the minimum argc check to respect that. Cater for the situation where argv[2] is not provided. Enhance both do_fsload() and do_ls() to check the maximum number of arguments too. While this check would typically be implemented via U_BOOT_CMD()'s max_args parameter, if these functions are called directly, then that check won't exist. Finally, alter do_ls() to check (argc >= 4) rather than (argc == 4) so that if the function is enhanced to allow extra arguments in the future, this test won't need to be changed at that time. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- fs/fs.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/fs/fs.c b/fs/fs.c index e148a07406..f570312610 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -258,10 +258,12 @@ int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int len_read; char buf[12]; - if (argc < 5) + if (argc < 2) + return CMD_RET_USAGE; + if (argc > 7) return CMD_RET_USAGE; - if (fs_set_blk_dev(argv[1], argv[2], fstype)) + if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype)) return 1; if (argc >= 4) { @@ -308,11 +310,13 @@ int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], { if (argc < 2) return CMD_RET_USAGE; + if (argc > 4) + return CMD_RET_USAGE; if (fs_set_blk_dev(argv[1], (argc >= 3) ? argv[2] : NULL, fstype)) return 1; - if (fs_ls(argc == 4 ? argv[3] : "/")) + if (fs_ls(argc >= 4 ? argv[3] : "/")) return 1; return 0; -- cgit v1.2.3 From b6a30444365be7ef4d323b50573a2c591ef36d08 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 30 Oct 2012 12:04:18 +0000 Subject: cmd_ext4: remove TABs from command help text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TABs in the help text won't line up in the same place on the console as in a source editor. Replace them with spaces to make ensuring correct alignment easier. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- common/cmd_ext4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index e193f29c47..b4a154ffeb 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -123,17 +123,17 @@ fail: U_BOOT_CMD(ext4write, 6, 1, do_ext4_write, "create a file in the root directory", " [Absolute filename path] [Address] [sizebytes]\n" - " - create a file in / directory"); + " - create a file in / directory"); #endif U_BOOT_CMD(ext4ls, 4, 1, do_ext4_ls, "list files in a directory (default /)", " [directory]\n" - " - list files from 'dev' on 'interface' in a 'directory'"); + " - list files from 'dev' on 'interface' in a 'directory'"); U_BOOT_CMD(ext4load, 6, 0, do_ext4_load, "load binary file from a Ext4 filesystem", " [addr] [filename] [bytes]\n" - " - load binary file 'filename' from 'dev' on 'interface'\n" - " to address 'addr' from ext4 filesystem"); + " - load binary file 'filename' from 'dev' on 'interface'\n" + " to address 'addr' from ext4 filesystem"); -- cgit v1.2.3 From 3f83c87ee58d86e9a9d2e50b62f38c728bfb31f6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 30 Oct 2012 12:04:19 +0000 Subject: fs: fix number base behaviour change in fatload/ext*load MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 045fa1e "fs: add filesystem switch libary, implement ls and fsload commands" unified the implementation of fatload and ext*load with the new command fsload. However, this altered the interpretation of command-line numbers from always being base-16, to requiring a "0x" prefix for base-16 numbers. Enhance do_fsload() to allow commands to specify which base to use. Use base 0, thus requiring a "0x" prefix for the new fsload command. This feels much cleaner than assuming base 16. Use base 16 for the pre-existing fatload and ext*load to prevent a change in behaviour. Use base 16 exclusively for the loadaddr environment variable, since that variable is interpreted in multiple places, so we don't want the behaviour to change. Update command help text to make it clear where numbers are assumed to be hex, and where an explicit "0x" prefix is required. Signed-off-by: Stephen Warren Reviewed-by: Benoît Thébaudeau --- common/cmd_ext2.c | 5 +++-- common/cmd_ext4.c | 5 +++-- common/cmd_fat.c | 5 +++-- common/cmd_fs.c | 6 ++++-- fs/fs.c | 8 ++++---- include/fs.h | 2 +- 6 files changed, 18 insertions(+), 13 deletions(-) diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index 06d0234a47..7f225987a0 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -49,7 +49,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT); + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); } U_BOOT_CMD( @@ -64,5 +64,6 @@ U_BOOT_CMD( "load binary file from a Ext2 filesystem", " [addr] [filename] [bytes]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" - " to address 'addr' from ext2 filesystem" + " to address 'addr' from ext2 filesystem.\n" + " All numeric parameters are assumed to be hex." ); diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index b4a154ffeb..b50bd0ae9a 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -59,7 +59,7 @@ int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT); + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); } int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) @@ -136,4 +136,5 @@ U_BOOT_CMD(ext4load, 6, 0, do_ext4_load, "load binary file from a Ext4 filesystem", " [addr] [filename] [bytes]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" - " to address 'addr' from ext4 filesystem"); + " to address 'addr' from ext4 filesystem.\n" + " All numeric parameters are assumed to be hex."); diff --git a/common/cmd_fat.c b/common/cmd_fat.c index c865d6d8a2..82804838d5 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -35,7 +35,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_FAT); + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_FAT, 16); } @@ -48,7 +48,8 @@ U_BOOT_CMD( " 'pos' gives the file position to start loading from.\n" " If 'pos' is omitted, 0 is used. 'pos' requires 'bytes'.\n" " 'bytes' gives the size to load. If 'bytes' is 0 or omitted,\n" - " the load stops on end of file." + " the load stops on end of file.\n" + " All numeric parameters are assumed to be hex." ); int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/common/cmd_fs.c b/common/cmd_fs.c index 296124b995..46fcef78ee 100644 --- a/common/cmd_fs.c +++ b/common/cmd_fs.c @@ -22,7 +22,7 @@ int do_fsload_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_ANY); + return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_ANY, 0); } U_BOOT_CMD( @@ -34,7 +34,9 @@ U_BOOT_CMD( " 'bytes' gives the size to load in bytes.\n" " If 'bytes' is 0 or omitted, the file is read until the end.\n" " 'pos' gives the file byte position to start reading from.\n" - " If 'pos' is 0 or omitted, the file is read from the start." + " If 'pos' is 0 or omitted, the file is read from the start.\n" + " All numeric parameters are assumed to be decimal,\n" + " unless specified otherwise using a leading \"0x\"." ); int do_ls_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/fs/fs.c b/fs/fs.c index f570312610..1553af59d3 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -248,7 +248,7 @@ int fs_read(const char *filename, ulong addr, int offset, int len) } int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int fstype) + int fstype, int cmdline_base) { unsigned long addr; const char *addr_str; @@ -267,7 +267,7 @@ int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], return 1; if (argc >= 4) { - addr = simple_strtoul(argv[3], NULL, 0); + addr = simple_strtoul(argv[3], NULL, cmdline_base); } else { addr_str = getenv("loadaddr"); if (addr_str != NULL) @@ -285,11 +285,11 @@ int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], } } if (argc >= 6) - bytes = simple_strtoul(argv[5], NULL, 0); + bytes = simple_strtoul(argv[5], NULL, cmdline_base); else bytes = 0; if (argc >= 7) - pos = simple_strtoul(argv[6], NULL, 0); + pos = simple_strtoul(argv[6], NULL, cmdline_base); else pos = 0; diff --git a/include/fs.h b/include/fs.h index f396d8492a..c3ac7ccc0d 100644 --- a/include/fs.h +++ b/include/fs.h @@ -58,7 +58,7 @@ int fs_read(const char *filename, ulong addr, int offset, int len); * to a specific filesystem type via the fstype parameter. */ int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], - int fstype); + int fstype, int cmdline_base); int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); -- cgit v1.2.3 From f9b55e22856a97523074f3dc40ea5d196298756a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 31 Oct 2012 11:05:07 +0000 Subject: fs: rename fsload command to load When the generic filesystem load command "fsload" was written, I felt that "load" was too generic of a name for it, since many other similar commands already existed. However, it turns out that there is already an "fsload" command, so that name cannot be used. Rename the new "fsload" to plain "load" to avoid the conflict. At least anyone who's used a Basic interpreter should feel familiar with the name! Signed-off-by: Stephen Warren --- common/cmd_ext2.c | 2 +- common/cmd_ext4.c | 2 +- common/cmd_fat.c | 2 +- common/cmd_fs.c | 6 +++--- fs/fs.c | 2 +- include/fs.h | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index 7f225987a0..f25e22b0a8 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -49,7 +49,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); } U_BOOT_CMD( diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index b50bd0ae9a..dcf76a50cd 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -59,7 +59,7 @@ int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_EXT, 16); } int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) diff --git a/common/cmd_fat.c b/common/cmd_fat.c index 82804838d5..2e2301e581 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -35,7 +35,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_FAT, 16); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_FAT, 16); } diff --git a/common/cmd_fs.c b/common/cmd_fs.c index 46fcef78ee..a681d03d1b 100644 --- a/common/cmd_fs.c +++ b/common/cmd_fs.c @@ -20,13 +20,13 @@ #include #include -int do_fsload_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return do_fsload(cmdtp, flag, argc, argv, FS_TYPE_ANY, 0); + return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY, 0); } U_BOOT_CMD( - fsload, 7, 0, do_fsload_wrapper, + load, 7, 0, do_load_wrapper, "load binary file from a filesystem", " [ [ [ [bytes [pos]]]]]\n" " - Load binary file 'filename' from partition 'part' on device\n" diff --git a/fs/fs.c b/fs/fs.c index 1553af59d3..ff360afd4b 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -247,7 +247,7 @@ int fs_read(const char *filename, ulong addr, int offset, int len) return ret; } -int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], +int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype, int cmdline_base) { unsigned long addr; diff --git a/include/fs.h b/include/fs.h index c3ac7ccc0d..4f30a385a0 100644 --- a/include/fs.h +++ b/include/fs.h @@ -57,7 +57,7 @@ int fs_read(const char *filename, ulong addr, int offset, int len); * Common implementation for various filesystem commands, optionally limited * to a specific filesystem type via the fstype parameter. */ -int do_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], +int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype, int cmdline_base); int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], int fstype); -- cgit v1.2.3 From eef1cf2d5cf1cae5fb76713e912263dedf110aeb Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:23 +0000 Subject: include/linux/byteorder: import latest endian definitions from linux u-boot's byteorder headers did not contain endianness attributions for use with sparse, causing a lot of false positives. Import the kernel's latest definitions, and enable them by including compiler.h and types.h. They come with 'const' added for some swab functions, so fix those up, too: include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default] Also, note: u-boot's historic __BYTE_ORDER definition has been preserved (for the time being at least). We also remove ad-hoc barrier() definitions, since we're including compiler.h in files that hadn't in the past: macb.c:54:0: warning: "barrier" redefined [enabled by default] In addition, including compiler.h in byteorder changes the 'noinline' definition to expand to __attribute__((noinline)). This fixes arch/powerpc/lib/bootm.c: bootm.c:329:16: error: attribute '__attribute__': unknown attribute bootm.c:329:16: error: expected ')' before '__attribute__' bootm.c:329:25: error: expected identifier or '(' before ')' token powerpc sparse builds yield: include/common.h:356:22: error: marked inline, but without a definition the unknown-reason inlining without a definition is considered obsolete given it was part of the 2002 initial commit, and no arm version was 'fixed.' also fixed: ydirectenv.h:60:0: warning: "inline" redefined [enabled by default] and: Configuring for devconcenter - Board: intip, Options: DEVCONCENTER make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1 make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2 powerpc-fsl-linux-size: './u-boot': No such file 4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration': include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available 4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here and: In file included from crc32.c:50:0: crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration] crc32table.h:4:1: error: initializer element is not constant crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]') Signed-off-by: Kim Phillips [trini: Remove '#endif' in include/common.h around setenv portion] Signed-off-by: Tom Rini --- arch/arm/cpu/arm1176/tnetv107x/clock.c | 4 - arch/powerpc/include/asm/ppc4xx-sdram.h | 2 +- arch/powerpc/lib/bootm.c | 2 +- drivers/mtd/ubi/crc32.c | 12 +-- drivers/net/macb.c | 2 - drivers/net/smc91111.c | 2 - drivers/serial/s3c64xx.c | 2 - fs/yaffs2/ydirectenv.h | 2 - include/common.h | 4 - include/linux/byteorder/big_endian.h | 135 +++++++++++++++++++++----------- include/linux/byteorder/little_endian.h | 133 ++++++++++++++++++++----------- include/linux/byteorder/swab.h | 6 +- 12 files changed, 182 insertions(+), 124 deletions(-) diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c index e26fec1f95..16876aeea8 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/clock.c +++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c @@ -168,10 +168,6 @@ static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff }; #define tdm_extra_clk {TDM_PLL, 1} #define tdm1_clk {TDM_PLL, 2} -/* Optimization barrier */ -#define barrier() \ - __asm__ __volatile__("mov r0, r0\n" : : : "memory"); - static const struct lpsc_map lpsc_clk_map[] = { [TNETV107X_LPSC_ARM] = sys_arm1176_clk, [TNETV107X_LPSC_GEM] = sys_dsp_clk, diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index d570d7915e..e35d9b677a 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -1404,7 +1404,7 @@ struct sdram_timing { /* * Prototypes */ -inline void ppc4xx_ibm_ddr2_register_dump(void); +void ppc4xx_ibm_ddr2_register_dump(void); u32 mfdcr_any(u32); void mtdcr_any(u32, u32); u32 ddr_wrdtr(u32); diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 53dc4df3fe..ac5bd6d4f1 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -326,7 +326,7 @@ static int boot_body_linux(bootm_headers_t *images) return 0; } -__attribute__((noinline)) +noinline int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { int ret; diff --git a/drivers/mtd/ubi/crc32.c b/drivers/mtd/ubi/crc32.c index a7e26b0456..ab439b3e20 100644 --- a/drivers/mtd/ubi/crc32.c +++ b/drivers/mtd/ubi/crc32.c @@ -38,17 +38,9 @@ #include "crc32defs.h" #define CRC_LE_BITS 8 -# define __force -#ifndef __constant_cpu_to_le32 -#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x)) -#endif -#ifndef __constant_le32_to_cpu -#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x)) -#endif - #if CRC_LE_BITS == 8 -#define tole(x) __constant_cpu_to_le32(x) -#define tobe(x) __constant_cpu_to_be32(x) +#define tole(x) cpu_to_le32(x) +#define tobe(x) cpu_to_be32(x) #else #define tole(x) (x) #define tobe(x) (x) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 0e1ced71c5..8bacbda719 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -51,8 +51,6 @@ #include "macb.h" -#define barrier() asm volatile("" ::: "memory") - #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096 #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128) #define CONFIG_SYS_MACB_TX_RING_SIZE 16 diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 6dc7ad52e4..1357edee6c 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -178,8 +178,6 @@ static void smc_phy_configure(struct eth_device *dev); * inx,outx functions fixed this problem. */ -#define barrier() __asm__ __volatile__("": : :"memory") - static inline word SMC_inw(struct eth_device *dev, dword offset) { word v; diff --git a/drivers/serial/s3c64xx.c b/drivers/serial/s3c64xx.c index ea8d734a9e..f53c2bf003 100644 --- a/drivers/serial/s3c64xx.c +++ b/drivers/serial/s3c64xx.c @@ -40,8 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; #error "Bad: you didn't configure serial ..." #endif -#define barrier() asm volatile("" ::: "memory") - /* * The coefficient, used to calculate the baudrate on S3C6400 UARTs is * calculated as diff --git a/fs/yaffs2/ydirectenv.h b/fs/yaffs2/ydirectenv.h index c912b09a40..c2ffbfd56d 100644 --- a/fs/yaffs2/ydirectenv.h +++ b/fs/yaffs2/ydirectenv.h @@ -56,8 +56,6 @@ void yaffs_qsort(void *aa, size_t n, size_t es, #ifdef NO_inline #define inline -#else -#define inline __inline__ #endif #define cond_resched() do {} while (0) diff --git a/include/common.h b/include/common.h index 12b3e039a0..5e3c5eeee1 100644 --- a/include/common.h +++ b/include/common.h @@ -341,11 +341,7 @@ char *getenv (const char *); int getenv_f (const char *name, char *buf, unsigned len); ulong getenv_ulong(const char *name, int base, ulong default_val); int saveenv (void); -#ifdef CONFIG_PPC /* ARM version to be fixed! */ -int inline setenv (const char *, const char *); -#else int setenv (const char *, const char *); -#endif /* CONFIG_PPC */ int setenv_ulong(const char *varname, ulong value); int setenv_addr(const char *varname, const void *addr); #ifdef CONFIG_ARM diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h index 19b0c86e43..aaf77577c4 100644 --- a/include/linux/byteorder/big_endian.h +++ b/include/linux/byteorder/big_endian.h @@ -7,63 +7,104 @@ #ifndef __BIG_ENDIAN_BITFIELD #define __BIG_ENDIAN_BITFIELD #endif -#define __BYTE_ORDER __BIG_ENDIAN +#define __BYTE_ORDER __BIG_ENDIAN +#include +#include #include -#define __constant_htonl(x) ((__u32)(x)) -#define __constant_ntohl(x) ((__u32)(x)) -#define __constant_htons(x) ((__u16)(x)) -#define __constant_ntohs(x) ((__u16)(x)) -#define __constant_cpu_to_le64(x) ___swab64((x)) -#define __constant_le64_to_cpu(x) ___swab64((x)) -#define __constant_cpu_to_le32(x) ___swab32((x)) -#define __constant_le32_to_cpu(x) ___swab32((x)) -#define __constant_cpu_to_le16(x) ___swab16((x)) -#define __constant_le16_to_cpu(x) ___swab16((x)) -#define __constant_cpu_to_be64(x) ((__u64)(x)) -#define __constant_be64_to_cpu(x) ((__u64)(x)) -#define __constant_cpu_to_be32(x) ((__u32)(x)) -#define __constant_be32_to_cpu(x) ((__u32)(x)) -#define __constant_cpu_to_be16(x) ((__u16)(x)) -#define __constant_be16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_le64(x) __swab64((x)) -#define __le64_to_cpu(x) __swab64((x)) -#define __cpu_to_le32(x) __swab32((x)) -#define __le32_to_cpu(x) __swab32((x)) -#define __cpu_to_le16(x) __swab16((x)) -#define __le16_to_cpu(x) __swab16((x)) -#define __cpu_to_be64(x) ((__u64)(x)) -#define __be64_to_cpu(x) ((__u64)(x)) -#define __cpu_to_be32(x) ((__u32)(x)) -#define __be32_to_cpu(x) ((__u32)(x)) -#define __cpu_to_be16(x) ((__u16)(x)) -#define __be16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_le64p(x) __swab64p((x)) -#define __le64_to_cpup(x) __swab64p((x)) -#define __cpu_to_le32p(x) __swab32p((x)) -#define __le32_to_cpup(x) __swab32p((x)) -#define __cpu_to_le16p(x) __swab16p((x)) -#define __le16_to_cpup(x) __swab16p((x)) -#define __cpu_to_be64p(x) (*(__u64*)(x)) -#define __be64_to_cpup(x) (*(__u64*)(x)) -#define __cpu_to_be32p(x) (*(__u32*)(x)) -#define __be32_to_cpup(x) (*(__u32*)(x)) -#define __cpu_to_be16p(x) (*(__u16*)(x)) -#define __be16_to_cpup(x) (*(__u16*)(x)) +#define __constant_htonl(x) ((__force __be32)(__u32)(x)) +#define __constant_ntohl(x) ((__force __u32)(__be32)(x)) +#define __constant_htons(x) ((__force __be16)(__u16)(x)) +#define __constant_ntohs(x) ((__force __u16)(__be16)(x)) +#define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x))) +#define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x))) +#define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x))) +#define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__force __be64)(__u64)(x)) +#define __constant_be64_to_cpu(x) ((__force __u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x)) +#define __constant_be32_to_cpu(x) ((__force __u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__force __be16)(__u16)(x)) +#define __constant_be16_to_cpu(x) ((__force __u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__force __le64)__swab64((x))) +#define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__force __le32)__swab32((x))) +#define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__force __le16)__swab16((x))) +#define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) +#define __be64_to_cpu(x) ((__force __u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__force __be32)(__u32)(x)) +#define __be32_to_cpu(x) ((__force __u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__force __be16)(__u16)(x)) +#define __be16_to_cpu(x) ((__force __u16)(__be16)(x)) + +static inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__force __le64)__swab64p(p); +} +static inline __u64 __le64_to_cpup(const __le64 *p) +{ + return __swab64p((__u64 *)p); +} +static inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__force __le32)__swab32p(p); +} +static inline __u32 __le32_to_cpup(const __le32 *p) +{ + return __swab32p((__u32 *)p); +} +static inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__force __le16)__swab16p(p); +} +static inline __u16 __le16_to_cpup(const __le16 *p) +{ + return __swab16p((__u16 *)p); +} +static inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__force __be64)*p; +} +static inline __u64 __be64_to_cpup(const __be64 *p) +{ + return (__force __u64)*p; +} +static inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__force __be32)*p; +} +static inline __u32 __be32_to_cpup(const __be32 *p) +{ + return (__force __u32)*p; +} +static inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__force __be16)*p; +} +static inline __u16 __be16_to_cpup(const __be16 *p) +{ + return (__force __u16)*p; +} #define __cpu_to_le64s(x) __swab64s((x)) #define __le64_to_cpus(x) __swab64s((x)) #define __cpu_to_le32s(x) __swab32s((x)) #define __le32_to_cpus(x) __swab32s((x)) #define __cpu_to_le16s(x) __swab16s((x)) #define __le16_to_cpus(x) __swab16s((x)) -#define __cpu_to_be64s(x) do {} while (0) -#define __be64_to_cpus(x) do {} while (0) -#define __cpu_to_be32s(x) do {} while (0) -#define __be32_to_cpus(x) do {} while (0) -#define __cpu_to_be16s(x) do {} while (0) -#define __be16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) do { (void)(x); } while (0) +#define __be64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be32s(x) do { (void)(x); } while (0) +#define __be32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_be16s(x) do { (void)(x); } while (0) +#define __be16_to_cpus(x) do { (void)(x); } while (0) +#ifdef __KERNEL__ #include +#endif #endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h index a46f3ecc12..a4cb3bfde5 100644 --- a/include/linux/byteorder/little_endian.h +++ b/include/linux/byteorder/little_endian.h @@ -9,54 +9,93 @@ #endif #define __BYTE_ORDER __LITTLE_ENDIAN +#include +#include #include -#define __constant_htonl(x) ___constant_swab32((x)) -#define __constant_ntohl(x) ___constant_swab32((x)) -#define __constant_htons(x) ___constant_swab16((x)) -#define __constant_ntohs(x) ___constant_swab16((x)) -#define __constant_cpu_to_le64(x) ((__u64)(x)) -#define __constant_le64_to_cpu(x) ((__u64)(x)) -#define __constant_cpu_to_le32(x) ((__u32)(x)) -#define __constant_le32_to_cpu(x) ((__u32)(x)) -#define __constant_cpu_to_le16(x) ((__u16)(x)) -#define __constant_le16_to_cpu(x) ((__u16)(x)) -#define __constant_cpu_to_be64(x) ___constant_swab64((x)) -#define __constant_be64_to_cpu(x) ___constant_swab64((x)) -#define __constant_cpu_to_be32(x) ___constant_swab32((x)) -#define __constant_be32_to_cpu(x) ___constant_swab32((x)) -#define __constant_cpu_to_be16(x) ___constant_swab16((x)) -#define __constant_be16_to_cpu(x) ___constant_swab16((x)) -#define __cpu_to_le64(x) ((__u64)(x)) -#define __le64_to_cpu(x) ((__u64)(x)) -#define __cpu_to_le32(x) ((__u32)(x)) -#define __le32_to_cpu(x) ((__u32)(x)) -#define __cpu_to_le16(x) ((__u16)(x)) -#define __le16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_be64(x) __swab64((x)) -#define __be64_to_cpu(x) __swab64((x)) -#define __cpu_to_be32(x) __swab32((x)) -#define __be32_to_cpu(x) __swab32((x)) -#define __cpu_to_be16(x) __swab16((x)) -#define __be16_to_cpu(x) __swab16((x)) -#define __cpu_to_le64p(x) (*(__u64*)(x)) -#define __le64_to_cpup(x) (*(__u64*)(x)) -#define __cpu_to_le32p(x) (*(__u32*)(x)) -#define __le32_to_cpup(x) (*(__u32*)(x)) -#define __cpu_to_le16p(x) (*(__u16*)(x)) -#define __le16_to_cpup(x) (*(__u16*)(x)) -#define __cpu_to_be64p(x) __swab64p((x)) -#define __be64_to_cpup(x) __swab64p((x)) -#define __cpu_to_be32p(x) __swab32p((x)) -#define __be32_to_cpup(x) __swab32p((x)) -#define __cpu_to_be16p(x) __swab16p((x)) -#define __be16_to_cpup(x) __swab16p((x)) -#define __cpu_to_le64s(x) do {} while (0) -#define __le64_to_cpus(x) do {} while (0) -#define __cpu_to_le32s(x) do {} while (0) -#define __le32_to_cpus(x) do {} while (0) -#define __cpu_to_le16s(x) do {} while (0) -#define __le16_to_cpus(x) do {} while (0) +#define __constant_htonl(x) ((__force __be32)___constant_swab32((x))) +#define __constant_ntohl(x) ___constant_swab32((__force __be32)(x)) +#define __constant_htons(x) ((__force __be16)___constant_swab16((x))) +#define __constant_ntohs(x) ___constant_swab16((__force __be16)(x)) +#define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x)) +#define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x)) +#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x)) +#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x)) +#define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x)) +#define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x)) +#define __constant_cpu_to_be64(x) ((__force __be64)___constant_swab64((x))) +#define __constant_be64_to_cpu(x) ___constant_swab64((__force __u64)(__be64)(x)) +#define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x))) +#define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be32)(x)) +#define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x))) +#define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be16)(x)) +#define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) +#define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) +#define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) +#define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) +#define __cpu_to_le16(x) ((__force __le16)(__u16)(x)) +#define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) +#define __cpu_to_be64(x) ((__force __be64)__swab64((x))) +#define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x)) +#define __cpu_to_be32(x) ((__force __be32)__swab32((x))) +#define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x)) +#define __cpu_to_be16(x) ((__force __be16)__swab16((x))) +#define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x)) + +static inline __le64 __cpu_to_le64p(const __u64 *p) +{ + return (__force __le64)*p; +} +static inline __u64 __le64_to_cpup(const __le64 *p) +{ + return (__force __u64)*p; +} +static inline __le32 __cpu_to_le32p(const __u32 *p) +{ + return (__force __le32)*p; +} +static inline __u32 __le32_to_cpup(const __le32 *p) +{ + return (__force __u32)*p; +} +static inline __le16 __cpu_to_le16p(const __u16 *p) +{ + return (__force __le16)*p; +} +static inline __u16 __le16_to_cpup(const __le16 *p) +{ + return (__force __u16)*p; +} +static inline __be64 __cpu_to_be64p(const __u64 *p) +{ + return (__force __be64)__swab64p(p); +} +static inline __u64 __be64_to_cpup(const __be64 *p) +{ + return __swab64p((__u64 *)p); +} +static inline __be32 __cpu_to_be32p(const __u32 *p) +{ + return (__force __be32)__swab32p(p); +} +static inline __u32 __be32_to_cpup(const __be32 *p) +{ + return __swab32p((__u32 *)p); +} +static inline __be16 __cpu_to_be16p(const __u16 *p) +{ + return (__force __be16)__swab16p(p); +} +static inline __u16 __be16_to_cpup(const __be16 *p) +{ + return __swab16p((__u16 *)p); +} +#define __cpu_to_le64s(x) do { (void)(x); } while (0) +#define __le64_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le32s(x) do { (void)(x); } while (0) +#define __le32_to_cpus(x) do { (void)(x); } while (0) +#define __cpu_to_le16s(x) do { (void)(x); } while (0) +#define __le16_to_cpus(x) do { (void)(x); } while (0) #define __cpu_to_be64s(x) __swab64s((x)) #define __be64_to_cpus(x) __swab64s((x)) #define __cpu_to_be32s(x) __swab32s((x)) @@ -64,6 +103,8 @@ #define __cpu_to_be16s(x) __swab16s((x)) #define __be16_to_cpus(x) __swab16s((x)) +#ifdef __KERNEL__ #include +#endif #endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h index b1d570e528..bb4a046937 100644 --- a/include/linux/byteorder/swab.h +++ b/include/linux/byteorder/swab.h @@ -100,7 +100,7 @@ static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) { return __arch__swab16(x); } -static __inline__ __u16 __swab16p(__u16 *x) +static __inline__ __u16 __swab16p(const __u16 *x) { return __arch__swab16p(x); } @@ -113,7 +113,7 @@ static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) { return __arch__swab32(x); } -static __inline__ __u32 __swab32p(__u32 *x) +static __inline__ __u32 __swab32p(const __u32 *x) { return __arch__swab32p(x); } @@ -133,7 +133,7 @@ static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) return __arch__swab64(x); # endif } -static __inline__ __u64 __swab64p(__u64 *x) +static __inline__ __u64 __swab64p(const __u64 *x) { return __arch__swab64p(x); } -- cgit v1.2.3 From 0d4c1c91bb2852ff6f4e46f40e72e74ec10599c5 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:24 +0000 Subject: include/linux/compat.h: fix warning: preprocessor token {__iomem, __user} redefined include/linux/compat.h:4:9: warning: preprocessor token __user redefined include/linux/compiler.h:7:10: this was the original definition include/linux/compat.h:5:9: warning: preprocessor token __iomem redefined include/linux/compiler.h:12:10: this was the original definition fixup __iomem, __user definitions in compat.h code appears to be placed there as a cover up from a code import from linux when u-boot didn't yet have a compiler.h, introduced by commit 932394ac43e2e778e664eeb6e456fecd0fae6e59 "Rewrite of NAND code based on what is in 2.6.12 Linux kernel". Signed-off-by: Kim Phillips --- include/linux/compat.h | 3 --- include/linux/mtd/mtd-abi.h | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/include/linux/compat.h b/include/linux/compat.h index 593b07f4b5..e1338bf489 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -1,9 +1,6 @@ #ifndef _LINUX_COMPAT_H_ #define _LINUX_COMPAT_H_ -#define __user -#define __iomem - #define ndelay(x) udelay(1) #define printk printf diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h index 5991157065..8bdd23112b 100644 --- a/include/linux/mtd/mtd-abi.h +++ b/include/linux/mtd/mtd-abi.h @@ -11,6 +11,8 @@ #include #endif +#include + struct erase_info_user { uint32_t start; uint32_t length; -- cgit v1.2.3 From 25b26ec69fb5390ce08601189d8848fcef91b97c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:25 +0000 Subject: include/linux/unaligned/generic.h: fix warning: preprocessor token __force redefined include/linux/unaligned/generic.h:5:9: warning: preprocessor token __force redefined include/linux/compiler.h:10:10: this was the original definition fixup __force definitions in compat.h code appears to be placed there as a cover up from a code import from linux when u-boot didn't yet have a compiler.h, introduced by commit b1b4e89a0f3b75854c39a62cae41bad56d210adf "Add LZO decompressor support". Signed-off-by: Kim Phillips --- include/linux/unaligned/generic.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/linux/unaligned/generic.h b/include/linux/unaligned/generic.h index cc688e1eb1..02d97ff3df 100644 --- a/include/linux/unaligned/generic.h +++ b/include/linux/unaligned/generic.h @@ -1,9 +1,6 @@ #ifndef _LINUX_UNALIGNED_GENERIC_H #define _LINUX_UNALIGNED_GENERIC_H -/* define __force to nothing in U-Boot */ -#define __force - /* * Cause a link-time error if we try an unaligned access other than * 1,2,4 or 8 bytes long -- cgit v1.2.3 From aa9e891c6331555a75ddcb490fc61160ca7d1657 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:26 +0000 Subject: include/linux/stddef.h: avoid 'warning: preprocessor token offsetof redefined' hack to avoid: /opt/gcc-4.6.3-nolibc/powerpc-linux/bin/../lib/gcc/powerpc-linux/4.6.3/include/stddef.h:413:9: warning: preprocessor token offsetof redefined u-boot/include/linux/stddef.h:20:9: this was the original definition tried protecting with __KERNEL__, and #including compiler.h first. Even tried include dir reordering to no avail: +++ b/config.mk @@ -194,7 +194,11 @@ OBJCFLAGS += --gap-fill=0xff gccincdir := $(shell $(CC) -print-file-name=include) CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ - -D__KERNEL__ + -D__KERNEL__ \ + -I $(gccincdir) \ + -nostdinc + +# -isystem $(gccincdir) \ # Enable garbage collection of un-used sections for SPL ifeq ($(CONFIG_SPL_BUILD),y) @@ -227,8 +231,7 @@ CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include endif CPPFLAGS += -I$(TOPDIR)/include -CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ - -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) +CPPFLAGS += -fno-builtin -ffreestanding -pipe $(PLATFORM_CPPFLAGS) Signed-off-by: Kim Phillips --- include/linux/stddef.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/stddef.h b/include/linux/stddef.h index 81e34c260f..c540f6100d 100644 --- a/include/linux/stddef.h +++ b/include/linux/stddef.h @@ -12,7 +12,9 @@ #include #endif +#ifndef __CHECKER__ #undef offsetof #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#endif #endif -- cgit v1.2.3 From cdfdb8d7f300cbe42fc22af75efd142644ee9373 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:27 +0000 Subject: arch/powerpc/include/asm/io.h: fix warning: preprocessor token __iomem redefined a fixup __iomem definition in arch code appears to be placed there as a cover up from a code import from linux when u-boot didn't yet have a compiler.h, introduced by commit 812711ce6b3a386125dcf0d6a59588e461abbb87 "Implement __raw_{read,write}[bwl] on all architectures". git show 812711ce6b3a386125dcf0d6a59588e461abbb87:include/linux/compiler.h fatal: Path 'include/linux/compiler.h' exists on disk, but not in '812711ce6b3a386125dcf0d6a59588e461abbb87'. Signed-off-by: Kim Phillips --- arch/powerpc/include/asm/io.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 9e208618d9..1f12c29ba8 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -127,7 +127,6 @@ static inline void isync(void) /* * Non ordered and non-swapping "raw" accessors */ -#define __iomem #define PCI_FIX_ADDR(addr) (addr) static inline unsigned char __raw_readb(const volatile void __iomem *addr) -- cgit v1.2.3 From fe44f452db0b92b7a36a048e3c6731494712d4d9 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:28 +0000 Subject: arch/powerpc/lib/extable.c: sparse fix extable.c:66:9: warning: symbol 'ex_tab_message' was not declared. Should it be static? making it static can produce a new build warning on some boards: extable.c:66:12: warning: 'ex_tab_message' defined but not used [-Wunused-variable] but ex_tab_message doesn't do much even when used, so just remove it. Signed-off-by: Kim Phillips --- arch/powerpc/lib/extable.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/powerpc/lib/extable.c b/arch/powerpc/lib/extable.c index 7408d5c969..60983aea4c 100644 --- a/arch/powerpc/lib/extable.c +++ b/arch/powerpc/lib/extable.c @@ -63,8 +63,6 @@ search_one_table(const struct exception_table_entry *first, return 0; } -int ex_tab_message = 1; - unsigned long search_exception_table(unsigned long addr) { @@ -74,8 +72,7 @@ search_exception_table(unsigned long addr) ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); /* if the serial port does not hang in exception, printf can be used */ #if !defined(CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION) - if (ex_tab_message) - debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); + debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); #endif if (ret) return ret; -- cgit v1.2.3 From 20051f2ab2b3f8d75bac2ec9466c52b2c4351323 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:29 +0000 Subject: arch/powerpc/lib/board.c, *traps.c: sparse fixes traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be static? traps.c:93:1: warning: symbol '_exception' was not declared. Should it be static? board.c:166:6: warning: symbol '__board_add_ram_info' was not declared. Should it be static? board.c:174:5: warning: symbol '__board_flash_wp_on' was not declared. Should it be static? board.c:187:6: warning: symbol '__cpu_secondary_init_r' was not declared. Should it be static? board.c:265:12: warning: symbol 'init_sequence' was not declared. Should it be static? board.c:348:5: warning: symbol '__fixup_cpu' was not declared. Should it be static? board.c:405:53: warning: Using plain integer as NULL pointer Signed-off-by: Kim Phillips --- arch/powerpc/cpu/74xx_7xx/traps.c | 28 +++------ arch/powerpc/cpu/mpc512x/traps.c | 110 ++++++++++++++++------------------- arch/powerpc/cpu/mpc5xx/traps.c | 6 +- arch/powerpc/cpu/mpc5xxx/traps.c | 29 ++++------ arch/powerpc/cpu/mpc8220/traps.c | 119 ++++++++++++++++++-------------------- arch/powerpc/cpu/mpc824x/traps.c | 29 ++++------ arch/powerpc/cpu/mpc8260/traps.c | 29 ++++------ arch/powerpc/cpu/mpc83xx/traps.c | 29 ++++------ arch/powerpc/cpu/mpc85xx/traps.c | 36 ++++-------- arch/powerpc/cpu/mpc86xx/traps.c | 27 +++------ arch/powerpc/cpu/mpc8xx/traps.c | 29 ++++------ arch/powerpc/cpu/ppc4xx/traps.c | 26 +++------ arch/powerpc/lib/board.c | 12 ++-- 13 files changed, 206 insertions(+), 303 deletions(-) diff --git a/arch/powerpc/cpu/74xx_7xx/traps.c b/arch/powerpc/cpu/74xx_7xx/traps.c index 7ae81eb7f3..a33e28368e 100644 --- a/arch/powerpc/cpu/74xx_7xx/traps.c +++ b/arch/powerpc/cpu/74xx_7xx/traps.c @@ -48,8 +48,7 @@ extern unsigned long search_exception_table(unsigned long); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -69,8 +68,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void -show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -100,16 +98,14 @@ show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Exception in kernel pc %lx signal %d",regs->nip,signr); } -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; @@ -152,8 +148,7 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -164,8 +159,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; @@ -190,8 +184,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -SoftEmuException(struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -202,9 +195,7 @@ SoftEmuException(struct pt_regs *regs) panic("Software Emulation Exception"); } - -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -218,8 +209,7 @@ UnknownException(struct pt_regs *regs) /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { #if 0 int retval; diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c index 786f4a5a7e..15468e5824 100644 --- a/arch/powerpc/cpu/mpc512x/traps.c +++ b/arch/powerpc/cpu/mpc512x/traps.c @@ -47,68 +47,65 @@ extern ulong get_effective_memsize(void); * Trap & Exception support */ -void -print_backtrace (unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; - puts ("Call backtrace: "); + puts("Call backtrace: "); while (sp) { if ((uint)sp > END_OF_MEM) break; i = sp[1]; if (cnt++ % 7 == 0) - putc ('\n'); - printf ("%08lX ", i); + putc('\n'); + printf("%08lX ", i); if (cnt > 32) break; sp = (unsigned long *) *sp; } - putc ('\n'); + putc('\n'); } -void show_regs (struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; - printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, regs->msr & MSR_DR ? 1 : 0); - putc ('\n'); + putc('\n'); for (i = 0; i < 32; i++) { if ((i % 8) == 0) { - printf ("GPR%02d: ", i); + printf("GPR%02d: ", i); } - printf ("%08lX ", regs->gpr[i]); + printf("%08lX ", regs->gpr[i]); if ((i % 8) == 7) { - putc ('\n'); + putc('\n'); } } } -void -_exception (int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { - show_regs (regs); - print_backtrace ((unsigned long *)regs->gpr[1]); - panic ("Exception at pc %lx signal %d", regs->nip,signr); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception at pc %lx signal %d", regs->nip, signr); } -void -MachineCheckException (struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { - unsigned long fixup; + unsigned long fixup = search_exception_table(regs->nip); - if ((fixup = search_exception_table (regs->nip)) != 0) { + if (fixup) { regs->nip = fixup; return; } @@ -118,95 +115,90 @@ MachineCheckException (struct pt_regs *regs) return; #endif - puts ("Machine check.\nCaused by (from msr): "); - printf ("regs %p ",regs); + puts("Machine check.\nCaused by (from msr): "); + printf("regs %p ", regs); switch (regs->msr & 0x00FF0000) { case (0x80000000 >> 10): - puts ("Instruction cache parity signal\n"); + puts("Instruction cache parity signal\n"); break; case (0x80000000 >> 11): - puts ("Data cache parity signal\n"); + puts("Data cache parity signal\n"); break; case (0x80000000 >> 12): - puts ("Machine check signal\n"); + puts("Machine check signal\n"); break; case (0x80000000 >> 13): - puts ("Transfer error ack signal\n"); + puts("Transfer error ack signal\n"); break; case (0x80000000 >> 14): - puts ("Data parity signal\n"); + puts("Data parity signal\n"); break; case (0x80000000 >> 15): - puts ("Address parity signal\n"); + puts("Address parity signal\n"); break; default: - puts ("Unknown values in msr\n"); + puts("Unknown values in msr\n"); } - show_regs (regs); - print_backtrace ((unsigned long *)regs->gpr[1]); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); - panic ("machine check"); + panic("machine check"); } -void -AlignmentException (struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - show_regs (regs); - print_backtrace ((unsigned long *)regs->gpr[1]); - panic ("Alignment Exception"); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); } -void -ProgramCheckException (struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { #ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - show_regs (regs); - print_backtrace ((unsigned long *)regs->gpr[1]); - panic ("Program Check Exception"); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); } -void -SoftEmuException (struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - show_regs (regs); - print_backtrace ((unsigned long *)regs->gpr[1]); - panic ("Software Emulation Exception"); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Software Emulation Exception"); } -void -UnknownException (struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #ifdef CONFIG_CMD_KGDB if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", regs->nip, regs->msr, regs->trap); - _exception (0, regs); + _exception(0, regs); } #ifdef CONFIG_CMD_BEDBUG -extern void do_bedbug_breakpoint (struct pt_regs *); +extern void do_bedbug_breakpoint(struct pt_regs *); #endif -void -DebugException (struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { - printf ("Debugger trap at @ %lx\n", regs->nip ); - show_regs (regs); + printf("Debugger trap at @ %lx\n", regs->nip); + show_regs(regs); #ifdef CONFIG_CMD_BEDBUG - do_bedbug_breakpoint (regs); + do_bedbug_breakpoint(regs); #endif } diff --git a/arch/powerpc/cpu/mpc5xx/traps.c b/arch/powerpc/cpu/mpc5xx/traps.c index e3ce11b2b3..90da73bc73 100644 --- a/arch/powerpc/cpu/mpc5xx/traps.c +++ b/arch/powerpc/cpu/mpc5xx/traps.c @@ -52,7 +52,7 @@ extern unsigned long search_exception_table(unsigned long); /* * Print stack backtrace */ -void print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -75,7 +75,7 @@ void print_backtrace(unsigned long *sp) /* * Print current registers */ -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", @@ -105,7 +105,7 @@ void show_regs(struct pt_regs * regs) /* * General exception handler routine */ -void _exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); diff --git a/arch/powerpc/cpu/mpc5xxx/traps.c b/arch/powerpc/cpu/mpc5xxx/traps.c index 5972f34579..438f8d3203 100644 --- a/arch/powerpc/cpu/mpc5xxx/traps.c +++ b/arch/powerpc/cpu/mpc5xxx/traps.c @@ -49,8 +49,7 @@ extern unsigned long search_exception_table(unsigned long); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -70,7 +69,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -98,16 +97,14 @@ void show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Exception in kernel pc %lx signal %d",regs->nip,signr); } -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; @@ -152,8 +149,7 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -164,8 +160,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -176,8 +171,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -SoftEmuException(struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -189,8 +183,7 @@ SoftEmuException(struct pt_regs *regs) } -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -205,8 +198,7 @@ UnknownException(struct pt_regs *regs) extern void do_bedbug_breakpoint(struct pt_regs *); #endif -void -DebugException(struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); @@ -219,8 +211,7 @@ DebugException(struct pt_regs *regs) /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { #if 0 int retval; diff --git a/arch/powerpc/cpu/mpc8220/traps.c b/arch/powerpc/cpu/mpc8220/traps.c index 13894c9050..19d6cb57cf 100644 --- a/arch/powerpc/cpu/mpc8220/traps.c +++ b/arch/powerpc/cpu/mpc8220/traps.c @@ -39,7 +39,7 @@ #include /* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table (unsigned long); +extern unsigned long search_exception_table(unsigned long); /* THIS NEEDS CHANGING to use the board info structure. */ @@ -49,171 +49,166 @@ extern unsigned long search_exception_table (unsigned long); * Trap & Exception support */ -void print_backtrace (unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; - printf ("Call backtrace: "); + printf("Call backtrace: "); while (sp) { if ((uint) sp > END_OF_MEM) break; i = sp[1]; if (cnt++ % 7 == 0) - printf ("\n"); - printf ("%08lX ", i); + printf("\n"); + printf("%08lX ", i); if (cnt > 32) break; sp = (unsigned long *) *sp; } - printf ("\n"); + printf("\n"); } -void show_regs (struct pt_regs *regs) +void show_regs(struct pt_regs *regs) { int i; - printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); - printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, regs->msr & MSR_DR ? 1 : 0); - printf ("\n"); + printf("\n"); for (i = 0; i < 32; i++) { if ((i % 8) == 0) { - printf ("GPR%02d: ", i); + printf("GPR%02d: ", i); } - printf ("%08lX ", regs->gpr[i]); + printf("%08lX ", regs->gpr[i]); if ((i % 8) == 7) { - printf ("\n"); + printf("\n"); } } } -void _exception (int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Exception in kernel pc %lx signal %d", regs->nip, signr); + show_regs(regs); + print_backtrace((unsigned long *) regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d", regs->nip, signr); } -void MachineCheckException (struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { - unsigned long fixup; + unsigned long fixup = search_exception_table(regs->nip); /* Probing PCI using config cycles cause this exception * when a device is not present. Catch it and return to * the PCI exception handler. */ - if ((fixup = search_exception_table (regs->nip)) != 0) { + if (fixup) { regs->nip = fixup; return; } #if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - printf ("Machine check in kernel mode.\n"); - printf ("Caused by (from msr): "); - printf ("regs %p ", regs); + printf("Machine check in kernel mode.\n"); + printf("Caused by (from msr): "); + printf("regs %p ", regs); /* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */ switch (regs->msr & 0x000F0000) { case (0x80000000 >> 12): - printf ("Machine check signal - probably due to mm fault\n" + printf("Machine check signal - probably due to mm fault\n" "with mmu off\n"); break; case (0x80000000 >> 13): - printf ("Transfer error ack signal\n"); + printf("Transfer error ack signal\n"); break; case (0x80000000 >> 14): - printf ("Data parity signal\n"); + printf("Data parity signal\n"); break; case (0x80000000 >> 15): - printf ("Address parity signal\n"); + printf("Address parity signal\n"); break; default: - printf ("Unknown values in msr\n"); + printf("Unknown values in msr\n"); } - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("machine check"); + show_regs(regs); + print_backtrace((unsigned long *) regs->gpr[1]); + panic("machine check"); } -void AlignmentException (struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Alignment Exception"); + show_regs(regs); + print_backtrace((unsigned long *) regs->gpr[1]); + panic("Alignment Exception"); } -void ProgramCheckException (struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Program Check Exception"); + show_regs(regs); + print_backtrace((unsigned long *) regs->gpr[1]); + panic("Program Check Exception"); } -void SoftEmuException (struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - show_regs (regs); - print_backtrace ((unsigned long *) regs->gpr[1]); - panic ("Software Emulation Exception"); + show_regs(regs); + print_backtrace((unsigned long *) regs->gpr[1]); + panic("Software Emulation Exception"); } -void UnknownException (struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler - && (*debugger_exception_handler) (regs)) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", regs->nip, regs->msr, regs->trap); - _exception (0, regs); + _exception(0, regs); } #if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint (struct pt_regs *); +extern void do_bedbug_breakpoint(struct pt_regs *); #endif -void DebugException (struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { - printf ("Debugger trap at @ %lx\n", regs->nip); - show_regs (regs); + printf("Debugger trap at @ %lx\n", regs->nip); + show_regs(regs); #if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint (regs); + do_bedbug_breakpoint(regs); #endif } /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int addr_probe (uint * addr) +int addr_probe(uint *addr) { #if 0 int retval; diff --git a/arch/powerpc/cpu/mpc824x/traps.c b/arch/powerpc/cpu/mpc824x/traps.c index 163b983340..9bcdd8f4ea 100644 --- a/arch/powerpc/cpu/mpc824x/traps.c +++ b/arch/powerpc/cpu/mpc824x/traps.c @@ -46,8 +46,7 @@ extern unsigned long search_exception_table(unsigned long); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -67,7 +66,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -95,16 +94,14 @@ void show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Exception in kernel pc %lx signal %d",regs->nip,signr); } -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; @@ -142,24 +139,21 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Program Check Exception"); } -void -SoftEmuException(struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); @@ -167,8 +161,7 @@ SoftEmuException(struct pt_regs *regs) } -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", regs->nip, regs->msr, regs->trap); @@ -179,8 +172,7 @@ UnknownException(struct pt_regs *regs) extern void do_bedbug_breakpoint(struct pt_regs *); #endif -void -DebugException(struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); @@ -193,8 +185,7 @@ DebugException(struct pt_regs *regs) /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { #if 0 int retval; diff --git a/arch/powerpc/cpu/mpc8260/traps.c b/arch/powerpc/cpu/mpc8260/traps.c index c116cdf69d..e1e68458e8 100644 --- a/arch/powerpc/cpu/mpc8260/traps.c +++ b/arch/powerpc/cpu/mpc8260/traps.c @@ -49,8 +49,7 @@ extern unsigned long search_exception_table(unsigned long); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -70,7 +69,7 @@ print_backtrace(unsigned long *sp) putc ('\n'); } -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -96,8 +95,7 @@ void show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); @@ -122,8 +120,7 @@ void dump_pci (void) } #endif -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; @@ -180,8 +177,7 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -192,8 +188,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -204,8 +199,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -SoftEmuException(struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -217,8 +211,7 @@ SoftEmuException(struct pt_regs *regs) } -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -233,8 +226,7 @@ UnknownException(struct pt_regs *regs) extern void do_bedbug_breakpoint(struct pt_regs *); #endif -void -DebugException(struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); @@ -247,8 +239,7 @@ DebugException(struct pt_regs *regs) /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { #if 0 int retval; diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index 9d71b8b730..53a1062ea8 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -42,8 +42,7 @@ extern unsigned long search_exception_table(unsigned long); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -63,7 +62,7 @@ print_backtrace(unsigned long *sp) putc ('\n'); } -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -89,8 +88,7 @@ void show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); @@ -114,8 +112,7 @@ void dump_pci (void) } #endif -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; @@ -174,8 +171,7 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -186,8 +182,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -198,8 +193,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -SoftEmuException(struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -211,8 +205,7 @@ SoftEmuException(struct pt_regs *regs) } -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -227,8 +220,7 @@ UnknownException(struct pt_regs *regs) extern void do_bedbug_breakpoint(struct pt_regs *); #endif -void -DebugException(struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); @@ -240,8 +232,7 @@ DebugException(struct pt_regs *regs) /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { #if 0 int retval; diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 78007177a1..476ae93594 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -82,8 +82,7 @@ extern void do_bedbug_breakpoint(struct pt_regs *); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -103,7 +102,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -131,24 +130,21 @@ void show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Exception in kernel pc %lx signal %d",regs->nip,signr); } -void -CritcalInputException(struct pt_regs *regs) +void CritcalInputException(struct pt_regs *regs) { panic("Critical Input Exception"); } int machinecheck_count = 0; int machinecheck_error = 0; -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; unsigned int mcsr, mcsrr0, mcsrr1, mcar; @@ -220,8 +216,7 @@ MachineCheckException(struct pt_regs *regs) } } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -233,8 +228,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { long esr_val; @@ -257,8 +251,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -PITException(struct pt_regs *regs) +void PITException(struct pt_regs *regs) { /* * Reset PIT interrupt @@ -271,9 +264,7 @@ PITException(struct pt_regs *regs) timer_interrupt(NULL); } - -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -285,8 +276,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -void -ExtIntException(struct pt_regs *regs) +void ExtIntException(struct pt_regs *regs) { volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); @@ -305,8 +295,7 @@ ExtIntException(struct pt_regs *regs) print_backtrace((unsigned long *)regs->gpr[1]); } -void -DebugException(struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); @@ -318,8 +307,7 @@ DebugException(struct pt_regs *regs) /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { return 0; } diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c index 406403e512..50069d55f5 100644 --- a/arch/powerpc/cpu/mpc86xx/traps.c +++ b/arch/powerpc/cpu/mpc86xx/traps.c @@ -52,8 +52,7 @@ extern ulong get_effective_memsize(void); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -74,8 +73,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void -show_regs(struct pt_regs *regs) +void show_regs(struct pt_regs *regs) { int i; @@ -103,16 +101,14 @@ show_regs(struct pt_regs *regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Exception in kernel pc %lx signal %d", regs->nip, signr); } -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; @@ -158,8 +154,7 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) @@ -170,8 +165,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; @@ -196,8 +190,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -SoftEmuException(struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) @@ -208,8 +201,7 @@ SoftEmuException(struct pt_regs *regs) panic("Software Emulation Exception"); } -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) @@ -226,8 +218,7 @@ UnknownException(struct pt_regs *regs) * If not present, return -1, * otherwise return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { return 0; } diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c index 343dced31f..f0ab78daf9 100644 --- a/arch/powerpc/cpu/mpc8xx/traps.c +++ b/arch/powerpc/cpu/mpc8xx/traps.c @@ -52,8 +52,7 @@ extern unsigned long search_exception_table(unsigned long); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -73,7 +72,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -101,16 +100,14 @@ void show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Exception in kernel pc %lx signal %d",regs->nip,signr); } -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; @@ -153,8 +150,7 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -165,8 +161,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -177,8 +172,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -SoftEmuException(struct pt_regs *regs) +void SoftEmuException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -190,8 +184,7 @@ SoftEmuException(struct pt_regs *regs) } -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -202,8 +195,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -void -DebugException(struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); @@ -215,8 +207,7 @@ DebugException(struct pt_regs *regs) /* Probe an address by reading. If not present, return -1, otherwise * return 0. */ -int -addr_probe(uint *addr) +int addr_probe(uint *addr) { #if 0 int retval; diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c index 9baa7a16d1..dae19cba58 100644 --- a/arch/powerpc/cpu/ppc4xx/traps.c +++ b/arch/powerpc/cpu/ppc4xx/traps.c @@ -74,8 +74,7 @@ extern void do_bedbug_breakpoint(struct pt_regs *); * Trap & Exception support */ -void -print_backtrace(unsigned long *sp) +static void print_backtrace(unsigned long *sp) { int cnt = 0; unsigned long i; @@ -95,7 +94,7 @@ print_backtrace(unsigned long *sp) printf("\n"); } -void show_regs(struct pt_regs * regs) +void show_regs(struct pt_regs *regs) { int i; @@ -121,16 +120,14 @@ void show_regs(struct pt_regs * regs) } -void -_exception(int signr, struct pt_regs *regs) +static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("Exception"); } -void -MachineCheckException(struct pt_regs *regs) +void MachineCheckException(struct pt_regs *regs) { unsigned long fixup, val; #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -312,8 +309,7 @@ MachineCheckException(struct pt_regs *regs) panic("machine check"); } -void -AlignmentException(struct pt_regs *regs) +void AlignmentException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -325,8 +321,7 @@ AlignmentException(struct pt_regs *regs) panic("Alignment Exception"); } -void -ProgramCheckException(struct pt_regs *regs) +void ProgramCheckException(struct pt_regs *regs) { long esr_val; @@ -349,8 +344,7 @@ ProgramCheckException(struct pt_regs *regs) panic("Program Check Exception"); } -void -DecrementerPITException(struct pt_regs *regs) +void DecrementerPITException(struct pt_regs *regs) { /* * Reset PIT interrupt @@ -364,8 +358,7 @@ DecrementerPITException(struct pt_regs *regs) } -void -UnknownException(struct pt_regs *regs) +void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) @@ -377,8 +370,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -void -DebugException(struct pt_regs *regs) +void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index ebf400851a..1b051e11c4 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -163,7 +163,7 @@ static int init_baudrate(void) /***********************************************************************/ -void __board_add_ram_info(int use_default) +static void __board_add_ram_info(int use_default) { /* please define platform specific board_add_ram_info() */ } @@ -171,7 +171,7 @@ void __board_add_ram_info(int use_default) void board_add_ram_info(int) __attribute__ ((weak, alias("__board_add_ram_info"))); -int __board_flash_wp_on(void) +static int __board_flash_wp_on(void) { /* * Most flashes can't be detected when write protection is enabled, @@ -184,7 +184,7 @@ int __board_flash_wp_on(void) int board_flash_wp_on(void) __attribute__ ((weak, alias("__board_flash_wp_on"))); -void __cpu_secondary_init_r(void) +static void __cpu_secondary_init_r(void) { } @@ -262,7 +262,7 @@ static int init_func_watchdog_reset(void) * Initialization sequence */ -init_fnc_t *init_sequence[] = { +static init_fnc_t *init_sequence[] = { #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) probecpu, #endif @@ -345,7 +345,7 @@ ulong get_effective_memsize(void) #endif } -int __fixup_cpu(void) +static int __fixup_cpu(void) { return 0; } @@ -402,7 +402,7 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_POST post_bootmode_init(); - post_run(NULL, POST_ROM | post_bootmode_get(0)); + post_run(NULL, POST_ROM | post_bootmode_get(NULL)); #endif WATCHDOG_RESET(); -- cgit v1.2.3 From 2f220500a460ca197ec06aa280519509252ea1d8 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:30 +0000 Subject: include/image.h: sparse fixes include/image.h:378:1: warning: cast to restricted __be32 include/image.h:381:1: warning: cast to restricted __be32 include/image.h:382:1: warning: cast to restricted __be32 include/image.h:383:1: warning: cast to restricted __be32 fix by annotating image header integers big endian. Signed-off-by: Kim Phillips --- include/image.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/include/image.h b/include/image.h index 4e5863ff7f..0a895f2044 100644 --- a/include/image.h +++ b/include/image.h @@ -34,6 +34,7 @@ #define __IMAGE_H__ #include "compiler.h" +#include #ifdef USE_HOSTCC @@ -183,13 +184,13 @@ * all data in network byte order (aka natural aka bigendian). */ typedef struct image_header { - uint32_t ih_magic; /* Image Header Magic Number */ - uint32_t ih_hcrc; /* Image Header CRC Checksum */ - uint32_t ih_time; /* Image Creation Timestamp */ - uint32_t ih_size; /* Image Data Size */ - uint32_t ih_load; /* Data Load Address */ - uint32_t ih_ep; /* Entry Point Address */ - uint32_t ih_dcrc; /* Image Data CRC Checksum */ + __be32 ih_magic; /* Image Header Magic Number */ + __be32 ih_hcrc; /* Image Header CRC Checksum */ + __be32 ih_time; /* Image Creation Timestamp */ + __be32 ih_size; /* Image Data Size */ + __be32 ih_load; /* Data Load Address */ + __be32 ih_ep; /* Entry Point Address */ + __be32 ih_dcrc; /* Image Data CRC Checksum */ uint8_t ih_os; /* Operating System */ uint8_t ih_arch; /* CPU architecture */ uint8_t ih_type; /* Image Type */ -- cgit v1.2.3 From 088f1b199112c7ec1bb8f94547f6a21107623f1d Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:31 +0000 Subject: common/cmd_*.c: sparse fixes cmd_boot.c:40:5: warning: symbol 'do_go' was not declared. Should it be static? cmd_bootm.c:164:6: warning: symbol '__arch_preboot_os' was not declared. Should it be static? cmd_bootm.c:477:5: warning: symbol 'do_bootm_subcommand' was not declared. Should it be static? cmd_bootm.c:1022:1: error: directive in argument list cmd_bootm.c:1028:1: error: directive in argument list cmd_bootm.c:1029:1: error: directive in argument list cmd_bootm.c:1036:1: error: directive in argument list cmd_bootm.c:1042:1: error: directive in argument list cmd_bootm.c:1044:1: error: directive in argument list cmd_bootm.c:1045:1: error: directive in argument list cmd_bootm.c:1047:1: error: directive in argument list cmd_bootm.c:1089:5: warning: symbol 'do_iminfo' was not declared. Should it be static? cmd_bootm.c:1176:5: warning: symbol 'do_imls' was not declared. Should it be static? cmd_bootm.c:1654:1: error: directive in argument list cmd_bootm.c:1660:1: error: directive in argument list cmd_console.c:32:5: warning: symbol 'do_coninfo' was not declared. Should it be s cmd_date.c:46:5: warning: symbol 'do_date' was not declared. Should it be static? cmd_echo.c:27:5: warning: symbol 'do_echo' was not declared. Should it be static? cmd_exit.c:27:5: warning: symbol 'do_exit' was not declared. Should it be static? cmd_fat.c:97:5: warning: symbol 'do_fat_ls' was not declared. Should it be static? cmd_fat.c:136:5: warning: symbol 'do_fat_fsinfo' was not declared. Should it be s cmd_fdt.c:66:5: warning: symbol 'do_fdt' was not declared. Should it be static? cmd_fdt.c:542:43: warning: incorrect type in assignment (different base types) cmd_fdt.c:542:43: expected unsigned int [unsigned] [usertype] cmd_fdt.c:542:43: got restricted __be32 [usertype] cmd_fdt.c:679:42: warning: cast to restricted __be32 cmd_fdt.c:820:1: error: directive in argument list cmd_fdt.c:822:1: error: directive in argument list cmd_flash.c:292:5: warning: symbol 'do_flinfo' was not declared. Should it be static? cmd_flash.c:324:5: warning: symbol 'do_flerase' was not declared. Should it be static? cmd_flash.c:457:5: warning: symbol 'do_protect' was not declared. Should it be st cmd_help.c:27:5: warning: symbol 'do_help' was not declared. Should it be static? cmd_i2c.c:136:6: warning: symbol '__def_i2c_init_board' was not declared. Should it be static? cmd_i2c.c:144:14: warning: symbol '__def_i2c_get_bus_speed' was not declared. Should it be static? cmd_i2c.c:151:5: warning: symbol '__def_i2c_set_bus_speed' was not declared. Should it be static? cmd_i2c.c:1322:1: error: directive in argument list cmd_i2c.c:1324:1: error: directive in argument list cmd_i2c.c:1326:1: error: directive in argument list cmd_i2c.c:1328:1: error: directive in argument list cmd_i2c.c:1337:1: error: directive in argument list cmd_i2c.c:1339:1: error: directive in argument list cmd_irq.c:27:5: warning: symbol 'do_interrupts' was not declared. Should it be static? cmd_itest.c:133:5: warning: symbol 'binary_test' was not declared. Should it be static? cmd_itest.c:158:5: warning: symbol 'do_itest' was not declared. Should it be stat cmd_load.c:54:5: warning: symbol 'do_load_serial' was not declared. Should it be static? cmd_load.c:431:6: warning: symbol 'his_eol' was not declared. Should it be static? cmd_load.c:432:6: warning: symbol 'his_pad_count' was not declared. Should it be static? cmd_load.c:433:6: warning: symbol 'his_pad_char' was not declared. Should it be static? cmd_load.c:434:6: warning: symbol 'his_quote' was not declared. Should it be static? cmd_load.c:436:5: warning: symbol 'do_load_serial_bin' was not declared. Should it be static? cmd_load.c:549:6: warning: symbol 'send_pad' was not declared. Should it be static? cmd_load.c:558:6: warning: symbol 'ktrans' was not declared. Should it be static? cmd_load.c:568:5: warning: symbol 'chk1' was not declared. Should it be static? cmd_load.c:578:6: warning: symbol 's1_sendpacket' was not declared. Should it be static? cmd_load.c:587:6: warning: symbol 'send_ack' was not declared. Should it be static? cmd_load.c:600:6: warning: symbol 'send_nack' was not declared. Should it be static? cmd_load.c:614:6: warning: symbol 'os_data_init' was not declared. Should it be static? cmd_load.c:615:6: warning: symbol 'os_data_char' was not declared. Should it be static? cmd_load.c:657:6: warning: symbol 'k_data_init' was not declared. Should it be static? cmd_load.c:663:6: warning: symbol 'k_data_save' was not declared. Should it be static? cmd_load.c:669:6: warning: symbol 'k_data_restore' was not declared. Should it be static? cmd_load.c:675:6: warning: symbol 'k_data_char' was not declared. Should it be static? cmd_load.c:693:6: warning: symbol 'send_parms' was not declared. Should it be static? cmd_load.c:694:6: warning: symbol 'send_ptr' was not declared. Should it be static? cmd_load.c:698:6: warning: symbol 'handle_send_packet' was not declared. Should i cmd_mdio.c:60:5: warning: symbol 'mdio_write_ranges' was not declared. Should it be static? cmd_mdio.c:82:5: warning: symbol 'mdio_read_ranges' was not declared. Should it be static? cmd_mdio.c:115:5: warning: symbol 'extract_reg_range' was not declared. Should it be static? cmd_mdio.c:144:5: warning: symbol 'extract_phy_range' was not declared. Should it cmd_mem.c:54:5: warning: symbol 'do_mem_md' was not declared. Should it be static? cmd_mem.c:150:5: warning: symbol 'do_mem_mm' was not declared. Should it be static? cmd_mem.c:154:5: warning: symbol 'do_mem_nm' was not declared. Should it be static? cmd_mem.c:159:5: warning: symbol 'do_mem_mw' was not declared. Should it be static? cmd_mem.c:256:5: warning: symbol 'do_mem_cmp' was not declared. Should it be static? cmd_mem.c:326:5: warning: symbol 'do_mem_cp' was not declared. Should it be static? cmd_mem.c:436:5: warning: symbol 'do_mem_base' was not declared. Should it be static? cmd_mem.c:449:5: warning: symbol 'do_mem_loop' was not declared. Should it be static? cmd_mem.c:595:5: warning: symbol 'do_mem_mtest' was not declared. Should it be static? cmd_mem.c:618:26: warning: Using plain integer as NULL pointer cmd_mem.c:1057:5: warning: symbol 'do_mem_crc' was not declared. Should it be static? cmd_misc.c:30:5: warning: symbol 'do_sleep' was not declared. Should it be static cmd_mmc.c:118:5: warning: symbol 'do_mmcinfo' was not declared. Should it be static? cmd_mmc.c:272:32: warning: Using plain integer as NULL pointer cmd_mmc.c:150:5: warning: symbol 'do_mmcops' was not declared. Should it be stati cmd_mp.c:27:1: warning: symbol 'cpu_cmd' was not declared. Should it be static? cmd_mp.c:85:1: error: directive in argument list cmd_mp.c:88:1: error: directive in argument list cmd_mtdparts.c:150:18: warning: symbol 'mtdids' was not declared. Should it be static? cmd_mtdparts.c:153:18: warning: symbol 'devices' was not declared. Should it be static? cmd_mtdparts.c:713:5: warning: symbol 'mtd_device_validate' was not declared. Should it be static? cmd_mtdparts.c:1887:5: warning: symbol 'do_chpart' was not declared. Should it be static? cmd_mtdparts.c:1925:5: warning: symbol 'do_mtdparts' was not declared. Should it be static? cmd_mtdparts.c:2060:1: error: directive in argument list cmd_mtdparts.c:2063:1: error: directive in argument list cmd_mtdparts.c:2066:1: error: directive in argument list cmd_mtdparts.c:2071:1: error: directive in argument list cmd_mtdparts.c:2073:1: error: directive in argument list cmd_nand.c:377:18: error: bad constant expression cmd_nand.c:431:5: warning: symbol 'do_nand' was not declared. Should it be static? cmd_nand.c:796:1: error: directive in argument list cmd_nand.c:801:1: error: directive in argument list cmd_nand.c:802:1: error: directive in argument list cmd_nand.c:806:1: error: directive in argument list cmd_nand.c:819:1: error: directive in argument list cmd_nand.c:824:1: error: directive in argument list cmd_nand.c:825:1: error: directive in argument list cmd_nand.c:831:1: error: directive in argument list cmd_nand.c:918:5: warning: symbol 'do_nandboot' was not declared. Should it be static? cmd_net.c:33:5: warning: symbol 'do_bootp' was not declared. Should it be static? cmd_net.c:107:5: warning: symbol 'do_dhcp' was not declared. Should it be static? cmd_net.c:120:5: warning: symbol 'do_nfs' was not declared. Should it be static? cmd_nvedit.c:138:5: warning: symbol 'do_env_print' was not declared. Should it be static? cmd_nvedit.c:323:5: warning: symbol '_do_env_set' was not declared. Should it be static? cmd_nvedit.c:435:5: warning: symbol 'do_env_set' was not declared. Should it be static? cmd_nvedit.c:514:5: warning: symbol 'do_env_edit' was not declared. Should it be static? cmd_nvedit.c:620:5: warning: symbol 'do_env_save' was not declared. Should it be static? cmd_nvedit.c:1016:1: error: directive in argument list cmd_nvedit.c:1018:1: error: directive in argument list cmd_nvedit.c:1021:1: error: directive in argument list cmd_nvedit.c:1023:1: error: directive in argument list cmd_nvedit.c:1024:1: error: directive in argument list cmd_nvedit.c:1026:1: error: directive in argument list cmd_nvedit.c:1027:1: error: directive in argument list cmd_nvedit.c:1029:1: error: directive in argument list cmd_nvedit.c:1030:1: error: directive in argument list cmd_nvedit.c:1032:1: error: directive in argument list cmd_nvedit.c:1034:1: error: directive in argument list cmd_nvedit.c:1036:1: error: directive in argument list cmd_nvedit.c:1037:1: error: directive in argument list cmd_nvedit.c:1039:1: error: directive in argument list cmd_pci.c:38:17: warning: symbol 'ShortPCIListing' was not declared. Should it be static? cmd_pci.c:38:22: warning: 'ShortPCIListing' defined but not used [-Wunused-variable] cmd_pci.c:411:5: warning: symbol 'do_pci' was not declared. Should it be static? cmd_pci.c:494:1: error: directive in argument list cmd_pci.c:497:1: error: directive in argument list cmd_reginfo.c:40:5: warning: symbol 'do_reginfo' was not declared. Should it be static? cmd_sata.c:31:5: warning: symbol 'sata_curr_device' was not declared. Should it be static? note -> ata_piix.c doesn't seem to use 'sata_curr_device'; deleted. cmd_sata.c:32:18: warning: symbol 'sata_dev_desc' was not declared. Should it be static? cmd_sata.c:70:5: warning: symbol 'do_sata' was not declared. Should it be static? cmd_setexpr.c:53:5: warning: symbol 'do_setexpr' was not declared. Should it be static? cmd_source.c:186:1: error: directive in argument list cmd_source.c:190:1: error: directive in argument list cmd_test.c:27:5: warning: symbol 'do_test' was not declared. Should it be static? cmd_test.c:153:5: warning: symbol 'do_false' was not declared. Should it be static? cmd_test.c:164:5: warning: symbol 'do_true' was not declared. Should it be static cmd_usb.c:43:6: warning: symbol 'usb_get_class_desc' was not declared. Should it be static? cmd_usb.c:69:6: warning: symbol 'usb_display_class_sub' was not declared. Should it be static? cmd_usb.c:151:6: warning: symbol 'usb_display_string' was not declared. Should it be static? cmd_usb.c:161:6: warning: symbol 'usb_display_desc' was not declared. Should it be static? cmd_usb.c:195:6: warning: symbol 'usb_display_conf_desc' was not declared. Should it be static? cmd_usb.c:210:6: warning: symbol 'usb_display_if_desc' was not declared. Should it be static? cmd_usb.c:227:6: warning: symbol 'usb_display_ep_desc' was not declared. Should it be static? cmd_usb.c:252:6: warning: symbol 'usb_display_config' was not declared. Should it be static? cmd_usb.c:283:6: warning: symbol 'usb_show_tree_graph' was not declared. Should it be static? cmd_usb.c:343:6: warning: symbol 'usb_show_tree' was not declared. Should it be static? cmd_usb.c:356:5: warning: symbol 'do_usbboot' was not declared. Should it be static? cmd_usb.c:366:5: warning: symbol 'do_usb' was not declared. Should it be static? cmd_version.c:31:5: warning: symbol 'do_version' was not declared. Should it be s cmd_ximg.c:46:1: warning: symbol 'do_imgextract' was not declared. Should it be static? cmd_ximg.c:272:1: error: directive in argument list cmd_ximg.c:276:1: error: directive in argument list Signed-off-by: Kim Phillips --- common/cmd_boot.c | 5 +- common/cmd_bootm.c | 31 ++++-- common/cmd_console.c | 2 +- common/cmd_date.c | 2 +- common/cmd_echo.c | 2 +- common/cmd_exit.c | 2 +- common/cmd_fat.c | 5 +- common/cmd_fdt.c | 21 ++-- common/cmd_flash.c | 6 +- common/cmd_help.c | 2 +- common/cmd_i2c.c | 20 ++-- common/cmd_irq.c | 3 +- common/cmd_itest.c | 4 +- common/cmd_load.c | 303 +++++++++++++++++++++++++------------------------- common/cmd_mdio.c | 20 ++-- common/cmd_mem.c | 25 +++-- common/cmd_misc.c | 6 +- common/cmd_mmc.c | 6 +- common/cmd_mp.c | 22 ++-- common/cmd_mtdparts.c | 26 +++-- common/cmd_nand.c | 19 ++-- common/cmd_net.c | 76 +++++++------ common/cmd_nvedit.c | 25 +++-- common/cmd_pci.c | 17 +-- common/cmd_reginfo.c | 3 +- common/cmd_sata.c | 4 +- common/cmd_setexpr.c | 2 +- common/cmd_source.c | 11 +- common/cmd_test.c | 6 +- common/cmd_usb.c | 30 ++--- common/cmd_version.c | 2 +- common/cmd_ximg.c | 13 ++- 32 files changed, 387 insertions(+), 334 deletions(-) diff --git a/common/cmd_boot.c b/common/cmd_boot.c index a799b338a4..d3836fdfd8 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -32,12 +32,13 @@ /* Allow ports to override the default behavior */ __attribute__((weak)) -unsigned long do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[]) +unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, + char * const argv[]) { return entry (argc, argv); } -int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_go(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr, rc; int rcode = 0; diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 83fa5d7bd8..d256ddfaa6 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -161,7 +161,7 @@ static boot_os_fn *boot_os[] = { bootm_headers_t images; /* pointers to os/initrd/fdt images */ /* Allow for arch specific config before we boot */ -void __arch_preboot_os(void) +static void __arch_preboot_os(void) { /* please define platform specific arch_preboot_os() */ } @@ -474,7 +474,7 @@ static cmd_tbl_t cmd_bootm_sub[] = { U_BOOT_CMD_MKENT(go, 0, 1, (void *)BOOTM_STATE_OS_GO, "", ""), }; -int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc, +static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int ret = 0; @@ -1013,9 +1013,8 @@ static void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, return (void *)img_addr; } -U_BOOT_CMD( - bootm, CONFIG_SYS_MAXARGS, 1, do_bootm, - "boot application image from memory", +#ifdef CONFIG_SYS_LONGHELP +static char bootm_help_text[] = "[addr [arg ...]]\n - boot application image stored in memory\n" "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n" "\t'arg' can be the address of an initrd image\n" @@ -1048,7 +1047,12 @@ U_BOOT_CMD( "\tcmdline - OS specific command line processing/setup\n" "\tbdt - OS specific bd_t processing\n" "\tprep - OS specific prep before relocation or go\n" - "\tgo - start OS" + "\tgo - start OS"; +#endif + +U_BOOT_CMD( + bootm, CONFIG_SYS_MAXARGS, 1, do_bootm, + "boot application image from memory", bootm_help_text ); /*******************************************************************/ @@ -1084,7 +1088,7 @@ U_BOOT_CMD( /* iminfo - print header info for a requested image */ /*******************************************************************/ #if defined(CONFIG_CMD_IMI) -int do_iminfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_iminfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int arg; ulong addr; @@ -1171,7 +1175,7 @@ U_BOOT_CMD( /* imls - list all images found in flash */ /*******************************************************************/ #if defined(CONFIG_CMD_IMLS) -int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { flash_info_t *info; int i, j; @@ -1643,9 +1647,8 @@ static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } -U_BOOT_CMD( - bootz, CONFIG_SYS_MAXARGS, 1, do_bootz, - "boot Linux zImage image from memory", +#ifdef CONFIG_SYS_LONGHELP +static char bootz_help_text[] = "[addr [initrd[:size]] [fdt]]\n" " - boot Linux zImage stored in memory\n" "\tThe argument 'initrd' is optional and specifies the address\n" @@ -1658,5 +1661,11 @@ U_BOOT_CMD( "\tuse a '-' for the second argument. If you do not pass a third\n" "\ta bd_info struct will be passed instead\n" #endif + ""; +#endif + +U_BOOT_CMD( + bootz, CONFIG_SYS_MAXARGS, 1, do_bootz, + "boot Linux zImage image from memory", bootz_help_text ); #endif /* CONFIG_CMD_BOOTZ */ diff --git a/common/cmd_console.c b/common/cmd_console.c index d8cad6b917..e8d9f11bde 100644 --- a/common/cmd_console.c +++ b/common/cmd_console.c @@ -29,7 +29,7 @@ #include extern void _do_coninfo (void); -int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char * const argv[]) +static int do_coninfo(cmd_tbl_t *cmd, int flag, int argc, char * const argv[]) { int l; struct list_head *list = stdio_get_list(); diff --git a/common/cmd_date.c b/common/cmd_date.c index 335bc05f2a..0ac032cf30 100644 --- a/common/cmd_date.c +++ b/common/cmd_date.c @@ -43,7 +43,7 @@ static const char * const weekdays[] = { int mk_date (const char *, struct rtc_time *); -int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_date(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct rtc_time tm; int rcode = 0; diff --git a/common/cmd_echo.c b/common/cmd_echo.c index 1e499fb0db..52123fee2a 100644 --- a/common/cmd_echo.c +++ b/common/cmd_echo.c @@ -24,7 +24,7 @@ #include #include -int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; int putnl = 1; diff --git a/common/cmd_exit.c b/common/cmd_exit.c index f3fc8f5e79..0f2ee4046f 100644 --- a/common/cmd_exit.c +++ b/common/cmd_exit.c @@ -24,7 +24,7 @@ #include #include -int do_exit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_exit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int r; diff --git a/common/cmd_fat.c b/common/cmd_fat.c index 2e2301e581..86be044725 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -52,7 +52,7 @@ U_BOOT_CMD( " All numeric parameters are assumed to be hex." ); -int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_fat_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return do_ls(cmdtp, flag, argc, argv, FS_TYPE_FAT); } @@ -64,7 +64,8 @@ U_BOOT_CMD( " - list files from 'dev' on 'interface' in a 'directory'" ); -int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_fat_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { int dev, part; block_dev_desc_t *dev_desc; diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index f9acfc19ce..9e2de34737 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -95,7 +95,7 @@ static int fdt_value_setenv(const void *nodep, int len, const char *var) /* * Flattened Device Tree command, see the help for parameter definitions. */ -int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc < 2) return CMD_RET_USAGE; @@ -682,7 +682,7 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len) cp = newp; tmp = simple_strtoul(cp, &newp, 0); - *(uint32_t *)data = __cpu_to_be32(tmp); + *(__be32 *)data = __cpu_to_be32(tmp); data += 4; *len += 4; @@ -818,7 +818,7 @@ static void print_data(const void *data, int len) if (len > CONFIG_CMD_FDT_MAX_DUMP) printf("* 0x%p [0x%08x]", data, len); else { - const u32 *p; + const __be32 *p; printf("<"); for (j = 0, p = data; j < len/4; j++) @@ -964,11 +964,9 @@ static int fdt_print(const char *pathp, char *prop, int depth) } /********************************************************************/ - -U_BOOT_CMD( - fdt, 255, 0, do_fdt, - "flattened device tree utility commands", - "addr [] - Set the fdt location to \n" +#ifdef CONFIG_SYS_LONGHELP +static char fdt_help_text[] = + "addr [] - Set the fdt location to \n" #ifdef CONFIG_OF_BOARD_SETUP "fdt boardsetup - Do board-specific set up\n" #endif @@ -992,5 +990,10 @@ U_BOOT_CMD( "fdt chosen [ ] - Add/update the /chosen branch in the tree\n" " / - initrd start/end addr\n" "NOTE: Dereference aliases by omiting the leading '/', " - "e.g. fdt print ethernet0." + "e.g. fdt print ethernet0."; +#endif + +U_BOOT_CMD( + fdt, 255, 0, do_fdt, + "flattened device tree utility commands", fdt_help_text ); diff --git a/common/cmd_flash.c b/common/cmd_flash.c index e55d366c65..687eb68db1 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -289,7 +289,7 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last, } #endif /* CONFIG_SYS_NO_FLASH */ -int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_flinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifndef CONFIG_SYS_NO_FLASH ulong bank; @@ -321,7 +321,7 @@ int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_flerase(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifndef CONFIG_SYS_NO_FLASH flash_info_t *info = NULL; @@ -454,7 +454,7 @@ int flash_sect_erase (ulong addr_first, ulong addr_last) } #endif /* CONFIG_SYS_NO_FLASH */ -int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_protect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rcode = 0; #ifndef CONFIG_SYS_NO_FLASH diff --git a/common/cmd_help.c b/common/cmd_help.c index 3178a1aa42..f832a96971 100644 --- a/common/cmd_help.c +++ b/common/cmd_help.c @@ -24,7 +24,7 @@ #include #include -int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +static int do_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd); const int len = ll_entry_count(cmd_tbl_t, cmd); diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 82e63e1322..4438db594c 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -133,7 +133,7 @@ DECLARE_GLOBAL_DATA_PTR; #define DISP_LINE_LEN 16 /* implement possible board specific board init */ -void __def_i2c_init_board(void) +static void __def_i2c_init_board(void) { return; } @@ -141,14 +141,14 @@ void i2c_init_board(void) __attribute__((weak, alias("__def_i2c_init_board"))); /* TODO: Implement architecture-specific get/set functions */ -unsigned int __def_i2c_get_bus_speed(void) +static unsigned int __def_i2c_get_bus_speed(void) { return CONFIG_SYS_I2C_SPEED; } unsigned int i2c_get_bus_speed(void) __attribute__((weak, alias("__def_i2c_get_bus_speed"))); -int __def_i2c_set_bus_speed(unsigned int speed) +static int __def_i2c_set_bus_speed(unsigned int speed) { if (speed != CONFIG_SYS_I2C_SPEED) return -1; @@ -1376,10 +1376,8 @@ static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } /***************************************************/ - -U_BOOT_CMD( - i2c, 6, 1, do_i2c, - "I2C sub-system", +#ifdef CONFIG_SYS_LONGHELP +static char i2c_help_text[] = #if defined(CONFIG_I2C_MUX) "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c " #endif /* CONFIG_I2C_MUX */ @@ -1399,7 +1397,13 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_SDRAM) "i2c sdram chip - print SDRAM configuration information\n" #endif - "i2c speed [speed] - show or set I2C bus speed" + "i2c speed [speed] - show or set I2C bus speed"; +#endif + +U_BOOT_CMD( + i2c, 6, 1, do_i2c, + "I2C sub-system", + i2c_help_text ); #if defined(CONFIG_I2C_MUX) diff --git a/common/cmd_irq.c b/common/cmd_irq.c index 9f158ef6e3..1e82883bd4 100644 --- a/common/cmd_irq.c +++ b/common/cmd_irq.c @@ -24,7 +24,8 @@ #include #include -int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { if (argc != 2) diff --git a/common/cmd_itest.c b/common/cmd_itest.c index d5df758a1f..2c8e5d05e1 100644 --- a/common/cmd_itest.c +++ b/common/cmd_itest.c @@ -130,7 +130,7 @@ static int arithcomp (char *s, char *t, int op, int w) return (0); } -int binary_test (char *op, char *arg1, char *arg2, int w) +static int binary_test(char *op, char *arg1, char *arg2, int w) { int len, i; const op_tbl_t *optp; @@ -155,7 +155,7 @@ int binary_test (char *op, char *arg1, char *arg2, int w) } /* command line interface to the shell test */ -int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ) +static int do_itest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int value, w; diff --git a/common/cmd_load.c b/common/cmd_load.c index f4d66deae3..2c8dab1a0a 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -34,15 +34,15 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_CMD_LOADB) -static ulong load_serial_ymodem (ulong offset); +static ulong load_serial_ymodem(ulong offset); #endif #if defined(CONFIG_CMD_LOADS) -static ulong load_serial (long offset); -static int read_record (char *buf, ulong len); +static ulong load_serial(long offset); +static int read_record(char *buf, ulong len); # if defined(CONFIG_CMD_SAVES) -static int save_serial (ulong offset, ulong size); -static int write_record (char *buf); +static int save_serial(ulong offset, ulong size); +static int write_record(char *buf); #endif static int do_echo = 1; @@ -51,7 +51,8 @@ static int do_echo = 1; /* -------------------------------------------------------------------- */ #if defined(CONFIG_CMD_LOADS) -int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_load_serial(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { long offset = 0; ulong addr; @@ -82,11 +83,11 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) load_baudrate = current_baudrate; } if (load_baudrate != current_baudrate) { - printf ("## Switch baudrate to %d bps and press ENTER ...\n", + printf("## Switch baudrate to %d bps and press ENTER ...\n", load_baudrate); udelay(50000); gd->baudrate = load_baudrate; - serial_setbrg (); + serial_setbrg(); udelay(50000); for (;;) { if (getc() == '\r') @@ -99,9 +100,9 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_SYS_LOADS_BAUD_CHANGE */ - printf ("## Ready for S-Record download ...\n"); + printf("## Ready for S-Record download ...\n"); - addr = load_serial (offset); + addr = load_serial(offset); /* * Gather any trailing characters (for instance, the ^D which @@ -116,21 +117,21 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (addr == ~0) { - printf ("## S-Record download aborted\n"); + printf("## S-Record download aborted\n"); rcode = 1; } else { - printf ("## Start Addr = 0x%08lX\n", addr); + printf("## Start Addr = 0x%08lX\n", addr); load_addr = addr; } #ifdef CONFIG_SYS_LOADS_BAUD_CHANGE if (load_baudrate != current_baudrate) { - printf ("## Switch baudrate to %d bps and press ESC ...\n", + printf("## Switch baudrate to %d bps and press ESC ...\n", current_baudrate); - udelay (50000); + udelay(50000); gd->baudrate = current_baudrate; - serial_setbrg (); - udelay (50000); + serial_setbrg(); + udelay(50000); for (;;) { if (getc() == 0x1B) /* ESC */ break; @@ -140,8 +141,7 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return rcode; } -static ulong -load_serial (long offset) +static ulong load_serial(long offset) { char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */ char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */ @@ -156,7 +156,7 @@ load_serial (long offset) int line_count = 0; while (read_record(record, SREC_MAXRECLEN + 1) >= 0) { - type = srec_decode (record, &binlen, &addr, binbuf); + type = srec_decode(record, &binlen, &addr, binbuf); if (type < 0) { return (~0); /* Invalid S-Record */ @@ -173,13 +173,13 @@ load_serial (long offset) rc = flash_write((char *)binbuf,store_addr,binlen); if (rc != 0) { - flash_perror (rc); + flash_perror(rc); return (~0); } } else #endif { - memcpy ((char *)(store_addr), binbuf, binlen); + memcpy((char *)(store_addr), binbuf, binlen); } if ((store_addr) < start_addr) start_addr = store_addr; @@ -189,15 +189,15 @@ load_serial (long offset) case SREC_END2: case SREC_END3: case SREC_END4: - udelay (10000); + udelay(10000); size = end_addr - start_addr + 1; - printf ("\n" + printf("\n" "## First Load Addr = 0x%08lX\n" "## Last Load Addr = 0x%08lX\n" "## Total Size = 0x%08lX = %ld Bytes\n", start_addr, end_addr, size, size ); - flush_cache (start_addr, size); + flush_cache(start_addr, size); sprintf(buf, "%lX", size); setenv("filesize", buf); return (addr); @@ -208,15 +208,14 @@ load_serial (long offset) } if (!do_echo) { /* print a '.' every 100 lines */ if ((++line_count % 100) == 0) - putc ('.'); + putc('.'); } } return (~0); /* Download aborted */ } -static int -read_record (char *buf, ulong len) +static int read_record(char *buf, ulong len) { char *p; char c; @@ -226,7 +225,7 @@ read_record (char *buf, ulong len) for (p=buf; p < buf+len; ++p) { c = getc(); /* read character */ if (do_echo) - putc (c); /* ... and echo it */ + putc(c); /* ... and echo it */ switch (c) { case '\r': @@ -280,11 +279,11 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) save_baudrate = current_baudrate; } if (save_baudrate != current_baudrate) { - printf ("## Switch baudrate to %d bps and press ENTER ...\n", + printf("## Switch baudrate to %d bps and press ENTER ...\n", save_baudrate); udelay(50000); gd->baudrate = save_baudrate; - serial_setbrg (); + serial_setbrg(); udelay(50000); for (;;) { if (getc() == '\r') @@ -297,24 +296,24 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_SYS_LOADS_BAUD_CHANGE */ - printf ("## Ready for S-Record upload, press ENTER to proceed ...\n"); + printf("## Ready for S-Record upload, press ENTER to proceed ...\n"); for (;;) { if (getc() == '\r') break; } - if(save_serial (offset, size)) { - printf ("## S-Record upload aborted\n"); + if (save_serial(offset, size)) { + printf("## S-Record upload aborted\n"); } else { - printf ("## S-Record upload complete\n"); + printf("## S-Record upload complete\n"); } #ifdef CONFIG_SYS_LOADS_BAUD_CHANGE if (save_baudrate != current_baudrate) { - printf ("## Switch baudrate to %d bps and press ESC ...\n", + printf("## Switch baudrate to %d bps and press ESC ...\n", (int)current_baudrate); - udelay (50000); + udelay(50000); gd->baudrate = current_baudrate; - serial_setbrg (); - udelay (50000); + serial_setbrg(); + udelay(50000); for (;;) { if (getc() == 0x1B) /* ESC */ break; @@ -329,7 +328,7 @@ int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #define SREC3_END "S70500000000FA\n" #define SREC_BYTES_PER_RECORD 16 -static int save_serial (ulong address, ulong count) +static int save_serial(ulong address, ulong count) { int i, c, reclen, checksum, length; char *hex = "0123456789ABCDEF"; @@ -384,8 +383,7 @@ static int save_serial (ulong address, ulong count) return(0); } -static int -write_record (char *buf) +static int write_record(char *buf) { char c; @@ -425,15 +423,16 @@ write_record (char *buf) static void set_kerm_bin_mode(unsigned long *); static int k_recv(void); -static ulong load_serial_bin (ulong offset); +static ulong load_serial_bin(ulong offset); -char his_eol; /* character he needs at end of packet */ -int his_pad_count; /* number of pad chars he needs */ -char his_pad_char; /* pad chars he needs */ -char his_quote; /* quote chars he'll use */ +static char his_eol; /* character he needs at end of packet */ +static int his_pad_count; /* number of pad chars he needs */ +static char his_pad_char; /* pad chars he needs */ +static char his_quote; /* quote chars he'll use */ -int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_load_serial_bin(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { ulong offset = 0; ulong addr; @@ -463,11 +462,11 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ } if (load_baudrate != current_baudrate) { - printf ("## Switch baudrate to %d bps and press ENTER ...\n", + printf("## Switch baudrate to %d bps and press ENTER ...\n", load_baudrate); udelay(50000); gd->baudrate = load_baudrate; - serial_setbrg (); + serial_setbrg(); udelay(50000); for (;;) { if (getc() == '\r') @@ -476,37 +475,37 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ } if (strcmp(argv[0],"loady")==0) { - printf ("## Ready for binary (ymodem) download " + printf("## Ready for binary (ymodem) download " "to 0x%08lX at %d bps...\n", offset, load_baudrate); - addr = load_serial_ymodem (offset); + addr = load_serial_ymodem(offset); } else { - printf ("## Ready for binary (kermit) download " + printf("## Ready for binary (kermit) download " "to 0x%08lX at %d bps...\n", offset, load_baudrate); - addr = load_serial_bin (offset); + addr = load_serial_bin(offset); if (addr == ~0) { load_addr = 0; - printf ("## Binary (kermit) download aborted\n"); + printf("## Binary (kermit) download aborted\n"); rcode = 1; } else { - printf ("## Start Addr = 0x%08lX\n", addr); + printf("## Start Addr = 0x%08lX\n", addr); load_addr = addr; } } if (load_baudrate != current_baudrate) { - printf ("## Switch baudrate to %d bps and press ESC ...\n", + printf("## Switch baudrate to %d bps and press ESC ...\n", current_baudrate); - udelay (50000); + udelay(50000); gd->baudrate = current_baudrate; - serial_setbrg (); - udelay (50000); + serial_setbrg(); + udelay(50000); for (;;) { if (getc() == 0x1B) /* ESC */ break; @@ -517,13 +516,13 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[ } -static ulong load_serial_bin (ulong offset) +static ulong load_serial_bin(ulong offset) { int size, i; char buf[32]; - set_kerm_bin_mode ((ulong *) offset); - size = k_recv (); + set_kerm_bin_mode((ulong *) offset); + size = k_recv(); /* * Gather any trailing characters (for instance, the ^D which @@ -537,7 +536,7 @@ static ulong load_serial_bin (ulong offset) udelay(1000); } - flush_cache (offset, size); + flush_cache(offset, size); printf("## Total Size = 0x%08x = %d Bytes\n", size, size); sprintf(buf, "%X", size); @@ -546,16 +545,16 @@ static ulong load_serial_bin (ulong offset) return offset; } -void send_pad (void) +static void send_pad(void) { int count = his_pad_count; while (count-- > 0) - putc (his_pad_char); + putc(his_pad_char); } /* converts escaped kermit char to binary char */ -char ktrans (char in) +static char ktrans(char in) { if ((in & 0x60) == 0x40) { return (char) (in & ~0x40); @@ -565,7 +564,7 @@ char ktrans (char in) return in; } -int chk1 (char *buffer) +static int chk1(char *buffer) { int total = 0; @@ -575,67 +574,67 @@ int chk1 (char *buffer) return (int) ((total + ((total >> 6) & 0x03)) & 0x3f); } -void s1_sendpacket (char *packet) +static void s1_sendpacket(char *packet) { - send_pad (); + send_pad(); while (*packet) { - putc (*packet++); + putc(*packet++); } } static char a_b[24]; -void send_ack (int n) +static void send_ack(int n) { a_b[0] = START_CHAR; - a_b[1] = tochar (3); - a_b[2] = tochar (n); + a_b[1] = tochar(3); + a_b[2] = tochar(n); a_b[3] = ACK_TYPE; a_b[4] = '\0'; - a_b[4] = tochar (chk1 (&a_b[1])); + a_b[4] = tochar(chk1(&a_b[1])); a_b[5] = his_eol; a_b[6] = '\0'; - s1_sendpacket (a_b); + s1_sendpacket(a_b); } -void send_nack (int n) +static void send_nack(int n) { a_b[0] = START_CHAR; - a_b[1] = tochar (3); - a_b[2] = tochar (n); + a_b[1] = tochar(3); + a_b[2] = tochar(n); a_b[3] = NACK_TYPE; a_b[4] = '\0'; - a_b[4] = tochar (chk1 (&a_b[1])); + a_b[4] = tochar(chk1(&a_b[1])); a_b[5] = his_eol; a_b[6] = '\0'; - s1_sendpacket (a_b); + s1_sendpacket(a_b); } -void (*os_data_init) (void); -void (*os_data_char) (char new_char); +static void (*os_data_init)(void); +static void (*os_data_char)(char new_char); static int os_data_state, os_data_state_saved; static char *os_data_addr, *os_data_addr_saved; static char *bin_start_address; -static void bin_data_init (void) +static void bin_data_init(void) { os_data_state = 0; os_data_addr = bin_start_address; } -static void os_data_save (void) +static void os_data_save(void) { os_data_state_saved = os_data_state; os_data_addr_saved = os_data_addr; } -static void os_data_restore (void) +static void os_data_restore(void) { os_data_state = os_data_state_saved; os_data_addr = os_data_addr_saved; } -static void bin_data_char (char new_char) +static void bin_data_char(char new_char) { switch (os_data_state) { case 0: /* data */ @@ -644,7 +643,7 @@ static void bin_data_char (char new_char) } } -static void set_kerm_bin_mode (unsigned long *addr) +static void set_kerm_bin_mode(unsigned long *addr) { bin_start_address = (char *) addr; os_data_init = bin_data_init; @@ -654,29 +653,29 @@ static void set_kerm_bin_mode (unsigned long *addr) /* k_data_* simply handles the kermit escape translations */ static int k_data_escape, k_data_escape_saved; -void k_data_init (void) +static void k_data_init(void) { k_data_escape = 0; - os_data_init (); + os_data_init(); } -void k_data_save (void) +static void k_data_save(void) { k_data_escape_saved = k_data_escape; - os_data_save (); + os_data_save(); } -void k_data_restore (void) +static void k_data_restore(void) { k_data_escape = k_data_escape_saved; - os_data_restore (); + os_data_restore(); } -void k_data_char (char new_char) +static void k_data_char(char new_char) { if (k_data_escape) { /* last char was escape - translate this character */ - os_data_char (ktrans (new_char)); + os_data_char(ktrans(new_char)); k_data_escape = 0; } else { if (new_char == his_quote) { @@ -684,18 +683,18 @@ void k_data_char (char new_char) k_data_escape = 1; } else { /* otherwise send this char as-is */ - os_data_char (new_char); + os_data_char(new_char); } } } #define SEND_DATA_SIZE 20 -char send_parms[SEND_DATA_SIZE]; -char *send_ptr; +static char send_parms[SEND_DATA_SIZE]; +static char *send_ptr; /* handle_send_packet interprits the protocol info and builds and sends an appropriate ack for what we can do */ -void handle_send_packet (int n) +static void handle_send_packet(int n) { int length = 3; int bytes; @@ -715,30 +714,30 @@ void handle_send_packet (int n) break; /* handle MAXL - max length */ /* ignore what he says - most I'll take (here) is 94 */ - a_b[++length] = tochar (94); + a_b[++length] = tochar(94); if (bytes-- <= 0) break; /* handle TIME - time you should wait for my packets */ /* ignore what he says - don't wait for my ack longer than 1 second */ - a_b[++length] = tochar (1); + a_b[++length] = tochar(1); if (bytes-- <= 0) break; /* handle NPAD - number of pad chars I need */ /* remember what he says - I need none */ - his_pad_count = untochar (send_parms[2]); - a_b[++length] = tochar (0); + his_pad_count = untochar(send_parms[2]); + a_b[++length] = tochar(0); if (bytes-- <= 0) break; /* handle PADC - pad chars I need */ /* remember what he says - I need none */ - his_pad_char = ktrans (send_parms[3]); + his_pad_char = ktrans(send_parms[3]); a_b[++length] = 0x40; /* He should ignore this */ if (bytes-- <= 0) break; /* handle EOL - end of line he needs */ /* remember what he says - I need CR */ - his_eol = untochar (send_parms[4]); - a_b[++length] = tochar (END_CHAR); + his_eol = untochar(send_parms[4]); + a_b[++length] = tochar(END_CHAR); if (bytes-- <= 0) break; /* handle QCTL - quote control char he'll use */ @@ -764,25 +763,25 @@ void handle_send_packet (int n) break; /* handle CAPAS - the capabilities mask */ /* ignore what he says - I only do long packets - I don't do windows */ - a_b[++length] = tochar (2); /* only long packets */ - a_b[++length] = tochar (0); /* no windows */ - a_b[++length] = tochar (94); /* large packet msb */ - a_b[++length] = tochar (94); /* large packet lsb */ + a_b[++length] = tochar(2); /* only long packets */ + a_b[++length] = tochar(0); /* no windows */ + a_b[++length] = tochar(94); /* large packet msb */ + a_b[++length] = tochar(94); /* large packet lsb */ } while (0); a_b[0] = START_CHAR; - a_b[1] = tochar (length); - a_b[2] = tochar (n); + a_b[1] = tochar(length); + a_b[2] = tochar(n); a_b[3] = ACK_TYPE; a_b[++length] = '\0'; - a_b[length] = tochar (chk1 (&a_b[1])); + a_b[length] = tochar(chk1(&a_b[1])); a_b[++length] = his_eol; a_b[++length] = '\0'; - s1_sendpacket (a_b); + s1_sendpacket(a_b); } /* k_recv receives a OS Open image file over kermit line */ -static int k_recv (void) +static int k_recv(void) { char new_char; char k_state, k_state_saved; @@ -801,9 +800,9 @@ static int k_recv (void) /* initialize the k_recv and k_data state machine */ done = 0; k_state = 0; - k_data_init (); + k_data_init(); k_state_saved = k_state; - k_data_save (); + k_data_save(); n = 0; /* just to get rid of a warning */ last_n = -1; @@ -848,17 +847,17 @@ static int k_recv (void) START: /* get length of packet */ sum = 0; - new_char = getc (); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; sum += new_char & 0xff; - length = untochar (new_char); + length = untochar(new_char); /* get sequence number */ - new_char = getc (); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; sum += new_char & 0xff; - n = untochar (new_char); + n = untochar(new_char); --length; /* NEW CODE - check sequence numbers for retried packets */ @@ -871,17 +870,17 @@ START: if (n == last_n) { /* same sequence number, restore the previous state */ k_state = k_state_saved; - k_data_restore (); + k_data_restore(); } else { /* new sequence number, checkpoint the download */ last_n = n; k_state_saved = k_state; - k_data_save (); + k_data_save(); } /* END NEW CODE */ /* get packet type */ - new_char = getc (); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; sum += new_char & 0xff; @@ -891,29 +890,29 @@ START: if (length == -2) { /* (length byte was 0, decremented twice) */ /* get the two length bytes */ - new_char = getc (); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; sum += new_char & 0xff; - len_hi = untochar (new_char); - new_char = getc (); + len_hi = untochar(new_char); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; sum += new_char & 0xff; - len_lo = untochar (new_char); + len_lo = untochar(new_char); length = len_hi * 95 + len_lo; /* check header checksum */ - new_char = getc (); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; - if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f)) goto packet_error; sum += new_char & 0xff; /* --length; */ /* new length includes only data and block check to come */ } /* bring in rest of packet */ while (length > 1) { - new_char = getc (); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; sum += new_char & 0xff; @@ -930,26 +929,26 @@ START: } } /* get and validate checksum character */ - new_char = getc (); + new_char = getc(); if ((new_char & 0xE0) == 0) goto packet_error; - if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + if (new_char != tochar((sum + ((sum >> 6) & 0x03)) & 0x3f)) goto packet_error; /* get END_CHAR */ - new_char = getc (); + new_char = getc(); if (new_char != END_CHAR) { packet_error: /* restore state machines */ k_state = k_state_saved; - k_data_restore (); + k_data_restore(); /* send a negative acknowledge packet in */ - send_nack (n); + send_nack(n); } else if (k_state == SEND_TYPE) { /* crack the protocol parms, build an appropriate ack packet */ - handle_send_packet (n); + handle_send_packet(n); } else { /* send simple acknowledge packet in */ - send_ack (n); + send_ack(n); /* quit if end of transmission */ if (k_state == BREAK_TYPE) done = 1; @@ -963,7 +962,7 @@ static int getcxmodem(void) { return (getc()); return -1; } -static ulong load_serial_ymodem (ulong offset) +static ulong load_serial_ymodem(ulong offset) { int size; char buf[32]; @@ -976,19 +975,19 @@ static ulong load_serial_ymodem (ulong offset) size = 0; info.mode = xyzModem_ymodem; - res = xyzModem_stream_open (&info, &err); + res = xyzModem_stream_open(&info, &err); if (!res) { while ((res = - xyzModem_stream_read (ymodemBuf, 1024, &err)) > 0) { + xyzModem_stream_read(ymodemBuf, 1024, &err)) > 0) { store_addr = addr + offset; size += res; addr += res; #ifndef CONFIG_SYS_NO_FLASH - if (addr2info (store_addr)) { + if (addr2info(store_addr)) { int rc; - rc = flash_write ((char *) ymodemBuf, + rc = flash_write((char *) ymodemBuf, store_addr, res); if (rc != 0) { flash_perror (rc); @@ -997,24 +996,24 @@ static ulong load_serial_ymodem (ulong offset) } else #endif { - memcpy ((char *) (store_addr), ymodemBuf, + memcpy((char *)(store_addr), ymodemBuf, res); } } } else { - printf ("%s\n", xyzModem_error (err)); + printf("%s\n", xyzModem_error(err)); } - xyzModem_stream_close (&err); - xyzModem_stream_terminate (false, &getcxmodem); + xyzModem_stream_close(&err); + xyzModem_stream_terminate(false, &getcxmodem); - flush_cache (offset, size); + flush_cache(offset, size); - printf ("## Total Size = 0x%08x = %d Bytes\n", size, size); - sprintf (buf, "%X", size); - setenv ("filesize", buf); + printf("## Total Size = 0x%08x = %d Bytes\n", size, size); + sprintf(buf, "%X", size); + setenv("filesize", buf); return offset; } @@ -1091,7 +1090,7 @@ U_BOOT_CMD( /* -------------------------------------------------------------------- */ #if defined(CONFIG_CMD_HWFLOW) -int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_hwflow(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { extern int hwflow_onoff(int); diff --git a/common/cmd_mdio.c b/common/cmd_mdio.c index 77d8df12c5..ff0063b30d 100644 --- a/common/cmd_mdio.c +++ b/common/cmd_mdio.c @@ -57,9 +57,9 @@ static int extract_range(char *input, int *plo, int *phi) return 0; } -int mdio_write_ranges(struct mii_dev *bus, int addrlo, - int addrhi, int devadlo, int devadhi, - int reglo, int reghi, unsigned short data) +static int mdio_write_ranges(struct mii_dev *bus, int addrlo, + int addrhi, int devadlo, int devadhi, + int reglo, int reghi, unsigned short data) { int addr, devad, reg; int err = 0; @@ -79,9 +79,9 @@ err_out: return err; } -int mdio_read_ranges(struct mii_dev *bus, int addrlo, - int addrhi, int devadlo, int devadhi, - int reglo, int reghi) +static int mdio_read_ranges(struct mii_dev *bus, int addrlo, + int addrhi, int devadlo, int devadhi, + int reglo, int reghi) { int addr, devad, reg; @@ -112,8 +112,8 @@ int mdio_read_ranges(struct mii_dev *bus, int addrlo, } /* The register will be in the form [a[-b].]x[-y] */ -int extract_reg_range(char *input, int *devadlo, int *devadhi, - int *reglo, int *reghi) +static int extract_reg_range(char *input, int *devadlo, int *devadhi, + int *reglo, int *reghi) { char *regstr; @@ -141,8 +141,8 @@ int extract_reg_range(char *input, int *devadlo, int *devadhi, return extract_range(regstr, reglo, reghi); } -int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus, - int *addrlo, int *addrhi) +static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus, + int *addrlo, int *addrhi) { struct phy_device *phydev; diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 18f0a3f50f..4d64cfffde 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -51,7 +51,7 @@ static ulong base_address = 0; * md{.b, .w, .l} {addr} {len} */ #define DISP_LINE_LEN 16 -int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr, length; #if defined(CONFIG_HAS_DATAFLASH) @@ -147,16 +147,16 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return (rc); } -int do_mem_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_mm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return mod_mem (cmdtp, 1, flag, argc, argv); } -int do_mem_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_nm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return mod_mem (cmdtp, 0, flag, argc, argv); } -int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr, writeval, count; int size; @@ -253,7 +253,7 @@ int do_mem_mwc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_MX_CYCLIC */ -int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr1, addr2, count, ngood; int size; @@ -323,7 +323,7 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return rcode; } -int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr, dest, count; int size; @@ -433,7 +433,8 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int do_mem_base (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_base(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { if (argc > 1) { /* Set new base address. @@ -446,7 +447,8 @@ int do_mem_base (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { ulong addr, length, i; int size; @@ -592,7 +594,8 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until * interrupted by ctrl-c or by a failure of one of the sub-tests. */ -int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { vu_long *addr, *start, *end; ulong val; @@ -612,7 +615,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_MEMTEST_SCRATCH) vu_long *dummy = (vu_long*)CONFIG_SYS_MEMTEST_SCRATCH; #else - vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */ + vu_long *dummy = NULL; /* yes, this is address 0x0, not NULL */ #endif int j; @@ -1054,7 +1057,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) #ifndef CONFIG_CRC32_VERIFY -int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr, length; ulong crc; diff --git a/common/cmd_misc.c b/common/cmd_misc.c index 3b47a0c095..dc2772e85d 100644 --- a/common/cmd_misc.c +++ b/common/cmd_misc.c @@ -27,7 +27,7 @@ #include #include -int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_sleep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong start = get_timer(0); ulong delay; @@ -38,10 +38,10 @@ int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) delay = simple_strtoul(argv[1], NULL, 10) * CONFIG_SYS_HZ; while (get_timer(start) < delay) { - if (ctrlc ()) + if (ctrlc()) return (-1); - udelay (100); + udelay(100); } return 0; diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 79a1088f3b..62a1c224d3 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -115,7 +115,7 @@ static void print_mmcinfo(struct mmc *mmc) printf("Bus Width: %d-bit\n", mmc->bus_width); } -int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct mmc *mmc; @@ -147,7 +147,7 @@ U_BOOT_CMD( "- dislay info of the current MMC device" ); -int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum mmc_state state; @@ -269,7 +269,7 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = (void *)simple_strtoul(argv[idx], NULL, 16); ++idx; } else - addr = 0; + addr = NULL; blk = simple_strtoul(argv[idx], NULL, 16); cnt = simple_strtoul(argv[idx + 1], NULL, 16); diff --git a/common/cmd_mp.c b/common/cmd_mp.c index 4b27be4956..2143814d4f 100644 --- a/common/cmd_mp.c +++ b/common/cmd_mp.c @@ -23,7 +23,7 @@ #include #include -int +static int cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long cpuid; @@ -61,8 +61,14 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#ifdef CONFIG_SYS_LONGHELP +static char cpu_help_text[] = + " reset - Reset cpu \n" + "cpu status - Status of cpu \n" + "cpu disable - Disable cpu \n" + "cpu release [args] - Release cpu at with [args]" #ifdef CONFIG_PPC -#define CPU_ARCH_HELP \ + "\n" " [args] : \n" \ " pir - processor id (if writeable)\n" \ " r3 - value for gpr 3\n" \ @@ -74,16 +80,10 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) " When cpu is released r4 and r5 = 0.\n" \ " r7 will contain the size of the initial mapped area" #endif + ""; +#endif U_BOOT_CMD( cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd, - "Multiprocessor CPU boot manipulation and release", - " reset - Reset cpu \n" - "cpu status - Status of cpu \n" - "cpu disable - Disable cpu \n" - "cpu release [args] - Release cpu at with [args]" -#ifdef CPU_ARCH_HELP - "\n" - CPU_ARCH_HELP -#endif + "Multiprocessor CPU boot manipulation and release", cpu_help_text ); diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index 22688293ae..06fc171fe3 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -147,10 +147,10 @@ static char last_partition[PARTITION_MAXLEN]; extern void jffs2_free_cache(struct part_info *part); /* mtdids mapping list, filled by parse_ids() */ -struct list_head mtdids; +static struct list_head mtdids; /* device/partition list, parse_cmdline() parses into here */ -struct list_head devices; +static struct list_head devices; /* current active device and partition number */ struct mtd_device *current_mtd_dev = NULL; @@ -710,7 +710,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i * @param size a pointer to the size of the mtd device (output) * @return 0 if device is valid, 1 otherwise */ -int mtd_device_validate(u8 type, u8 num, u32 *size) +static int mtd_device_validate(u8 type, u8 num, u32 *size) { struct mtd_info *mtd = NULL; @@ -1042,7 +1042,8 @@ static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_ * @param dev_num parsed device number (output) * @return 0 on success, 1 otherwise */ -int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num) +int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, + u8 *dev_num) { const char *p = id; @@ -1884,7 +1885,7 @@ static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part * @param argv arguments list * @return 0 on success, 1 otherwise */ -int do_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { /* command line only */ struct mtd_device *dev; @@ -1922,7 +1923,8 @@ int do_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * @param argv arguments list * @return 0 on success, 1 otherwise */ -int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { if (argc == 2) { if (strcmp(argv[1], "default") == 0) { @@ -2046,9 +2048,8 @@ U_BOOT_CMD( " - change active partition (e.g. part-id = nand0,1)" ); -U_BOOT_CMD( - mtdparts, 6, 0, do_mtdparts, - "define flash/nand partitions", +#ifdef CONFIG_SYS_LONGHELP +static char mtdparts_help_text[] = "\n" " - list partition table\n" "mtdparts delall\n" @@ -2090,6 +2091,11 @@ U_BOOT_CMD( " := standard linux memsize OR '-' to denote all remaining space\n" " := partition start offset within the device\n" " := '(' NAME ')'\n" - " := when set to 'ro' makes partition read-only (not used, passed to kernel)" + " := when set to 'ro' makes partition read-only (not used, passed to kernel)"; +#endif + +U_BOOT_CMD( + mtdparts, 6, 0, do_mtdparts, + "define flash/nand partitions", mtdparts_help_text ); /***************************************************/ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index e24ed7f9c4..4b1606972b 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -373,8 +373,7 @@ static void nand_print_and_set_info(int idx) { nand_info_t *nand = &nand_info[idx]; struct nand_chip *chip = nand->priv; - const int bufsz = 32; - char buf[bufsz]; + char buf[32]; printf("Device %d: ", idx); if (chip->numchips > 1) @@ -429,7 +428,7 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count, return ret; } -int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret = 0; ulong addr; @@ -781,9 +780,8 @@ usage: return CMD_RET_USAGE; } -U_BOOT_CMD( - nand, CONFIG_SYS_MAXARGS, 1, do_nand, - "NAND sub-system", +#ifdef CONFIG_SYS_LONGHELP +static char nand_help_text[] = "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read - addr off|partition size\n" @@ -829,6 +827,12 @@ U_BOOT_CMD( "nand env.oob set off|partition - set enviromnent offset\n" "nand env.oob get - get environment offset" #endif + ""; +#endif + +U_BOOT_CMD( + nand, CONFIG_SYS_MAXARGS, 1, do_nand, + "NAND sub-system", nand_help_text ); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, @@ -913,7 +917,8 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, return bootm_maybe_autostart(cmdtp, cmd); } -int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +static int do_nandboot(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { char *boot_device = NULL; int idx; diff --git a/common/cmd_net.c b/common/cmd_net.c index a9ade8b927..3b93ef27c0 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -30,9 +30,9 @@ static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []); -int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_bootp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return netboot_common (BOOTP, cmdtp, argc, argv); + return netboot_common(BOOTP, cmdtp, argc, argv); } U_BOOT_CMD( @@ -41,7 +41,7 @@ U_BOOT_CMD( "[loadAddress] [[hostIPaddr:]bootfilename]" ); -int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int ret; @@ -91,9 +91,9 @@ U_BOOT_CMD( #ifdef CONFIG_CMD_RARP -int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_rarpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - return netboot_common (RARP, cmdtp, argc, argv); + return netboot_common(RARP, cmdtp, argc, argv); } U_BOOT_CMD( @@ -104,7 +104,7 @@ U_BOOT_CMD( #endif #if defined(CONFIG_CMD_DHCP) -int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_dhcp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return netboot_common(DHCP, cmdtp, argc, argv); } @@ -117,7 +117,7 @@ U_BOOT_CMD( #endif #if defined(CONFIG_CMD_NFS) -int do_nfs (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_nfs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return netboot_common(NFS, cmdtp, argc, argv); } @@ -129,29 +129,29 @@ U_BOOT_CMD( ); #endif -static void netboot_update_env (void) +static void netboot_update_env(void) { char tmp[22]; if (NetOurGatewayIP) { - ip_to_string (NetOurGatewayIP, tmp); - setenv ("gatewayip", tmp); + ip_to_string(NetOurGatewayIP, tmp); + setenv("gatewayip", tmp); } if (NetOurSubnetMask) { - ip_to_string (NetOurSubnetMask, tmp); - setenv ("netmask", tmp); + ip_to_string(NetOurSubnetMask, tmp); + setenv("netmask", tmp); } if (NetOurHostName[0]) - setenv ("hostname", NetOurHostName); + setenv("hostname", NetOurHostName); if (NetOurRootPath[0]) - setenv ("rootpath", NetOurRootPath); + setenv("rootpath", NetOurRootPath); if (NetOurIP) { - ip_to_string (NetOurIP, tmp); - setenv ("ipaddr", tmp); + ip_to_string(NetOurIP, tmp); + setenv("ipaddr", tmp); } #if !defined(CONFIG_BOOTP_SERVERIP) /* @@ -159,35 +159,35 @@ static void netboot_update_env (void) * could have set it */ if (NetServerIP) { - ip_to_string (NetServerIP, tmp); - setenv ("serverip", tmp); + ip_to_string(NetServerIP, tmp); + setenv("serverip", tmp); } #endif if (NetOurDNSIP) { - ip_to_string (NetOurDNSIP, tmp); - setenv ("dnsip", tmp); + ip_to_string(NetOurDNSIP, tmp); + setenv("dnsip", tmp); } #if defined(CONFIG_BOOTP_DNS2) if (NetOurDNS2IP) { - ip_to_string (NetOurDNS2IP, tmp); - setenv ("dnsip2", tmp); + ip_to_string(NetOurDNS2IP, tmp); + setenv("dnsip2", tmp); } #endif if (NetOurNISDomain[0]) - setenv ("domain", NetOurNISDomain); + setenv("domain", NetOurNISDomain); #if defined(CONFIG_CMD_SNTP) \ && defined(CONFIG_BOOTP_TIMEOFFSET) if (NetTimeOffset) { - sprintf (tmp, "%d", NetTimeOffset); - setenv ("timeoffset", tmp); + sprintf(tmp, "%d", NetTimeOffset); + setenv("timeoffset", tmp); } #endif #if defined(CONFIG_CMD_SNTP) \ && defined(CONFIG_BOOTP_NTPSERVER) if (NetNtpServerIP) { - ip_to_string (NetNtpServerIP, tmp); - setenv ("ntpserverip", tmp); + ip_to_string(NetNtpServerIP, tmp); + setenv("ntpserverip", tmp); } #endif } @@ -224,7 +224,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc, break; case 3: load_addr = simple_strtoul(argv[1], NULL, 16); - copy_filename (BootFile, argv[2], sizeof(BootFile)); + copy_filename(BootFile, argv[2], sizeof(BootFile)); break; @@ -274,7 +274,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc, } #if defined(CONFIG_CMD_PING) -int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_ping(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc < 2) return -1; @@ -322,7 +322,7 @@ static void cdp_update_env(void) } -int do_cdp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_cdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int r; @@ -345,27 +345,29 @@ U_BOOT_CMD( #endif #if defined(CONFIG_CMD_SNTP) -int do_sntp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_sntp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *toff; if (argc < 2) { - NetNtpServerIP = getenv_IPaddr ("ntpserverip"); + NetNtpServerIP = getenv_IPaddr("ntpserverip"); if (NetNtpServerIP == 0) { - printf ("ntpserverip not set\n"); + printf("ntpserverip not set\n"); return (1); } } else { NetNtpServerIP = string_to_ip(argv[1]); if (NetNtpServerIP == 0) { - printf ("Bad NTP server IP address\n"); + printf("Bad NTP server IP address\n"); return (1); } } - toff = getenv ("timeoffset"); - if (toff == NULL) NetTimeOffset = 0; - else NetTimeOffset = simple_strtol (toff, NULL, 10); + toff = getenv("timeoffset"); + if (toff == NULL) + NetTimeOffset = 0; + else + NetTimeOffset = simple_strtol(toff, NULL, 10); if (NetLoop(SNTP) < 0) { printf("SNTP failed: host %pI4 not responding\n", diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 68c38f4e5c..006131f45c 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -136,7 +136,8 @@ static int env_print(char *name) return 0; } -int do_env_print (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_env_print(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { int i; int rcode = 0; @@ -322,7 +323,7 @@ int env_check_apply(const char *name, const char *oldval, * Set a new environment variable, * or replace or delete an existing one. */ -int _do_env_set(int flag, int argc, char * const argv[]) +static int _do_env_set(int flag, int argc, char * const argv[]) { int i, len; char *name, *value, *s; @@ -435,7 +436,7 @@ int setenv_addr(const char *varname, const void *addr) } #ifndef CONFIG_SPL_BUILD -int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc < 2) return CMD_RET_USAGE; @@ -514,7 +515,8 @@ int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Interactively edit an environment variable */ #if defined(CONFIG_CMD_EDITENV) -int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { char buffer[CONFIG_SYS_CBSIZE]; char *init_val; @@ -622,7 +624,8 @@ ulong getenv_ulong(const char *name, int base, ulong default_val) #ifndef CONFIG_SPL_BUILD #if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) -int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_env_save(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { printf("Saving Environment to %s...\n", env_name_spec); @@ -1020,9 +1023,8 @@ static int do_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_USAGE; } -U_BOOT_CMD( - env, CONFIG_SYS_MAXARGS, 1, do_env, - "environment handling commands", +#ifdef CONFIG_SYS_LONGHELP +static char env_help_text[] = #if defined(CONFIG_CMD_ASKENV) "ask name [message] [size] - ask for environment variable\nenv " #endif @@ -1047,7 +1049,12 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) "env save - save environment\n" #endif - "env set [-f] name [arg ...]\n" + "env set [-f] name [arg ...]\n"; +#endif + +U_BOOT_CMD( + env, CONFIG_SYS_MAXARGS, 1, do_env, + "environment handling commands", env_help_text ); /* diff --git a/common/cmd_pci.c b/common/cmd_pci.c index a1fe519f61..8550b64008 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -35,8 +35,6 @@ #include #include -unsigned char ShortPCIListing = 1; - /* * Follows routines for the output of infos about devices on PCI bus. */ @@ -408,7 +406,7 @@ pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag * pci modify[.b, .w, .l] bus.device.function [addr] * pci write[.b, .w, .l] bus.device.function addr value */ -int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr = 0, value = 0, size = 0; pci_dev_t bdf = 0; @@ -485,10 +483,8 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /***************************************************/ - -U_BOOT_CMD( - pci, 5, 1, do_pci, - "list and access PCI Configuration Space", +#ifdef CONFIG_SYS_LONGHELP +static char pci_help_text[] = "[bus] [long]\n" " - short or long list of PCI devices on bus 'bus'\n" #ifdef CONFIG_CMD_PCI_ENUM @@ -504,5 +500,10 @@ U_BOOT_CMD( "pci modify[.b, .w, .l] b.d.f address\n" " - modify, auto increment CFG address\n" "pci write[.b, .w, .l] b.d.f address value\n" - " - write to CFG address" + " - write to CFG address"; +#endif + +U_BOOT_CMD( + pci, 5, 1, do_pci, + "list and access PCI Configuration Space", pci_help_text ); diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 908876ce45..08a6563448 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -37,7 +37,8 @@ extern void mpc86xx_reginfo(void); extern void mpc85xx_reginfo(void); #endif -int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { #if defined(CONFIG_8xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 3f98235a38..b401bd1024 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -28,7 +28,7 @@ #include #include -int sata_curr_device = -1; +static int sata_curr_device = -1; block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; int __sata_initialize(void) @@ -67,7 +67,7 @@ block_dev_desc_t *sata_get_dev(int dev) } #endif -int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int rc = 0; diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c index 1b3edb7b02..7b140deea3 100644 --- a/common/cmd_setexpr.c +++ b/common/cmd_setexpr.c @@ -50,7 +50,7 @@ static ulong get_arg(char *s, int w) } } -int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong a, b; char buf[16]; diff --git a/common/cmd_source.c b/common/cmd_source.c index c4cde982a5..02a862cc5a 100644 --- a/common/cmd_source.c +++ b/common/cmd_source.c @@ -177,9 +177,8 @@ do_source (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return rcode; } -U_BOOT_CMD( - source, 2, 0, do_source, - "run script from memory", +#ifdef CONFIG_SYS_LONGHELP +static char source_help_text[] = "[addr]\n" "\t- run script starting at addr\n" "\t- A valid image header must be present" @@ -188,5 +187,11 @@ U_BOOT_CMD( "For FIT format uImage addr must include subimage\n" "unit name in the form of addr:" #endif + ""; +#endif + +U_BOOT_CMD( + source, 2, 0, do_source, + "run script from memory", source_help_text ); #endif diff --git a/common/cmd_test.c b/common/cmd_test.c index 6da06b9f78..d4ec18672e 100644 --- a/common/cmd_test.c +++ b/common/cmd_test.c @@ -24,7 +24,7 @@ #include #include -int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char * const *ap; int left, adv, expr, last_expr, neg, last_cmp; @@ -150,7 +150,7 @@ U_BOOT_CMD( "[args..]" ); -int do_false(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_false(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return 1; } @@ -161,7 +161,7 @@ U_BOOT_CMD( NULL ); -int do_true(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_true(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return 0; } diff --git a/common/cmd_usb.c b/common/cmd_usb.c index c128455d74..8ad0b23058 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -40,7 +40,7 @@ static int usb_ether_curr_dev = -1; /* current ethernet device */ #endif /* some display routines (info command) */ -char *usb_get_class_desc(unsigned char dclass) +static char *usb_get_class_desc(unsigned char dclass) { switch (dclass) { case USB_CLASS_PER_INTERFACE: @@ -66,8 +66,8 @@ char *usb_get_class_desc(unsigned char dclass) } } -void usb_display_class_sub(unsigned char dclass, unsigned char subclass, - unsigned char proto) +static void usb_display_class_sub(unsigned char dclass, unsigned char subclass, + unsigned char proto) { switch (dclass) { case USB_CLASS_PER_INTERFACE: @@ -148,7 +148,7 @@ void usb_display_class_sub(unsigned char dclass, unsigned char subclass, } } -void usb_display_string(struct usb_device *dev, int index) +static void usb_display_string(struct usb_device *dev, int index) { ALLOC_CACHE_ALIGN_BUFFER(char, buffer, 256); @@ -158,7 +158,7 @@ void usb_display_string(struct usb_device *dev, int index) } } -void usb_display_desc(struct usb_device *dev) +static void usb_display_desc(struct usb_device *dev) { if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) { printf("%d: %s, USB Revision %x.%x\n", dev->devnum, @@ -192,8 +192,8 @@ void usb_display_desc(struct usb_device *dev) } -void usb_display_conf_desc(struct usb_configuration_descriptor *config, - struct usb_device *dev) +static void usb_display_conf_desc(struct usb_configuration_descriptor *config, + struct usb_device *dev) { printf(" Configuration: %d\n", config->bConfigurationValue); printf(" - Interfaces: %d %s%s%dmA\n", config->bNumInterfaces, @@ -207,8 +207,8 @@ void usb_display_conf_desc(struct usb_configuration_descriptor *config, } } -void usb_display_if_desc(struct usb_interface_descriptor *ifdesc, - struct usb_device *dev) +static void usb_display_if_desc(struct usb_interface_descriptor *ifdesc, + struct usb_device *dev) { printf(" Interface: %d\n", ifdesc->bInterfaceNumber); printf(" - Alternate Setting %d, Endpoints: %d\n", @@ -224,7 +224,7 @@ void usb_display_if_desc(struct usb_interface_descriptor *ifdesc, } } -void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc) +static void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc) { printf(" - Endpoint %d %s ", epdesc->bEndpointAddress & 0xf, (epdesc->bEndpointAddress & 0x80) ? "In" : "Out"); @@ -249,7 +249,7 @@ void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc) } /* main routine to diasplay the configs, interfaces and endpoints */ -void usb_display_config(struct usb_device *dev) +static void usb_display_config(struct usb_device *dev) { struct usb_config *config; struct usb_interface *ifdesc; @@ -280,7 +280,7 @@ static inline char *portspeed(int speed) } /* shows the device tree recursively */ -void usb_show_tree_graph(struct usb_device *dev, char *pre) +static void usb_show_tree_graph(struct usb_device *dev, char *pre) { int i, index; int has_child, last_child; @@ -340,7 +340,7 @@ void usb_show_tree_graph(struct usb_device *dev, char *pre) } /* main routine for the tree command */ -void usb_show_tree(struct usb_device *dev) +static void usb_show_tree(struct usb_device *dev) { char preamble[32]; @@ -353,7 +353,7 @@ void usb_show_tree(struct usb_device *dev) * usb boot command intepreter. Derived from diskboot */ #ifdef CONFIG_USB_STORAGE -int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return common_diskboot(cmdtp, "usb", argc, argv); } @@ -363,7 +363,7 @@ int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /****************************************************************************** * usb command intepreter */ -int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; diff --git a/common/cmd_version.c b/common/cmd_version.c index e4b2ac1efc..ab4c560ae0 100644 --- a/common/cmd_version.c +++ b/common/cmd_version.c @@ -28,7 +28,7 @@ const char __weak version_string[] = U_BOOT_VERSION_STRING; -int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf("\n%s\n", version_string); #ifdef CC_VERSION_STRING diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index 0414589bad..42a7eba766 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -42,7 +42,7 @@ #define CONFIG_SYS_XIMG_LEN 0x800000 #endif -int +static int do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { ulong addr = load_addr; @@ -264,9 +264,8 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 0; } -U_BOOT_CMD( - imxtract, 4, 1, do_imgextract, - "extract a part of a multi-image", +#ifdef CONFIG_SYS_LONGHELP +static char imgextract_help_text[] = "addr part [dest]\n" " - extract from legacy image at and copy to " #if defined(CONFIG_FIT) @@ -274,4 +273,10 @@ U_BOOT_CMD( "addr uname [dest]\n" " - extract subimage from FIT image at and copy to " #endif + ""; +#endif + +U_BOOT_CMD( + imxtract, 4, 1, do_imgextract, + "extract a part of a multi-image", imgextract_help_text ); -- cgit v1.2.3 From 199adb601ff34bdbbd0667fac80dfe0a87bffc2b Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:32 +0000 Subject: common/misc: sparse fixes command.c:44:38: error: bad constant expression dlmalloc.c:1468:2: warning: Using plain integer as NULL pointer dlmalloc.c:1468:5: warning: Using plain integer as NULL pointer dlmalloc.c:2176:12: warning: Using plain integer as NULL pointer dlmalloc.c:2179:31: warning: Using plain integer as NULL pointer dlmalloc.c:2382:14: warning: Using plain integer as NULL pointer dlmalloc.c:2436:14: warning: Using plain integer as NULL pointer dlmalloc.c:2582:31: warning: Using plain integer as NULL pointer dlmalloc.c:2585:17: warning: Using plain integer as NULL pointer dlmalloc.c:2646:14: warning: Using plain integer as NULL pointer dlmalloc.c:2659:19: warning: Using plain integer as NULL pointer dlmalloc.c:2692:19: warning: Using plain integer as NULL pointer dlmalloc.c:2707:19: warning: Using plain integer as NULL pointer dlmalloc.c:2708:14: warning: Using plain integer as NULL pointer dlmalloc.c:2786:31: warning: Using plain integer as NULL pointer dlmalloc.c:2801:12: warning: Using plain integer as NULL pointer dlmalloc.c:2801:22: warning: Using plain integer as NULL pointer dlmalloc.c:2926:27: warning: Using plain integer as NULL pointer dlmalloc.c:2928:14: warning: Using plain integer as NULL pointer dlmalloc.c:2929:12: warning: Using plain integer as NULL pointer dlmalloc.c:3075:14: warning: Using plain integer as NULL pointer hush.c:292:14: warning: symbol 'last_return_code' was not declared. Should it be static? hush.c:293:5: warning: symbol 'nesting_level' was not declared. Should it be static? hush.c:2175:20: warning: Using plain integer as NULL pointer hush.c:2175:34: warning: Using plain integer as NULL pointer hush.c:2210:41: warning: Using plain integer as NULL pointer hush.c:2216:45: warning: Using plain integer as NULL pointer hush.c:2249:25: warning: Using plain integer as NULL pointer hush.c:2332:13: warning: symbol 'new_pipe' was not declared. Should it be static? hush.c:2390:5: warning: symbol 'reserved_word' was not declared. Should it be static? hush.c:2927:5: warning: symbol 'parse_stream' was not declared. Should it be static? hush.c:3127:6: warning: symbol 'mapset' was not declared. Should it be static? hush.c:3133:6: warning: symbol 'update_ifs_map' was not declared. Should it be static? hush.c:3161:5: warning: symbol 'parse_stream_outer' was not declared. Should it be static? hush.c:3295:34: warning: Using plain integer as NULL pointer hush.c:3631:5: warning: symbol 'do_showvar' was not declared. Should it be static image.c:1282:29: warning: Using plain integer as NULL pointer image.c:1315:41: warning: Using plain integer as NULL pointer image.c:1330:25: warning: Using plain integer as NULL pointer image.c:1706:25: warning: Using plain integer as NULL pointer main.c:510:10: warning: symbol 'hist_num' was not declared. Should it be static? main.c:512:5: warning: symbol 'hist_list' was not declared. Should it be static? main.c:513:6: warning: symbol 'hist_lines' was not declared. Should it be static? usb_storage.c:195:6: warning: symbol 'usb_show_progress' was not declared. Should it be static? usb_storage.c:440:48: warning: Using plain integer as NULL pointer usb_storage.c:503:5: warning: symbol 'usb_stor_BBB_comdat' was not declared. Should it be static? usb_storage.c:551:5: warning: symbol 'usb_stor_CB_comdat' was not declared. Should it be static? usb_storage.c:629:55: warning: Using plain integer as NULL pointer usb_storage.c:620:5: warning: symbol 'usb_stor_CBI_get_status' was not declared. Should it be static? usb_storage.c:675:43: warning: Using plain integer as NULL pointer usb_storage.c:668:5: warning: symbol 'usb_stor_BBB_clear_endpt_stall' was not declared. Should it be static? usb_storage.c:679:5: warning: symbol 'usb_stor_BBB_transport' was not declared. Should it be static? usb_storage.c:801:5: warning: symbol 'usb_stor_CB_transport' was not declared. Sh xyzModem.c:104:1: warning: symbol 'CYGACC_COMM_IF_GETC_TIMEOUT' was not declared. Should it be static? xyzModem.c:122:1: warning: symbol 'CYGACC_COMM_IF_PUTC' was not declared. Should it be static? xyzModem.c:169:1: warning: symbol 'parse_num' was not declared. Should it be stat note: hush.c's nesting_level deleted because not used. Signed-off-by: Kim Phillips --- common/command.c | 9 ++++++++- common/dlmalloc.c | 36 ++++++++++++++++++------------------ common/hush.c | 31 ++++++++++++++++--------------- common/image.c | 8 ++++---- common/main.c | 10 +++++----- common/usb_storage.c | 20 ++++++++++---------- common/xyzModem.c | 6 +++--- 7 files changed, 64 insertions(+), 56 deletions(-) diff --git a/common/command.c b/common/command.c index 50c84292c1..f51df26bf9 100644 --- a/common/command.c +++ b/common/command.c @@ -40,8 +40,15 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int int i; int rcode = 0; + if (cmd_items > CONFIG_SYS_MAXARGS) { + printf("%s: cmd_items %d exceeds hardcoded limit %d." + " Recompile with higher CONFIG_SYS_MAXARGS?\n", + __func__, cmd_items, CONFIG_SYS_MAXARGS); + return -1; + } + if (argc == 1) { /*show list of commands */ - cmd_tbl_t *cmd_array[cmd_items]; + cmd_tbl_t *cmd_array[CONFIG_SYS_MAXARGS]; int i, j, swaps; /* Make array of commands from .uboot_cmd section */ diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 1d7e527b9d..b2f0a1ad52 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1465,7 +1465,7 @@ typedef struct malloc_chunk* mbinptr; #define IAV(i) bin_at(i), bin_at(i) static mbinptr av_[NAV * 2 + 2] = { - 0, 0, + NULL, NULL, IAV(0), IAV(1), IAV(2), IAV(3), IAV(4), IAV(5), IAV(6), IAV(7), IAV(8), IAV(9), IAV(10), IAV(11), IAV(12), IAV(13), IAV(14), IAV(15), IAV(16), IAV(17), IAV(18), IAV(19), IAV(20), IAV(21), IAV(22), IAV(23), @@ -2173,10 +2173,10 @@ Void_t* mALLOc(bytes) size_t bytes; /* check if mem_malloc_init() was run */ if ((mem_malloc_start == 0) && (mem_malloc_end == 0)) { /* not initialized yet */ - return 0; + return NULL; } - if ((long)bytes < 0) return 0; + if ((long)bytes < 0) return NULL; nb = request2size(bytes); /* padded request size; */ @@ -2379,7 +2379,7 @@ Void_t* mALLOc(bytes) size_t bytes; /* Try to extend */ malloc_extend_top(nb); if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE) - return 0; /* propagate failure */ + return NULL; /* propagate failure */ } victim = top; @@ -2433,7 +2433,7 @@ void fREe(mem) Void_t* mem; mchunkptr fwd; /* misc temp for linking */ int islr; /* track whether merging with last_remainder */ - if (mem == 0) /* free(0) has no effect */ + if (mem == NULL) /* free(0) has no effect */ return; p = mem2chunk(mem); @@ -2579,10 +2579,10 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; if (bytes == 0) { fREe(oldmem); return 0; } #endif - if ((long)bytes < 0) return 0; + if ((long)bytes < 0) return NULL; /* realloc of null is supposed to be same as malloc */ - if (oldmem == 0) return mALLOc(bytes); + if (oldmem == NULL) return mALLOc(bytes); newp = oldp = mem2chunk(oldmem); newsize = oldsize = chunksize(oldp); @@ -2643,7 +2643,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; } else { - next = 0; + next = NULL; nextsize = 0; } @@ -2656,7 +2656,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; /* try forward + backward first to save a later consolidation */ - if (next != 0) + if (next != NULL) { /* into top */ if (next == top) @@ -2689,7 +2689,7 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; } /* backward only */ - if (prev != 0 && (long)(prevsize + newsize) >= (long)nb) + if (prev != NULL && (long)(prevsize + newsize) >= (long)nb) { unlink(prev, bck, fwd); newp = prev; @@ -2704,8 +2704,8 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; newmem = mALLOc (bytes); - if (newmem == 0) /* propagate failure */ - return 0; + if (newmem == NULL) /* propagate failure */ + return NULL; /* Avoid copy if newp is next chunk after oldp. */ /* (This can only happen when new chunk is sbrk'ed.) */ @@ -2783,7 +2783,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; mchunkptr remainder; /* spare room at end to split off */ long remainder_size; /* its size */ - if ((long)bytes < 0) return 0; + if ((long)bytes < 0) return NULL; /* If need less alignment than we give anyway, just relay to malloc */ @@ -2798,7 +2798,7 @@ Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; nb = request2size(bytes); m = (char*)(mALLOc(nb + alignment + MINSIZE)); - if (m == 0) return 0; /* propagate failure */ + if (m == NULL) return NULL; /* propagate failure */ p = mem2chunk(m); @@ -2923,10 +2923,10 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; #endif Void_t* mem = mALLOc (sz); - if ((long)n < 0) return 0; + if ((long)n < 0) return NULL; - if (mem == 0) - return 0; + if (mem == NULL) + return NULL; else { p = mem2chunk(mem); @@ -3072,7 +3072,7 @@ size_t malloc_usable_size(mem) Void_t* mem; #endif { mchunkptr p; - if (mem == 0) + if (mem == NULL) return 0; else { diff --git a/common/hush.c b/common/hush.c index 4c84c2f501..eb6c879c53 100644 --- a/common/hush.c +++ b/common/hush.c @@ -289,8 +289,7 @@ struct variables { char **global_argv; unsigned int global_argc; #endif -unsigned int last_return_code; -int nesting_level; +static unsigned int last_return_code; #ifndef __U_BOOT__ extern char **environ; /* This is in , but protected with __USE_GNU */ #endif @@ -2172,7 +2171,7 @@ int set_local_var(const char *s, int flg_export) * NAME=VALUE format. So the first order of business is to * split 's' on the '=' into 'name' and 'value' */ value = strchr(name, '='); - if (value==0 && ++value==0) { + if (value == NULL && ++value == NULL) { free(name); return -1; } @@ -2207,13 +2206,13 @@ int set_local_var(const char *s, int flg_export) result = -1; } else { cur->name = strdup(name); - if(cur->name == 0) { + if (cur->name == NULL) { free(cur); result = -1; } else { struct variables *bottom = top_vars; cur->value = strdup(value); - cur->next = 0; + cur->next = NULL; cur->flg_export = flg_export; cur->flg_read_only = 0; while(bottom->next) bottom=bottom->next; @@ -2246,7 +2245,7 @@ void unset_local_var(const char *name) if(strcmp(cur->name, name)==0) break; } - if(cur!=0) { + if (cur != NULL) { struct variables *next = top_vars; if(cur->flg_read_only) { error_msg("%s: readonly variable", name); @@ -2329,7 +2328,8 @@ static int setup_redirect(struct p_context *ctx, int fd, redir_type style, } #endif -struct pipe *new_pipe(void) { +static struct pipe *new_pipe(void) +{ struct pipe *pi; pi = xmalloc(sizeof(struct pipe)); pi->num_progs = 0; @@ -2387,7 +2387,7 @@ static struct reserved_combo reserved_list[] = { }; #define NRES (sizeof(reserved_list)/sizeof(struct reserved_combo)) -int reserved_word(o_string *dest, struct p_context *ctx) +static int reserved_word(o_string *dest, struct p_context *ctx) { struct reserved_combo *r; for (r=reserved_list; @@ -2924,8 +2924,8 @@ int parse_string(o_string *dest, struct p_context *ctx, const char *src) #endif /* return code is 0 for normal exit, 1 for syntax error */ -int parse_stream(o_string *dest, struct p_context *ctx, - struct in_str *input, int end_trigger) +static int parse_stream(o_string *dest, struct p_context *ctx, + struct in_str *input, int end_trigger) { unsigned int ch, m; #ifndef __U_BOOT__ @@ -3124,13 +3124,13 @@ int parse_stream(o_string *dest, struct p_context *ctx, return 0; } -void mapset(const unsigned char *set, int code) +static void mapset(const unsigned char *set, int code) { const unsigned char *s; for (s=set; *s; s++) map[*s] = code; } -void update_ifs_map(void) +static void update_ifs_map(void) { /* char *ifs and char map[256] are both globals. */ ifs = (uchar *)getenv("IFS"); @@ -3158,7 +3158,7 @@ void update_ifs_map(void) /* most recursion does not come through here, the exeception is * from builtin_source() */ -int parse_stream_outer(struct in_str *inp, int flag) +static int parse_stream_outer(struct in_str *inp, int flag) { struct p_context ctx; @@ -3292,7 +3292,7 @@ int u_boot_hush_start(void) top_vars = malloc(sizeof(struct variables)); top_vars->name = "HUSH_VERSION"; top_vars->value = "0.01"; - top_vars->next = 0; + top_vars->next = NULL; top_vars->flg_export = 0; top_vars->flg_read_only = 1; #ifdef CONFIG_NEEDS_MANUAL_RELOC @@ -3628,7 +3628,8 @@ static char * make_string(char ** inp) } #ifdef __U_BOOT__ -int do_showvar (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_showvar(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) { int i, k; int rcode = 0; diff --git a/common/image.c b/common/image.c index 750a98b6ba..df642e656c 100644 --- a/common/image.c +++ b/common/image.c @@ -1279,7 +1279,7 @@ void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob) int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) { void *fdt_blob = *of_flat_tree; - void *of_start = 0; + void *of_start = NULL; char *fdt_high; ulong of_len = 0; int err; @@ -1312,7 +1312,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) of_start = (void *)(ulong) lmb_alloc_base(lmb, of_len, 0x1000, (ulong)desired_addr); - if (of_start == 0) { + if (of_start == NULL) { puts("Failed using fdt_high value for Device Tree"); goto error; } @@ -1327,7 +1327,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) + getenv_bootm_low()); } - if (of_start == 0) { + if (of_start == NULL) { puts("device tree - allocation error\n"); goto error; } @@ -1703,7 +1703,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], return 0; error: - *of_flat_tree = 0; + *of_flat_tree = NULL; *of_size = 0; return 1; } diff --git a/common/main.c b/common/main.c index 9507cec88b..592ce077d2 100644 --- a/common/main.c +++ b/common/main.c @@ -505,13 +505,13 @@ void reset_cmd_timeout(void) #define HIST_MAX 20 #define HIST_SIZE CONFIG_SYS_CBSIZE -static int hist_max = 0; -static int hist_add_idx = 0; +static int hist_max; +static int hist_add_idx; static int hist_cur = -1; -unsigned hist_num = 0; +static unsigned hist_num; -char* hist_list[HIST_MAX]; -char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ +static char *hist_list[HIST_MAX]; +static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */ #define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1) diff --git a/common/usb_storage.c b/common/usb_storage.c index 0c2a4c718f..2d92ee1bb3 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -192,7 +192,7 @@ block_dev_desc_t *usb_stor_get_dev(int index) } #endif -void usb_show_progress(void) +static void usb_show_progress(void) { debug("."); } @@ -437,7 +437,7 @@ static int usb_stor_BBB_reset(struct us_data *us) result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT * 5); + 0, us->ifnum, NULL, 0, USB_CNTL_TIMEOUT * 5); if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { USB_STOR_PRINTF("RESET:stall\n"); @@ -500,7 +500,7 @@ static int usb_stor_CB_reset(struct us_data *us) * Set up the command for a BBB device. Note that the actual SCSI * command is copied into cbw.CBWCDB. */ -int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) +static int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) { int result; int actlen; @@ -548,7 +548,7 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) /* FIXME: we also need a CBI_command which sets up the completion * interrupt, and waits for it */ -int usb_stor_CB_comdat(ccb *srb, struct us_data *us) +static int usb_stor_CB_comdat(ccb *srb, struct us_data *us) { int result = 0; int dir_in, retry; @@ -617,7 +617,7 @@ int usb_stor_CB_comdat(ccb *srb, struct us_data *us) } -int usb_stor_CBI_get_status(ccb *srb, struct us_data *us) +static int usb_stor_CBI_get_status(ccb *srb, struct us_data *us) { int timeout; @@ -626,7 +626,7 @@ int usb_stor_CBI_get_status(ccb *srb, struct us_data *us) (void *) &us->ip_data, us->irqmaxp, us->irqinterval); timeout = 1000; while (timeout--) { - if ((volatile int *) us->ip_wanted == 0) + if ((volatile int *) us->ip_wanted == NULL) break; mdelay(10); } @@ -665,18 +665,18 @@ int usb_stor_CBI_get_status(ccb *srb, struct us_data *us) #define USB_TRANSPORT_NOT_READY_RETRY 10 /* clear a stall on an endpoint - special for BBB devices */ -int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt) +static int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt) { int result; /* ENDPOINT_HALT = 0, so set value to 0 */ result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, - 0, endpt, 0, 0, USB_CNTL_TIMEOUT * 5); + 0, endpt, NULL, 0, USB_CNTL_TIMEOUT * 5); return result; } -int usb_stor_BBB_transport(ccb *srb, struct us_data *us) +static int usb_stor_BBB_transport(ccb *srb, struct us_data *us) { int result, retry; int dir_in; @@ -798,7 +798,7 @@ again: return result; } -int usb_stor_CB_transport(ccb *srb, struct us_data *us) +static int usb_stor_CB_transport(ccb *srb, struct us_data *us) { int result, status; ccb *psrb; diff --git a/common/xyzModem.c b/common/xyzModem.c index a1f955b9d7..f30b0020a3 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -100,7 +100,7 @@ static struct #ifndef REDBOOT /*SB */ typedef int cyg_int32; -int +static int CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c) { #define DELAY 20 @@ -118,7 +118,7 @@ CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c) return 0; } -void +static void CYGACC_COMM_IF_PUTC (char x, char y) { putc (y); @@ -165,7 +165,7 @@ _tolower (char c) } /* Parse (scan) a number */ -bool +static bool parse_num (char *s, unsigned long *val, char **es, char *delim) { bool first = true; -- cgit v1.2.3 From 0637059088a2579b3c0d67a5ca7d34dd7721204f Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:33 +0000 Subject: net/: sparse fixes bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips --- common/update.c | 1 + drivers/net/phy/atheros.c | 2 +- include/net.h | 9 +++++---- net/arp.c | 6 +++--- net/bootp.c | 6 +++--- net/net.c | 2 +- net/ping.h | 3 --- net/tftp.h | 3 +++ 8 files changed, 17 insertions(+), 15 deletions(-) diff --git a/common/update.c b/common/update.c index 5b1a064c29..94d6a82aeb 100644 --- a/common/update.c +++ b/common/update.c @@ -37,6 +37,7 @@ #include #include #include +#include #include /* env variable holding the location of the update file */ diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 798473dd68..9b3808bfa9 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -30,7 +30,7 @@ static int ar8021_config(struct phy_device *phydev) return 0; } -struct phy_driver AR8021_driver = { +static struct phy_driver AR8021_driver = { .name = "AR8021", .uid = 0x4dd040, .mask = 0xfffff0, diff --git a/include/net.h b/include/net.h index 35393366d3..970d4d1fab 100644 --- a/include/net.h +++ b/include/net.h @@ -102,12 +102,13 @@ extern int eth_register(struct eth_device* dev);/* Register network device */ extern int eth_unregister(struct eth_device *dev);/* Remove network device */ extern void eth_try_another(int first_restart); /* Change the device */ extern void eth_set_current(void); /* set nterface to ethcur var */ + /* get the current device MAC */ +extern struct eth_device *eth_current; + static inline __attribute__((always_inline)) struct eth_device *eth_get_dev(void) { - extern struct eth_device *eth_current; - return eth_current; } extern struct eth_device *eth_get_dev_by_name(const char *devname); @@ -517,10 +518,10 @@ enum net_loop_state { NETLOOP_SUCCESS, NETLOOP_FAIL }; +extern enum net_loop_state net_state; + static inline void net_set_state(enum net_loop_state state) { - extern enum net_loop_state net_state; - debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state); net_state = state; } diff --git a/net/arp.c b/net/arp.c index 8e1d2edd62..20c6b2d42a 100644 --- a/net/arp.c +++ b/net/arp.c @@ -27,15 +27,15 @@ #endif IPaddr_t NetArpWaitPacketIP; -IPaddr_t NetArpWaitReplyIP; +static IPaddr_t NetArpWaitReplyIP; /* MAC address of waiting packet's destination */ uchar *NetArpWaitPacketMAC; int NetArpWaitTxPacketSize; ulong NetArpWaitTimerStart; int NetArpWaitTry; -uchar *NetArpTxPacket; /* THE ARP transmit packet */ -uchar NetArpPacketBuf[PKTSIZE_ALIGN + PKTALIGN]; +static uchar *NetArpTxPacket; /* THE ARP transmit packet */ +static uchar NetArpPacketBuf[PKTSIZE_ALIGN + PKTALIGN]; void ArpInit(void) { diff --git a/net/bootp.c b/net/bootp.c index cd5c5dd1d7..4300f1c2f1 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -41,9 +41,9 @@ ulong BootpID; int BootpTry; #if defined(CONFIG_CMD_DHCP) -dhcp_state_t dhcp_state = INIT; -unsigned long dhcp_leasetime; -IPaddr_t NetDHCPServerIP; +static dhcp_state_t dhcp_state = INIT; +static unsigned long dhcp_leasetime; +static IPaddr_t NetDHCPServerIP; static void DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, unsigned len); diff --git a/net/net.c b/net/net.c index 569fec41e7..82c4cc9117 100644 --- a/net/net.c +++ b/net/net.c @@ -180,7 +180,7 @@ IPaddr_t NetNtpServerIP; int NetTimeOffset; #endif -uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN]; +static uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN]; /* Receive packet */ uchar *NetRxPackets[PKTBUFSRX]; diff --git a/net/ping.h b/net/ping.h index fd8d8d9778..8c71be4fdf 100644 --- a/net/ping.h +++ b/net/ping.h @@ -8,8 +8,6 @@ * Copyright 2000-2002 Wolfgang Denk, wd@denx.de */ -#if defined(CONFIG_CMD_PING) - #ifndef __PING_H__ #define __PING_H__ @@ -31,4 +29,3 @@ void ping_start(void); void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len); #endif /* __PING_H__ */ -#endif diff --git a/net/tftp.h b/net/tftp.h index 18e4c9c25d..2b686e3ca6 100644 --- a/net/tftp.h +++ b/net/tftp.h @@ -22,6 +22,9 @@ void TftpStart(enum proto_t protocol); /* Begin TFTP get/put */ extern void TftpStartServer(void); /* Wait for incoming TFTP put */ #endif +extern ulong TftpRRQTimeoutMSecs; +extern int TftpRRQTimeoutCountMax; + /**********************************************************************/ #endif /* __TFTP_H__ */ -- cgit v1.2.3 From 960d70c60055cbc4fbf4ce170959ecf2839bc788 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:34 +0000 Subject: drivers/net/: sparse fixes phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static? phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static? phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static? phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static? phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static? phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static? phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static? vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static? tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static? tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static? tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static? eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static? p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static? Signed-off-by: Kim Phillips --- drivers/net/fm/eth.c | 2 +- drivers/net/fm/p1023.c | 2 +- drivers/net/fm/p4080.c | 2 +- drivers/net/fm/p5020.c | 2 +- drivers/net/fm/tgec_phy.c | 10 +++++----- drivers/net/phy/phy.c | 19 ++++++++++--------- drivers/net/phy/vitesse.c | 2 +- drivers/net/vsc7385.c | 1 + 8 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 82c787bf38..54b142f47d 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -46,7 +46,7 @@ static int num_controllers; TBICR_FULL_DUPLEX | TBICR_SPEED1_SET) /* Configure the TBI for SGMII operation */ -void dtsec_configure_serdes(struct fm_eth *priv) +static void dtsec_configure_serdes(struct fm_eth *priv) { #ifdef CONFIG_SYS_FMAN_V3 u32 value; diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index 9765da5b23..387d2a382d 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -23,7 +23,7 @@ #include #include -u32 port_to_devdisr[] = { +static u32 port_to_devdisr[] = { [FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1, [FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2, }; diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 9dc6049c36..b04fd0f656 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -23,7 +23,7 @@ #include #include -u32 port_to_devdisr[] = { +static u32 port_to_devdisr[] = { [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index a7a6e43fe2..5391044833 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -23,7 +23,7 @@ #include #include -u32 port_to_devdisr[] = { +static u32 port_to_devdisr[] = { [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c index 2d349ad037..2be69d7162 100644 --- a/drivers/net/fm/tgec_phy.c +++ b/drivers/net/fm/tgec_phy.c @@ -30,8 +30,8 @@ * until the write is done before it returns. All PHY configuration has to be * done through the TSEC1 MIIM regs */ -int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, - int regnum, u16 value) +static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum, u16 value) { u32 mdio_ctl; u32 stat_val; @@ -72,8 +72,8 @@ int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, * Clears miimcom first. All PHY configuration has to be done through the * TSEC1 MIIM regs */ -int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, - int regnum) +static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, + int regnum) { u32 mdio_ctl; u32 stat_val; @@ -114,7 +114,7 @@ int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, return in_be32(®s->mdio_data) & 0xffff; } -int tgec_mdio_reset(struct mii_dev *bus) +static int tgec_mdio_reset(struct mii_dev *bus) { return 0; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index baef60f827..1ffa791dce 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -43,7 +43,7 @@ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement * hasn't changed, and > 0 if it has changed. */ -int genphy_config_advert(struct phy_device *phydev) +static int genphy_config_advert(struct phy_device *phydev) { u32 advertise; int oldadv, adv; @@ -118,7 +118,7 @@ int genphy_config_advert(struct phy_device *phydev) * Description: Configures MII_BMCR to force speed/duplex * to the values in phydev. Assumes that the values are valid. */ -int genphy_setup_forced(struct phy_device *phydev) +static int genphy_setup_forced(struct phy_device *phydev) { int err; int ctl = 0; @@ -465,7 +465,7 @@ int phy_register(struct phy_driver *drv) return 0; } -int phy_probe(struct phy_device *phydev) +static int phy_probe(struct phy_device *phydev) { int err = 0; @@ -488,7 +488,7 @@ static struct phy_driver *generic_for_interface(phy_interface_t interface) return &genphy_driver; } -struct phy_driver *get_phy_driver(struct phy_device *phydev, +static struct phy_driver *get_phy_driver(struct phy_device *phydev, phy_interface_t interface) { struct list_head *entry; @@ -505,8 +505,9 @@ struct phy_driver *get_phy_driver(struct phy_device *phydev, return generic_for_interface(interface); } -struct phy_device *phy_device_create(struct mii_dev *bus, int addr, int phy_id, - phy_interface_t interface) +static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, + int phy_id, + phy_interface_t interface) { struct phy_device *dev; @@ -549,7 +550,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr, int phy_id, * Description: Reads the ID registers of the PHY at @addr on the * @bus, stores it in @phy_id and returns zero on success. */ -int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) { int phy_reg; @@ -581,8 +582,8 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) * Description: Reads the ID registers of the PHY at @addr on the * @bus, then allocates and returns the phy_device to represent it. */ -struct phy_device *get_phy_device(struct mii_dev *bus, int addr, - phy_interface_t interface) +static struct phy_device *get_phy_device(struct mii_dev *bus, int addr, + phy_interface_t interface) { u32 phy_id = 0x1fffffff; int i; diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 0a0f40dbde..6c5cb99774 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -123,7 +123,7 @@ static int cis8204_config(struct phy_device *phydev) } /* Vitesse VSC8601 */ -int vsc8601_config(struct phy_device *phydev) +static int vsc8601_config(struct phy_device *phydev) { /* Configure some basic stuff */ #ifdef CONFIG_SYS_VSC8601_SKEWFIX diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index ada42c41f8..a5110e516d 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -16,6 +16,7 @@ #include #include #include +#include "vsc7385.h" /* * Upload a Vitesse VSC7385 firmware image to the hardware -- cgit v1.2.3 From ee820b5e5b2a4145ef2266052acd306367051d4c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:35 +0000 Subject: lib/zlib: sparse fixes define Z_NULL to (void *)0 include/u-boot/zlib.h to get rid of most of the NULL pointer warnings. inflate.c:942:1: warning: non-ANSI definition of function 'inflateEnd' inflate.c:9:1: warning: non-ANSI definition of function 'inflateReset' inflate.c:12:17: warning: Using plain integer as NULL pointer inflate.c:12:42: warning: Using plain integer as NULL pointer inflate.c:15:17: warning: Using plain integer as NULL pointer inflate.c:21:19: warning: Using plain integer as NULL pointer inflate.c:35:1: warning: non-ANSI definition of function 'inflateInit2_' inflate.c:38:20: warning: Using plain integer as NULL pointer inflate.c:41:17: warning: Using plain integer as NULL pointer inflate.c:42:17: warning: Using plain integer as NULL pointer inflate.c:50:18: warning: Using plain integer as NULL pointer inflate.c:65:23: warning: Using plain integer as NULL pointer inflate.c:69:21: warning: Using plain integer as NULL pointer inflate.c:78:1: warning: non-ANSI definition of function 'inflateInit_' inflate.c:86:1: warning: non-ANSI definition of function 'fixedtables' inflate.c:108:26: warning: Using plain integer as NULL pointer inflate.c:109:1: warning: non-ANSI definition of function 'updatewindow' inflate.c:112:30: warning: Using plain integer as NULL pointer inflate.c:339:1: warning: non-ANSI definition of function 'inflate' inflate.c:349:17: warning: Using plain integer as NULL pointer inflate.c:349:42: warning: Using plain integer as NULL pointer inflate.c:350:27: warning: Using plain integer as NULL pointer inflate.c:369:42: warning: Using plain integer as NULL pointer inflate.c:376:32: warning: Using plain integer as NULL pointer inflate.c:401:54: warning: Using plain integer as NULL pointer inflate.c:419:32: warning: Using plain integer as NULL pointer inflate.c:426:32: warning: Using plain integer as NULL pointer inflate.c:433:32: warning: Using plain integer as NULL pointer inflate.c:444:36: warning: Using plain integer as NULL pointer inflate.c:449:37: warning: Using plain integer as NULL pointer inflate.c:450:38: warning: Using plain integer as NULL pointer inflate.c:457:40: warning: Using plain integer as NULL pointer inflate.c:458:47: warning: Using plain integer as NULL pointer inflate.c:480:40: warning: Using plain integer as NULL pointer inflate.c:481:50: warning: Using plain integer as NULL pointer inflate.c:491:37: warning: Using plain integer as NULL pointer inflate.c:492:37: warning: Using plain integer as NULL pointer inflate.c:501:40: warning: Using plain integer as NULL pointer inflate.c:502:53: warning: Using plain integer as NULL pointer inflate.c:512:37: warning: Using plain integer as NULL pointer inflate.c:513:40: warning: Using plain integer as NULL pointer inflate.c:525:32: warning: Using plain integer as NULL pointer inflate.c:529:52: warning: Using plain integer as NULL pointer inflate.c:543:54: warning: Using plain integer as NULL pointer inflate.c:932:17: warning: Using plain integer as NULL pointer inflate.c:932:42: warning: Using plain integer as NULL pointer inflate.c:935:26: warning: Using plain integer as NULL pointer inflate.c:940:19: warning: Using plain integer as NULL pointer adler32.c:58:5: warning: non-ANSI definition of function 'adler32' adler32.c:81:16: warning: Using plain integer as NULL pointer zutil.c:53:9: warning: non-ANSI definition of function 'zcalloc' zutil.c:64:9: warning: non-ANSI definition of function 'zcfree' inffast.c:70:1: warning: non-ANSI definition of function 'inflate_fast' inftrees.c:33:1: warning: non-ANSI definition of function 'inflate_table' Signed-off-by: Kim Phillips --- include/u-boot/zlib.h | 2 +- lib/zlib/adler32.c | 5 +---- lib/zlib/inffast.c | 5 ++--- lib/zlib/inflate.c | 29 ++++++++--------------------- lib/zlib/inftrees.c | 10 +++------- lib/zlib/zutil.c | 10 ++-------- 6 files changed, 17 insertions(+), 44 deletions(-) diff --git a/include/u-boot/zlib.h b/include/u-boot/zlib.h index b611fe7c79..e23ceb50ca 100644 --- a/include/u-boot/zlib.h +++ b/include/u-boot/zlib.h @@ -505,7 +505,7 @@ typedef gz_header FAR *gz_headerp; #define Z_DEFLATED 8 /* The deflate compression method (the only one supported in this version) */ -#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */ +#define Z_NULL (void *)0 /* for initializing zalloc, zfree, opaque */ /* basic functions */ diff --git a/lib/zlib/adler32.c b/lib/zlib/adler32.c index dc9480d92f..b468441d73 100644 --- a/lib/zlib/adler32.c +++ b/lib/zlib/adler32.c @@ -54,10 +54,7 @@ #endif /* ========================================================================= */ -uLong ZEXPORT adler32(adler, buf, len) - uLong adler; - const Bytef *buf; - uInt len; +uLong ZEXPORT adler32(uLong adler, const Bytef *buf, uInt len) { unsigned long sum2; unsigned n; diff --git a/lib/zlib/inffast.c b/lib/zlib/inffast.c index 38f2f905e8..0700e04cb9 100644 --- a/lib/zlib/inffast.c +++ b/lib/zlib/inffast.c @@ -66,9 +66,8 @@ requires strm->avail_out >= 258 for each loop to avoid checking for output space. */ -void inflate_fast(strm, start) -z_streamp strm; -unsigned start; /* inflate()'s starting value for strm->avail_out */ +void inflate_fast(z_streamp strm, unsigned start) +/* start: inflate()'s starting value for strm->avail_out */ { struct inflate_state FAR *state; unsigned char FAR *in; /* local strm->next_in */ diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c index 1eef609de5..6411c47932 100644 --- a/lib/zlib/inflate.c +++ b/lib/zlib/inflate.c @@ -5,8 +5,7 @@ local void fixedtables OF((struct inflate_state FAR *state)); local int updatewindow OF((z_streamp strm, unsigned out)); -int ZEXPORT inflateReset(strm) -z_streamp strm; +int ZEXPORT inflateReset(z_streamp strm) { struct inflate_state FAR *state; @@ -31,11 +30,8 @@ z_streamp strm; return Z_OK; } -int ZEXPORT inflateInit2_(strm, windowBits, version, stream_size) -z_streamp strm; -int windowBits; -const char *version; -int stream_size; +int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, const char *version, + int stream_size) { struct inflate_state FAR *state; @@ -74,16 +70,12 @@ int stream_size; return inflateReset(strm); } -int ZEXPORT inflateInit_(strm, version, stream_size) -z_streamp strm; -const char *version; -int stream_size; +int ZEXPORT inflateInit_(z_streamp strm, const char *version, int stream_size) { return inflateInit2_(strm, DEF_WBITS, version, stream_size); } -local void fixedtables(state) -struct inflate_state FAR *state; +local void fixedtables(struct inflate_state FAR *state) { state->lencode = lenfix; state->lenbits = 9; @@ -105,9 +97,7 @@ struct inflate_state FAR *state; output will fall in the output data, making match copies simpler and faster. The advantage may be dependent on the size of the processor's data caches. */ -local int updatewindow(strm, out) -z_streamp strm; -unsigned out; +local int updatewindow(z_streamp strm, unsigned out) { struct inflate_state FAR *state; unsigned copy, dist; @@ -335,9 +325,7 @@ unsigned out; when flush is set to Z_FINISH, inflate() cannot return Z_OK. Instead it will return Z_BUF_ERROR if it has not reached the end of the stream. */ -int ZEXPORT inflate(strm, flush) -z_streamp strm; -int flush; +int ZEXPORT inflate(z_streamp strm, int flush) { struct inflate_state FAR *state; unsigned char FAR *next; /* next input */ @@ -938,8 +926,7 @@ int flush; return ret; } -int ZEXPORT inflateEnd(strm) -z_streamp strm; +int ZEXPORT inflateEnd(z_streamp strm) { struct inflate_state FAR *state; if (strm == Z_NULL || strm->state == Z_NULL || strm->zfree == (free_func)0) diff --git a/lib/zlib/inftrees.c b/lib/zlib/inftrees.c index c6d4c038dc..7474a52e7f 100644 --- a/lib/zlib/inftrees.c +++ b/lib/zlib/inftrees.c @@ -29,13 +29,9 @@ table index bits. It will differ if the request is greater than the longest code or if it is less than the shortest code. */ -int inflate_table(type, lens, codes, table, bits, work) -codetype type; -unsigned short FAR *lens; -unsigned codes; -code FAR * FAR *table; -unsigned FAR *bits; -unsigned short FAR *work; +int inflate_table(codetype type, unsigned short FAR *lens, unsigned codes, + code FAR * FAR *table, unsigned FAR *bits, + unsigned short FAR *work) { unsigned len; /* a code's length in bits */ unsigned sym; /* index of code symbols */ diff --git a/lib/zlib/zutil.c b/lib/zlib/zutil.c index 65f9554747..14f6eb1e07 100644 --- a/lib/zlib/zutil.c +++ b/lib/zlib/zutil.c @@ -49,10 +49,7 @@ extern voidp calloc OF((uInt items, uInt size)); extern void free OF((voidpf ptr)); #endif -voidpf zcalloc (opaque, items, size) - voidpf opaque; - unsigned items; - unsigned size; +voidpf zcalloc(voidpf opaque, unsigned items, unsigned size) { if (opaque) items += size - size; /* make compiler happy */ @@ -60,10 +57,7 @@ voidpf zcalloc (opaque, items, size) (voidpf)calloc(items, size); } -void zcfree (opaque, ptr, nb) - voidpf opaque; - voidpf ptr; - unsigned nb; +void zcfree(voidpf opaque, voidpf ptr, unsigned nb) { free(ptr); if (opaque) -- cgit v1.2.3 From 0eb257683ded98431d6c30b360b7bd37235f518d Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:36 +0000 Subject: lib/vsprintf.c: sparse fixes vsprintf.c:31:12: warning: symbol 'hex_asc' was not declared. Should it be static? vsprintf.c:398:18: warning: Using plain integer as NULL pointer Signed-off-by: Kim Phillips --- lib/vsprintf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/vsprintf.c b/lib/vsprintf.c index dd13bca5a7..b7a79c0e0c 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -28,7 +28,7 @@ /* some reluctance to put this into a new limits.h, so it is here */ #define INT_MAX ((int)(~0U>>1)) -const char hex_asc[] = "0123456789abcdef"; +static const char hex_asc[] = "0123456789abcdef"; #define hex_asc_lo(x) hex_asc[((x) & 0x0f)] #define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] @@ -395,7 +395,7 @@ static char *string(char *buf, char *end, char *s, int field_width, { int len, i; - if (s == 0) + if (s == NULL) s = ""; len = strnlen(s, precision); -- cgit v1.2.3 From 2ed2e9121f220673389e2459870a396085287325 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:37 +0000 Subject: arch/powerpc/cpu/mpc8xxx/: sparse fixes ctrl_regs.c:31:5: warning: symbol 'fsl_ddr_get_version' was not declared. Should it be static? cpu.c:135:14: warning: non-ANSI function declaration of function 'cpu_mask' cpu.c:154:18: warning: non-ANSI function declaration of function 'cpu_numcores' cpu.c:37:17: warning: symbol 'cpu_type_list' was not declared. Should it be static? cpu.c:117:17: warning: symbol 'cpu_type_unknown' was not declared. Should it be static? fsl_lbc.c:14:6: warning: symbol '__lbc_sdram_init' was not declared. Should it be static? and: lc_common_dimm_params.c:15:1: warning: symbol 'compute_cas_latency_ddr3' was not declared. Should it be static? making it static produces the following compiler warning: lc_common_dimm_params.c:15:1: warning: 'compute_cas_latency_ddr3' defined but not used [-Wunused-function] so we protect it with the preprocessor. Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc8xxx/cpu.c | 9 +++++---- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 2 +- arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 4 +++- arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 2 +- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 2c487cac20..e8613be393 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -struct cpu_type cpu_type_list [] = { +static struct cpu_type cpu_type_list[] = { #if defined(CONFIG_MPC85xx) CPU_TYPE_ENTRY(8533, 8533, 1), CPU_TYPE_ENTRY(8535, 8535, 1), @@ -125,7 +125,7 @@ u32 compute_ppc_cpumask(void) #define compute_ppc_cpumask() 1 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ -struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0); +static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0); struct cpu_type *identify_cpu(u32 ver) { @@ -143,7 +143,7 @@ struct cpu_type *identify_cpu(u32 ver) /* * Return a 32-bit mask indicating which cores are present on this SOC. */ -u32 cpu_mask() +u32 cpu_mask(void) { ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->cpu; @@ -162,7 +162,8 @@ u32 cpu_mask() /* * Return the number of cores on this SOC. */ -int cpu_numcores() { +int cpu_numcores(void) +{ struct cpu_type *cpu = gd->cpu; /* diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 5928eb8806..088cc0e855 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -28,7 +28,7 @@ #error "Undefined _DDR_ADDR" #endif -u32 fsl_ddr_get_version(void) +static u32 fsl_ddr_get_version(void) { ccsr_ddr_t *ddr; u32 ver_major_minor_errata; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 6a1f4e4e38..9adde31010 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -11,7 +11,8 @@ #include "ddr.h" -unsigned int +#if defined(CONFIG_FSL_DDR3) +static unsigned int compute_cas_latency_ddr3(const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms) @@ -65,6 +66,7 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params, return 0; } +#endif /* * compute_lowest_common_dimm_parameters() diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 023ac9ab30..c1fe5790a3 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -11,7 +11,7 @@ #ifdef CONFIG_MPC85xx /* Boards should provide their own version of this if they use lbc sdram */ -void __lbc_sdram_init(void) +static void __lbc_sdram_init(void) { /* Do nothing */ } -- cgit v1.2.3 From e56143e54f64c849340d448adb0ca5e69a08421b Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:38 +0000 Subject: powerpc/mpc85xx: sparse fixes fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static? cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static? bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart' bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write' bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write' bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio' bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write' bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write' bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec' bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect' ngpixis.c:245:1: error: directive in argument list ngpixis.c:247:1: error: directive in argument list Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 2 +- board/freescale/common/ngpixis.c | 12 ++++++++---- board/freescale/mpc8568mds/bcsr.c | 8 ++++---- board/freescale/mpc8569mds/bcsr.c | 8 ++++---- 5 files changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 736293c41d..f01804bbb9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -182,7 +182,7 @@ static void enable_cpc(void) printf("Corenet Platform Cache: %d KB enabled\n", size); } -void invalidate_cpc(void) +static void invalidate_cpc(void) { int i; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index e6b1b1b7ee..7f466ac6a9 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -489,7 +489,7 @@ static void wait_for_rstdone(unsigned int bank) } -void __soc_serdes_init(void) +static void __soc_serdes_init(void) { /* Allow for SoC-specific initialization in _serdes.c */ }; diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 276ae3c5cf..3c7502879b 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -237,13 +237,17 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -U_BOOT_CMD( - pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, - "Reset the board using the FPGA sequencer", +#ifdef CONFIG_SYS_LONGHELP +static char pixis_help_text[] = "- hard reset to default bank\n" "pixis_reset altbank - reset to alternate bank\n" #ifdef DEBUG "pixis_reset dump - display the PIXIS registers\n" #endif - "pixis_reset sysclk - reset with SYSCLK frequency(KHz)\n" + "pixis_reset sysclk - reset with SYSCLK frequency(KHz)\n"; +#endif + +U_BOOT_CMD( + pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, + "Reset the board using the FPGA sequencer", pixis_help_text ); diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c index 30676e1e1c..2a172ccdef 100644 --- a/board/freescale/mpc8568mds/bcsr.c +++ b/board/freescale/mpc8568mds/bcsr.c @@ -25,7 +25,7 @@ #include "bcsr.h" -void enable_8568mds_duart() +void enable_8568mds_duart(void) { volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); @@ -36,21 +36,21 @@ void enable_8568mds_duart() bcsr[5] |= 0x01; /* Enable Duart in BCSR*/ } -void enable_8568mds_flash_write() +void enable_8568mds_flash_write(void) { volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[9] |= 0x01; } -void disable_8568mds_flash_write() +void disable_8568mds_flash_write(void) { volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[9] &= ~(0x01); } -void enable_8568mds_qe_mdio() +void enable_8568mds_qe_mdio(void) { u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index b688e5cc73..37d0c5f9a9 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -25,17 +25,17 @@ #include "bcsr.h" -void enable_8569mds_flash_write() +void enable_8569mds_flash_write(void) { setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); } -void disable_8569mds_flash_write() +void disable_8569mds_flash_write(void) { clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); } -void enable_8569mds_qe_uec() +void enable_8569mds_qe_uec(void) { #if defined(CONFIG_SYS_UCC_RGMII_MODE) setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), @@ -60,7 +60,7 @@ void enable_8569mds_qe_uec() #endif } -void disable_8569mds_brd_eeprom_write_protect() +void disable_8569mds_brd_eeprom_write_protect(void) { clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); } -- cgit v1.2.3 From a2873bde4ceb18d2915b0ef144e16f87b88b8625 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:39 +0000 Subject: powerpc/mpc83xx: sparse fixes fdt.c:91:78: warning: Using plain integer as NULL pointer fdt.c:103:78: warning: Using plain integer as NULL pointer speed.c:55:11: warning: symbol 'corecnf_tab' was not declared. Should it be static? speed.c:519:5: warning: symbol 'do_clocks' was not declared. Should it be static? mpc8313erdb.c:73:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:74:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:75:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:76:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:79:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:80:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:81:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:82:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:85:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:86:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:87:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:88:17: warning: obsolete struct initializer, use C99 syntax Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/fdt.c | 6 ++++-- arch/powerpc/cpu/mpc83xx/speed.c | 4 ++-- board/freescale/mpc8313erdb/mpc8313erdb.c | 24 ++++++++++++------------ 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 028c8f0d58..1f54781b7e 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -88,7 +88,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 }; path = fdt_path_offset(blob, prop); - prop = fdt_getprop(blob, path, "interrupts", 0); + prop = fdt_getprop(blob, path, "interrupts", + NULL); if (prop) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); @@ -100,7 +101,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 }; path = fdt_path_offset(blob, prop); - prop = fdt_getprop(blob, path, "interrupts", 0); + prop = fdt_getprop(blob, path, "interrupts", + NULL); if (prop) fdt_setprop(blob, path, "interrupts", &tmp, sizeof(tmp)); diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index fb0f7aad6d..b8c05d1592 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -52,7 +52,7 @@ typedef struct { mult_t vco_divider; } corecnf_t; -corecnf_t corecnf_tab[] = { +static corecnf_t corecnf_tab[] = { {_byp, _byp}, /* 0x00 */ {_byp, _byp}, /* 0x01 */ {_byp, _byp}, /* 0x02 */ @@ -531,7 +531,7 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; } -int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char buf[32]; diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 730ec4e734..1071803c79 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -70,22 +70,22 @@ int checkboard(void) #ifndef CONFIG_NAND_SPL static struct pci_region pci_regions[] = { { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + .bus_start = CONFIG_SYS_PCI1_MEM_BASE, + .phys_start = CONFIG_SYS_PCI1_MEM_PHYS, + .size = CONFIG_SYS_PCI1_MEM_SIZE, + .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM + .bus_start = CONFIG_SYS_PCI1_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS, + .size = CONFIG_SYS_PCI1_MMIO_SIZE, + .flags = PCI_REGION_MEM }, { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO + .bus_start = CONFIG_SYS_PCI1_IO_BASE, + .phys_start = CONFIG_SYS_PCI1_IO_PHYS, + .size = CONFIG_SYS_PCI1_IO_SIZE, + .flags = PCI_REGION_IO } }; -- cgit v1.2.3 From 00caa7f508f37327f7d4f6ca08ffdec09e411c10 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:40 +0000 Subject: drivers/block/: sparse fixes sata_sil.c:371:7: warning: symbol 'sil_sata_rw_lba28' was not declared. Should it be static? sata_sil.c:399:7: warning: symbol 'sil_sata_rw_lba48' was not declared. Should it be static? sata_sil.c:429:6: warning: symbol 'sil_sata_cmd_flush_cache' was not declared. Should it be static? sata_sil.c:441:6: warning: symbol 'sil_sata_cmd_flush_cache_ext' was not declared. Should it be static? sata_sil.c:489:7: warning: symbol 'sata_read' was not declared. Should it be static? sata_sil.c:505:7: warning: symbol 'sata_write' was not declared. Should it be static? sata_sil.c:526:5: warning: symbol 'init_sata' was not declared. Should it be static? sata_sil.c:588:5: warning: symbol 'scan_sata' was not declared. Should it be static? fsl_sata.c:59:6: warning: symbol 'dprint_buffer' was not declared. Should it be static? fsl_sata.c:187:42: warning: incorrect type in assignment (different base types) fsl_sata.c:187:42: expected unsigned int [unsigned] [usertype] cda fsl_sata.c:187:42: got restricted __le32 [usertype] fsl_sata.c:291:6: warning: symbol 'fsl_sata_hardware_reset' was not declared. Should it be static? fsl_sata.c:418:27: warning: incorrect type in assignment (different base types) fsl_sata.c:418:27: expected unsigned int [unsigned] [usertype] dba fsl_sata.c:418:27: got restricted __le32 [usertype] fsl_sata.c:424:41: warning: incorrect type in assignment (different base types) fsl_sata.c:424:41: expected unsigned int [unsigned] [usertype] ext_c_ddc fsl_sata.c:424:41: got restricted __le32 [usertype] fsl_sata.c:431:41: warning: incorrect type in assignment (different base types) fsl_sata.c:431:41: expected unsigned int [unsigned] [usertype] ext_c_ddc fsl_sata.c:431:41: got restricted __le32 [usertype] fsl_sata.c:442:22: warning: incorrect type in assignment (different base types) fsl_sata.c:442:22: expected unsigned int [unsigned] [usertype] cda fsl_sata.c:442:22: got restricted __le32 [usertype] fsl_sata.c:446:31: warning: incorrect type in assignment (different base types) fsl_sata.c:446:31: expected unsigned int [unsigned] [usertype] prde_fis_len fsl_sata.c:446:31: got restricted __le32 [usertype] fsl_sata.c:448:22: warning: incorrect type in assignment (different base types) fsl_sata.c:448:22: expected unsigned int [unsigned] [usertype] ttl fsl_sata.c:448:22: got restricted __le32 [usertype] fsl_sata.c:460:28: warning: incorrect type in assignment (different base types) fsl_sata.c:460:28: expected unsigned int [unsigned] [usertype] attribute fsl_sata.c:460:28: got restricted __le32 [usertype] fsl_sata.c:623:6: warning: symbol 'fsl_sata_flush_cache' was not declared. Should it be static? fsl_sata.c:667:5: warning: symbol 'fsl_sata_rw_ncq_cmd' was not declared. Should it be static? fsl_sata.c:710:6: warning: symbol 'fsl_sata_flush_cache_ext' was not declared. Should it be static? fsl_sata.c:725:6: warning: symbol 'fsl_sata_software_reset' was not declared. Should it be static? fsl_sata.c:760:5: warning: symbol 'ata_low_level_rw_lba48' was not declared. Should it be static? fsl_sata.c:795:5: warning: symbol 'ata_low_level_rw_lba28' was not declared. Should it be static? the following compiler warnings show up after fixing the above, so remove those three functions: fsl_sata.c:59:13: warning: 'dprint_buffer' defined but not used [-Wunused-function] fsl_sata.c:291:13: warning: 'fsl_sata_hardware_reset' defined but not used [-Wunused-function] fsl_sata.c:726:13: warning: 'fsl_sata_software_reset' defined but not used [-Wunused-function] Other than that, the following are fixed by __iomem annotation: fsl_sata.c:84:39: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:84:39: expected unsigned int const volatile [noderef] *addr fsl_sata.c:84:39: got unsigned int volatile *addr fsl_sata.c:172:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:172:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:172:26: got unsigned int * fsl_sata.c:175:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:175:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:175:19: got unsigned int * fsl_sata.c:181:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:181:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:181:19: got unsigned int * fsl_sata.c:184:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:184:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:184:26: got unsigned int * fsl_sata.c:186:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:186:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:186:19: got unsigned int * fsl_sata.c:189:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:189:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:189:26: got unsigned int * fsl_sata.c:191:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:191:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:191:19: got unsigned int * fsl_sata.c:194:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:194:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:194:26: got unsigned int * fsl_sata.c:195:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:195:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:195:19: got unsigned int * fsl_sata.c:198:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:198:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:198:19: got unsigned int * fsl_sata.c:201:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:201:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:201:19: got unsigned int * fsl_sata.c:204:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:204:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:204:26: got unsigned int * fsl_sata.c:205:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:205:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:205:19: got unsigned int * fsl_sata.c:208:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:208:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:208:26: got unsigned int * fsl_sata.c:209:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:209:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:209:19: got unsigned int * fsl_sata.c:212:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:212:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:212:26: got unsigned int * fsl_sata.c:213:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:213:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:213:19: got unsigned int * fsl_sata.c:216:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:216:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:216:19: got unsigned int * fsl_sata.c:219:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:219:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:219:19: got unsigned int * fsl_sata.c:222:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:222:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:222:19: got unsigned int * fsl_sata.c:225:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:225:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:225:26: got unsigned int * fsl_sata.c:227:19: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:227:19: expected unsigned int volatile [noderef] *addr fsl_sata.c:227:19: got unsigned int * fsl_sata.c:242:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:242:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:242:26: got unsigned int * fsl_sata.c:256:32: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:256:32: expected unsigned int const volatile [noderef] *addr fsl_sata.c:256:32: got unsigned int * fsl_sata.c:262:26: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:262:26: expected unsigned int const volatile [noderef] *addr fsl_sata.c:262:26: got unsigned int * fsl_sata.c:274:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:274:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:274:53: got unsigned int * fsl_sata.c:275:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:275:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:275:53: got unsigned int * fsl_sata.c:276:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:276:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:276:53: got unsigned int * fsl_sata.c:277:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:277:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:277:53: got unsigned int * fsl_sata.c:278:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:278:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:278:53: got unsigned int * fsl_sata.c:279:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:279:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:279:53: got unsigned int * fsl_sata.c:280:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:280:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:280:53: got unsigned int * fsl_sata.c:281:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:281:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:281:53: got unsigned int * fsl_sata.c:282:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:282:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:282:53: got unsigned int * fsl_sata.c:283:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:283:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:283:53: got unsigned int * fsl_sata.c:284:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:284:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:284:53: got unsigned int * fsl_sata.c:285:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:285:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:285:53: got unsigned int * fsl_sata.c:286:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:286:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:286:53: got unsigned int * fsl_sata.c:287:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:287:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:287:53: got unsigned int * fsl_sata.c:288:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:288:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:288:53: got unsigned int * fsl_sata.c:289:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:289:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:289:53: got unsigned int * fsl_sata.c:290:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:290:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:290:53: got unsigned int * fsl_sata.c:291:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:291:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:291:53: got unsigned int * fsl_sata.c:292:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:292:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:292:53: got unsigned int * fsl_sata.c:293:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:293:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:293:53: got unsigned int * fsl_sata.c:294:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:294:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:294:53: got unsigned int * fsl_sata.c:295:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:295:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:295:53: got unsigned int * fsl_sata.c:296:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:296:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:296:53: got unsigned int * fsl_sata.c:297:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:297:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:297:53: got unsigned int * fsl_sata.c:298:53: warning: incorrect type in argument 1 (different address spaces) fsl_sata.c:298:53: expected unsigned int const volatile [noderef] *addr fsl_sata.c:298:53: got unsigned int * Signed-off-by: Kim Phillips --- drivers/block/fsl_sata.c | 81 +++++++----------------------------------------- drivers/block/fsl_sata.h | 13 ++++---- drivers/block/sata_sil.c | 13 ++++---- 3 files changed, 25 insertions(+), 82 deletions(-) diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index fda3389e8b..1f9d7b097c 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -56,25 +56,6 @@ static inline void sdelay(unsigned long sec) mdelay(1000); } -void dprint_buffer(unsigned char *buf, int len) -{ - int i, j; - - i = 0; - j = 0; - printf("\n\r"); - - for (i = 0; i < len; i++) { - printf("%02x ", *buf++); - j++; - if (j == 16) { - printf("\n\r"); - j = 0; - } - } - printf("\n\r"); -} - static void fsl_sata_dump_sfis(struct sata_fis_d2h *s) { printf("Status FIS dump:\n\r"); @@ -94,7 +75,7 @@ static void fsl_sata_dump_sfis(struct sata_fis_d2h *s) printf("sector_count_exp: %02x\n\r", s->sector_count_exp); } -static int ata_wait_register(volatile unsigned *addr, u32 mask, +static int ata_wait_register(unsigned __iomem *addr, u32 mask, u32 val, u32 timeout_msec) { int i; @@ -112,7 +93,7 @@ int init_sata(int dev) cmd_hdr_tbl_t *cmd_hdr; u32 cda; u32 val32; - fsl_sata_reg_t *reg; + fsl_sata_reg_t __iomem *reg; u32 sig; int i; fsl_sata_t *sata; @@ -287,42 +268,7 @@ int init_sata(int dev) return 0; } -/* Hardware reset, like Power-on and COMRESET */ -void fsl_sata_hardware_reset(u32 reg_base) -{ - fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base; - u32 scontrol; - - /* Disable the SATA interface and put PHY offline */ - scontrol = in_le32(®->scontrol); - scontrol = (scontrol & 0x0f0) | 0x304; - out_le32(®->scontrol, scontrol); - - /* No speed strict */ - scontrol = in_le32(®->scontrol); - scontrol = scontrol & ~0x0f0; - out_le32(®->scontrol, scontrol); - - /* Issue PHY wake/reset, Hardware_reset_asserted */ - scontrol = in_le32(®->scontrol); - scontrol = (scontrol & 0x0f0) | 0x301; - out_le32(®->scontrol, scontrol); - - mdelay(100); - - /* Resume PHY, COMRESET negated, the device initialize hardware - * and execute diagnostics, send good status-signature to host, - * which is D2H register FIS, and then the device enter idle state. - */ - scontrol = in_le32(®->scontrol); - scontrol = (scontrol & 0x0f0) | 0x300; - out_le32(®->scontrol, scontrol); - - mdelay(100); - return; -} - -static void fsl_sata_dump_regs(fsl_sata_reg_t *reg) +static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg) { printf("\n\rSATA: %08x\n\r", (u32)reg); printf("CQR: %08x\n\r", in_le32(®->cqr)); @@ -363,7 +309,7 @@ static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis u32 prde_count; u32 val32; u32 ttl; - fsl_sata_reg_t *reg = sata->reg_base; + fsl_sata_reg_t __iomem *reg = sata->reg_base; int i; /* Check xfer length */ @@ -620,7 +566,7 @@ static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_wr return blkcnt; } -void fsl_sata_flush_cache(int dev) +static void fsl_sata_flush_cache(int dev) { fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; struct sata_fis_h2d h2d, *cfis = &h2d; @@ -664,7 +610,8 @@ static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int i return blkcnt; } -u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write) +static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, + int is_write) { fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; struct sata_fis_h2d h2d, *cfis = &h2d; @@ -707,7 +654,7 @@ u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write return blkcnt; } -void fsl_sata_flush_cache_ext(int dev) +static void fsl_sata_flush_cache_ext(int dev) { fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; struct sata_fis_h2d h2d, *cfis = &h2d; @@ -721,12 +668,6 @@ void fsl_sata_flush_cache_ext(int dev) fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0); } -/* Software reset, set SRST of the Device Control register */ -void fsl_sata_software_reset(int dev) -{ - return; -} - static void fsl_sata_init_wcache(int dev, u16 *id) { fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; @@ -757,7 +698,7 @@ static int fsl_sata_get_flush_ext(int dev) return sata->flush_ext; } -u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt, +static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt, const void *buffer, int is_write) { u32 start, blks; @@ -792,8 +733,8 @@ u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt, return blkcnt; } -u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, const void *buffer, - int is_write) +static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, + const void *buffer, int is_write) { u32 start, blks; u8 *addr; diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h index cecff68da3..a9c27bc868 100644 --- a/drivers/block/fsl_sata.h +++ b/drivers/block/fsl_sata.h @@ -176,10 +176,11 @@ typedef struct fsl_sata_reg { * Command Header Entry */ typedef struct cmd_hdr_entry { - u32 cda; /* Command Descriptor Address, 4 bytes aligned */ - u32 prde_fis_len; /* Number of PRD entries and FIS length */ - u32 ttl; /* Total transfer length */ - u32 attribute; /* the attribute of command */ + __le32 cda; /* Command Descriptor Address, + 4 bytes aligned */ + __le32 prde_fis_len; /* Number of PRD entries and FIS length */ + __le32 ttl; /* Total transfer length */ + __le32 attribute; /* the attribute of command */ } __attribute__ ((packed)) cmd_hdr_entry_t; #define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) @@ -230,10 +231,10 @@ typedef struct cmd_hdr_tbl { * PRD entry - Physical Region Descriptor entry */ typedef struct prd_entry { - u32 dba; /* Data base address, 4 bytes aligned */ + __le32 dba; /* Data base address, 4 bytes aligned */ u32 res1; u32 res2; - u32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */ + __le32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */ } __attribute__ ((packed)) prd_entry_t; #define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry) diff --git a/drivers/block/sata_sil.c b/drivers/block/sata_sil.c index 245b872f99..b70f04de8b 100644 --- a/drivers/block/sata_sil.c +++ b/drivers/block/sata_sil.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "sata_sil.h" /* Convert sectorsize to wordsize */ @@ -369,8 +370,8 @@ static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt, return blkcnt; } -ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt, - const void *buffer, int is_write) +static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt, + const void *buffer, int is_write) { ulong start, blks, max_blks; u8 *addr; @@ -397,8 +398,8 @@ ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt, return blkcnt; } -ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt, - const void *buffer, int is_write) +static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt, + const void *buffer, int is_write) { ulong start, blks, max_blks; u8 *addr; @@ -427,7 +428,7 @@ ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt, return blkcnt; } -void sil_sata_cmd_flush_cache(int dev) +static void sil_sata_cmd_flush_cache(int dev) { struct sil_cmd_block cmdb, *pcmd = &cmdb; @@ -439,7 +440,7 @@ void sil_sata_cmd_flush_cache(int dev) sil_exec_cmd(dev, pcmd, 0); } -void sil_sata_cmd_flush_cache_ext(int dev) +static void sil_sata_cmd_flush_cache_ext(int dev) { struct sil_cmd_block cmdb, *pcmd = &cmdb; -- cgit v1.2.3 From 8121d3c5ccc2cb552ddcf7eba7be5e1196232e1c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:41 +0000 Subject: drivers/gpio/mpc83xx_gpio.c: sparse fixes mpc83xx_gpio.c:166:26: warning: non-ANSI function declaration of function 'mpc83xx_gpio_init_f' mpc83xx_gpio.c:190:26: warning: non-ANSI function declaration of function 'mpc83xx_gpio_init_r' Signed-off-by: Kim Phillips --- drivers/gpio/mpc83xx_gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/mpc83xx_gpio.c b/drivers/gpio/mpc83xx_gpio.c index a9afcb2dd6..e167852b83 100644 --- a/drivers/gpio/mpc83xx_gpio.c +++ b/drivers/gpio/mpc83xx_gpio.c @@ -163,7 +163,7 @@ int gpio_set_value(unsigned gpio, int value) } /* Configure GPIO registers early */ -void mpc83xx_gpio_init_f() +void mpc83xx_gpio_init_f(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -187,7 +187,7 @@ void mpc83xx_gpio_init_f() } /* Initialize GPIO soft-copies */ -void mpc83xx_gpio_init_r() +void mpc83xx_gpio_init_r(void) { #if MPC83XX_GPIO_CTRLRS >= 1 gpio_output_value[0] = CONFIG_MPC83XX_GPIO_0_INIT_VALUE; -- cgit v1.2.3 From c14e94e56064e35ab1b0107985b5f6dea298d5a9 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:42 +0000 Subject: drivers/input/input.c: sparse fix input.c:97:5: warning: symbol 'input_queue_ascii' was not declared. Should it be Signed-off-by: Kim Phillips Acked-by: Simon Glass --- drivers/input/input.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/input.c b/drivers/input/input.c index 98006679b3..04fa5f0bd2 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c @@ -110,7 +110,7 @@ static struct { /* Maximum number of output characters that an ANSI sequence expands to */ #define ANSI_CHAR_MAX 3 -int input_queue_ascii(struct input_config *config, int ch) +static int input_queue_ascii(struct input_config *config, int ch) { if (config->fifo_in + 1 == INPUT_BUFFER_LEN) { if (!config->fifo_out) -- cgit v1.2.3 From fdbb873eb09dcb27aeb70242c1c85fbf57764a88 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:43 +0000 Subject: drivers/mmc/mmc.c: sparse fixes mmc.c:137:5: warning: symbol 'mmc_send_cmd' was not declared. Should it be static? mmc.c:203:5: warning: symbol 'mmc_send_status' was not declared. Should it be static? mmc.c:247:5: warning: symbol 'mmc_set_blocklen' was not declared. Should it be static? mmc.c:440:5: warning: symbol 'mmc_read_blocks' was not declared. Should it be static? mmc.c:510:5: warning: symbol 'mmc_go_idle' was not declared. Should it be static? mmc.c:532:1: warning: symbol 'sd_send_op_cond' was not declared. Should it be static? mmc.c:597:5: warning: symbol 'mmc_send_op_cond' was not declared. Should it be static? mmc.c:661:5: warning: symbol 'mmc_send_ext_csd' was not declared. Should it be static? mmc.c:683:5: warning: symbol 'mmc_switch' was not declared. Should it be static? mmc.c:705:5: warning: symbol 'mmc_change_freq' was not declared. Should it be static? mmc.c:775:5: warning: symbol 'sd_switch' was not declared. Should it be static? mmc.c:796:5: warning: symbol 'sd_change_freq' was not declared. Should it be static? mmc.c:935:6: warning: symbol 'mmc_set_ios' was not declared. Should it be static? mmc.c:953:6: warning: symbol 'mmc_set_bus_width' was not declared. Should it be static? mmc.c:1108:26: warning: dubious: !x & y mmc.c:960:5: warning: symbol 'mmc_startup' was not declared. Should it be static? mmc.c:1243:5: warning: symbol 'mmc_send_if_cond' was not declared. Should it be s Signed-off-by: Kim Phillips --- drivers/mmc/mmc.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 5fbf956302..5ffd8c59e6 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -47,7 +47,8 @@ int __board_mmc_getcd(struct mmc *mmc) { int board_mmc_getcd(struct mmc *mmc)__attribute__((weak, alias("__board_mmc_getcd"))); -int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) { struct mmc_data backup; int ret; @@ -108,7 +109,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) return ret; } -int mmc_send_status(struct mmc *mmc, int timeout) +static int mmc_send_status(struct mmc *mmc, int timeout) { struct mmc_cmd cmd; int err, retries = 5; @@ -152,7 +153,7 @@ int mmc_send_status(struct mmc *mmc, int timeout) return 0; } -int mmc_set_blocklen(struct mmc *mmc, int len) +static int mmc_set_blocklen(struct mmc *mmc, int len) { struct mmc_cmd cmd; @@ -345,7 +346,8 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) return blkcnt; } -int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt) +static int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, + lbaint_t blkcnt) { struct mmc_cmd cmd; struct mmc_data data; @@ -415,7 +417,7 @@ static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst) return blkcnt; } -int mmc_go_idle(struct mmc* mmc) +static int mmc_go_idle(struct mmc *mmc) { struct mmc_cmd cmd; int err; @@ -436,8 +438,7 @@ int mmc_go_idle(struct mmc* mmc) return 0; } -int -sd_send_op_cond(struct mmc *mmc) +static int sd_send_op_cond(struct mmc *mmc) { int timeout = 1000; int err; @@ -502,7 +503,7 @@ sd_send_op_cond(struct mmc *mmc) return 0; } -int mmc_send_op_cond(struct mmc *mmc) +static int mmc_send_op_cond(struct mmc *mmc) { int timeout = 10000; struct mmc_cmd cmd; @@ -566,7 +567,7 @@ int mmc_send_op_cond(struct mmc *mmc) } -int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) +static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) { struct mmc_cmd cmd; struct mmc_data data; @@ -588,7 +589,7 @@ int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) } -int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) { struct mmc_cmd cmd; int timeout = 1000; @@ -610,7 +611,7 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) } -int mmc_change_freq(struct mmc *mmc) +static int mmc_change_freq(struct mmc *mmc) { ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, 512); char cardtype; @@ -680,7 +681,7 @@ int mmc_getcd(struct mmc *mmc) return cd; } -int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) +static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) { struct mmc_cmd cmd; struct mmc_data data; @@ -701,7 +702,7 @@ int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) } -int sd_change_freq(struct mmc *mmc) +static int sd_change_freq(struct mmc *mmc) { int err; struct mmc_cmd cmd; @@ -840,7 +841,7 @@ static const int multipliers[] = { 80, }; -void mmc_set_ios(struct mmc *mmc) +static void mmc_set_ios(struct mmc *mmc) { mmc->set_ios(mmc); } @@ -858,14 +859,14 @@ void mmc_set_clock(struct mmc *mmc, uint clock) mmc_set_ios(mmc); } -void mmc_set_bus_width(struct mmc *mmc, uint width) +static void mmc_set_bus_width(struct mmc *mmc, uint width) { mmc->bus_width = width; mmc_set_ios(mmc); } -int mmc_startup(struct mmc *mmc) +static int mmc_startup(struct mmc *mmc) { int err, width; uint mult, freq; @@ -1013,7 +1014,7 @@ int mmc_startup(struct mmc *mmc) if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { /* check ext_csd version and capacity */ err = mmc_send_ext_csd(mmc, ext_csd); - if (!err & (ext_csd[EXT_CSD_REV] >= 2)) { + if (!err && (ext_csd[EXT_CSD_REV] >= 2)) { /* * According to the JEDEC Standard, the value of * ext_csd's capacity is valid if the value is more @@ -1148,7 +1149,7 @@ int mmc_startup(struct mmc *mmc) return 0; } -int mmc_send_if_cond(struct mmc *mmc) +static int mmc_send_if_cond(struct mmc *mmc) { struct mmc_cmd cmd; int err; -- cgit v1.2.3 From eafa90a16cb518ad3dad858d1782f9f816164fcc Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:44 +0000 Subject: drivers/mmc/fsl_esdhc.c: sparse fixes fsl_esdhc.c:71:6: warning: symbol 'esdhc_xfertyp' was not declared. Should it be static? fsl_esdhc.c:413:6: warning: symbol 'set_sysctl' was not declared. Should it be st Signed-off-by: Kim Phillips --- drivers/mmc/fsl_esdhc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 3f8d30db4c..301dd8c7b9 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -68,7 +68,7 @@ struct fsl_esdhc { }; /* Return the XFERTYP flags for a given command and data packet */ -uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) +static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) { uint xfertyp = 0; @@ -410,7 +410,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) return 0; } -void set_sysctl(struct mmc *mmc, uint clock) +static void set_sysctl(struct mmc *mmc, uint clock) { int sdhc_clk = gd->sdhc_clk; int div, pre_div; -- cgit v1.2.3 From 11dc40107915a81c92596fa18d188cbf4a3c5254 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:45 +0000 Subject: drivers/mtd/cfi_flash.c: sparse fixes cfi_flash.c:756:43: warning: Using plain integer as NULL pointer cfi_flash.c:1150:52: warning: cast to non-scalar cfi_flash.c:1433:46: warning: cast truncates bits from constant value (890089 becomes 89) cfi_flash.c:1490:61: warning: cast truncates bits from constant value (1f001f becomes 1f) cfi_flash.c:1508:61: warning: cast truncates bits from constant value (10001 becomes 1) cfi_flash.c:1738:63: warning: cast truncates bits from constant value (10001 becomes 1) cfi_flash.c:1857:6: warning: symbol '__flash_cmd_reset' was not declared. Should it be static? Signed-off-by: Kim Phillips --- drivers/mtd/cfi_flash.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 43140f3647..b2dfc5369d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -752,8 +752,8 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) */ static flash_sect_t find_sector (flash_info_t * info, ulong addr) { - static flash_sect_t saved_sector = 0; /* previously found sector */ - static flash_info_t *saved_info = 0; /* previously used flash bank */ + static flash_sect_t saved_sector; /* previously found sector */ + static flash_info_t *saved_info; /* previously used flash bank */ flash_sect_t sector = saved_sector; if ((info != saved_info) || (sector >= info->sector_count)) @@ -1147,8 +1147,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } if (use_flash_status_poll(info)) { - cfiword_t cword = (cfiword_t)0xffffffffffffffffULL; + cfiword_t cword; void *dest; + cword.ll = 0xffffffffffffffffULL; dest = flash_map(info, sect, 0); st = flash_status_poll(info, &cword, dest, info->erase_blk_tout, "erase"); @@ -1430,8 +1431,8 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) { - if ((info->manufacturer_id == (uchar)INTEL_MANUFACT) && - (info->device_id == NUMONYX_256MBIT)) { + if (info->manufacturer_id == ((INTEL_MANUFACT & FLASH_VENDMASK) >> 16) + && info->device_id == NUMONYX_256MBIT) { /* * see errata called * "Numonyx Axcell P33/P30 Specification Update" :) @@ -1487,7 +1488,8 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: /* U-Boot only checks the first byte */ - if (info->manufacturer_id == (uchar)ATM_MANUFACT) { + if (info->manufacturer_id == + ((ATM_MANUFACT & FLASH_VENDMASK) >> 16)) { if (prot) { flash_unlock_seq (info, 0); flash_write_cmd (info, 0, @@ -1505,7 +1507,8 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) 0, ATM_CMD_UNLOCK_SECT); } } - if (info->manufacturer_id == (uchar)AMD_MANUFACT) { + if (info->manufacturer_id == + ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) { int flag = disable_interrupts(); int lock_flag; @@ -1735,7 +1738,8 @@ static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); #ifdef CONFIG_SYS_FLASH_PROTECTION - if (info->ext_addr && info->manufacturer_id == (uchar)AMD_MANUFACT) { + if (info->ext_addr && info->manufacturer_id == + ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) { ushort spus; /* read sector protect/unprotect scheme */ @@ -1854,7 +1858,7 @@ static void flash_read_cfi (flash_info_t *info, void *buf, p[i] = flash_read_uchar(info, start + i); } -void __flash_cmd_reset(flash_info_t *info) +static void __flash_cmd_reset(flash_info_t *info) { /* * We do not yet know what kind of commandset to use, so we issue -- cgit v1.2.3 From 7d2ab9ae4e3a3eac81cf88d752a0cdedb70bd534 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:46 +0000 Subject: drivers/mtd/nand: sparse fixes nand_ecc.c:82:5: warning: symbol 'nand_calculate_ecc' was not declared. Should it be static? nand_ecc.c:155:5: warning: symbol 'nand_correct_data' was not declared. Should it be static? nand_base.c:2854:1: error: directive in argument list nand_base.c:2856:1: error: directive in argument list Signed-off-by: Kim Phillips Acked-by: Scott Wood --- drivers/mtd/nand/nand_base.c | 13 +++++++------ drivers/mtd/nand/nand_ecc.c | 1 + 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 71f5027889..d3b71a50ad 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2601,6 +2601,7 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, int *maf_id, int *dev_id, const struct nand_flash_dev *type) { + const char *name; int i, maf_idx; u8 id_data[8]; int ret; @@ -2848,14 +2849,14 @@ ident_done: chip->cmdfunc = nand_command_lp; /* TODO onfi flash name */ - MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:" - " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id, - nand_manuf_ids[maf_idx].name, + name = type->name; #ifdef CONFIG_SYS_NAND_ONFI_DETECTION - chip->onfi_version ? chip->onfi_params.model : type->name); -#else - type->name); + if (chip->onfi_version) + name = chip->onfi_params.model; #endif + MTDDEBUG(MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:" + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id, + nand_manuf_ids[maf_idx].name, name); return type; } diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c index 81f0e0812b..097cf625b8 100644 --- a/drivers/mtd/nand/nand_ecc.c +++ b/drivers/mtd/nand/nand_ecc.c @@ -39,6 +39,7 @@ #include #include +#include /* The PPC4xx NDFC uses Smart Media (SMC) bytes order */ #ifdef CONFIG_NAND_NDFC -- cgit v1.2.3 From ac63f2a2ecb24e309c2ca3b7b4c91b1941d3038b Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 29 Oct 2012 13:34:47 +0000 Subject: drivers/serial/serial_ns16550.c: sparse fixes Signed-off-by: Kim Phillips --- drivers/serial/serial_ns16550.c | 42 ++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 4176e257e0..bf280baab2 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -78,21 +78,33 @@ static NS16550_t serial_ports[4] = { /* Multi serial device functions */ #define DECLARE_ESERIAL_FUNCTIONS(port) \ - static int eserial##port##_init (void) {\ - int clock_divisor; \ - clock_divisor = calc_divisor(serial_ports[port-1]); \ - NS16550_init(serial_ports[port-1], clock_divisor); \ - return(0);}\ - static void eserial##port##_setbrg (void) {\ - serial_setbrg_dev(port);}\ - static int eserial##port##_getc (void) {\ - return serial_getc_dev(port);}\ - static int eserial##port##_tstc (void) {\ - return serial_tstc_dev(port);}\ - static void eserial##port##_putc (const char c) {\ - serial_putc_dev(port, c);}\ - static void eserial##port##_puts (const char *s) {\ - serial_puts_dev(port, s);} + static int eserial##port##_init(void) \ + { \ + int clock_divisor; \ + clock_divisor = calc_divisor(serial_ports[port-1]); \ + NS16550_init(serial_ports[port-1], clock_divisor); \ + return 0 ; \ + } \ + static void eserial##port##_setbrg(void) \ + { \ + serial_setbrg_dev(port); \ + } \ + static int eserial##port##_getc(void) \ + { \ + return serial_getc_dev(port); \ + } \ + static int eserial##port##_tstc(void) \ + { \ + return serial_tstc_dev(port); \ + } \ + static void eserial##port##_putc(const char c) \ + { \ + serial_putc_dev(port, c); \ + } \ + static void eserial##port##_puts(const char *s) \ + { \ + serial_puts_dev(port, s); \ + } /* Serial device descriptor */ #define INIT_ESERIAL_STRUCTURE(port, __name) { \ -- cgit v1.2.3 From 57a87a25f7563158d2b8a83d782568f1e6fc7fc5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 31 Oct 2012 13:30:41 +0000 Subject: usb gadget ether: Fix warning in is_eth_addr_valid() The gadget ethernet driver needs to keep copies of the MAC address (at both endpoints) as strings so it needs a custom function for validation of the MAC. It was not however performing a totally correct check and also was emitting a warning about a set but unused variable. The solution to both is that after checking the string contents we use the standard test for a valid MAC. Cc: Joe Hershberger Cc: Marek Vasut Signed-off-by: Tom Rini Acked-by: Joe Hershberger --- drivers/usb/gadget/ether.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 1e187e5b52..8b24e00e27 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -1978,8 +1978,8 @@ static int is_eth_addr_valid(char *str) p = q; } - if (i == 6) /* it looks ok */ - return 1; + /* Now check the contents. */ + return is_valid_ether_addr(ea); } return 0; } -- cgit v1.2.3 From 619dd5de69bc506e4f4607aa1e698b2fd61b99fe Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 Nov 2012 06:38:43 +0000 Subject: patman: Add additional tags to ignore The BRANCH= tag can be used to indicate the destination branch for a commit. Ignore this tag. Also ignore the gerrit 'Commit-Ready:' tag. Signed-off-by: Simon Glass --- tools/patman/patchstream.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index ad280cc46c..f7ee75a25f 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -30,8 +30,8 @@ import gitutil from series import Series # Tags that we detect and remove -re_remove = re.compile('^BUG=|^TEST=|^Change-Id:|^Review URL:' - '|Reviewed-on:|Reviewed-by:') +re_remove = re.compile('^BUG=|^TEST=|^BRANCH=|^Change-Id:|^Review URL:' + '|Reviewed-on:|Reviewed-by:|Commit-Ready:') # Lines which are allowed after a TEST= line re_allowed_after_test = re.compile('^Signed-off-by:') -- cgit v1.2.3 From 3ae7b240ad8c723d02aa79654220a07049b7ae4d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Nov 2012 11:44:08 -0700 Subject: Prepare v2013.01-rc1 Signed-off-by: Tom Rini --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 2fe149045b..bc15209c7c 100644 --- a/Makefile +++ b/Makefile @@ -21,9 +21,9 @@ # MA 02111-1307 USA # -VERSION = 2012 -PATCHLEVEL = 10 -SUBLEVEL = +VERSION = 2013 +PATCHLEVEL = 01 +SUBLEVEL = -rc1 EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) -- cgit v1.2.3 From a6e8dcaf350fe8e780e29c57ececfece039725c7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 4 Nov 2012 17:50:54 -0700 Subject: Makefile: use EXTRAVERSION for -rc? tag When using SUBLEVEL for the -rc? tag, this results in an ugly version string like "2013.01.-rc1" - let's use EXTRAVERSION instead to get the simple "2013.01-rc1" Signed-off-by: Wolfgang Denk Signed-off-by: Tom Rini --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index bc15209c7c..e144eb13ca 100644 --- a/Makefile +++ b/Makefile @@ -23,8 +23,8 @@ VERSION = 2013 PATCHLEVEL = 01 -SUBLEVEL = -rc1 -EXTRAVERSION = +SUBLEVEL = +EXTRAVERSION = -rc1 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else -- cgit v1.2.3 From 548ce4bf7690420dc50aa36172d920d2895a698e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Sep 2012 14:42:38 +0200 Subject: microblaze: Fix compilation warning in ext2_find_next_zero_bit ext2_find_next_zero_bit must be also static if __swab32 is also static. Warning: include/asm/bitops.h:369:22: warning: '__fswab32' is static but used in inline function 'ext2_find_next_zero_bit' which is not static [enabled by default] Signed-off-by: Michal Simek Acked-by: Stephan Linz --- arch/microblaze/include/asm/bitops.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h index e8c835f7c0..eafa2b576b 100644 --- a/arch/microblaze/include/asm/bitops.h +++ b/arch/microblaze/include/asm/bitops.h @@ -319,7 +319,8 @@ extern __inline__ int ext2_test_bit(int nr, const volatile void * addr) #define ext2_find_first_zero_bit(addr, size) \ ext2_find_next_zero_bit((addr), (size), 0) -extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +static inline unsigned long ext2_find_next_zero_bit(void *addr, + unsigned long size, unsigned long offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; -- cgit v1.2.3 From ea0122816c6467c7ede80744363624c41822c93f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Sep 2012 15:24:51 +0200 Subject: microblaze: Fix byteorder for microblaze Just remove ancient code. Signed-off-by: Michal Simek Acked-by: Stephan Linz Reviewed-by: Marek Vasut --- arch/microblaze/include/asm/byteorder.h | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/arch/microblaze/include/asm/byteorder.h b/arch/microblaze/include/asm/byteorder.h index b2757a41f8..f3a471d1b2 100644 --- a/arch/microblaze/include/asm/byteorder.h +++ b/arch/microblaze/include/asm/byteorder.h @@ -20,29 +20,6 @@ #ifdef __GNUC__ -/* This is effectively a dupe of the arch-independent byteswap - code in include/linux/byteorder/swab.h, however we force a cast - of the result up to 32 bits. This in turn forces the compiler - to explicitly clear the high 16 bits, which it wasn't doing otherwise. - - I think this is a symptom of a bug in mb-gcc. JW 20040303 -*/ - - -static __inline__ __u16 ___arch__swab16 (__u16 half_word) -{ - /* 32 bit temp to cast result, forcing clearing of high word */ - __u32 temp; - - temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8); - - return (__u16) temp; -} - -#define __arch__swab16(x) ___arch__swab16(x) - -/* Microblaze has no arch-specific endian conversion insns */ - #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ -- cgit v1.2.3 From 5811830fae92cf0a3bb11ead54ef1267464a1280 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Sep 2012 10:13:35 +0200 Subject: microblaze: Flush caches before enabling them Flushing caches is necessary because of soft reset which doesn't clear caches. Signed-off-by: Michal Simek Reviewed-by: Marek Vasut --- arch/microblaze/cpu/cache.c | 5 ----- arch/microblaze/cpu/start.S | 6 ++++++ arch/microblaze/lib/bootm.c | 5 ----- include/configs/microblaze-generic.h | 4 ++++ 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index d258a69382..ce066b96e9 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -61,12 +61,7 @@ void dcache_enable (void) { void dcache_disable(void) { #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif MSRCLR(0x80); } diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8564c4e30a..3da711d4d5 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -132,6 +132,12 @@ _start: rsubi r8, r10, 0x26 sh r6, r0, r8 + /* Flush cache before enable cache */ + addik r5, r0, 0 + addik r6, r0, XILINX_DCACHE_BYTE_SIZE +flush: bralid r15, flush_cache + nop + /* enable instruction and data cache */ mfs r12, rmsr ori r12, r12, 0xa0 diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 95cee509d2..66d21f4ef6 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -70,12 +70,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima #endif #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif /* * Linux Kernel Parameters (passing device tree): diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 721cd906ad..eed38c165f 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -287,6 +287,10 @@ # undef CONFIG_DCACHE #endif +#ifndef XILINX_DCACHE_BYTE_SIZE +#define XILINX_DCACHE_BYTE_SIZE 32768 +#endif + /* * BOOTP options */ -- cgit v1.2.3 From f8c1ed092c828b51683873c0c79acc44b27eb8e9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 7 Nov 2012 15:25:39 +0100 Subject: microblaze: Remove asm/bitops.h from asm/posix_types.h The patch "include/linux/byteorder: import latest endian definitions from linux" (sha1: eef1cf2d5cf1cae5fb76713e912263dedf110aeb) Introduced a lot of compilation failures with unknow types. include/linux/byteorder/big_endian.h:45:1: error: unknown type name '__le64' include/linux/byteorder/big_endian.h: In function '__cpu_to_le64p': include/linux/byteorder/big_endian.h:47:18: error: '__le64' undeclared (first use in this function) include/linux/byteorder/big_endian.h:47:18: note: each undeclared identifier is reported only once for each function it appears in include/linux/byteorder/big_endian.h:47:25: error: expected ';' before '__swab64p' include/linux/byteorder/big_endian.h: At top level: include/linux/byteorder/big_endian.h:49:1: error: unknown type name '__le64' include/linux/byteorder/big_endian.h:53:1: error: unknown type name '__le32' include/linux/byteorder/big_endian.h: In function '__cpu_to_le32p': include/linux/byteorder/big_endian.h:55:18: error: '__le32' undeclared (first use in this function) include/linux/byteorder/big_endian.h:55:25: error: expected ';' before '__swab32p' include/linux/byteorder/big_endian.h: At top level: include/linux/byteorder/big_endian.h:57:1: error: unknown type name '__le32' include/linux/byteorder/big_endian.h:61:1: error: unknown type name '__le16' ... Removing asm/bitops.h solved this problem. Signed-off-by: Michal Simek --- arch/microblaze/include/asm/posix_types.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/microblaze/include/asm/posix_types.h b/arch/microblaze/include/asm/posix_types.h index 9a2cc663ec..38dc5aa85d 100644 --- a/arch/microblaze/include/asm/posix_types.h +++ b/arch/microblaze/include/asm/posix_types.h @@ -16,9 +16,6 @@ #ifndef __MICROBLAZE_POSIX_TYPES_H__ #define __MICROBLAZE_POSIX_TYPES_H__ -#include - - typedef unsigned int __kernel_dev_t; typedef unsigned long __kernel_ino_t; typedef unsigned long long __kernel_ino64_t; -- cgit v1.2.3 From b3e5cd17f6e180642efafb20bcda948c3cbcff10 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Sep 2012 14:24:05 +0200 Subject: microblaze: Fix compilation failure because of missing libdts Microblaze platform can use CONFIG_OF_EMBED option but also it is necessary to support boards which don't want to use this option. U-Boot doesn't compile dts/libdts.o for #undef CONFIG_OF_EMBED case that's why it should be guarded by ifdef. Signed-off-by: Michal Simek --- arch/microblaze/cpu/u-boot.lds | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 4297b93443..fe3d97dad8 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -45,7 +45,9 @@ SECTIONS .data ALIGN(0x4): { __data_start = .; +#ifdef CONFIG_OF_EMBED dts/libdts.o (.data) +#endif *(.data) __data_end = .; } -- cgit v1.2.3 From 22b6fcb50d06ee281a338e78f8d0a7c9ddee8629 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 8 Nov 2012 12:40:17 +0100 Subject: common/command.c: revert changes from commit 199adb60 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 199adb601ff34bdbbd0667fac80dfe0a87bffc2b "common/misc: sparse fixes" broke the help command trying to fix the sparse error "command.c:44:38: error: bad constant expression". As Henrik points out, the fix was bad because the commit used CONFIG_SYS_MAXARGS whereas the code intended to use the maximum number of commands (not arguments to a command). Revert command.c changes to the original code as asked by Wolfgang. Reported-by: Henrik Nordström Signed-off-by: Anatolij Gustschin --- common/command.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/common/command.c b/common/command.c index f51df26bf9..50c84292c1 100644 --- a/common/command.c +++ b/common/command.c @@ -40,15 +40,8 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int int i; int rcode = 0; - if (cmd_items > CONFIG_SYS_MAXARGS) { - printf("%s: cmd_items %d exceeds hardcoded limit %d." - " Recompile with higher CONFIG_SYS_MAXARGS?\n", - __func__, cmd_items, CONFIG_SYS_MAXARGS); - return -1; - } - if (argc == 1) { /*show list of commands */ - cmd_tbl_t *cmd_array[CONFIG_SYS_MAXARGS]; + cmd_tbl_t *cmd_array[cmd_items]; int i, j, swaps; /* Make array of commands from .uboot_cmd section */ -- cgit v1.2.3