From 3c1274e4347c1326f61191808aa2d3139e6007cd Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Wed, 10 Apr 2024 11:58:31 +0200 Subject: arm: k3: j784s4: Fix call to spl_enable_dcache by calling spl_enable_cache Since commit [1] spl_enable_dcache is no more available and, at the same time, by enabling instruction cache, boot time is reduced. [1] 536d0d5eef24 ("arm: k3: Enable instruction cache for main domain SPL") Upstream-Status: Inappropriate Commit [1] is already upstreamed. am62p5 and j784s4 were introduced afterwards and they are using the new function. Signed-off-by: Emanuele Ghidoli --- arch/arm/mach-k3/am62p5_init.c | 2 +- arch/arm/mach-k3/j784s4_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c index 08ad6cfee1..8ce92d506f 100644 --- a/arch/arm/mach-k3/am62p5_init.c +++ b/arch/arm/mach-k3/am62p5_init.c @@ -184,7 +184,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - spl_enable_dcache(); + spl_enable_cache(); debug("am62px_init: %s done\n", __func__); } diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4_init.c index af0f46e2ab..a9c3f52394 100644 --- a/arch/arm/mach-k3/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4_init.c @@ -240,7 +240,7 @@ void board_init_f(ulong dummy) } } - spl_enable_dcache(); + spl_enable_cache(); } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) -- cgit v1.2.3