From 3456a4958ec2ecb2b2e35b1f37039fb28274f182 Mon Sep 17 00:00:00 2001 From: Scott Sweeny Date: Wed, 1 Sep 2010 12:02:01 -0400 Subject: Freescale board patch for MPC5125_TWR board --- 5121e_nand_loader_program | Bin 0 -> 9409 bytes Makefile | 33 +- add-uboot-head | Bin 0 -> 6172 bytes board/ads5121/ads5121.c | 299 ++++++-- board/ads5121/ads5121_diu.c | 11 +- board/ads5125/Makefile | 56 ++ board/ads5125/ads5125.c | 515 ++++++++++++++ board/ads5125/config.mk | 28 + board/ads5125/u-boot.lds | 122 ++++ board/freescale/common/fsl_diu_fb.c | 170 ++++- board/freescale/common/fsl_logo_bmp.c | 4 + common/cmd_fdt.c | 2 +- common/cmd_ide.c | 16 + common/cmd_nvedit.c | 23 +- common/cmd_pci.c | 11 + common/cmd_yaffs2.c | 10 +- common/env_common.c | 11 +- common/env_nand.c | 67 +- config.mk | 26 + cpu/mpc512x/cpu.c | 11 +- cpu/mpc512x/iopin.c | 25 +- cpu/mpc512x/serial.c | 15 +- cpu/mpc512x/start.S | 46 +- drivers/mtd/nand/Makefile | 3 + drivers/mtd/nand/fsl_nfc_nand.c | 1104 +++++++++++++++++++++++++++++ drivers/mtd/nand/fsl_nfc_nand_5125.c | 919 ++++++++++++++++++++++++ drivers/mtd/nand/mpc5125_nfc_mtc.mtc | Bin 0 -> 18720 bytes drivers/mtd/nand/mpc5125_nfc_struct.h | 27 + drivers/mtd/nand/nand_base.c | 14 +- drivers/mtd/nand/nand_ids.c | 3 + drivers/net/mpc512x_fec.c | 65 +- fs/yaffs2/yaffscfg.c | 4 +- include/asm-ppc/global_data.h | 2 +- include/asm-ppc/immap_512x.h | 83 ++- include/configs/ads5121.h | 170 +++-- include/configs/ads5125.h | 650 +++++++++++++++++ include/linux/mtd/compat.h | 2 +- include/linux/mtd/mtd-abi.h | 2 +- include/linux/mtd/mtd.h | 4 +- include/linux/mtd/nand.h | 4 +- include/mpc5125_nfc.h | 357 ++++++++++ include/mpc512x.h | 307 +++++++- lib_ppc/Makefile | 5 +- lib_ppc/board.c | 109 ++- lib_ppc/bootm.c | 5 + lib_ppc/sil9022init.mtc | Bin 0 -> 34220 bytes nand_flash_program | Bin 0 -> 8240 bytes nand_load_program | Bin 0 -> 8999 bytes nand_program_block1_uboot | Bin 0 -> 7759 bytes nand_spl/board/ads5125/Makefile | 93 +++ nand_spl/board/ads5125/config.mk | 233 ++++++ nand_spl/board/ads5125/dram.h | 101 +++ nand_spl/board/ads5125/nandload.h | 16 + nand_spl/board/ads5125/nandload.mtc | Bin 0 -> 5924 bytes nand_spl/board/ads5125/nandstart.S | 299 ++++++++ nand_spl/board/ads5125/nfc.h | 122 ++++ nand_spl/board/ads5125/u-boot.lds | 52 ++ net/eth.c | 13 + net/net.c | 2 +- onenand_ipl/board/apollon/low_levelinit.S | 205 ------ 60 files changed, 6057 insertions(+), 419 deletions(-) create mode 100644 5121e_nand_loader_program create mode 100644 add-uboot-head create mode 100644 board/ads5125/Makefile create mode 100644 board/ads5125/ads5125.c create mode 100644 board/ads5125/config.mk create mode 100644 board/ads5125/u-boot.lds create mode 100644 drivers/mtd/nand/fsl_nfc_nand.c create mode 100644 drivers/mtd/nand/fsl_nfc_nand_5125.c create mode 100644 drivers/mtd/nand/mpc5125_nfc_mtc.mtc create mode 100644 drivers/mtd/nand/mpc5125_nfc_struct.h create mode 100644 include/configs/ads5125.h create mode 100644 include/mpc5125_nfc.h create mode 100644 lib_ppc/sil9022init.mtc create mode 100644 nand_flash_program create mode 100644 nand_load_program create mode 100644 nand_program_block1_uboot create mode 100644 nand_spl/board/ads5125/Makefile create mode 100644 nand_spl/board/ads5125/config.mk create mode 100644 nand_spl/board/ads5125/dram.h create mode 100644 nand_spl/board/ads5125/nandload.h create mode 100644 nand_spl/board/ads5125/nandload.mtc create mode 100644 nand_spl/board/ads5125/nandstart.S create mode 100644 nand_spl/board/ads5125/nfc.h create mode 100644 nand_spl/board/ads5125/u-boot.lds delete mode 100644 onenand_ipl/board/apollon/low_levelinit.S diff --git a/5121e_nand_loader_program b/5121e_nand_loader_program new file mode 100644 index 0000000000..bdc329283d Binary files /dev/null and b/5121e_nand_loader_program differ diff --git a/Makefile b/Makefile index 61bae6d2ac..c13428f4e9 100644 --- a/Makefile +++ b/Makefile @@ -148,7 +148,7 @@ ifeq ($(HOSTARCH),$(ARCH)) CROSS_COMPILE = else ifeq ($(ARCH),ppc) -CROSS_COMPILE = ppc_8xx- +CROSS_COMPILE = powerpc-e300c3-linux-gnu- endif ifeq ($(ARCH),arm) CROSS_COMPILE = arm-linux- @@ -287,6 +287,9 @@ SUBDIRS = tools \ ifeq ($(CONFIG_NAND_U_BOOT),y) NAND_SPL = nand_spl U_BOOT_NAND = $(obj)u-boot-nand.bin +ifndef NAND_PAD_SIZE +NAND_PAD_SIZE = 16k +endif endif ifeq ($(CONFIG_ONENAND_U_BOOT),y) @@ -300,13 +303,14 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) ######################################################################### ######################################################################### -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) +ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) $(obj)u-boot-second.bin $(obj)u-boot-second-scrip.txt $(obj)u-boot-scrip.txt ifeq ($(ARCH),blackfin) ALL += $(obj)u-boot.ldr endif all: $(ALL) + $(obj)u-boot.hex: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ @@ -335,6 +339,14 @@ $(obj)u-boot.img: $(obj)u-boot.bin $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin +$(obj)u-boot-second.bin:$(obj)u-boot.bin + $(PWD)/add-uboot-head $< $@ + +$(obj)u-boot-second-scrip.txt:$(obj)u-boot-second.bin + $(PWD)/nand_program_block1_uboot $< $@ +$(obj)u-boot-scrip.txt:$(obj)u-boot.bin + $(PWD)/nand_flash_program $< $@ + $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@ @@ -364,7 +376,7 @@ $(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C nand_spl/board/$(BOARDDIR) all $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin + cat $(obj)nand_spl/u-boot-spl-$(NAND_PAD_SIZE).bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin $(ONENAND_IPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all @@ -799,6 +811,21 @@ ads5121_rev2_config \ fi @$(MKCONFIG) -a ads5121 ppc mpc512x ads5121 +ads5125_config \ + : unconfig + @mkdir -p $(obj)include + @$(MKCONFIG) -a ads5125 ppc mpc512x ads5125 + +ads5125_nand_config \ + : unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/ads5125 + @mkdir -p $(obj)nand_spl/board/ads5125 + echo "TEXT_BASE = 0x01000000" > $(obj)board/ads5125/config.tmp ; + echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h ; + @$(MKCONFIG) -a ads5125 ppc mpc512x ads5125 + echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; + echo "NAND_PAD_SIZE = 2k" >> $(obj)include/config.mk; ######################################################################### ## MPC8xx Systems diff --git a/add-uboot-head b/add-uboot-head new file mode 100644 index 0000000000..3f6f84f04a Binary files /dev/null and b/add-uboot-head differ diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 6c40e94416..9c1270dcc4 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -1,6 +1,8 @@ /* * (C) Copyright 2007 DENX Software Engineering * + * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -24,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -36,10 +39,11 @@ DECLARE_GLOBAL_DATA_PTR; /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ CLOCK_SCCR1_PSCFIFO_EN | \ CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_FEC1_EN | \ CLOCK_SCCR1_PATA_EN | \ CLOCK_SCCR1_PCI_EN | \ CLOCK_SCCR1_TPR_EN) @@ -52,6 +56,12 @@ DECLARE_GLOBAL_DATA_PTR; #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) +/* Defines used to Exit Self Refresh after Hibernation */ +#define DDRC_CCR_CLOCK_ON_CMD 0x00001CFF; /* Clock ON */ +#define DDRC_CCR_CKE_HIGH_CMD 0x00003CFF; /* cke high and 200 NOP delay */ +#define DDRC_CCR_SR_CMD 0x00004200; /* Send a Self Refresh */ +#define DDRC_CCR_CMD_MODE_CMD 0x000038FF; /* Set to Normal Mode */ + long int fixed_sdram(void); int board_early_init_f (void) @@ -111,6 +121,40 @@ int board_early_init_f (void) return 0; } +u32 is_micron(void){ + + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + char *mac, *end, macaddr[6]; + u32 brddate, macchk, ismicron; + u32 i; + + /* + * MAC address has serial number with date of manufacture + * Boards made before Nov-08 #1180 use Micron memory; + * 001e59 is the STx vendor # + */ + ismicron = 0; + if (brd_rev >= 0x0400 && (mac = getenv("ethaddr"))) { + for (i=0; i<6; i++) { + macaddr[i] = mac ? + simple_strtoul (mac, &end, 16) : 0; + if (mac) + mac = (*end) ? end+1 : end; + } + brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; + macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; + debug("brddate = %d\n\t",brddate); + + if (macchk == 0x001e59 && brddate <= 8111180) + ismicron = 1; + } else if (brd_rev < 0x400) { + ismicron = 1; + } + debug("Using %s Memory settings\n\t", + ismicron ? "Micron" : "Elpida"); + return(ismicron); +} + phys_size_t initdram (int board_type) { u32 msize = 0; @@ -120,13 +164,103 @@ phys_size_t initdram (int board_type) return msize; } +/* + * hibernation_check -- Check if the board is hibernating and has a kernel + * sleeping in RAM. If so jump there. + */ +void hibernation_check(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + void (*hib_wkup_fnptr)(void); + volatile u32 reg; + u32 use_micron; + +#if DEBUG + printf("RTC_KAR -0x%x\n", im->rtc.kar); +#endif /* DEBUG END */ +#define RTC_KAR_BC6 (1 << 8) + if (im->rtc.kar & RTC_KAR_BC6) { + + printf("\nComing out of Hibernate !\n"); + reg = im->rtc.kar; + + /* setting the DIS_HIB mode bit */ + reg |= 0x00000080; + /* Clear OFF only the WU_SRC sticky Bits */ + reg &= 0xFFFFFFF9; + + /* Writing back to KAR, this will clear the Sticky bit */ + im->rtc.kar = reg; + + /* Disabling the wake-up sources and BC6 bit used for + * Hibernation. + */ + im->rtc.kar &= 0xE0FF02F9; + + use_micron = is_micron(); + + /* Initialize MDDRC */ + if (use_micron) { + im->mddrc.ddr_sys_config = (MDDRC_SYS_CFG_MICRON & + ~(MDDRC_SYS_CFG_CLK_BIT | + MDDRC_SYS_CFG_CKE_BIT)); /* CMD MODE */ + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_MICRON; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_MICRON; + } else { + im->mddrc.ddr_sys_config = (MDDRC_SYS_CFG_ELPIDA & + ~(MDDRC_SYS_CFG_CLK_BIT | + MDDRC_SYS_CFG_CKE_BIT)); /* CMD MODE */ + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_ELPIDA; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_ELPIDA; + } + + /* Bringing the DDR out of Self-Refresh State */ + /* Clock ON */ + im->mddrc.ddr_compact_command = DDRC_CCR_CLOCK_ON_CMD; + __asm__ __volatile__ ("sync"); + /* cke high and 200 NOP delay */ + im->mddrc.ddr_compact_command = DDRC_CCR_CKE_HIGH_CMD; + __asm__ __volatile__ ("sync"); + /* Send a Self Refresh */ + im->mddrc.ddr_compact_command = DDRC_CCR_SR_CMD; + __asm__ __volatile__ ("sync"); + /* Set to Normal Mode */ + im->mddrc.ddr_compact_command = DDRC_CCR_CMD_MODE_CMD; + __asm__ __volatile__ ("sync"); + + /* Start MDDRC */ + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0_RUN; + + if (use_micron) + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON_RUN; + else + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA_RUN; + + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("sync"); + + hib_wkup_fnptr = *((void **)0x00000000); + + if (hib_wkup_fnptr != NULL) + hib_wkup_fnptr(); + else { + printf("func pointer is NULL!! returning to normal uboot intialisation\n"); + return; + } + } +} + /* * fixed sdram init -- the board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ long int fixed_sdram (void) { + u32 use_micron = 0; volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2 (msize); u32 i; @@ -147,68 +281,105 @@ long int fixed_sdram (void) __asm__ __volatile__ ("isync"); /* Enable DDR */ - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN; + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_EN; /* Initialize DDR Priority Manager */ - im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1; - im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2; - im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG; - im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU; - im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML; - im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU; - im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML; - im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU; - im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML; - im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU; - im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML; - im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU; - im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML; - im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU; - im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL; - im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU; - im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL; - im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU; - im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL; - im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU; - im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL; - im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU; - im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL; + im->mddrc.prioman_config1 = MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = MDDRCGRP_LUT0_MU; + im->mddrc.lut_table0_main_lower = MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_upper = MDDRCGRP_LUT1_MU; + im->mddrc.lut_table1_main_lower = MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_upper = MDDRCGRP_LUT2_MU; + im->mddrc.lut_table2_main_lower = MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_upper = MDDRCGRP_LUT3_MU; + im->mddrc.lut_table3_main_lower = MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_upper = MDDRCGRP_LUT4_MU; + im->mddrc.lut_table4_main_lower = MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = MDDRCGRP_LUT0_AU; + im->mddrc.lut_table0_alternate_lower = MDDRCGRP_LUT0_AL; + im->mddrc.lut_table1_alternate_upper = MDDRCGRP_LUT1_AU; + im->mddrc.lut_table1_alternate_lower = MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_upper = MDDRCGRP_LUT2_AU; + im->mddrc.lut_table2_alternate_lower = MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_upper = MDDRCGRP_LUT3_AU; + im->mddrc.lut_table3_alternate_lower = MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_upper = MDDRCGRP_LUT4_AU; + im->mddrc.lut_table4_alternate_lower = MDDRCGRP_LUT4_AL; + + /* This function will not return if system was hibernating */ + hibernation_check(); + + /* determine which memory settings to use Micron or Elpida */ + use_micron = is_micron(); /* Initialize MDDRC */ - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG; - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; - im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1; - im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2; + if (use_micron) { + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_MICRON; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_MICRON; + } else { + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = MDDRC_TIME_CFG1_ELPIDA; + im->mddrc.ddr_time_config2 = MDDRC_TIME_CFG2_ELPIDA; + } /* Initialize DDR */ for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - + im->mddrc.ddr_command = DDR_NOP; + + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_NOP; + + if (use_micron) { + /* Micron init sequence */ + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_NOP; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_EM3; + im->mddrc.ddr_command = DDR_EN_DLL; + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = MICRON_INIT_DEV_OP; + udelay(200); + } else { + /* Elpida init -works for Micron too but runs more slowly */ + im->mddrc.ddr_command = DDR_EM2; + im->mddrc.ddr_command = DDR_EM3; + im->mddrc.ddr_command = DDR_EN_DLL; + im->mddrc.ddr_command = DDR_RES_DLL; + im->mddrc.ddr_command = DDR_PCHG_ALL; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = DDR_RFSH; + im->mddrc.ddr_command = ELPIDA_INIT_DEV_OP; + udelay(200); + } + im->mddrc.ddr_command = DDR_OCD_DEFAULT; + im->mddrc.ddr_command = DDR_OCD_EXIT; + im->mddrc.ddr_command = DDR_NOP; + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = DDR_NOP; /* Start MDDRC */ - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN; - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN; + im->mddrc.ddr_time_config0 = MDDRC_TIME_CFG0_RUN; + + if (use_micron) + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_MICRON_RUN; + else + im->mddrc.ddr_sys_config = MDDRC_SYS_CFG_ELPIDA_RUN; return msize; } @@ -225,17 +396,21 @@ int misc_init_r(void) i2c_set_bus_num(2); tmp_val = 0xBF; i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); +#if DEBUG /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n", tmp_val); +#endif tmp_val = 0x10; i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); +#if DEBUG /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n", tmp_val); +#endif #ifdef CONFIG_FSL_DIU_FB #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) @@ -430,3 +605,17 @@ int ide_preinit (void) } #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ + +#if defined(CONFIG_NAND_FSL_NFC) +void ads5121_fsl_nfc_board_cs(int chip) +{ + unsigned char *csreg = (unsigned char *)CONFIG_SYS_CPLD_BASE + 0x09; + u8 v; + + v = in_8(csreg); + v |= 0xf; + v &= ~(1<= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) { @@ -79,6 +81,7 @@ char *valid_bmp(char *addr) return 0; } else return (char *)h_addr; +#endif } int ads5121_diu_init(void) @@ -87,8 +90,8 @@ int ads5121_diu_init(void) char *bmp = NULL; char *bmp_env; - xres = 1024; - yres = 768; + xres = 1280; + yres = 720; pixel_format = 0x88883316; debug("ads5121_diu_init\n"); diff --git a/board/ads5125/Makefile b/board/ads5125/Makefile new file mode 100644 index 0000000000..c6e3488030 --- /dev/null +++ b/board/ads5125/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +$(shell mkdir -p $(OBJTREE)/board/freescale/common) + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-${CONFIG_FSL_DIU_FB} += ../ads5121/ads5121_diu.o +COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o +COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ads5125/ads5125.c b/board/ads5125/ads5125.c new file mode 100644 index 0000000000..2bc5a46e5f --- /dev/null +++ b/board/ads5125/ads5125.c @@ -0,0 +1,515 @@ +/* + * (C) Copyright 2008 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#undef DEBUG +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_MISC_INIT_R +#include +#endif + +/* PSC Clocks in use */ +#ifdef CONFIG_PSC_CONSOLE2 +#define CLOCK_SCCR1_PSC_EN_BITS ( \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE2) \ + ) +#else +#define CLOCK_SCCR1_PSC_EN_BITS CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) +#endif + +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PSC_EN_BITS | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC1_EN | \ + CLOCK_SCCR1_TPR_EN) +#define SCCR1_CFG1_CLOCKS_EN (CLOCK_SCCR1_FEC2_EN) + + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_I2C_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_SDHC1_EN) + +#define SCCR2_CFG0_CLOCKS_EN (CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_DIU_EN) + +#define SCCR2_CFG1_CLOCKS_EN (CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_USB2_EN) + +#define CSAW_START(start) ((start) & 0xFFFF0000) +#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) + +long int fixed_sdram(void); + +static iopin_t ioregs_common_init[] = { + + /* FUNC3=LPC_CS2 Sets Next 3 to LPC pads - done in start.S since + it's CPLD and catch22 here...must read what CFG switch is set + { + IO_CTRL_LPC_AX03, 3, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } */ + /* FUNC1=PSC9_3 Sets Next 2 to PSC9 pads x4f & x50*/ + { + IO_CTRL_I2C1_SCL, 2, 0, + IO_PIN_FMUX(1) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO14 Sets 1 pad */ + { + IO_CTRL_PSC_MCLK_IN, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=IRQ0 Sets 1 pad */ + { + IO_CTRL_PSC1_1, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=CKSTP_OUT Sets 1 pad */ + { + IO_CTRL_PSC1_4, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=I2C1_SCL Sets Next 2 to I2C1 pads */ + { + IO_CTRL_J1850_TX, 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* ORs all pads to highest slew rate*/ + { + IO_CTRL_LPC_CLK, IO_CTRL_PSC1_4 - IO_CTRL_LPC_CLK +1, 1, + IO_PIN_FMUX(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; +static iopin_t ioregs_cfg0_init[] = { + /* FUNC2=DIU_LD00 Sets Next 2 to DIU pads */ + { + IO_CTRL_DIU_LD00, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + }, + /* FUNC2=DIU_LD08 Sets Next 2 to DIU pads */ + { + IO_CTRL_DIU_LD08, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + }, + /* FUNC2=DIU_LD16 Sets Next 2 to DIU pads */ + { + IO_CTRL_DIU_LD16, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + }, + /* FUNC2=FEC2_RXD_1 Sets Next 12 to FEC2 pads */ + { + IO_CTRL_USB1_DATA0, 12, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) + } +}; + +static iopin_t ioregs_cfg1_init[] = { + /* FUNC2=USB1_DATA0 Sets Next 4 to USB1 pads */ + { + IO_CTRL_DIU_CLK, 4, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO32 Sets 1 (2 ??) pad */ + { + IO_CTRL_DIU_LD00, 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB1_DATA4 Sets Next 6 to USB1 pads */ + { + IO_CTRL_DIU_LD02, 6, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO37 Sets 2 to GPIO pads */ + { + IO_CTRL_DIU_LD08, 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB1_NEXT Sets Next 6 to USB1 and USB2 pads */ + { + IO_CTRL_DIU_LD10, 6, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=I2C3_SCL Sets Next 2 to I2C3 pads */ + { + IO_CTRL_DIU_LD16, 8, 0, + IO_PIN_FMUX(1) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB2_DATA4 Sets Next 8 to USB2 pads */ + { + IO_CTRL_DIU_LD18, 8, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=FEC2_RXD_1 Sets Next 12 to FEC2 pads */ + { + IO_CTRL_USB1_DATA0, 12, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } + /* FUNC3=GPIO10 Sets 1 pad -- COL unused in RMII?? + { + IO_CTRL_USB1_DIR, 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } */ +}; +int board_early_init_f (void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 lpcaw; + + + /* + * Initialize Local Window for the CPLD registers access (CS2 selects + * the CPLD chip) + */ +/* + out_be32(&im->sysconf.lpcs2aw, CSAW_START(CONFIG_SYS_CPLD_BASE) | + CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)); + out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); +*/ + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lpcaw = in_be32(&im->sysconf.lpcs2aw); + __asm__ __volatile__ ("isync"); + + /* + * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control + * + * Without this the flash identification routine fails, as it needs to issue + * write commands in order to establish the device ID. + */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { + out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); + } else { + /* running from Backup flash */ + out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); + } +#endif + /* + * Configure Flash Speed + */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); + out_be32((u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG),CONFIG_SYS_CS_ALETIMING); +#endif + /* + * Enable clocks + */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + if (IS_CFG1_SWITCH) { + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN | SCCR1_CFG1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN | SCCR2_CFG1_CLOCKS_EN); + } else { + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN | SCCR2_CFG0_CLOCKS_EN); + } +#else + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN | SCCR1_CFG1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN | SCCR2_CFG1_CLOCKS_EN); +#endif + /* initialize function mux & slew rate IO inter alia on IO Pins */ + /* there are two peripheral options controlled by switch 8 */ +#if (BOARD_TYPE==BOARD_TYPE_ADS5125) + if (IS_CFG1_SWITCH) + iopin_initialize(ioregs_cfg1_init, + sizeof(ioregs_cfg1_init) / sizeof(ioregs_cfg1_init[0])); + else +#endif + iopin_initialize(ioregs_cfg0_init, + sizeof(ioregs_cfg0_init) / sizeof(ioregs_cfg0_init[0])); + + iopin_initialize(ioregs_common_init, + sizeof(ioregs_common_init) / sizeof(ioregs_common_init[0])); + + /* enable default pins */ + out_8(&im->io_ctrl.regs[IO_CTRL_GBOBE], IOCTRL_GBOBE_ON); + /*enable nfc_ce2 Cloudy*/ + out_8(&im->io_ctrl.regs[IO_CTRL_LPC_ACK_B], 0x3b); + return 0; +} + +phys_size_t initdram (int board_type) +{ + u32 msize = 0; + + msize = fixed_sdram (); + + return msize; +} + +/* + * fixed sdram init -- the board doesn't use memory modules that have serial presence + * detect or similar mechanism for discovery of the DRAM settings + */ +long int fixed_sdram (void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; +#if ( BOARD_TYPE!=BOARD_TYPE_5125_MPU) + u32 msize_log2 = __ilog2 (msize); + u32 i; + + /* Initialize IO Control */ + out_8(&im->io_ctrl.regs[IO_CTRL_MEM], IOCTRL_MUX_DDR); + + /* Initialize DDR Local Window */ + out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); + out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + i = im->sysconf.ddrlaw.ar; + __asm__ __volatile__ ("isync"); + + /* Enable DDR */ + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); + + /* Initialize DDR Priority Manager */ + out_be32(&im->mddrc.prioman_config1, MDDRCGRP_PM_CFG1); + out_be32(&im->mddrc.prioman_config2, MDDRCGRP_PM_CFG2); + out_be32(&im->mddrc.hiprio_config, MDDRCGRP_HIPRIO_CFG); + out_be32(&im->mddrc.lut_table0_main_upper, MDDRCGRP_LUT0_MU); + out_be32(&im->mddrc.lut_table0_main_lower, MDDRCGRP_LUT0_ML); + out_be32(&im->mddrc.lut_table1_main_upper, MDDRCGRP_LUT1_MU); + out_be32(&im->mddrc.lut_table1_main_lower, MDDRCGRP_LUT1_ML); + out_be32(&im->mddrc.lut_table2_main_upper, MDDRCGRP_LUT2_MU); + out_be32(&im->mddrc.lut_table2_main_lower, MDDRCGRP_LUT2_ML); + out_be32(&im->mddrc.lut_table3_main_upper, MDDRCGRP_LUT3_MU); + out_be32(&im->mddrc.lut_table3_main_lower, MDDRCGRP_LUT3_ML); + out_be32(&im->mddrc.lut_table4_main_upper, MDDRCGRP_LUT4_MU); + out_be32(&im->mddrc.lut_table4_main_lower, MDDRCGRP_LUT4_ML); + out_be32(&im->mddrc.lut_table0_alternate_upper, MDDRCGRP_LUT0_AU); + out_be32(&im->mddrc.lut_table0_alternate_lower, MDDRCGRP_LUT0_AL); + out_be32(&im->mddrc.lut_table1_alternate_upper, MDDRCGRP_LUT1_AU); + out_be32(&im->mddrc.lut_table1_alternate_lower, MDDRCGRP_LUT1_AL); + out_be32(&im->mddrc.lut_table2_alternate_upper, MDDRCGRP_LUT2_AU); + out_be32(&im->mddrc.lut_table2_alternate_lower, MDDRCGRP_LUT2_AL); + out_be32(&im->mddrc.lut_table3_alternate_upper, MDDRCGRP_LUT3_AU); + out_be32(&im->mddrc.lut_table3_alternate_lower, MDDRCGRP_LUT3_AL); + out_be32(&im->mddrc.lut_table4_alternate_upper, MDDRCGRP_LUT4_AU); + out_be32(&im->mddrc.lut_table4_alternate_lower, MDDRCGRP_LUT4_AL); + + /* Initialize MDDRC */ + out_be32(&im->mddrc.ddr_time_config0, MDDRC_SYS_CFG); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, MDDRC_TIME_CFG1); + out_be32(&im->mddrc.ddr_time_config2, MDDRC_TIME_CFG2); + /* Initialize DDR */ + for (i = 0; i < 10; i++) + out_be32(&im->mddrc.ddr_command,DDR_NOP); + udelay(1); + out_be32(&im->mddrc.ddr_command,DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_EM2); + out_be32(&im->mddrc.ddr_command,DDR_EM3); + out_be32(&im->mddrc.ddr_command,DDR_EN_DLL); + out_be32(&im->mddrc.ddr_command,DDR_RES_DLL); + out_be32(&im->mddrc.ddr_command,DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_NOP); + out_be32(&im->mddrc.ddr_command,DDR_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command,DDR_PCHG_ALL); + for (i = 0; i < 5; i++) + out_be32(&im->mddrc.ddr_command,DDR_RFSH); + out_be32(&im->mddrc.ddr_command,DDR_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command,DDR_OCD_EXIT); + for (i = 0; i < 5; i++) + out_be32(&im->mddrc.ddr_command,DDR_NOP); + udelay(10); + /* Start MDDRC */ + out_be32(&im->mddrc.ddr_time_config0,MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_RUN); +#endif + return msize; +} +#ifdef CONFIG_MISC_INIT_R +struct i2c_init_struct{ + u8 reg_addr; + u8 data; +}; +extern void OnHdmiCableConnected(void); +int misc_init_r(void) +{ + u8 tmp_val; + + extern int ads5121_diu_init(void); +#if(BOARD_TYPE!=BOARD_TYPE_5125_MPU) + if (IS_CFG1_SWITCH) /* no diu in CFG1 */ + return 0; + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + + if (IS_CFG1_SWITCH){ + /* turn on ??? */ + i2c_set_bus_num(2); + } else { + /* Using this for DIU init before the driver in linux takes over + * Enable the TFP410 Encoder (I2C address 0x38) + */ + + i2c_set_bus_num(1); + tmp_val = 0xBF; + i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + + tmp_val = 0x10; + i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + } +#endif +#ifdef CONFIG_FSL_DIU_FB +#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) + ads5121_diu_init(); +#endif +#endif +#endif +#if(BOARD_TYPE == BOARD_TYPE_5125_MPU ) +#if (HDMI_CHIP_SELECT==HDMI_CHIP_SIL9034) + /*sil9034 enable */ + struct i2c_init_struct i2c_data[6]= + { + {0x08,0x36}, + {0x0c,0x03}, + {0x0f,0x04}, + {0x33,0x30}, + {0x34,0x00}, + {0x08,0x37}, + }; + for(tmp_val=0;tmp_valbi_memstart, (u64)bd->bi_memsize); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + + +#if defined(CONFIG_NAND_FSL_NFC) +void ads5125_fsl_nfc_board_cs(int chip) +{ +#if(BOARD_TYPE==BOARD_TYPE_ADS5125) + unsigned char *csreg = (unsigned char *)(CONFIG_SYS_CPLD_BASE + 0x09); + u8 v; + printf("ads5125_fsl_nfc_board_cs chip=%d\n",chip); + v = in_8(csreg); + v |= 0xf; + v &= ~(1<> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 2fc878be8a..bc0cf2e897 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -22,7 +22,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include #include #include @@ -70,7 +69,82 @@ static struct fb_videomode fsl_diu_mode_1024 = { .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .vmode = FB_VMODE_NONINTERLACED }; +static struct fb_videomode fsl_diu_mode_1024_768_26 = { + .refresh = 26, + .xres = 1024, + .yres = 768, + .pixclock = 36644, + .left_margin = 144, + .right_margin = 144, + .upper_margin = 16, + .lower_margin = 16, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_640_480 = { + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock =39682, + .left_margin = 80, + .right_margin = 80, + .upper_margin =23, + .lower_margin = 22, + .hsync_len =20 , + .vsync_len =13, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_videomode fsl_diu_mode_800_600_42= { + .refresh = 42, + .xres = 800, + .yres = 600, + .pixclock =36849, + .left_margin = 112, + .right_margin = 112, + .upper_margin =16, + .lower_margin = 15, + .hsync_len =20 , + .vsync_len =13, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_720x576= { + .refresh = 60, + .xres = 720, + .yres = 576, + .pixclock =27997, + .left_margin = 106, + .right_margin = 106, + .upper_margin =30, + .lower_margin = 30, + .hsync_len =20 , + .vsync_len =13, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_720x480= { + .refresh = 60, + .xres = 720, + .yres = 480, + .pixclock =37000, + .left_margin = 62, + .right_margin = 16, + .upper_margin =32, + .lower_margin = 10, + .hsync_len =60 , + .vsync_len =3, + .sync = 0, + //.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; static struct fb_videomode fsl_diu_mode_1280 = { .name = "1280x1024-60", .refresh = 60, @@ -86,7 +160,51 @@ static struct fb_videomode fsl_diu_mode_1280 = { .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .vmode = FB_VMODE_NONINTERLACED }; - +static struct fb_videomode fsl_diu_mode_1280x720 = { + .name = "1280x720-50", + .refresh = 50, + .xres = 1280, + .yres = 720, + .pixclock = 13468, + .left_margin = 440, + .right_margin = 40, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 220, + .vsync_len = 20, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_1280x720_60 = { + .name = "1280x720-60", + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13468, + .left_margin = 40, + .right_margin = 110, + .upper_margin = 5, + .lower_margin = 5, + .hsync_len = 220, + .vsync_len = 20, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; +static struct fb_videomode fsl_diu_mode_800x600_60 = { + .name = "800x600-60", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 24996, + .left_margin = 88, + .right_margin = 40, + .upper_margin = 23, + .lower_margin = 1, + .hsync_len = 128, + .vsync_len = 4, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; /* * These are the fields of area descriptor(in DDR memory) for every plane */ @@ -190,7 +308,25 @@ static int fsl_diu_enable_panel(struct fb_info *info); static int fsl_diu_disable_panel(struct fb_info *info); static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align); void diu_set_pixel_clock(unsigned int pixclock); +#ifdef CONFIG_ADS5125 +#include +#define CONFIG_SYS_IOCTL_ADDR CONFIG_SYS_IMMR+0xA000 +static void mpc5125_cfg_LCD_iopad_init(void) +{ + printf("mpc5125_cfg_LCD_iopad_init\n"); + out_8(CONFIG_SYS_IOCTL_ADDR+0x33,0x43); /* AB9 DIU_LD00*/ + out_8(CONFIG_SYS_IOCTL_ADDR+0x34,0x43); /* Y10 DIU_LD01*/ + + out_8(CONFIG_SYS_IOCTL_ADDR+0x3b,0x43); /* W13 DIU_LD08*/ + out_8(CONFIG_SYS_IOCTL_ADDR+0x3c,0x43); /* AB12 DIU_LD09*/ + + out_8(CONFIG_SYS_IOCTL_ADDR+0x43,0x43); /* AB15 DIU_LD16*/ + out_8(CONFIG_SYS_IOCTL_ADDR+0x44,0x43); /* AB16 DIU_LD17*/ + +} +#endif + int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix, @@ -203,7 +339,9 @@ int fsl_diu_init(int xres, struct fb_var_screeninfo *var = &info->var; unsigned char *gamma_table_base; unsigned int i, j; - +#ifdef CONFIG_ADS5125 + mpc5125_cfg_LCD_iopad_init(); +#endif debug("Enter fsl_diu_init\n"); dr.diu_reg = (struct diu *) (CONFIG_SYS_DIU_ADDR); hw = (struct diu *) dr.diu_reg; @@ -211,9 +349,10 @@ int fsl_diu_init(int xres, disable_lcdc(); if (xres == 1280) { - fsl_diu_mode_db = &fsl_diu_mode_1280; + fsl_diu_mode_db = &fsl_diu_mode_1280x720_60; } else { - fsl_diu_mode_db = &fsl_diu_mode_1024; + + fsl_diu_mode_db = &fsl_diu_mode_720x480; } if (0 == fb_initialized) { @@ -324,7 +463,7 @@ int fsl_diu_init(int xres, var->vsync_len << 11 | /* PW_V */ var->lower_margin; /* FP_V */ - hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ + hw->syn_pol = 3; /* SYNC SIGNALS POLARITY */ hw->thresholds = 0x00037800; /* The Thresholds */ hw->int_status = 0; /* INTERRUPT STATUS */ hw->int_mask = 0; /* INT MASK */ @@ -506,6 +645,23 @@ int fsl_diu_display_bmp(unsigned char *bmp, return 0; } if (bpp < 24) { + if(ncolors==0) + { + switch(bpp) + { + case 1: + ncolors=2; + break; + case 4: + ncolors=16; + break; + case 8: + ncolors=256; + break; + default: + break; + } + } for (i = 0, offset = 54; i < ncolors; i++, offset += 4) palette[i] = (bmp[offset+2] << 16) + (bmp[offset+1] << 8) + bmp[offset]; @@ -547,7 +703,7 @@ int fsl_diu_display_bmp(unsigned char *bmp, for (y = height - 1; y >= 0; y--) { fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); for (x = 0; x < width; x++) { - *fb_t++ = palette[ *bitmap++ ]; + *fb_t++ = palette[ *bitmap++ ]|0xff000000; } for (i = (width / 2) % 4; i > 0; i--) bitmap++; diff --git a/board/freescale/common/fsl_logo_bmp.c b/board/freescale/common/fsl_logo_bmp.c index 956dbee9da..ac5a155f78 100644 --- a/board/freescale/common/fsl_logo_bmp.c +++ b/board/freescale/common/fsl_logo_bmp.c @@ -27,6 +27,9 @@ * A 340x128x4bpp BMP logo. *--------------------------------------------------------------------------- */ + #if 1 + unsigned int FSL_Logo_BMP[]={}; + #else unsigned int FSL_Logo_BMP[] = { 0x424d765c, 0x00000000,0x00007600,0x00002800,0x00006c01,0x00008000,0x00000100,0x04000000, @@ -876,3 +879,4 @@ unsigned int FSL_Logo_BMP[] = { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, 0x00000000,0x0000babe }; + #endif diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 0947b72d20..20f5238bf5 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -55,7 +55,7 @@ void set_working_fdt_addr(void *addr) char buf[17]; working_fdt = addr; - + sprintf(buf, "%lx", (unsigned long)addr); setenv("fdtaddr", buf); } diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 7f04577f5f..1b66b17509 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -185,10 +185,26 @@ static void set_pcmcia_timing (int pmode); /* ------------------------------------------------------------------------- */ +#ifdef CONFIG_FASTBOOT +int ide_init_skipped; +#endif + int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int rcode = 0; +#ifdef CONFIG_FASTBOOT + if (ide_init_skipped) { + ide_init_skipped = 0; +#ifdef CONFIG_IDE_8xx_PCCARD + puts ("PCMCIA:"); +#else + puts ("IDE: "); +#endif + ide_init(); + } +#endif + switch (argc) { case 0: case 1: diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 68c673e7cc..a5cee7b03c 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -192,13 +192,16 @@ int _do_setenv (int flag, int argc, char *argv[]) /* Allow serial# forced overwrite with 0xdeaf4add flag */ ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || #else - (strcmp (name, "serial#") == 0) || + (strcmp (name, "serial#") == 0) #endif +#if 0 ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) #endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */ - ) ) { + ) +#endif + ) { printf ("Can't overwrite \"%s\"\n", name); return 1; } @@ -551,7 +554,22 @@ int getenv_r (char *name, char *buf, unsigned len) } return (-1); } +#if(BOARD_TYPE==BOARD_TYPE_5125_MPU) +int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + extern char * env_name_spec; + + printf ("Saving Environment to %s...\n", env_name_spec); + + return (saveenv() ? 1 : 0); +} +U_BOOT_CMD( + saveenv, 1, 0, do_saveenv, + "save environment variables to persistent storage", + NULL +); +#else #if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -570,6 +588,7 @@ U_BOOT_CMD( ); #endif +#endif /************************************************************************ diff --git a/common/cmd_pci.c b/common/cmd_pci.c index 4a9317f16c..ef57533f5c 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -37,6 +37,10 @@ unsigned char ShortPCIListing = 1; +#ifdef CONFIG_FASTBOOT +int pci_init_skipped; +#endif + /* * Follows routines for the output of infos about devices on PCI bus. */ @@ -477,6 +481,13 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) pci_dev_t bdf = 0; char cmd = 's'; +#ifdef CONFIG_FASTBOOT + if (pci_init_skipped) { + pci_init_skipped = 0; + pci_init(); + } +#endif + if (argc > 1) cmd = argv[1][0]; diff --git a/common/cmd_yaffs2.c b/common/cmd_yaffs2.c index c47ea769fe..0f2ccecfef 100644 --- a/common/cmd_yaffs2.c +++ b/common/cmd_yaffs2.c @@ -139,7 +139,15 @@ int do_ydump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("yaffs_DumpDevStruct returning error when dumping path: , %s\n", dirname); return 0; } - +int mtdparts_init(void) +{ + return -1; +} +int find_dev_and_part(const char *id, struct mtd_device **dev, + u8 *part_num, struct part_info **part) +{ + return 1; +} U_BOOT_CMD( ymount, 3, 0, do_ymount, "mount yaffs", diff --git a/common/env_common.c b/common/env_common.c index 6be3bb04ac..f6de2c1796 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -143,10 +143,16 @@ uchar default_environment[] = { || defined(CONFIG_ENV_IS_IN_SPI_FLASH) int default_environment_size = sizeof(default_environment); #endif - +#if(BOARD_TYPE==BOARD_TYPE_5125_MPU) +static unsigned int env_crc=0; +#endif void env_crc_update (void) { +#if 0 + env_crc=crc32(0, (void *)gd->env_addr, ENV_SIZE); +#else env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); +#endif } static uchar env_get_char_init (int index) @@ -237,6 +243,7 @@ void env_relocate (void) #endif #ifdef ENV_IS_EMBEDDED +#error failed environent /* * The environment buffer is embedded with the text segment, * just relocate the environment pointer @@ -264,7 +271,7 @@ void env_relocate (void) env_relocate_spec (); } gd->env_addr = (ulong)&(env_ptr->data); - + /*puts("env_ptr:\n");*/ #ifdef CONFIG_AMIGAONEG3SE disable_nvram(); #endif diff --git a/common/env_nand.c b/common/env_nand.c index 76569da0fe..3c60ddee69 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -72,7 +72,13 @@ char * env_name_spec = "NAND"; extern uchar environment[]; env_t *env_ptr = (env_t *)(&environment[0]); #else /* ! ENV_IS_EMBEDDED */ + #if(BOARD_TYPE==BOARD_TYPE_5125_MPU) + #define ENV_NAND_FLAGS 0x4d + env_t environment_strct[4]; + env_t *env_ptr=&environment_strct; + #else env_t *env_ptr = 0; + #endif #endif /* ENV_IS_EMBEDDED */ @@ -140,8 +146,41 @@ int env_init(void) else if (gd->env_valid == 2) env_ptr = tmp_env2; #else /* ENV_IS_EMBEDDED */ + #if(BOARD_TYPE==BOARD_TYPE_5125_MPU) + unsigned int env_crc,size; + unsigned char *start,*end; + nand_read_pages(env_ptr, CONFIG_ENV_START_PAGE, sizeof(env_t)); + if(ENV_NAND_FLAGS==env_ptr->flags) + { + gd->env_addr = env_ptr->data; + gd->env_valid = 1; + } + else + { + end=start=default_environment; + while(1) + { + while(*end)end++; + end++; + end++; + if(!(*end))break; + end++; + + } + size=end-start; + size=(size>ENV_SIZE)?ENV_SIZE:size; + + memcpy(env_ptr->data,default_environment,size); + gd->env_addr = env_ptr->data; + gd->env_valid = 1; + + env_ptr->crc=crc32(0, env_ptr->data, ENV_SIZE); + env_ptr->flags=ENV_NAND_FLAGS; + } + #else gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 1; +#endif #endif /* ENV_IS_EMBEDDED */ return (0); @@ -185,6 +224,14 @@ int saveenv(void) { size_t total; int ret = 0; +#if(BOARD_TYPE==BOARD_TYPE_5125_MPU) + puts ("Erasing Nand...\n"); + nand_erase_block(CONFIG_ENV_START_PAGE, CONFIG_ENV_START_PAGE+1); + puts ("Writing to Nand... "); + env_ptr->flags=ENV_NAND_FLAGS; + nand_write_pages((u_char *) env_ptr, CONFIG_ENV_START_PAGE, CONFIG_ENV_SIZE); + puts ("done\n"); + #else nand_erase_options_t nand_erase_options; env_ptr->flags++; @@ -221,6 +268,7 @@ int saveenv(void) puts ("done\n"); gd->env_valid = (gd->env_valid == 2 ? 1 : 2); +#endif return ret; } #else /* ! CONFIG_ENV_OFFSET_REDUND */ @@ -228,6 +276,7 @@ int saveenv(void) { size_t total; int ret = 0; + nand_erase_options_t nand_erase_options; nand_erase_options.length = CONFIG_ENV_RANGE; @@ -248,7 +297,6 @@ int saveenv(void) puts("FAILED!\n"); return 1; } - puts ("done\n"); return ret; } @@ -286,6 +334,22 @@ int readenv (size_t offset, u_char * buf) #ifdef CONFIG_ENV_OFFSET_REDUND void env_relocate_spec (void) { +#if(BOARD_TYPE==BOARD_TYPE_5125_MPU) + size_t total; + int crc1_ok = 0, crc2_ok = 0; + env_t *tmp_env1, *tmp_env2; + if((env_ptr!=environment_strct)&&(env_ptr)) + { + free(env_ptr); + } + tmp_env1 = (env_t *) malloc(CONFIG_ENV_SIZE*2); + tmp_env1->flags=ENV_NAND_FLAGS; + tmp_env1->crc=environment_strct[0].crc; + memcpy(tmp_env1->data,(void *)gd->env_addr,ENV_SIZE); + env_ptr=tmp_env1; + gd->env_addr = env_ptr->data; + gd->env_valid = 1; +#else #if !defined(ENV_IS_EMBEDDED) size_t total; int crc1_ok = 0, crc2_ok = 0; @@ -337,6 +401,7 @@ void env_relocate_spec (void) } #endif /* ! ENV_IS_EMBEDDED */ +#endif } #else /* ! CONFIG_ENV_OFFSET_REDUND */ /* diff --git a/config.mk b/config.mk index b1254e9042..195787ecdb 100644 --- a/config.mk +++ b/config.mk @@ -41,7 +41,11 @@ endif # clean the slate ... PLATFORM_RELFLAGS = +ifdef CONFIG_CW +PLATFORM_CPPFLAGS = -DCONFIG_CW +else PLATFORM_CPPFLAGS = +endif PLATFORM_LDFLAGS = ######################################################################### @@ -108,8 +112,13 @@ else ARFLAGS = crv endif RELFLAGS= $(PLATFORM_RELFLAGS) +ifdef CONFIG_CW +DBGFLAGS= -g2 -gdwarf-2 +OPTFLAGS= -O1 +else DBGFLAGS= -g # -DDEBUG OPTFLAGS= -Os #-fomit-frame-pointer +endif ifndef LDSCRIPT #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug ifeq ($(CONFIG_NAND_U_BOOT),y) @@ -136,6 +145,17 @@ CPPFLAGS += -I$(TOPDIR)/include CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) +ifdef CONFIG_CW + +ifdef BUILD_TAG +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -ggdb \ + -DBUILD_TAG='"$(BUILD_TAG)"' +else +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -ggdb +endif + +else # !define CONFIG_CW + ifdef BUILD_TAG CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ -DBUILD_TAG='"$(BUILD_TAG)"' @@ -145,6 +165,8 @@ endif CFLAGS += $(call cc-option,-fno-stack-protector) +endif # CONFIG_CW + # avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) # this option have to be placed behind -Wall -- that's why it is here ifeq ($(ARCH),nios) @@ -155,7 +177,11 @@ endif # $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g # option to the assembler. +ifdef CONFIG_CW +AFLAGS_DEBUG := -Wa,-gdwarf2 +else AFLAGS_DEBUG := +endif # turn jbsr into jsr for m68k ifeq ($(ARCH),m68k) diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index b9069b065e..afcf78f0d6 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2006, 2009 Freescale Semiconductor, Inc. All right reserved. * (C) Copyright 2007 DENX Software Engineering * * See file CREDITS for list of people who contributed to this @@ -53,6 +53,9 @@ int checkcpu (void) case SPR_5121E: puts ("MPC5121e "); break; + case SPR_5125: + puts ("MPC5125 "); + break; default: printf ("Unknown part ID %08x ", spridr & 0xffff0000); } @@ -71,6 +74,8 @@ int checkcpu (void) return 0; } +#define RESET_MAGIC_WORD 0x52535445 + int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) @@ -87,11 +92,11 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* * Enable Reset Control Reg - "RSTE" is the magic word that let us go */ - immap->reset.rpr = 0x52535445; + immap->reset.rpr = RESET_MAGIC_WORD; /* Verify Reset Control Reg is enabled */ while (!((immap->reset.rcer) & RCER_CRE)) - ; + immap->reset.rpr = RESET_MAGIC_WORD; printf ("Resetting the board.\n"); udelay(200); diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c index 78f4fa1e8c..4067eb2141 100644 --- a/cpu/mpc512x/iopin.c +++ b/cpu/mpc512x/iopin.c @@ -24,26 +24,41 @@ #include #include #include +#include void iopin_initialize(iopin_t *ioregs_init, int len) { short i, j, p; - u_long *reg; immap_t *im = (immap_t *)CONFIG_SYS_IMMR; +#ifdef CONFIG_ADS5125 + u_char *reg; +#else + u_long *reg; +#endif - reg = (u_long *)&(im->io_ctrl.regs[0]); - + reg = &im->io_ctrl.regs[0]; if (sizeof(ioregs_init) == 0) return; for (i = 0; i < len; i++) { +#ifdef CONFIG_ADS5125 + for (p = 0, j = ioregs_init[i].p_offset; + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or) + setbits(8, &(reg[j]), ioregs_init[i].val); + else + out_8(®[j], ioregs_init[i].val); + } +#else for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); p < ioregs_init[i].nr_pins; p++, j++) { if (ioregs_init[i].bit_or) - reg[j] |= ioregs_init[i].val; + setbits(be32, &(reg[j]), ioregs_init[i].val); else - reg[j] = ioregs_init[i].val; + out_be32(®[j], ioregs_init[i].val); } +#endif } + return; } diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index 7db87a80a1..6c334fbe97 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -67,8 +67,10 @@ int serial_init(void) fifo_init (psc); +#ifndef ADS5125 /* set MR register to point to MR1 */ psc->command = PSC_SEL_MODE_REG_1; +#endif /* disable Tx/Rx */ psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE; @@ -79,15 +81,22 @@ int serial_init(void) /* switch to UART mode */ psc->sicr = 0; - /* mode register points to mr1 */ /* configure parity, bit length and so on in mode register 1*/ +#ifdef CONFIG_ADS5125 + psc->mr1 = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + psc->mr2 = PSC_MODE_1_STOPBIT; + + /* calculate divisor for setting PSC CTUR and CTLR registers */ + div = gd->ips_clk/(16 * gd->baudrate); +#else + /* mode register points to mr1 */ psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; /* now, mode register points to mr2 */ psc->mode = PSC_MODE_1_STOPBIT; - - /* calculate dividor for setting PSC CTUR and CTLR registers */ + /* calculate divisor for setting PSC CTUR and CTLR registers */ baseclk = (gd->ips_clk + 8) / 16; div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; +#endif psc->ctur = (div >> 8) & 0xff; /* set baudrate */ diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 360682dafc..3623ce5714 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -190,16 +190,35 @@ _end_of_vectors: boot_cold: /* Save msr contents */ mfmsr r5 + lis r4, CONFIG_DEFAULT_IMMR@h /* Set IMMR area to our preferred location */ - lis r4, CONFIG_DEFAULT_IMMR@h + mfspr r6, MBAR lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l + + /* see if it has already been set (RAMBOOT or BDI configured) */ + + cmpw r3, r6 + beq 1f stw r3, IMMRBAR(r4) - mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ + /* IMMRBAR is mirrored into the MBAR SPR (311) */ + mtspr MBAR, r3 + +1: lwz r4, RCWHR(r3) + lis r5, NAND_BOOT + and. r4, r4, r5 + beq 3f + + /* in NAND boot reset the NFC Access Window */ + li r4, 0 + lis r4, START_REG(CFG_NAND_BASE) + stw r4, NFCBAR(r3) + lwz r4, NFCBAR(r3) + isync /* Initialise the machine */ - bl cpu_early_init +3: bl cpu_early_init /* * Set up Local Access Windows: @@ -207,15 +226,16 @@ boot_cold: * 1) Boot/CS0 (boot FLASH) * 2) On-chip SRAM (initial stack purposes) */ - + isync /* Boot CS/CS0 window range */ lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l - + #if(BOARD_TYPE==BOARD_TYPE_5125_MPU) + #else lis r4, START_REG(CONFIG_SYS_FLASH_BASE) ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE) stw r4, LPCS0AW(r3) - +#endif /* * The SRAM window has a fixed size (256K), so only the start address * is necessary @@ -235,13 +255,27 @@ boot_cold: * Set configuration of the Boot/CS0, the SRAM window does not have a * config register so no params can be set for it */ +#if(BOARD_TYPE==BOARD_TYPE_5125_MPU) +#else lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l lis r4, CONFIG_SYS_CS0_CFG@h ori r4, r4, CONFIG_SYS_CS0_CFG@l stw r4, CS0_CONFIG(r3) +#endif +#ifdef CONFIG_ADS5125 /* CS2 FUNC MUX must be done before CS is enabled */ + lis r4, (CONFIG_SYS_IOCTRL_ADDR)@h + ori r4, r4, (CONFIG_SYS_IOCTRL_ADDR)@l + li r5, IOCTRL_MUX_CS2 + stb r5, IO_CTRL_LPC_AX03(r4) +/* change the pin muxing on PSC9 here in case it is being used as console*/ + li r5, IOCTRL_MUX_PSC9 + stb r5, IO_CTRL_I2C1_SCL(r4) + stb r5, IO_CTRL_I2C1_SDA(r4) + +#endif /* Master enable all CS's */ lis r4, CS_CTRL_ME@h ori r4, r4, CS_CTRL_ME@l diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 5974d7768d..33fcb91fcf 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -41,6 +41,8 @@ COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +#COBJS-$(CONFIG_NAND_FSL_NFC) += fsl_nfc_nand.o +COBJS-$(CONFIG_NAND_FSL_NFC) += fsl_nfc_nand_5125.o mpc5125_nfc_mtc.mtc endif COBJS := $(COBJS-y) @@ -49,6 +51,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) all: $(LIB) + $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/drivers/mtd/nand/fsl_nfc_nand.c b/drivers/mtd/nand/fsl_nfc_nand.c new file mode 100644 index 0000000000..6efe18e865 --- /dev/null +++ b/drivers/mtd/nand/fsl_nfc_nand.c @@ -0,0 +1,1104 @@ +/* + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Based on drivers/mtd/nand/mpc5121_nand.c + * which was based on drivers/mtd/nand/mxc_nd.c + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +#include +#include +#include + +#include +#include + +#define MIN(x, y) ((x < y) ? x : y) + +static struct fsl_nfc_private { + struct mtd_info mtd; + char spare_only; + char status_req; + u16 col_addr; + int writesize; + int sparesize; + int width; + int chipsel; +} *priv; + +#define IS_2K_PAGE_NAND (priv->writesize == 2048) +#define IS_4K_PAGE_NAND (priv->writesize == 4096) +#define IS_LARGE_PAGE_NAND (priv->writesize > 512) + +#define NFC_REG_BASE ((void *)CONFIG_SYS_NAND_BASE) +/* + * FSL NFC registers Definition + */ +#define NFC_BUF_ADDR (NFC_REG_BASE + 0x1E04) +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0x1E06) +#define NFC_FLASH_CMD (NFC_REG_BASE + 0x1E08) +#define NFC_CONFIG (NFC_REG_BASE + 0x1E0A) +#define NFC_ECC_STATUS1 (NFC_REG_BASE + 0x1E0C) +#define NFC_ECC_STATUS2 (NFC_REG_BASE + 0x1E0E) +#define NFC_SPAS (NFC_REG_BASE + 0x1E10) +#define NFC_WRPROT (NFC_REG_BASE + 0x1E12) +#define NFC_NF_WRPRST (NFC_REG_BASE + 0x1E18) +#define NFC_CONFIG1 (NFC_REG_BASE + 0x1E1A) +#define NFC_CONFIG2 (NFC_REG_BASE + 0x1E1C) +#define NFC_UNLOCKSTART_BLKADDR0 (NFC_REG_BASE + 0x1E20) +#define NFC_UNLOCKEND_BLKADDR0 (NFC_REG_BASE + 0x1E22) +#define NFC_UNLOCKSTART_BLKADDR1 (NFC_REG_BASE + 0x1E24) +#define NFC_UNLOCKEND_BLKADDR1 (NFC_REG_BASE + 0x1E26) +#define NFC_UNLOCKSTART_BLKADDR2 (NFC_REG_BASE + 0x1E28) +#define NFC_UNLOCKEND_BLKADDR2 (NFC_REG_BASE + 0x1E2A) +#define NFC_UNLOCKSTART_BLKADDR3 (NFC_REG_BASE + 0x1E2C) +#define NFC_UNLOCKEND_BLKADDR3 (NFC_REG_BASE + 0x1E2E) + +/*! + * Addresses for NFC MAIN RAM BUFFER areas + */ +#define MAIN_AREA(n) (NFC_REG_BASE + (n)*0x200) + +/*! + * Addresses for NFC SPARE BUFFER areas + */ +#define SPARE_LEN 0x40 +#define SPARE_AREA(n) (NFC_REG_BASE + 0x1000 + (n)*SPARE_LEN) + +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +/* Bit Definitions */ +#define NFC_INT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLOCKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + +#define NFC_ECC_MODE_4 1 +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 + +#if defined(CONFIG_PPC) +#define NFC_WRITEL(r, v) out_be32(r, v) +#define NFC_WRITEW(r, v) out_be16(r, v) +#define NFC_WRITEB(r, v) out_8(r, v) +#define NFC_READL(r) in_be32(r) +#define NFC_READW(r) in_be16(r) +#define NFC_READB(r) in_8(r) +#elif defined(CONFIG_ARM) +#define NFC_WRITEL(r, v) writel(v, r) +#define NFC_WRITEW(r, v) writew(v, r) +#define NFC_WRITEB(r, v) writeb(r, v) +#define NFC_READL(r) readl(r) +#define NFC_READW(r) readw(r) +#define NFC_READB(r) readb(r) +#endif + + +#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC +static int hardware_ecc; +#else +static int hardware_ecc = 1; +#endif + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_512 = { + .eccbytes = 9, + .eccpos = { + 7, 8, 9, 10, 11, 12, 13, 14, 15, + }, + .oobfree = { + {0, 5} /* byte 5 is factory bad block marker */ + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 36, + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 64, /* actually 72 but only room for 64 */ + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + 71, 72, 73, 74, 75, 76, 77, 78, 79, + 87, 88, 89, 90, 91, 92, 93, 94, 95, + 103, 104, 105, 106, 107, 108, 109, 110, 111, + 119, /* 120, 121, 122, 123, 124, 125, 126, 127, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + {64, 7}, + {80, 7}, + {96, 7}, + {112, 7}, + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_4k_218_spare = { + .eccbytes = 64, /* actually 144 but only room for 64 */ + .eccpos = { + /* 18 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, + 33, 34, 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, 49, 50, + 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, + 85, 86, 87, 88, 89, 90, 91, 92, 93, + 94, /* 95, 96, 97, 98, 99, 100, 101, 102, + 111, 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, 128, + 137, 138, 139, 140, 141, 142, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152, 153, 154, + 163, 164, 165, 166, 167, 168, 169, 170, 171, + 172, 173, 174, 175, 176, 177, 178, 179, 180, + 189, 190, 191, 192, 193, 194, 195, 196, 197, + 198, 199, 200, 201, 202, 203, 204, 205, 206, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {25, 8}, + {51, 8}, + {77, 8}, + {103, 8}, + {129, 8}, + {155, 8}, + {181, 8}, + }, +}; + +/* + * Functions to transfer data to/from spare erea. + */ +static void copy_from_spare(struct mtd_info *mtd, void *pbuf, int len) +{ + int i, copy_count, copy_size; + + copy_count = mtd->writesize / 512; + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + copy_size = priv->sparesize == 218 ? 26 : 16; + + for (i = 0; i < copy_count - 1 && len > 0; i++) { + memcpy_fromio(pbuf, SPARE_AREA(i), MIN(len, copy_size)); + pbuf += copy_size; + len -= copy_size; + } + if (len > 0) + memcpy_fromio(pbuf, SPARE_AREA(i), len); +} + +static void copy_to_spare(struct mtd_info *mtd, void *pbuf, int len) +{ + int i, copy_count, copy_size; + + copy_count = mtd->writesize / 512; + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + copy_size = priv->sparesize == 218 ? 26 : 16; + + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + for (i = 0; i < copy_count - 1 && len > 0; i++) { + memcpy_toio(SPARE_AREA(i), pbuf, MIN(len, copy_size)); + pbuf += copy_size; + len -= copy_size; + } + if (len > 0) + memcpy_toio(SPARE_AREA(i), pbuf, len); +} + +/*! + * This function polls the NFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @max_retries number of retry attempts (separated by 1 us) + */ +static void wait_op_done(int max_retries) +{ + + while (1) { + max_retries--; + if (NFC_READW(NFC_CONFIG2) & NFC_INT) + break; + udelay(1); + } + if (max_retries <= 0) + MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n", __FUNCTION__); +} + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @cmds command for NAND Flash + */ +static void send_cmd(u16 cmd) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(%#x)\n", cmd); + + NFC_WRITEW(NFC_FLASH_CMD, cmd); + NFC_WRITEW(NFC_CONFIG2, NFC_CMD); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @addr address to be written to NFC. + */ +static void send_addr(u16 addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(%#x)\n", addr); + NFC_WRITEW(NFC_FLASH_ADDR, (addr << NFC_FLASH_ADDR_SHIFT)); + + NFC_WRITEW(NFC_CONFIG2, NFC_ADDR); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to initate the transfer + * of data currently in the NFC RAM buffer to the NAND device. + * + * @buf_id Specify Internal RAM Buffer number (0-3) + */ +static void send_prog_page(u8 buf_id) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* Set RBA bits for BUFFER val */ + val &= ~0x7; + val |= buf_id; + NFC_WRITEW(NFC_BUF_ADDR, val); + + NFC_WRITEW(NFC_CONFIG2, NFC_INPUT); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to initated the transfer + * of data from the NAND device into in the NFC ram buffer. + * + * @buf_id Specify Internal RAM Buffer number (0-3) + */ +static void send_read_page(u8 buf_id) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* Set RBA bits for BUFFER val */ + val &= ~0x7; + val |= buf_id; + NFC_WRITEW(NFC_BUF_ADDR, val); + + NFC_WRITEW(NFC_CONFIG2, NFC_OUTPUT); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + + /* NFC buffer 0 is used for device ID output */ + /* Set RBA bits for BUFFER0 */ + val &= ~0x7; + NFC_WRITEW(NFC_BUF_ADDR, val); + + /* Read ID into main buffer */ + NFC_WRITEW(NFC_CONFIG2, NFC_ID); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ + u32 save; + u16 ret; + u32 val; + /* Issue status request to NAND device */ + + /* save the main area1 first word, later do recovery */ + save = NFC_READL(MAIN_AREA(1)); + NFC_WRITEL(MAIN_AREA(1), 0); + + /* + * NFC buffer 1 is used for device status to prevent + * corruption of read/write buffer on status requests. + */ + + /* Select BUFFER1 */ + val = NFC_READW(NFC_BUF_ADDR); + val &= ~0x7; + val |= 1; + NFC_WRITEW(NFC_BUF_ADDR, val); + + /* Read status into main buffer */ + NFC_WRITEW(NFC_CONFIG2, NFC_STATUS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + if (NFC_READW(NFC_CONFIG1) & NFC_BIG) + ret = NFC_READB(MAIN_AREA(1)); + else + ret = NFC_READB(MAIN_AREA(1) + 3); + + NFC_WRITEL(MAIN_AREA(1), save); + return ret; +} + +/*! + * This functions is used by upper layer to checks if device is ready + * + * @mtd MTD structure for the NAND Flash + * + * @return 0 if device is busy else 1 + */ +static int fsl_nfc_dev_ready(struct mtd_info *mtd) +{ + return 1; +} + +static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode) +{ + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_ECC_EN)); + return; +} + +/* + * Function to record the ECC corrected/uncorrected errors resulted + * after a page read. This NFC detects and corrects upto to 4 symbols + * of 9-bits each. + */ +static int fsl_nfc_check_ecc_status(struct mtd_info *mtd) +{ + u32 ecc_stat, err; + int no_subpages = 1; + int ret = 0; + u8 ecc_bit_mask, err_limit; + int is_4bit_ecc = NFC_READW(NFC_CONFIG1) & NFC_ECC_MODE_4; + + ecc_bit_mask = (is_4bit_ecc ? 0x7 : 0xf); + err_limit = (is_4bit_ecc ? 0x4 : 0x8); + + no_subpages = mtd->writesize >> 9; + + ecc_stat = NFC_READW(NFC_ECC_STATUS1); + do { + err = ecc_stat & ecc_bit_mask; + if (err > err_limit) + return -1; + else + ret += err; + ecc_stat >>= 4; + } while (--no_subpages); + + return ret; +} + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte(struct mtd_info *mtd) +{ + void *area_buf; + u_char rv; + + /* Check for status request */ + if (priv->status_req) { + rv = get_dev_status() & 0xff; + return rv; + } + + if (priv->spare_only) + area_buf = SPARE_AREA(0); + else + area_buf = MAIN_AREA(0); + + rv = NFC_READB(area_buf + priv->col_addr); + priv->col_addr++; + return rv; +} + +/*! + * This function reads word from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 fsl_nfc_read_word(struct mtd_info *mtd) +{ + u16 rv; + void *area_buf; + + /* If we are accessing the spare region */ + if (priv->spare_only) + area_buf = SPARE_AREA(0); + else + area_buf = MAIN_AREA(0); + + /* Update saved column address */ + rv = NFC_READW(area_buf + priv->col_addr); + priv->col_addr += 2; + + return rv; +} + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte16(struct mtd_info *mtd) +{ + /* Check for status request */ + if (priv->status_req) + return (get_dev_status() & 0xff); + + return fsl_nfc_read_word(mtd) & 0xff; +} + +/*! + * This function writes data of length \b len from buffer \b buf to the NAND + * internal RAM buffer's MAIN area 0. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be written to NAND Flash + * @len number of bytes to be written + */ +static void fsl_nfc_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_to_spare(mtd, (char *)buf, len); + return; + } else { + priv->col_addr += len; + memcpy_toio(MAIN_AREA(0), (void *)buf, len); + } +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be read from NAND Flash + * @len number of bytes to be read + */ +static void fsl_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_from_spare(mtd, buf, len); + return; + } else { + priv->col_addr += len; + memcpy_fromio((void *)buf, MAIN_AREA(0), len); + } +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be verified + * @len length of the data to be verified + * + * @return -1 if error else 0 + * + */ +static int fsl_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + void *main_buf = MAIN_AREA(0); + /* check for 32-bit alignment? */ + u32 *p = (u32 *) buf; + u32 v = 0; + + for (; len > 0; len -= 4, main_buf += 4) + v = NFC_READL(main_buf); + if (v != *p++) + return -1; + return 0; +} + +static int fsl_nfc_get_hw_config(struct nand_chip *this) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 rcwh; + int rcwh_romloc; + int rcwh_ps; + int width; + int writesize = 0; + int sparesize = 0; + + /* + * Only support 2K for now. + * Remove this when others are tested and debugged. + */ +#if 0 + if (CONFIG_FSL_NFC_WRITE_SIZE != 2048) { + printf("FSL NFC: " + "%d byte write size flash support is untested\n", + CONFIG_FSL_NFC_WRITE_SIZE); + return -1; + } +#endif + rcwh = NFC_READL((void *)&(im->reset.rcwh)); + width = ((rcwh >> 6) & 0x1) ? 2 : 1; + + if (width != CONFIG_FSL_NFC_WIDTH) { + printf("FSL NFC: Device width mismatch, compiled for %d, " + "reset configuration word width is %d\n", + CONFIG_FSL_NFC_WIDTH, width); + return -1; + } + + if (width == 2) { + this->options |= NAND_BUSWIDTH_16; + this->read_byte = fsl_nfc_read_byte16; + } + + /* + * Decode the rcwh_ps and rcwh_romloc + * bits from reset config word + * to determine write size + */ + rcwh_ps = (rcwh >> 7) & 0x1; + rcwh_romloc = (rcwh >> 21) & 0x3; + switch (rcwh_ps << 2 | rcwh_romloc) { + case 0x0: + case 0x1: + writesize = 512; + sparesize = 16; + break; + case 0x2: + case 0x3: + writesize = 4096; + sparesize = 128; + break; + case 0x4: + case 0x5: + writesize = 2048; + sparesize = 64; + break; + case 0x6: + case 0x7: + writesize = 4096; + sparesize = 218; + break; + } + if (CONFIG_FSL_NFC_WRITE_SIZE != writesize) { + printf("FSL NFC: " + "Device write size mismatch, " + "compiled for %d, " + "size from reset configuration word is %d\n", + CONFIG_FSL_NFC_WRITE_SIZE, writesize); + return -1; + } + if (CONFIG_FSL_NFC_SPARE_SIZE != sparesize) { + printf("FSL NFC: " + "Device spare size mismatch, " + "compiled for %d, " + "size from reset configuration word is %d\n", + CONFIG_FSL_NFC_SPARE_SIZE, sparesize); + return -1; + } + + priv->sparesize = sparesize; + priv->writesize = writesize; + priv->width = width; + return 0; +} + + +#ifndef CONFIG_FSL_NFC_BOARD_CS_FUNC +static void fsl_nfc_select_chip(u8 cs) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + + val &= ~0x60; + val |= cs << 5; + NFC_WRITEW(NFC_BUF_ADDR, val); +} +#define CONFIG_FSL_NFC_BOARD_CS_FUNC fsl_nfc_select_chip +#endif + + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @mtd MTD structure for the NAND Flash + * @chip val indicating select or deselect + */ +static void fsl_nfc_select_chip(struct mtd_info *mtd, int chip) +{ + /* + * This is different than the linux version. + * Switching between chips is done via + * board_nand_select_device. + * + * Only valid chip numbers here are + * 0 select + * -1 deselect + */ + if (chip < -1 || chip > 0) { + printf("FSL NFC: " + "ERROR: Illegal chip select (chip = %d)\n", chip); + } + + if (chip < 0) { + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) & ~NFC_CE)); + return; + } + + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_CE)); + + /* + * Turn on appropriate chip. + */ + CONFIG_FSL_NFC_BOARD_CS_FUNC(priv->chipsel); +} + +/* + * Function to perform the address cycles. + */ +static void fsl_nfc_do_addr_cycle(struct mtd_info *mtd, int column, + int page_addr) +{ + struct nand_chip *this = mtd->priv; + u32 page_mask = this->pagemask; + + if (column != -1) { + send_addr(column & 0xff); + /* large page nand needs an extra column addr cycle */ + if (IS_2K_PAGE_NAND) + send_addr((column >> 8) & 0xf); + else if (IS_4K_PAGE_NAND) + send_addr((column >> 8) & 0x1f); + } + if (page_addr != -1) { + do { + send_addr((page_addr & 0xff)); + page_mask >>= 8; + page_addr >>= 8; + } while (page_mask != 0); + } +} + +/* + * Function to read a page from nand device. + */ +static void read_full_page(struct mtd_info *mtd, int page_addr) +{ + send_cmd(NAND_CMD_READ0); + + fsl_nfc_do_addr_cycle(mtd, 0, page_addr); + + if (IS_LARGE_PAGE_NAND) { + send_cmd(NAND_CMD_READSTART); + send_read_page(0); + } else { + send_read_page(0); + } +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @mtd MTD structure for the NAND Flash + * @command command for NAND Flash + * @column column offset for the page read + * @page_addr page to be read from NAND Flash + */ +static void fsl_nfc_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, + "fsl_nfc_command (cmd = %#x, col = %#x, page = %#x)\n", + command, column, page_addr); + /* + * Reset command state information + */ + priv->status_req = 0; + + /* Reset column address to 0 */ + priv->col_addr = 0; + + /* + * Command pre-processing step + */ + switch (command) { + case NAND_CMD_STATUS: + priv->status_req = 1; + break; + + case NAND_CMD_READ0: + priv->spare_only = 0; + break; + + case NAND_CMD_READOOB: + priv->col_addr = column; + priv->spare_only = 1; + command = NAND_CMD_READ0; /* only READ0 is valid */ + break; + + case NAND_CMD_SEQIN: + if (column >= mtd->writesize) + priv->spare_only = 1; + else + priv->spare_only = 0; + break; + + case NAND_CMD_PAGEPROG: + if (!priv->spare_only) + send_prog_page(0); + else + return; + break; + + case NAND_CMD_ERASE1: + break; + case NAND_CMD_ERASE2: + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(command); + + fsl_nfc_do_addr_cycle(mtd, column, page_addr); + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (IS_LARGE_PAGE_NAND) { + /* send read confirm command */ + send_cmd(NAND_CMD_READSTART); + /* read for each AREA */ + send_read_page(0); + } else + send_read_page(0); + break; + + case NAND_CMD_READID: + send_read_id(); + break; + } +} + +static int fsl_nfc_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + return get_dev_status(); +} + +static int fsl_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int sndcmd) +{ + if (sndcmd) { + read_full_page(mtd, page); + sndcmd = 0; + } + + copy_from_spare(mtd, chip->oob_poi, mtd->oobsize); + return sndcmd; +} + +static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + int read_oob_col = 0; + + send_cmd(NAND_CMD_READ0); + send_cmd(NAND_CMD_SEQIN); + fsl_nfc_do_addr_cycle(mtd, read_oob_col, page); + + /* copy the oob data */ + copy_to_spare(mtd, chip->oob_poi, mtd->oobsize); + + send_prog_page(0); + + send_cmd(NAND_CMD_PAGEPROG); + + status = fsl_nfc_wait(mtd, chip); + if (status & NAND_STATUS_FAIL) + return -1; + return 0; +} + +static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf) +{ + int stat; + + stat = fsl_nfc_check_ecc_status(mtd); + if (stat == -1) { + mtd->ecc_stats.failed++; + printf("FSL NFC: UnCorrectable RS-ECC Error\n"); + } else { + mtd->ecc_stats.corrected += stat; + if (stat) + printf("%d Symbol Correctable RS-ECC Error\n", stat); + } + + memcpy_fromio((void *)buf, MAIN_AREA(0), mtd->writesize); + copy_from_spare(mtd, chip->oob_poi, mtd->oobsize); + return 0; +} + +static void fsl_nfc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + memcpy_toio(MAIN_AREA(0), buf, mtd->writesize); + copy_to_spare(mtd, chip->oob_poi, mtd->oobsize); +} + + +/* + * Generic flash bbt decriptors + */ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +/* + * These are identical to the generic versions except + * for the offsets. + */ +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + if (chip >= CONFIG_FSL_NFC_CHIPS) { + printf("FSL NFC: " + "ERROR: Illegal chip select (chip = %d)\n", chip); + return; + } + priv->chipsel = chip; +} + + +int board_nand_init(struct nand_chip *nand) +{ + struct mtd_info *mtd; + + priv = malloc(sizeof(*priv)); + if (!priv) { + printf("FSL NFC: failed to allocate priv structure\n"); + return -1; + } + memset(priv, 0, sizeof(*priv)); + + if (fsl_nfc_get_hw_config(nand) < 0) + return -1; + + mtd = &priv->mtd; + mtd->priv = nand; + + /* 5 us command delay time */ + nand->chip_delay = 5; + + nand->dev_ready = fsl_nfc_dev_ready; + nand->cmdfunc = fsl_nfc_command; + nand->waitfunc = fsl_nfc_wait; + nand->select_chip = fsl_nfc_select_chip; + nand->options = NAND_USE_FLASH_BBT; + if (priv->width == 2) { + nand->options |= NAND_BUSWIDTH_16; + nand->read_byte = fsl_nfc_read_byte16; + } + nand->read_byte = fsl_nfc_read_byte; + nand->read_word = fsl_nfc_read_word; + nand->write_buf = fsl_nfc_write_buf; + nand->read_buf = fsl_nfc_read_buf; + nand->verify_buf = fsl_nfc_verify_buf; + + nand->bbt_td = &bbt_main_descr; + nand->bbt_md = &bbt_mirror_descr; + + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_RST)); + + /* Disable interrupt */ + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_INT_MSK)); + + if (hardware_ecc) { + nand->ecc.read_page = fsl_nfc_read_page; + nand->ecc.write_page = fsl_nfc_write_page; + nand->ecc.read_oob = fsl_nfc_read_oob; + nand->ecc.write_oob = fsl_nfc_write_oob; + if (IS_2K_PAGE_NAND) + nand->ecc.layout = &nand_hw_eccoob_2k; + else if (IS_4K_PAGE_NAND) + if (priv->sparesize == 128) + nand->ecc.layout = &nand_hw_eccoob_4k; + else + nand->ecc.layout = &nand_hw_eccoob_4k_218_spare; + else + nand->ecc.layout = &nand_hw_eccoob_512; + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = nand->ecc.layout; + nand->ecc.calculate = NULL; + nand->ecc.hwctl = fsl_nfc_enable_hwecc; + nand->ecc.correct = NULL; + nand->ecc.mode = NAND_ECC_HW; + /* RS-ECC is applied for both MAIN+SPARE not MAIN alone */ + nand->ecc.size = 512; + nand->ecc.bytes = 9; + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_ECC_EN)); + } else { + nand->ecc.mode = NAND_ECC_SOFT; + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) & ~NFC_ECC_EN)); + } + + NFC_WRITEW(NFC_CONFIG1, NFC_READW(NFC_CONFIG1) & ~NFC_SP_EN); + + + /* Reset NAND */ + nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* preset operation */ + /* Unlock the internal RAM Buffer */ + NFC_WRITEW(NFC_CONFIG, NFC_BLS_UNLOCKED); + + /* Blocks to be unlocked */ + NFC_WRITEW(NFC_UNLOCKSTART_BLKADDR0, 0x0); + NFC_WRITEW(NFC_UNLOCKEND_BLKADDR0, 0xffff); + + /* Unlock Block Command for given address range */ + NFC_WRITEW(NFC_WRPROT, NFC_WPC_UNLOCK); + + /* Set sparesize */ + NFC_WRITEW(NFC_SPAS, + (NFC_READW(NFC_SPAS) & 0xff00) | (priv->sparesize/2)); + + /* + * Only use 8bit ecc (aka not 4 bit) if large spare size + */ + if (priv->sparesize == 218) + NFC_WRITEW(NFC_CONFIG1, + (NFC_READW(NFC_CONFIG1) & ~NFC_ECC_MODE_4)); + else + NFC_WRITEW(NFC_CONFIG1, + (NFC_READW(NFC_CONFIG1) | NFC_ECC_MODE_4)); + + return 0; +} diff --git a/drivers/mtd/nand/fsl_nfc_nand_5125.c b/drivers/mtd/nand/fsl_nfc_nand_5125.c new file mode 100644 index 0000000000..d0dc9f209c --- /dev/null +++ b/drivers/mtd/nand/fsl_nfc_nand_5125.c @@ -0,0 +1,919 @@ +/* + * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Based on drivers/mtd/nand/mpc5121_nand.c + * which was based on drivers/mtd/nand/mxc_nd.c + * ported by Cloudy chen LimePC Multimedia Technologies Co., Limited + *from mpc5121 to mpc5125 + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include + +#include +#include +#include +#include "mpc5125_nfc_struct.h" +#define MIN(x, y) ((x < y) ? x : y) + +#define NAND_DEBUG_INFO() printf("%s line:%d\n",__func__,__LINE__) +#ifndef CONFIG_PPC +#define CONFIG_PPC +#endif + +static struct fsl_nfc_private { + struct mtd_info mtd; + char spare_only; + char status_req; + u16 col_addr; + int writesize; + int sparesize; + int width; + int chipsel; +} *priv; + +static int get_status; +static int get_id; + +#define IS_2K_PAGE_NAND (priv->writesize == 2048) +#define IS_4K_PAGE_NAND (priv->writesize == 4096) +#define IS_LARGE_PAGE_NAND (priv->writesize > 512) + +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 + +#if defined(CONFIG_PPC) +#define NFC_WRITEL(r, v) out_be32(r, v) +#define NFC_WRITEW(r, v) out_be16(r, v) +#define NFC_WRITEB(r, v) out_8(r, v) +#define NFC_READL(r) in_be32(r) +#define NFC_READW(r) in_be16(r) +#define NFC_READB(r) in_8(r) +#elif defined(CONFIG_ARM) +#define NFC_WRITEL(r, v) writel(v, r) +#define NFC_WRITEW(r, v) writew(v, r) +#define NFC_WRITEB(r, v) writeb(r, v) +#define NFC_READL(r) readl(r) +#define NFC_READW(r) readw(r) +#define NFC_READB(r) readb(r) +#endif + + +#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC +static int hardware_ecc; +#else +static int hardware_ecc = 0; +#endif + + +static void mpc5125_nfc_addr_cycle(struct mtd_info *mtd, int column, int page); +u8 mpc5125_nfc_get_id(struct mtd_info *mtd,int col); +static void mpc5125_cfg_iopad_init(void) +{ + //printf("enter mpc5125_cfg_iopad_init\n"); + /* FLASH IO PAD Setting */ + out_8(ioctl + BALL_NFC_IO0, PAD_NFC_IO | DS_MSR_3); + out_8(ioctl + BALL_NFC_IO1, PAD_NFC_IO | DS_MSR_3); + out_8(ioctl + BALL_NFC_IO2, PAD_NFC_IO | DS_MSR_3); + out_8(ioctl + BALL_NFC_IO3, PAD_NFC_IO | DS_MSR_3); + out_8(ioctl + BALL_NFC_IO4, PAD_NFC_IO | DS_MSR_3); + out_8(ioctl + BALL_NFC_IO5, PAD_NFC_IO | DS_MSR_3); + out_8(ioctl + BALL_NFC_IO6, PAD_NFC_IO | DS_MSR_3); + out_8(ioctl + BALL_NFC_IO7, PAD_NFC_IO | DS_MSR_3); + + /* FLASH CONTROL PAD Setting */ + out_8(ioctl + BALL_NFC_ALE, PAD_NFC_ALE | DS_MSR_3); + out_8(ioctl + BALL_NFC_CLE, PAD_NFC_CLE | DS_MSR_3); + out_8(ioctl + BALL_NFC_WE, PAD_NFC_WE | DS_MSR_3); + out_8(ioctl + BALL_NFC_RE, PAD_NFC_RE | DS_MSR_3); + + /* NFC_CE0 */ + out_8(ioctl + BALL_NFC_CE0, PAD_NFC_CE0 | DS_MSR_3); + + out_8(ioctl + BALL_NFC_RB0, PAD_NFC_RB0| ST_Enabled | DS_MSR_3 | PUD_PUE); +} + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_512 = { + .eccbytes = 9, + .eccpos = { + 7, 8, 9, 10, 11, 12, 13, 14, 15, + }, + .oobfree = { + {0, 5} /* byte 5 is factory bad block marker */ + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 36, + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + }, +}; +#if 1 +/*for ecc_MODE=0x6 45bytes*2*/ +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 90, /* actually 72 but only room for 64 */ + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 19,20,21,22,23,24,25,26,27,28,29,30, + 31,32,33,34,35,36,37,38,39,40, + 41, 42, 43, 44, 45, 46, 47,48,49,50, + 51,52,53,54,55, 56, 57, 58, 59, 60, + 61, 62, 63, + 83,84,85,86,87,88,89,90,91,92,93,94,95,96,97, + 98,99,100, + 101,102,103,104,105,106,107,108,109,110, + 111,112,113,114,115,116,117,118,119,120, + 121,122,123,124,125,126,127/* 120, 121, 122, 123, 124, 125, 126, 127, */ + }, + .oobavail = 30, + .oobfree = { {4, 15}, {68, 15}} +}; +#else +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 64, /* actually 72 but only room for 64 */ + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + 71, 72, 73, 74, 75, 76, 77, 78, 79, + 87, 88, 89, 90, 91, 92, 93, 94, 95, + 103, 104, 105, 106, 107, 108, 109, 110, 111, + 119, /* 120, 121, 122, 123, 124, 125, 126, 127, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + {64, 7}, + {80, 7}, + {96, 7}, + {112, 7}, + }, +}; +#endif +static struct nand_ecclayout nand_hw_eccoob_4k_218_spare = { + .eccbytes = 64, /* actually 144 but only room for 64 */ + .eccpos = { + /* 18 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, + 33, 34, 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, 49, 50, + 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, + 85, 86, 87, 88, 89, 90, 91, 92, 93, + 94, /* 95, 96, 97, 98, 99, 100, 101, 102, + 111, 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, 128, + 137, 138, 139, 140, 141, 142, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152, 153, 154, + 163, 164, 165, 166, 167, 168, 169, 170, 171, + 172, 173, 174, 175, 176, 177, 178, 179, 180, + 189, 190, 191, 192, 193, 194, 195, 196, 197, + 198, 199, 200, 201, 202, 203, 204, 205, 206, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {25, 8}, + {51, 8}, + {77, 8}, + {103, 8}, + {129, 8}, + {155, 8}, + {181, 8}, + }, +}; + + struct mpc5125_nfc_save_struct g_nfc_save; +/* + * Functions to transfer data to/from spare erea. + */ +static void copy_from_spare(struct mtd_info *mtd, void *pbuf, int len) +{ + + u16 ooblen = mtd->oobsize; + u8 i, count; + unsigned int sbsize, blksize; + /* Calculate number of valid bytes in each spare buffer */ + count = mtd->writesize >> 11; + count=(count>0)?count:1; + sbsize = (ooblen / count >> 1) << 1; + /*printk("%s line:%d %s len:%d\n",__FUNCTION__,__LINE__,wr?"write":"read",size);*/ + for(i=0;(ioobsize; + u8 i, count; + unsigned int sbsize, blksize; + /* Calculate number of valid bytes in each spare buffer */ + count = mtd->writesize >> 11; + count=(count>0)?count:1; + sbsize = (ooblen / count >> 1) << 1; + /*printk("%s line:%d %s len:%d\n",__FUNCTION__,__LINE__,wr?"write":"read",size);*/ + for(i=0;(icol_addr = (column >= 0) ? column : 0; + priv->spare_only = 0; + get_id = 0; + get_status = 0; + MTDDEBUG (MTD_DEBUG_LEVEL2, "command %08x page:%08x column:%08x\n",command,page,column); + switch (command) { + case NAND_CMD_PAGEPROG: + mpc5125_nfc_send_cmd(PROGRAM_PAGE_CMD_BYTE1, + PROGRAM_PAGE_CMD_BYTE2, + PROGRAM_PAGE_CMD_CODE); + wait_op_done(TROP_US_DELAY); + nfc_write(NFC_ROW_ADDR_INC, 0x0); + nfc_write(NFC_FLASH_CMD2, 0x8001c003); + wait_op_done(TROP_US_DELAY); + break; + /* + * NFC does not support sub-page reads and writes, + * so emulate them using full page transfers. + */ + case NAND_CMD_READ0: + column = 0; + goto read0; + break; + + case NAND_CMD_READ1: + priv->col_addr += 256; + command = NAND_CMD_READ0; + column = 0; + goto read0; + break; + + case NAND_CMD_READOOB: + priv->spare_only = 1; + command = NAND_CMD_READ0; + column = 0; +read0: + mpc5125_nfc_send_cmd( PAGE_READ_CMD_BYTE1, + PAGE_READ_CMD_BYTE2, + READ_PAGE_CMD_CODE); + break; + + case NAND_CMD_SEQIN: + /*mpc5125_nfc_command(mtd,NAND_CMD_READ0, column, page);*/ + column = 0; + goto read0; + break; + + case NAND_CMD_ERASE1: + mpc5125_nfc_send_cmd( ERASE_CMD_BYTE1, + ERASE_CMD_BYTE2, + ERASE_CMD_CODE); + break; + case NAND_CMD_ERASE2: + return; + case NAND_CMD_READID: + get_id = 1; + mpc5125_nfc_send_one_byte(command, READ_ID_CMD_CODE); + wait_op_done(TROP_US_DELAY); + copy_id_to_sram(); + + return; + case NAND_CMD_STATUS: + get_status = 1; + mpc5125_nfc_send_one_byte(command, STATUS_READ_CMD_CODE); + break; + case NAND_CMD_RNDOUT: + mpc5125_nfc_send_cmd( RANDOM_OUT_CMD_BYTE1, + RANDOM_OUT_CMD_BYTE2, + RANDOM_OUT_CMD_CODE); + break; + + + case NAND_CMD_RESET: + mpc5125_nfc_send_one_byte(command, RESET_CMD_CODE); + break; + + default: + return; + } + mpc5125_nfc_addr_cycle(mtd, priv->col_addr, page); + wait_op_done(TROP_US_DELAY); + MTDDEBUG (MTD_DEBUG_LEVEL2,"%s line:%d\n",__func__,__LINE__); +} + + +/*! + * This function requests the NFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ + + u32 flash_status = 0; + u8 *pstatus; + + flash_status = nfc_read(NFC_FLASH_STATUS2); + pstatus = (u8 *)&flash_status; + return *(pstatus + 3); +} + u8 mpc5125_nfc_get_id(struct mtd_info *mtd,int col) +{ + u32 flash_id1 = 0; + u8 *pid; + + flash_id1 = nfc_read(NFC_FLASH_STATUS1); + pid = (u8 *)&flash_id1; + + return *(pid+col ); +} + +/*! + * This functions is used by upper layer to checks if device is ready + * + * @mtd MTD structure for the NAND Flash + * + * @return 0 if device is busy else 1 + */ +static int fsl_nfc_dev_ready(struct mtd_info *mtd) +{ + return 1; +} + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte(struct mtd_info *mtd) +{ + void *area_buf; + u_char rv; + + if (priv->status_req) { + rv = get_dev_status() & 0xff; + return rv; + } + + if (priv->spare_only) + area_buf = CONFIG_SYS_NAND_BASE + NFC_SPARE_AREA(0); + else + area_buf = CONFIG_SYS_NAND_BASE + NFC_MAIN_AREA(0); + + rv = NFC_READB(area_buf + priv->col_addr); + priv->col_addr++; + return rv; +} + +/*! + * This function reads word from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 fsl_nfc_read_word(struct mtd_info *mtd) +{ + u16 rv; + void *area_buf; + + /* If we are accessing the spare region */ + if (priv->spare_only) + area_buf = CONFIG_SYS_NAND_BASE + NFC_SPARE_AREA(0); + else + area_buf = CONFIG_SYS_NAND_BASE + NFC_MAIN_AREA(0); + + /* Update saved column address */ + rv = NFC_READW(area_buf + priv->col_addr); + priv->col_addr += 2; + + return rv; +} + + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte16(struct mtd_info *mtd) +{ + /* Check for status request */ + if (priv->status_req) + return (get_dev_status() & 0xff); + + return fsl_nfc_read_word(mtd) & 0xff; +} + +/*! + * This function writes data of length \b len from buffer \b buf to the NAND + * internal RAM buffer's MAIN area 0. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be written to NAND Flash + * @len number of bytes to be written + */ +static void fsl_nfc_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_to_spare(mtd, (char *)buf, len); + return; + } else { + unsigned int size,i; + unsigned int c=priv->col_addr; + priv->col_addr += len; + for(i=(c/PAGE_2K);i<4;i++) + { + size=min(len,PAGE_2K); + memcpy_toio(CONFIG_SYS_NAND_BASE + NFC_MAIN_AREA(i)+c, (void *)buf, size); + buf+=size; + len-=size; + if(!len)break; + } + } +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be read from NAND Flash + * @len number of bytes to be read + */ +static void fsl_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_from_spare(mtd, buf, len); + return; + } else { + unsigned int size,i; + unsigned int c=priv->col_addr; + priv->col_addr += len; + for(i=(c/PAGE_2K);i<4;i++) + { + size=min(len,PAGE_2K); + memcpy_fromio(buf,CONFIG_SYS_NAND_BASE + NFC_MAIN_AREA(i) + c, size); + buf+=size; + len-=size; + if(!len)break; + } + + } +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be verified + * @len length of the data to be verified + * + * @return -1 if error else 0 + * + */ +static int fsl_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + void *main_buf = CONFIG_SYS_NAND_BASE + NFC_MAIN_AREA(0); + /* check for 32-bit alignment? */ + u32 *p = (u32 *) buf; + u32 v = 0; + + for (; len > 0; len -= 4, main_buf += 4) + v = NFC_READL(main_buf); + if (v != *p++) + return -1; + return 0; +} + +static int fsl_nfc_get_hw_config(struct nand_chip *this) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 rcwh; + int rcwh_romloc; + int rcwh_ps; + int width; + int writesize = 0; + int sparesize = 0; + + /* + * Only support 2K for now. + * Remove this when others are tested and debugged. + */ + + writesize=CONFIG_FSL_NFC_WRITE_SIZE; + sparesize = CONFIG_FSL_NFC_SPARE_SIZE; + width=1; + + priv->sparesize = sparesize; + priv->writesize = writesize; + priv->width = width; + return 0; +} + + +#ifndef CONFIG_FSL_NFC_BOARD_CS_FUNC +#error failed +static void fsl_nfc_select_chip(u8 cs) +{ + +/* + u32 val = NFC_READW(NFC_BUF_ADDR); + + val &= ~0x60; + val |= cs << 5; + NFC_WRITEW(NFC_BUF_ADDR, val); +*/ +} +#define CONFIG_FSL_NFC_BOARD_CS_FUNC fsl_nfc_select_chip +#endif + + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @mtd MTD structure for the NAND Flash + * @chip val indicating select or deselect + */ +static void fsl_nfc_select_chip(struct mtd_info *mtd, int chip) +{ + /* + * This is different than the linux version. + * Switching between chips is done via + * board_nand_select_device. + * + * Only valid chip numbers here are + * 0 select + * -1 deselect + */ + + + /* + * Turn on appropriate chip. + */ + + nfc_write(NFC_ROW_ADDR, ((1<= CONFIG_FSL_NFC_CHIPS) { + printf("FSL NFC: " + "ERROR: Illegal chip select (chip = %d)\n", chip); + return; + } + priv->chipsel = chip; +} +/** + * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * + * Not for syndrome calculating ecc controllers which need a special oob layout + */ +static int mpc5125_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf) +{ + + unsigned int stat; + u8 ecc_bytes=0,i; + u8 ecc_bytes_map[]={0,8,12,15,23,30,45,60}; + stat=nfc_read(NFC_FLASH_CONFIG); + stat>>=17; + stat&=0x7; + ecc_bytes=ecc_bytes_map[stat]; + stat=nfc_read( MPC5125_NFC_ECC_STATUS_ADD+4); + if(stat&0x80) + { + /*check the page is erased*/ + if(stat&0x3f) + { + mtd->ecc_stats.failed++; + printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); + } + + } + else if(stat&0x3f) + { + /*printk(KERN_WARNING "Correctable ECC %d\n",stat&0x3f);*/ + mtd->ecc_stats.corrected+=stat&0x3f; + } + fsl_nfc_read_buf (mtd, buf, mtd->writesize); + copy_from_spare(mtd,chip->oob_poi, mtd->oobsize); + return 0; +} +/** + * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + */ +static void mpc5125_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + fsl_nfc_write_buf(mtd, buf, mtd->writesize); + copy_to_spare(mtd,chip->oob_poi, mtd->oobsize); +} + + +int board_nand_init(struct nand_chip *nand) +{ + struct mtd_info *mtd; + + priv = malloc(sizeof(*priv)); + if (!priv) { + printf("FSL NFC: failed to allocate priv structure\n"); + return -1; + } + memset(priv, 0, sizeof(*priv)); + + mpc5125_cfg_iopad_init(); + if (fsl_nfc_get_hw_config(nand) < 0) + return -1; + + mtd = &priv->mtd; + mtd->priv = nand; + + /* 5 us command delay time */ + nand->chip_delay = 8; + nand->page_shift =0; + nand->chip_shift = 0; + + nand->dev_ready = fsl_nfc_dev_ready; + nand->cmdfunc = mpc5125_nfc_command; + nand->waitfunc = fsl_nfc_wait; + nand->select_chip = fsl_nfc_select_chip; + nand->options = NAND_USE_FLASH_BBT; + if (priv->width == 2) { + nand->options |= NAND_BUSWIDTH_16; + nand->read_byte = fsl_nfc_read_byte16; + } + nand->read_byte = fsl_nfc_read_byte; + nand->read_word = fsl_nfc_read_word; + nand->write_buf = fsl_nfc_write_buf; + nand->read_buf = fsl_nfc_read_buf; + nand->verify_buf = fsl_nfc_verify_buf; + nand->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT; + nand->ecc.mode = NAND_ECC_HW; + nand->ecclayout=&nand_hw_eccoob_4k; + nand->ecc.size = 512; /* RS-ECC is applied for both MAIN+SPARE not MAIN alone */ + nand->ecc.bytes = 9; /* used for both main and spare area */ + nand->ecc.read_page = mpc5125_nand_read_page_hwecc; + nand->ecc.write_page = mpc5125_nand_write_page_hwecc; + + nfc_clear(NFC_IRQ_STATUS, CMD_DONE_EN_MASK| IDLE_EN_MASK); + + /* SET SECTOR SIZE */ + nfc_set_field( NFC_FLASH_CONFIG, + CONFIG_ECC_SRAM_ADDR_MASK, + CONFIG_ECC_SRAM_ADDR_SHIFT, (MPC5125_NFC_ECC_STATUS_ADD>>3)&0x00001ff); + + nfc_write(NFC_SECTOR_SIZE, CONFIG_FSL_NFC_WRITE_SIZE/2 | CONFIG_FSL_NFC_SPARE_SIZE/2); + nfc_set_field(NFC_FLASH_CONFIG, + CONFIG_ECC_MODE_MASK, + CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE); + nfc_set_field( NFC_FLASH_CONFIG, + CONFIG_ADDR_AUTO_INCR_MASK, + CONFIG_ADDR_AUTO_INCR_SHIFT, 0); + + nfc_set_field(NFC_FLASH_CONFIG, + CONFIG_BUFNO_AUTO_INCR_MASK, + CONFIG_BUFNO_AUTO_INCR_SHIFT, 1); + + nfc_set_field(NFC_FLASH_CONFIG, + CONFIG_16BIT_MASK, + CONFIG_16BIT_SHIFT, 0); + /* SET FAST_FLASH = 1 */ + nfc_set_field(NFC_FLASH_CONFIG, + CONFIG_FAST_FLASH_MASK, + CONFIG_FAST_FLASH_SHIFT, 1); + + nfc_set_field(NFC_FLASH_CONFIG, + CONFIG_BOOT_MODE_MASK, + CONFIG_BOOT_MODE_SHIFT, 0); + + nfc_set_field(NFC_FLASH_CONFIG, + CONFIG_ECC_SRAM_REQ_MASK, + CONFIG_ECC_SRAM_REQ_SHIFT, 1); + g_nfc_save.nfc_config=nfc_read(NFC_FLASH_CONFIG); + g_nfc_save.nfc_sectsize=nfc_read(NFC_SECTOR_SIZE); + g_nfc_save.nfc_status=nfc_read(NFC_IRQ_STATUS); + return 0; +} + + + diff --git a/drivers/mtd/nand/mpc5125_nfc_mtc.mtc b/drivers/mtd/nand/mpc5125_nfc_mtc.mtc new file mode 100644 index 0000000000..4f13032b5c Binary files /dev/null and b/drivers/mtd/nand/mpc5125_nfc_mtc.mtc differ diff --git a/drivers/mtd/nand/mpc5125_nfc_struct.h b/drivers/mtd/nand/mpc5125_nfc_struct.h new file mode 100644 index 0000000000..fb35b53e3a --- /dev/null +++ b/drivers/mtd/nand/mpc5125_nfc_struct.h @@ -0,0 +1,27 @@ +/* + Provider: LimePC Multimedia Technologies Co., Limited + Date:04/15/2010 + Copyright note: without provider's written consensus by the provider, any release + of provider's code could result in infrigement of provider's intellectural properties. + Autor:Cloudy Chen +*/ +#ifndef MPC5125_NFC_STRUCT_H +#define MPC5125_NFC_STRUCT_H +#define IS_2K_PAGE_NAND (priv->writesize == 2048) +#define IS_4K_PAGE_NAND (priv->writesize == 4096) +#define IS_LARGE_PAGE_NAND (priv->writesize > 512) + +#define PAGES_PER_BLOCK 0x100 +#define MPC5125_NFC_ECC_STATUS_ADD (NFC_SPARE_AREA(0)+0xf0) +#define PAGE_virtual_2K 0x0840 + +#define ioctl CONFIG_SYS_IOCTRL_ADDR + + +struct mpc5125_nfc_save_struct{ + u32 nfc_sectsize; + u32 nfc_config; + u32 nfc_status; +}; +#endif + diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index d33fee242f..e2470d8178 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2454,6 +2454,9 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) /* * Get the flash and manufacturer id and lookup if the type is supported */ + #ifdef CONFIG_ADS5125 + extern u8 mpc5125_nfc_get_id(struct mtd_info *mtd,int col); + #endif static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, struct nand_chip *chip, int busw, int *maf_id) @@ -2473,11 +2476,11 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Send the command for reading device ID */ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); - + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read manufacturer and device IDs */ + *maf_id = chip->read_byte(mtd); dev_id = chip->read_byte(mtd); - /* Try again to make sure, as some systems the bus-hold or other * interface concerns can cause random data which looks like a * possibly credible NAND flash to appear. If the two results do @@ -2487,10 +2490,9 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); /* Read manufacturer and device IDs */ - + tmp_manf = chip->read_byte(mtd); tmp_id = chip->read_byte(mtd); - if (tmp_manf != *maf_id || tmp_id != dev_id) { printk(KERN_INFO "%s: second ID read did not match " "%02x,%02x against %02x,%02x\n", __func__, @@ -2762,7 +2764,9 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.mode = NAND_ECC_SOFT; case NAND_ECC_SOFT: +#ifndef CONFIG_NAND_SPL chip->ecc.calculate = nand_calculate_ecc; +#endif chip->ecc.correct = nand_correct_data; chip->ecc.read_page = nand_read_page_swecc; chip->ecc.read_subpage = nand_read_subpage; @@ -2774,8 +2778,10 @@ int nand_scan_tail(struct mtd_info *mtd) break; case NAND_ECC_NONE: + /* printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " "This is not recommended !!\n"); + */ chip->ecc.read_page = nand_read_page_raw; chip->ecc.write_page = nand_write_page_raw; chip->ecc.read_oob = nand_read_oob_std; diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 077c3051bc..5d243a62ff 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -110,6 +110,9 @@ struct nand_flash_dev nand_flash_ids[] = { {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + /*64 Gigabit*/ + {"NAND 8 GiB 3,3V 8-bit", 0x68, 4096, 0x1000, 4096*256, 0}, + /* * Renesas AND 1 Gigabit. Those chips do not support extended id and * have a strange page/block layout ! The chosen minimum erasesize is diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c index 7078c4ef77..dd461307be 100644 --- a/drivers/net/mpc512x_fec.c +++ b/drivers/net/mpc512x_fec.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -17,6 +18,8 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUG 0 +#define CURFEC_ADDR(devname) ((devname[3]=='2') ? \ + (MPC512X_FEC + 0x2000) : MPC512X_FEC) #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC512x_FEC) @@ -41,13 +44,18 @@ static int rx_buff_idx = 0; static void mpc512x_fec_phydump (char *devname) { uint16 phyStatus, i; +#ifdef CONFIG_ADS5125 + uint8 phyAddr = ((devname[3]=='2') ? CONFIG_PHY2_ADDR : CONFIG_PHY_ADDR); +#else uint8 phyAddr = CONFIG_PHY_ADDR; +#endif uint8 reg_mask[] = { /* regs to print: 0...8, 21,27,31 */ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, }; + printf("Dump of %s at addr %2x\n", devname, phyAddr); for (i = 0; i < 32; i++) { if (reg_mask[i]) { miiphy_read (devname, phyAddr, i, &phyStatus); @@ -223,7 +231,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; #if (DEBUG & 0x1) - printf ("mpc512x_fec_init... Begin\n"); + printf ("mpc512x_fec_init... with eth_device %s Begin\n", dev->name); #endif /* Set interrupt mask register */ @@ -239,7 +247,12 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) fec->eth->op_pause = 0x00010020; /* Frame length=1522; MII mode */ +#ifdef CONFIG_ADS5125 + /* RMII Mode */ + fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x124; +#else fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24; +#endif /* Half-duplex, heartbeat disabled */ fec->eth->x_cntrl = 0x00000000; @@ -277,12 +290,16 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) { mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; - const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ +#ifdef CONFIG_ADS5125 + const uint8 phyAddr = ((dev->name[3]=='2') ? CONFIG_PHY2_ADDR : CONFIG_PHY_ADDR); +#else + const uint8 phyAddr = CONFIG_PHY_ADDR; +#endif int timeout = 1; uint16 phyStatus; #if (DEBUG & 0x1) - printf ("mpc512x_fec_init_phy... Begin\n"); + printf ("mpc512x_fec_init_phy... with dev %s Begin\n", dev->name); #endif /* @@ -407,6 +424,7 @@ static void mpc512x_fec_halt (struct eth_device *dev) int counter = 0xffff; #if (DEBUG & 0x2) + printf("In FEC Halt with device %s\n", dev->name); if (fec->xcv_type != SEVENWIRE) mpc512x_fec_phydump (dev->name); #endif @@ -458,7 +476,7 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data, volatile FEC_TBD *pTbd; #if (DEBUG & 0x20) - printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status); + printf("%s tbd status: 0x%04x\n", dev->name, fec->bdBase->tbd[fec->tbdIndex].status); #endif /* @@ -608,14 +626,23 @@ int mpc512x_fec_initialize (bd_t * bis) mpc512x_fec_priv *fec; struct eth_device *dev; int i; + char *memaddr; char *tmp, *end, env_enetaddr[6]; void * bd; +#ifdef CONFIG_ADS5125 /* 2nd RMII ethernet */ + char *act = getenv("ethact"); + memaddr = (char *)MPC512X_FEC; + if (act[3] == '2') + memaddr += 0x2000; +#else + memaddr = (char *)MPC512X_FEC; +#endif fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); dev = (struct eth_device *) malloc (sizeof(*dev)); memset (dev, 0, sizeof *dev); - fec->eth = (ethernet_regs *) MPC512X_FEC; + fec->eth = (ethernet_regs *) memaddr; # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; @@ -623,13 +650,17 @@ int mpc512x_fec_initialize (bd_t * bis) fec->xcv_type = MII10; # endif dev->priv = (void *)fec; - dev->iobase = MPC512X_FEC; + dev->iobase = (int)memaddr; dev->init = mpc512x_fec_init; dev->halt = mpc512x_fec_halt; dev->send = mpc512x_fec_send; dev->recv = mpc512x_fec_recv; sprintf (dev->name, "FEC ETHERNET"); +#ifdef CONFIG_ADS5125 + if (memaddr != (char *)MPC512X_FEC) + sprintf (dev->name, "FEC2 ETHERNET"); +#endif eth_register (dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) @@ -638,7 +669,7 @@ int mpc512x_fec_initialize (bd_t * bis) #endif /* Clean up space FEC's MIB and FIFO RAM ...*/ - memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400); + memset ((void *) memaddr + 0x200, 0x00, 0x400); /* * Malloc space for BDs (must be quad word-aligned) @@ -658,18 +689,26 @@ int mpc512x_fec_initialize (bd_t * bis) */ fec->eth->ievent = 0xffffffff; + /* rmii mode */ + fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x124; + /* * Try to set the mac address now. The fec mac address is * a garbage after reset. When not using fec for booting * the Linux fec driver will try to work with this garbage. */ tmp = getenv ("ethaddr"); + + if(!tmp) + tmp = "AA:BB:CC:DD:EE:FF"; // fixme + if (tmp) { for (i=0; i<6; i++) { env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0; if (tmp) tmp = (*end) ? end+1 : end; } + mpc512x_fec_set_hwaddr (fec, env_enetaddr); fec->eth->gaddr1 = 0x00000000; fec->eth->gaddr2 = 0x00000000; @@ -684,7 +723,7 @@ int mpc512x_fec_initialize (bd_t * bis) /********************************************************************/ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) { - ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + ethernet_regs *eth = (ethernet_regs *) CURFEC_ADDR(devname); uint32 reg; /* convenient holder for the PHY register */ uint32 phy; /* convenient holder for the PHY */ int timeout = 0xffff; @@ -705,7 +744,7 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r if (timeout == 0) { #if (DEBUG & 0x2) - printf ("Read MDIO failed...\n"); + printf ("Read MDIO addr %x failed (%s)...\n", phyAddr, devname); #endif return -1; } @@ -726,7 +765,7 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r /********************************************************************/ int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) { - ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + ethernet_regs *eth = (ethernet_regs *) CURFEC_ADDR(devname); uint32 reg; /* convenient holder for the PHY register */ uint32 phy; /* convenient holder for the PHY */ int timeout = 0xffff; @@ -744,7 +783,7 @@ int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 da if (timeout == 0) { #if (DEBUG & 0x2) - printf ("Write MDIO failed...\n"); + printf ("Write MDIO failed (%s)...\n", devname); #endif return -1; } diff --git a/fs/yaffs2/yaffscfg.c b/fs/yaffs2/yaffscfg.c index 16e84a4210..162b5deda1 100644 --- a/fs/yaffs2/yaffscfg.c +++ b/fs/yaffs2/yaffscfg.c @@ -185,8 +185,8 @@ int yaffs_StartUp(void) nBlocks = mtd->size / mtd->erasesize; flashDev->nCheckpointReservedBlocks = 10; - flashDev->startBlock = 0; - flashDev->endBlock = nBlocks - 1; + flashDev->startBlock = CONFIG_UBOOT_YAFFS2_START/mtd->erasesize; + flashDev->endBlock =(CONFIG_UBOOT_YAFFS2_START+CONFIG_UBOOT_YAFFS2_SIZE)/mtd->erasesize- 1; } else { diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index e5a3b2c170..476419a8b8 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -92,7 +92,7 @@ typedef struct global_data { #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) u32 lbc_clk; #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ -#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) ||defined(CONFIG_ADS5125) u32 i2c1_clk; u32 i2c2_clk; #endif diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 808786985e..8e341b9bb6 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -76,7 +76,10 @@ typedef struct wdt512x { * RTC Module Registers */ typedef struct rtclk512x { - u8 fixme[0x100]; + u8 fixme[0x24]; + u32 atr; + u32 kar; + u8 fixme1[0xD4]; } rtclk512x_t; /* @@ -387,7 +390,7 @@ typedef struct fec512x { * ULPI */ typedef struct ulpi512x { - u8 fixme[0x600]; + u8 fixme[0x400]; } ulpi512x_t; /* @@ -408,7 +411,11 @@ typedef struct pcidma512x { * IO Control */ typedef struct ioctrl512x { +#ifdef CONFIG_ADS5125 + u8 regs[0x1000]; +#else u32 regs[0x400]; +#endif } ioctrl512x_t; /* @@ -503,7 +510,54 @@ typedef struct pata512x { * PSC */ typedef struct psc512x { +#ifdef CONFIG_ADS5125 + volatile u8 mr1; /* PSC + 0x00 */ + volatile u8 res0[3]; + volatile u8 mr2; /* PSC + 0x04 */ + volatile u8 res0a[3]; + volatile u16 psc_status; /* PSC + 0x08 */ + volatile u16 res1; + volatile u16 psc_clock_select;/* PSC + 0x0C mpc5125 manual has this as u8 */ + /* it has u8 res after it and for compatibility */ + /* will keep u16 so high bits are set as before */ + volatile u16 res1a; + volatile u8 command; /* PSC + 0x10 */ + volatile u8 res2[3]; + union { /* PSC + 0x14 */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } buffer; +#define psc_buffer_8 buffer.buffer_8 +#define psc_buffer_16 buffer.buffer_16 +#define psc_buffer_32 buffer.buffer_32 + volatile u8 psc_ipcr; /* PSC + 0x18 */ + volatile u8 res3[3]; + volatile u8 psc_acr; /* PSC + 0x1C */ + volatile u8 res3a[3]; + volatile u16 psc_isr; /* PSC + 0x20 */ + volatile u16 res4; + volatile u16 psc_imr; /* PSC + 0x24 */ + volatile u16 res4a; + volatile u8 ctur; /* PSC + 0x28 */ + volatile u8 res5[3]; + volatile u8 ctlr; /* PSC + 0x2c */ + volatile u8 res6[3]; + volatile u32 ccr; /* PSC + 0x30 */ + volatile u8 res7[12]; + volatile u8 ivr; /* PSC + 0x40 */ + volatile u8 res8[3]; + volatile u8 ip; /* PSC + 0x44 */ + volatile u8 res9[3]; + volatile u8 op1; /* PSC + 0x48 */ + volatile u8 res10[3]; + volatile u8 op0; /* PSC + 0x4c */ + volatile u8 res11[3]; + volatile u32 sicr; /* PSC + 0x50 */ + volatile u8 res12[44]; +#else volatile u8 mode; /* PSC + 0x00 */ + /* serves as both mr1 and mr2 (only mr1 on mpc5121 */ volatile u8 res0[3]; union { /* PSC + 0x04 */ volatile u16 status; @@ -537,7 +591,7 @@ typedef struct psc512x { #define psc_imr isr_imr.imr volatile u16 res4; volatile u8 ctur; /* PSC + 0x18 */ - volatile u8 res5[3]; + volatile u8 res5[3];/*28*/ volatile u8 ctlr; /* PSC + 0x1c */ volatile u8 res6[3]; volatile u32 ccr; /* PSC + 0x20 */ @@ -552,6 +606,7 @@ typedef struct psc512x { volatile u8 res11[3]; volatile u32 sicr; /* PSC + 0x40 */ volatile u8 res12[60]; +#endif /* FIFOC is the same for all mpc512x */ volatile u32 tfcmd; /* PSC + 0x80 */ volatile u32 tfalarm; /* PSC + 0x84 */ volatile u32 tfstat; /* PSC + 0x88 */ @@ -561,8 +616,10 @@ typedef struct psc512x { volatile u16 tfwptr; /* PSC + 0x98 */ volatile u16 tfrptr; /* PSC + 0x9A */ volatile u32 tfsize; /* PSC + 0x9C */ +#ifndef ADS5125 volatile u8 res13[28]; - union { /* PSC + 0xBC */ +#endif + union { /* PSC + 0xBC */ volatile u8 buffer_8; volatile u16 buffer_16; volatile u32 buffer_32; @@ -635,7 +692,15 @@ typedef struct immap { u8 res3[0x500]; fec512x_t fec; /* Fast Ethernet Controller */ ulpi512x_t ulpi; /* USB ULPI */ - u8 res4[0xa00]; + u8 res4[0xc00]; +#ifdef CONFIG_ADS5125 + ulpi512x_t ulpi2; /* USB ULPI */ + u8 res5[0x400]; + fec512x_t fec2; /* 2nd Fast Ethernet Controller */ + gpt512x_t gpt2; /* 2nd General Purpose Timer */ + sdhc512x_t sdhc2; /* 2nd SDHC */ + u8 res6[0x3e00]; +#else utmi512x_t utmi; /* USB UTMI */ u8 res5[0x1000]; pcidma512x_t pci_dma; /* PCI DMA */ @@ -644,6 +709,7 @@ typedef struct immap { ios512x_t ios; /* PCI Sequencer */ pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ u8 res7[0xa00]; +#endif ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ ioctrl512x_t io_ctrl; /* IO Control */ iim512x_t iim; /* IC Identification module */ @@ -651,9 +717,14 @@ typedef struct immap { lpc512x_t lpc; /* LocalPlus Controller */ pata512x_t pata; /* Parallel ATA */ u8 res9[0xd00]; +#ifdef CONFIG_ADS5125 + psc512x_t psc[10]; /* PSCs */ + u8 res10[0x500]; +#else psc512x_t psc[12]; /* PSCs */ u8 res10[0x300]; - fifoc512x_t fifoc; /* FIFO Controller */ +#endif + fifoc512x_t fifoc; /* FIFO Controller PSC +0xF00 */ u8 res11[0x2000]; dma512x_t dma; /* DMA */ u8 res12[0xa800]; diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 8fda3f29fa..f326bfc244 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -33,6 +33,7 @@ * * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x4000_0000 - 0x400F_FFFF NFC (1 MB) * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) * 0x8200_0000 - 0x8200_001F CPLD (32 B) * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) @@ -65,6 +66,10 @@ #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ #define CONFIG_PCI #endif +/* + * Enable Fast boot + */ +#define CONFIG_FASTBOOT #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R @@ -130,54 +135,65 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ +#define MDDRC_SYS_CFG_RUN ~(0x10000000) #ifdef CONFIG_ADS5121_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 +#define MDDRC_SYS_CFG_MICRON 0xF8604A00 +#define MDDRC_TIME_CFG1_MICRON 0x54EC1168 +#define MDDRC_TIME_CFG2_MICRON 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#define MDDRC_SYS_CFG_MICRON 0xFA804A00 +#define MDDRC_SYS_CFG_MICRON_RUN 0xEA804A00 +#define MDDRC_TIME_CFG1_MICRON 0x68EC1168 +#define MDDRC_TIME_CFG2_MICRON 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define MDDRC_SYS_CFG_ELPIDA 0xFA802B00 +#define MDDRC_SYS_CFG_ELPIDA_RUN 0xEA802B00 +#define MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define MDDRC_TIME_CFG2_ELPIDA 0x35310864 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x06183D2E +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_CLK_BIT (1 << 29) +#define MDDRC_SYS_CFG_CKE_BIT (1 << 30) + +#define DDR_MRS_CAS(n) (n << 4) +#define DDR_MRS_WR(n) ((n-1) << 9) +#define MICRON_INIT_DEV_OP 0x01000002 | DDR_MRS_WR(2) | DDR_MRS_CAS(3) +#define ELPIDA_INIT_DEV_OP 0x01000002 | DDR_MRS_WR(4) | DDR_MRS_CAS(4) +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_EM2 0x01020000 +#define DDR_EM3 0x01030000 +#define DDR_EN_DLL 0x01010000 +#define DDR_RES_DLL 0x01000932 +#define DDR_RFSH 0x01080000 +#define DDR_OCD_DEFAULT 0x01010780 +#define DDR_OCD_EXIT 0x01010400 /* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111 /* * NOR FLASH on the Local Bus @@ -199,6 +215,42 @@ #undef CONFIG_SYS_FLASH_CHECKSUM +/* + * NAND FLASH + * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon/rev 4 boards only) + */ +#define CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0x40000000 +#endif +#define CONFIG_CMD_NAND 1 +/* + * The flash on ADS5121 board is two flash chips in one package + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 +/* + * Configuration parameters for MPC5121 NAND driver + */ +#define CONFIG_FSL_NFC_WIDTH 1 +#define CONFIG_FSL_NFC_WRITE_SIZE 2048 +#define CONFIG_FSL_NFC_SPARE_SIZE 64 +#define CONFIG_FSL_NFC_CHIPS 2 + +#ifndef __ASSEMBLY__ +/* + * ADS board as a custom chip select + */ +extern void ads5121_fsl_nfc_board_cs(int); +#define CONFIG_FSL_NFC_BOARD_CS_FUNC ads5121_fsl_nfc_board_cs +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_NAND_FSL_NFC */ + + /* * CPLD registers area is really only 32 bytes in size, but the smallest possible LP * window is 64KB @@ -222,7 +274,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ #else @@ -238,6 +290,7 @@ /* * Serial console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ #if CONFIG_PSC_CONSOLE != 3 #error CONFIG_PSC_CONSOLE must be 3 @@ -317,12 +370,6 @@ #define CONFIG_FEC_AN_TIMEOUT 1 #define CONFIG_HAS_ETH0 -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - /* * Environment */ @@ -349,12 +396,13 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#define CONFIG_CMD_NFS +#undef CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DATE -#undef CONFIG_CMD_FUSE +#undef CONFIG_CMD_DATE +#define CONFIG_IMM /* needed for CONFIG_CMD_FUSE */ +#define CONFIG_CMD_FUSE #define CONFIG_CMD_IDE #define CONFIG_CMD_EXT2 @@ -410,8 +458,8 @@ #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | HID0_ICE #define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_HIGH_BATS 1 /* High BATs supported */ @@ -462,12 +510,14 @@ "u-boot=ads5121/u-boot.bin\0" \ "bootfile=ads5121/uImage\0" \ "fdtfile=ads5121/ads5121.dtb\0" \ - "rootpath=/opt/eldk/ppc_6xx\n" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ "netdev=eth0\0" \ "consdev=ttyPSC0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsroot=${serverip}:${rootpath} ${othbootargs}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw ${othbootargs}\0" \ + "jffs2args=setenv bootargs root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 ${othbootargs}\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ @@ -486,6 +536,8 @@ "tftp ${fdt_addr_r} ${fdtfile};" \ "run ramargs addip addtty;" \ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ + "flash_jffs2=run jffs2args addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ "update=protect off ${u-boot_addr} +${filesize};" \ "era ${u-boot_addr} +${filesize};" \ @@ -493,7 +545,7 @@ "upd=run load update\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_BOOTCOMMAND "run flash_jffs2" #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 diff --git a/include/configs/ads5125.h b/include/configs/ads5125.h new file mode 100644 index 0000000000..1393665802 --- /dev/null +++ b/include/configs/ads5125.h @@ -0,0 +1,650 @@ +/* + * (C) Copyright 2008-2009 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ADS5125 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ADS5125 +/* + * Memory map for the ADS5125 board: + * + * 0x0000_0000 - 0x00FF_FFFF DDR RAM (16 MB) + * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x4000_0000 - 0x400F_FFFF NAND FLASH CONTROLLER + * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) + * 0x8200_0000 - 0x8200_001F CPLD (32 B) + * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ +#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ + +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_NAND +#endif + +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_YAFFS2 +#define CONFIG_UBOOT_YAFFS2_START 0xc00000 +#define CONFIG_UBOOT_YAFFS2_SIZE 0x10c00000 +#define BOARD_TYPE_ADS5125 1 +#define BOARD_TYPE_5125_MPU 2 +#define BOARD_TYPE BOARD_TYPE_5125_MPU + +#define HDMI_CHIP_SIL9034 1 +#define HDMI_CHIP_SIL9022A 2 +#define HDMI_CHIP_SELECT HDMI_CHIP_SIL9022A +#if (HDMI_CHIP_SELECT==HDMI_CHIP_SIL9022A) +#define CONFIG_HDMI_CHIP_SIL9022A +#endif +#define CONFIG_MISC_INIT_R +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif +/* + * Enable Fast boot + */ +#define CONFIG_FASTBOOT + +#define CONFIG_SYS_MPC512X_CLKIN 32768000 /* in Hz Change by Cloudy Chen */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +/* +#define CONFIG_MISC_INIT_R +*/ + +#define CFG_SYS_IMMR 0x80000000 +#define CFG_IMMR 0x80000000 +#define CONFIG_SYS_IMMR 0x80000000 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) +#define CONFIG_SYS_IOCTRL_ADDR (CONFIG_SYS_IMMR+0xA000) + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE + +#define CFG_DDR_BASE CONFIG_SYS_DDR_BASE +/* DDR Controller Configuration + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ + +#define MDDRC_SYS_CFG 0xfa804A00 +#define MDDRC_SYS_CFG_RUN 0xea804A00 +#define CFG_MDDRC_SYS_CFG_RUN MDDRC_SYS_CFG_RUN + +#define MDDRC_TIME_CFG1 0x68ec1189 //0x690e1189 +#define CFG_MDDRC_TIME_CFG1 MDDRC_TIME_CFG1 +#define MDDRC_TIME_CFG2 0x34310864 //0x34a90864 +#define CFG_MDDRC_TIME_CFG2 MDDRC_TIME_CFG2 +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define CFG_MDDRC_SYS_CFG_EN MDDRC_SYS_CFG_EN +#define MDDRC_TIME_CFG0 0x00003c2d //0x00003D2E +#define CFG_MDDRC_TIME_CFG0 MDDRC_TIME_CFG0 +#define MDDRC_TIME_CFG0_RUN 0x06183c2d +#define CFG_MDDRC_TIME_CFG0_RUN MDDRC_TIME_CFG0_RUN + +#define DDR_ODT_150 0x40 +#define DDR_ODT_75 0x04 +#define DDR_ODT_50 0x44 +#define DDR_OCD_DFLT_MASK 0x00000380 +#define DDR_MRS_CAS(n) (n << 4) +#define DDR_MRS_WR(n) ((n-1) << 9) +#define MDDRC_SYS_CFG_CLK_BIT (1 << 29) +#define MDDRC_SYS_CFG_CKE_BIT (1 << 30) + +#define DDR_RFSH 0x01080000 +#define CFG_MICRON_RFSH DDR_RFSH +#define DDR_INIT_DEV_OP 0x01000432 /*0x01000002 | DDR_MRS_WR(4) | DDR_MRS_CAS(4)*/ +#define CFG_MICRON_INIT_DEV_OP DDR_INIT_DEV_OP +#define DDR_NOP 0x01380000 +#define CFG_MICRON_NOP DDR_NOP +#define DDR_PCHG_ALL 0x01100400 +#define CFG_MICRON_PCHG_ALL DDR_PCHG_ALL +#define DDR_EM2 0x01020000 +#define CFG_MICRON_EM2 DDR_EM2 +#define DDR_EM3 0x01030000 +#define CFG_MICRON_EM3 DDR_EM3 +#define DDR_EN_DLL 0x01010000 +#define CFG_MICRON_EN_DLL DDR_EN_DLL +#define DDR_RES_DLL DDR_INIT_DEV_OP | 0x00000100 +#define DDR_RFSH 0x01080000 +#define DDR_OCD_DEFAULT 0x01010400 | DDR_OCD_DFLT_MASK | DDR_ODT_50 +#define CFG_MICRON_OCD_DEFAULT DDR_OCD_DEFAULT +#define DDR_OCD_EXIT DDR_OCD_DEFAULT & ~DDR_OCD_DFLT_MASK + +/* DDR Priority Manager Configuration */ +#define MDDRCGRP_PM_CFG1 0x000777aa //0x00077777 +#define CFG_MDDRCGRP_PM_CFG1 MDDRCGRP_PM_CFG1 +#define MDDRCGRP_PM_CFG2 0x00000055 //0x00000000 +#define CFG_MDDRCGRP_PM_CFG2 MDDRCGRP_PM_CFG2 +#define MDDRCGRP_HIPRIO_CFG 0x00000000 //0x00000001 +#define CFG_MDDRCGRP_HIPRIO_CFG MDDRCGRP_HIPRIO_CFG +#define MDDRCGRP_LUT0_MU 0x11111117 //0xFFEEDDCC +#define CFG_MDDRCGRP_LUT0_MU MDDRCGRP_LUT0_MU +#define MDDRCGRP_LUT0_ML 0x7777777a //0xBBAAAAAA +#define CFG_MDDRCGRP_LUT0_ML MDDRCGRP_LUT0_ML +#define MDDRCGRP_LUT1_MU 0x444eeeee //0x66666666 +#define CFG_MDDRCGRP_LUT1_MU MDDRCGRP_LUT1_MU +#define MDDRCGRP_LUT1_ML 0xeeeeeeee //0x55555555 +#define CFG_MDDRCGRP_LUT1_ML MDDRCGRP_LUT1_ML +#define MDDRCGRP_LUT2_MU 0x44444444 +#define CFG_MDDRCGRP_LUT2_MU MDDRCGRP_LUT2_MU +#define MDDRCGRP_LUT2_ML 0x44444444 +#define CFG_MDDRCGRP_LUT2_ML MDDRCGRP_LUT2_ML +#define MDDRCGRP_LUT3_MU 0x55555555 +#define CFG_MDDRCGRP_LUT3_MU MDDRCGRP_LUT3_MU +#define MDDRCGRP_LUT3_ML 0x55555558 +#define CFG_MDDRCGRP_LUT3_ML MDDRCGRP_LUT3_ML +#define MDDRCGRP_LUT4_MU 0x11111111 +#define CFG_MDDRCGRP_LUT4_MU MDDRCGRP_LUT4_MU +#define MDDRCGRP_LUT4_ML 0x1111117c //0x11111122 +#define CFG_MDDRCGRP_LUT4_ML MDDRCGRP_LUT4_ML +#define MDDRCGRP_LUT0_AU 0x33333377 //0xaaaaaaaa +#define CFG_MDDRCGRP_LUT0_AU MDDRCGRP_LUT0_AU +#define MDDRCGRP_LUT0_AL 0x7777eeee //0xaaaaaaaa +#define CFG_MDDRCGRP_LUT0_AL MDDRCGRP_LUT0_AL +#define MDDRCGRP_LUT1_AU 0x11111111 //0x66666666 +#define CFG_MDDRCGRP_LUT1_AU MDDRCGRP_LUT1_AU +#define MDDRCGRP_LUT1_AL 0x11111111 //0x66666666 +#define CFG_MDDRCGRP_LUT1_AL MDDRCGRP_LUT1_AL +#define MDDRCGRP_LUT2_AU 0x11111111 +#define CFG_MDDRCGRP_LUT2_AU MDDRCGRP_LUT2_AU +#define MDDRCGRP_LUT2_AL 0x11111111 +#define CFG_MDDRCGRP_LUT2_AL MDDRCGRP_LUT2_AL +#define MDDRCGRP_LUT3_AU 0x11111111 +#define CFG_MDDRCGRP_LUT3_AU MDDRCGRP_LUT3_AU +#define MDDRCGRP_LUT3_AL 0x11111111 +#define CFG_MDDRCGRP_LUT3_AL MDDRCGRP_LUT3_AL +#define MDDRCGRP_LUT4_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_AU MDDRCGRP_LUT4_AU +#define MDDRCGRP_LUT4_AL 0x11111111 +#define CFG_MDDRCGRP_LUT4_AL MDDRCGRP_LUT4_AL + +#define IOCTRL_MUX_CS2 0x43 /* CS2 IO pin must be set in start.S */ +#define IOCTRL_MUX_PSC9 0x23 /* ditto for UART1 in case it's Console */ +#define IOCTRL_GBOBE_ON 0x01 + +/* + * NOR FLASH on the Local Bus + */ + #if(BOARD_TYPE==BOARD_TYPE_5125_MPU) +#define CONFIG_SYS_NO_FLASH + #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + #else +#undef CONFIG_BKUP_FLASH +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#ifdef CONFIG_BKUP_FLASH +/* Backup and main flash may not be the same size & same sector in the future */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* max flash size in bytes */ +#else +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* max flash size in bytes */ +#endif +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ +#define CONFIG_SYS_FLASH_SIZE 0x02000000 +#define CFG_FLASH_SIZE CONFIG_SYS_FLASH_SIZE +#endif +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * NAND FLASH + * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon/rev 4 boards only) + */ +#define RCWHR 0xe04 +#define NAND_BOOT (1<<5) +/* +#define CONFIG_NAND_SPL +*/ +#define CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#define CONFIG_SYS_NAND_SPACE 0x100000 +#define CFG_FLASH_BASE CONFIG_SYS_NAND_BASE +#define CFG_FLASH_SIZE CONFIG_SYS_NAND_SPACE +#define CFG_NAND_U_BOOT_SIZE (256 << 10) +#define CFG_LOADER_DDR_START 0x00100000 +#define CFG_NAND_U_BOOT_DST (0x1000000) +#define CFG_NAND_U_BOOT_START (CFG_NAND_U_BOOT_DST+0x100) /* 1st 2K page of NAND is copied so * + * we need to offset by 0x800 */ + +#else +#define CONFIG_SYS_NAND_BASE 0x40000000 +#endif +#define CONFIG_CMD_NAND 1 + +#define CFG_NAND_BASE CONFIG_SYS_NAND_BASE +/* + * The flash on ADS5121 board is two flash chips in one package + */ + #define CFG_NAND_BLOCK_SIZE 0x20000 /* 128K, 64 x 2K opages per block */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 +/* + * Configuration parameters for MPC5121 NAND driver + */ + + +#define CONFIG_FSL_NFC_WRITE_SIZE 4096 +#define CONFIG_FSL_NFC_SPARE_SIZE 128 + +#define CONFIG_FSL_NFC_WIDTH 1 + +#define CONFIG_FSL_NFC_CHIPS 1 + +#ifndef __ASSEMBLY__ +/* + * ADS board as a custom chip select + */ +extern void ads5125_fsl_nfc_board_cs(int); +#define CONFIG_FSL_NFC_BOARD_CS_FUNC ads5125_fsl_nfc_board_cs +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_NAND_FSL_NFC */ + +#if(BOARD_TYPE!=BOARD_TYPE_5125_MPU) +/* + * CPLD registers area is really only 32 bytes in size, but the smallest possible LP + * window is 64KB + */ +#define CONFIG_SYS_CPLD_BASE 0x82000000 +#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ +#define IS_CFG1_SWITCH (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x13)) & 0x80) +#endif + +#define CONFIG_SYS_SRAM_BASE 0x30000000 +#define CONFIG_SYS_SRAM_SIZE 0x00008000 /* 32 KB */ +#define CFG_SRAM_BASE CONFIG_SYS_SRAM_BASE +#define CFG_SRAM_SIZE CONFIG_SYS_SRAM_SIZE /* 32 KB */ + + +#define CONFIG_SYS_CS0_CFG 0x05059110 /* ALE active low, data size 2bytes */ +#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ +#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ + +/* Use SRAM for initial stack */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ +#define CFG_MONITOR_BASE CONFIG_SYS_MONITOR_BASE /* Start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */ +/* Use SRAM for initial stack */ +#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE CONFIG_SYS_GBL_DATA_SIZE /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CONFIG_SYS_INIT_SP_OFFSET + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_SPLASH_SIZE (2 * 1024 * 1024) +#else +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC9 */ +#if CONFIG_PSC_CONSOLE != 1 +#error CONFIG_PSC_CONSOLE must be 1 +#endif +#define CONFIG_PSC_CONSOLE2 9 /* other console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC1_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC1_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC1_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC1_RX_ADDR + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + + +/* I2C */ +#define CONFIG_HARD_I2C /* defd in ads5121 I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#if 0 +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#endif + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 10ms of delay */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1 +#define CONFIG_PHY2_ADDR 0x1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + + +/* + * Environment + */ + #if defined(CONFIG_NAND_U_BOOT) +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x2000) +#define CONFIG_SYS_ENV_ADDR CONFIG_ENV_ADDR +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET (512 * 1024) +#define CONFIG_ENV_SECT_SIZE CFG_NAND_BLOCK_SIZE +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_SYS_ENV_SIZE CONFIG_ENV_SIZE + +#define CMD_SAVEENV +#define CONFIG_ENV_START_PAGE 0x200 + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) +#elif !defined(CFG_RAMBOOT) +#define CONFIG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the Flash sector size */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE 0x2000 +#ifdef CONFIG_BKUP_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (128K) for env */ +#define CONFIG_SYS_ENV_SECT_SIZE 0x20000 /* one sector (128K) for env */ +#else +#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (128K) for env */ +#define CONFIG_SYS_ENV_SECT_SIZE 0x20000 /* one sector (128K) for env */ +#endif +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_ENV_ADDR + CONFIG_SYS_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#endif +/* + * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. + * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set + * to 0xFFFF, watchdog timeouts after about 64s. For details refer + * to chapter 36 of the MPC5125e Reference Manual. + */ +/* #define CONFIG_WATCHDOG */ /* enable watchdog */ +#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF + + /* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#ifdef CONFIG_CMD_KGDB + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_INIT CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | HID0_ICE +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_TIMESTAMP + +#define CONFIG_HOSTNAME ads5125 +#define CONFIG_BOOTFILE ads5125/uImage +#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx + +#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ethaddr=AA:BB:CC:DD:EE:FF\0" \ + "ramdiskfile=ads5125/uRamdisk\0" \ + "fdtfile=ads5125/ads5125.dtb\0" \ + "u-boot=ads5125/u-boot.bin\0" \ + "netdev=eth0\0" \ + "ipaddr=192.168.10.205\0" \ + "consdev=tty0\0" \ + "serverip=192.168.10.74\0" \ + "fdtaddr=4000000\0" \ + "fdtfile=mpc5125-twr.dtb\0" \ + "kernel_name=vmlinux-twr-5125.bin\0" \ + "consoledev=ttyPSC0\0" \ + "flash_kernel=0x300\0" \ + "flash_dtb=0xb00\0" \ + "nandboot=setenv bootargs root=/dev/mtdblock6 rw rootfstype=yaffs2 console=$consdev,$baudrate;"\ + "nand_r $kernel_loader_addr $flash_kernel 0x400000;nand_r $fdt_loader_addr $flash_dtb 0x3000;bootm $kernel_loader_addr - $fdt_loader_addr\0" \ + "fdt_name=mpc5125-twr.dtb\0" \ + "ramdisk_name=rootfs.ext2.gz.uboot-common\0" \ + "ramdisk_flash_addr=0xc00\0" \ + "kernel_loader_addr=0x2000000\0" \ + "fdt_loader_addr=0x2800000\0" \ + "ramdisk_loader_addr=0x3000000\0" \ + "nand_ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate;"\ + "nand_r 0x2000000 $flash_kernel 0x400000;nand_r 0x2800000 $flash_dtb 0x3000;nand_r 0x3000000 0xc00 0x500000;;bootm $kernel_loader_addr $ramdisk_loader_addr $fdt_loader_addr\0" \ + "uboot_name=u-boot-second-usb.bin\0" \ + "uboot_name_first=u-boot-first-usb.bin\0" \ + "uboot_size=0x60000\0" \ + "uboot_update=tftp 0x1000000 u-boot-spl-2k.bin;nand_e 0x00 0x01;nand_loader 0x1000000 0x00 0x800;"\ + "tftp 0x1000000 $uboot_name_first ;nand_w 0x1000000 0x8 0x60000;" \ + "tftp 0x1000000 $uboot_name ;nand_e 0x100 0x101;nand_w 0x1000000 0x100 0x60000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "mqx_name=extram_d.bin\0" \ + "mqx_size=0xa00000\0" \ + "mqx_addr=0x10000\0" \ + "mqx_flash_addr_s=0x80000\0" \ + "mqx_flash_addr_e=0x863ff\0" \ + "kernel_rootfs_update=tftp 0x3000000 $fdt_name;nand_e $flash_dtb 0xb01;nand_w 0x3000000 $flash_dtb 0x3000;tftp 0x3000000 $kernel_name;nand_e $flash_kernel 0xaff;nand_w 0x3000000 $flash_kernel 0x400000;tftp 0x3000000 $ramdisk_name;nand_e 0xc00 0x13ff;nand_w 0x3000000 0xc00 0x500000\0" \ + "mqx_update=tftp $mqx_addr $mqx_name;nand_e $mqx_flash_addr_s $mqx_flash_addr_e;nand_w $mqx_addr $mqx_flash_addr_s $mqx_size\0"\ + "mqxboot=nand_r $mqx_addr $mqx_flash_addr_s $mqx_size;go $mqx_addr\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run nandboot" + +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 + +#define OF_CPU "PowerPC,5125@0" +#define OF_SOC_COMPAT "fsl,mpc5125-immr" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@80000000/serial@11300" + +#endif /* __CONFIG_H */ diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h index 9036b74f86..32b1900b1e 100644 --- a/include/linux/mtd/compat.h +++ b/include/linux/mtd/compat.h @@ -24,7 +24,7 @@ #define vfree(ptr) free(ptr) #define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) - +#define LINUX_VERSION_CODE KERNEL_VERSION(2,6,29) /* * ..and if you can't take the strict * types, you can specify one yourself. diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h index 410c5dd2fb..8d5f60c75e 100644 --- a/include/linux/mtd/mtd-abi.h +++ b/include/linux/mtd/mtd-abi.h @@ -123,7 +123,7 @@ struct nand_oobfree { */ struct nand_ecclayout { uint32_t eccbytes; - uint32_t eccpos[64]; + uint32_t eccpos[128]; uint32_t oobavail; struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; }; diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 354e3a0bc4..e9bf5c4a8a 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -110,7 +110,7 @@ struct mtd_oob_ops { struct mtd_info { u_char type; u_int32_t flags; - u_int32_t size; /* Total size of the MTD */ + u_int64_t size; /* Total size of the MTD */ /* "Major" erase size for the device. Naïve users may take this * to be the only erase size available, or may use the more detailed @@ -268,11 +268,13 @@ int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs, #ifdef CONFIG_MTD_PARTITIONS void mtd_erase_callback(struct erase_info *instr); #else +/* static inline void mtd_erase_callback(struct erase_info *instr) { if (instr->callback) instr->callback(instr); } +*/ #endif /* diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index a4ad5711d6..212a593b97 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -396,7 +396,7 @@ struct nand_chip { int bbt_erase_shift; int chip_shift; int numchips; - unsigned long chipsize; + u64 chipsize; int pagemask; int pagebuf; int subpagesize; @@ -454,7 +454,7 @@ struct nand_flash_dev { char *name; int id; unsigned long pagesize; - unsigned long chipsize; + u64 chipsize; unsigned long erasesize; unsigned long options; }; diff --git a/include/mpc5125_nfc.h b/include/mpc5125_nfc.h new file mode 100644 index 0000000000..cd3e6c61c4 --- /dev/null +++ b/include/mpc5125_nfc.h @@ -0,0 +1,357 @@ +/* + * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. + * + * Author: Shaohui Xie + * + * Description: + * MPC5125 Nand driver. + * + * This is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef MPC5125_NFC_H +#define MPC5125_NFC_H + +/* I/O Control Register OFFSETS */ +#define NFC_CE0 1 +#define NFC_CE1 2 +#define NFC_CE2 4 +#define NFC_CE3 8 +#define NFC_SEL_RB0 1 +#define NFC_SEL_RB1 2 +#define NFC_SEL_RB2 4 +#define NFC_SEL_RB3 8 + +/******************** IO control fields ************************/ +#define DS_MSR_1 0x00 +#define DS_MSR_2 0x01 +#define DS_MSR_3 0x02 +#define DS_MSR_4 0x03 +#define ST_Disabled 0x00 +#define ST_Enabled 0x04 +#define PAD_FUNC0 0x00 +#define PAD_FUNC1 0x20 +#define PAD_FUNC2 0x40 +#define PAD_FUNC3 0x60 +#define PUD_PUE 0x18 +/**************************************************************/ + +/* Chip select and rb select Define */ + +/* NFC PAD Define */ +#define PAD_NFC_IO PAD_FUNC0 +#define PAD_NFC_ALE PAD_FUNC0 +#define PAD_NFC_CLE PAD_FUNC0 +#define PAD_NFC_WE PAD_FUNC0 +#define PAD_NFC_RE PAD_FUNC0 +#define PAD_NFC_CE0 PAD_FUNC0 +#define PAD_NFC_CE1 PAD_FUNC1 +#define PAD_NFC_CE2 PAD_FUNC2 +#define PAD_NFC_CE3 PAD_FUNC2 +#define PAD_NFC_RB0 PAD_FUNC0 +#define PAD_NFC_RB1 PAD_FUNC2 +#define PAD_NFC_RB2 PAD_FUNC2 +#define PAD_NFC_RB3 PAD_FUNC2 + +/* NFC Control PAD Define */ +#define BALL_NFC_CE0 IOCTL_NFC_CE0_B +#define BALL_NFC_CE1 IOCTL_SDHC1_CLK +#define BALL_NFC_CE2 IOCTL_PSC1_4 +#define BALL_NFC_CE3 IOCTL_J1850_TX +#define BALL_NFC_RB0 IOCTL_NFC_RB +#define BALL_NFC_RB1 IOCTL_FEC1_TXD_0 +#define BALL_NFC_RB2 IOCTL_PSC1_3 +#define BALL_NFC_RB3 IOCTL_J1850_RX +#define BALL_NFC_ALE IOCTL_EMB_AD19 +#define BALL_NFC_CLE IOCTL_EMB_AD18 +#define BALL_NFC_WE IOCTL_EMB_AD16 +#define BALL_NFC_RE IOCTL_EMB_AD17 + +/* NFC IO Pad Define */ +#define BALL_NFC_IO0 IOCTL_EMB_AD00 +#define BALL_NFC_IO1 IOCTL_EMB_AD01 +#define BALL_NFC_IO2 IOCTL_EMB_AD02 +#define BALL_NFC_IO3 IOCTL_EMB_AD03 +#define BALL_NFC_IO4 IOCTL_EMB_AD04 +#define BALL_NFC_IO5 IOCTL_EMB_AD05 +#define BALL_NFC_IO6 IOCTL_EMB_AD06 +#define BALL_NFC_IO7 IOCTL_EMB_AD07 + +/* Addresses for NFC MAIN RAM BUFFER areas */ +#define NFC_MAIN_AREA(n) ((n) * 0x1000) + +/* Addresses for NFC SPARE BUFFER areas */ +#define NFC_SPARE_BUFFERS 8 +#define NFC_SPARE_LEN 0x10 +#define NFC_SPARE_AREA(n) (0x800 + NFC_MAIN_AREA(n) ) + +#define PAGE_2K 0x0800 +#define PAGE_64 0x0040 + +/* MPC5125 NFC registers */ +/* Typical Flash Commands */ +#define READ_PAGE_CMD_CODE 0x7EE0 +#define PROGRAM_PAGE_CMD_CODE 0x7FC0 +#define ERASE_CMD_CODE 0x4EC0 +#define READ_ID_CMD_CODE 0x4804 +#define RESET_CMD_CODE 0x4040 +#define DMA_PROGRAM_PAGE_CMD_CODE 0xFFC8 +#define RANDOM_IN_CMD_CODE 0x7140 +#define RANDOM_OUT_CMD_CODE 0x70E0 +#define STATUS_READ_CMD_CODE 0x4068 + +#define PAGE_READ_CMD_BYTE1 0x00 +#define PAGE_READ_CMD_BYTE2 0x30 +#define PROGRAM_PAGE_CMD_BYTE1 0x80 +#define PROGRAM_PAGE_CMD_BYTE2 0x10 +#define READ_STATUS_CMD_BYTE 0x70 +#define ERASE_CMD_BYTE1 0x60 +#define ERASE_CMD_BYTE2 0xD0 +#define READ_ID_CMD_BYTE 0x90 +#define RESET_CMD_BYTE 0xFF +#define RANDOM_OUT_CMD_BYTE1 0x05 +#define RANDOM_OUT_CMD_BYTE2 0xE0 + +/* NFC ECC mode define */ +#define ECC_BYPASS 0x0 +#define ECC_8_BYTE 0x1 +#define ECC_12_BYTE 0x2 +#define ECC_15_BYTE 0x3 +#define ECC_23_BYTE 0x4 +#define ECC_30_BYTE 0x5 +#define ECC_45_BYTE 0x6 +#define ECC_60_BYTE 0x7 +#define ECC_ERROR 1 +#define ECC_RIGHT 0 + +/***************** Module-Relative Register Offsets *************************/ +#define NFC_SRAM_BUFFER 0x0000 +#define NFC_FLASH_CMD1 0x3F00 +#define NFC_FLASH_CMD2 0x3F04 +#define NFC_COL_ADDR 0x3F08 +#define NFC_ROW_ADDR 0x3F0c +#define NFC_FLASH_COMMAND_REPEAT 0x3F10 +#define NFC_ROW_ADDR_INC 0x3F14 +#define NFC_FLASH_STATUS1 0x3F18 +#define NFC_FLASH_STATUS2 0x3F1c +#define NFC_DMA1_ADDR 0x3F20 +#define NFC_DMA2_ADDR 0x3F34 +#define NFC_DMA_CONFIG 0x3F24 +#define NFC_CACHE_SWAP 0x3F28 +#define NFC_SECTOR_SIZE 0x3F2c +#define NFC_FLASH_CONFIG 0x3F30 +#define NFC_IRQ_STATUS 0x3F38 + +/***************** Module-Relative Register Reset Value *********************/ +#define NFC_SRAM_BUFFER_RSTVAL 0x00000000 +#define NFC_FLASH_CMD1_RSTVAL 0x30FF0000 +#define NFC_FLASH_CMD2_RSTVAL 0x007EE000 +#define NFC_COL_ADDR_RSTVAL 0x00000000 +#define NFC_ROW_ADDR_RSTVAL 0x11000000 +#define NFC_FLASH_COMMAND_REPEAT_RSTVAL 0x00000000 +#define NFC_ROW_ADDR_INC_RSTVAL 0x00000001 +#define NFC_FLASH_STATUS1_RSTVAL 0x00000000 +#define NFC_FLASH_STATUS2_RSTVAL 0x00000000 +#define NFC_DMA1_ADDR_RSTVAL 0x00000000 +#define NFC_DMA2_ADDR_RSTVAL 0x00000000 +#define NFC_DMA_CONFIG_RSTVAL 0x00000000 +#define NFC_CACHE_SWAP_RSTVAL 0x0FFE0FFE +#define NFC_SECTOR_SIZE_RSTVAL 0x00000420 +#define NFC_FLASH_CONFIG_RSTVAL 0x000EA631 +#define NFC_IRQ_STATUS_RSTVAL 0x04000000 + +/***************** Module-Relative Register Mask *************************/ + +/* NFC_FLASH_CMD1 Field */ +#define CMD1_MASK 0xFFFF0000 +#define CMD1_SHIFT 0 +#define CMD_BYTE2_MASK 0xFF000000 +#define CMD_BYTE2_SHIFT 24 +#define CMD_BYTE3_MASK 0x00FF0000 +#define CMD_BYTE3_SHIFT 16 + +/* NFC_FLASH_CM2 Field */ +#define CMD2_MASK 0xFFFFFF07 +#define CMD2_SHIFT 0 +#define CMD_BYTE1_MASK 0xFF000000 +#define CMD_BYTE1_SHIFT 24 +#define CMD_CODE_MASK 0x00FFFF00 +#define CMD_CODE_SHIFT 8 +#define BUFNO_MASK 0x00000006 +#define BUFNO_SHIFT 1 +#define BUSY_MASK 0x00000001 +#define BUSY_SHIFT 0 +#define START_MASK 0x00000001 +#define START_SHIFT 0 + +/* NFC_COL_ADDR Field */ +#define COL_ADDR_MASK 0x0000FFFF +#define COL_ADDR_SHIFT 0 +#define COL_ADDR_COL_ADDR2_MASK 0x0000FF00 +#define COL_ADDR_COL_ADDR2_SHIFT 8 +#define COL_ADDR_COL_ADDR1_MASK 0x000000FF +#define COL_ADDR_COL_ADDR1_SHIFT 0 + +/* NFC_ROW_ADDR Field */ +#define ROW_ADDR_MASK 0x00FFFFFF +#define ROW_ADDR_SHIFT 0 +#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 +#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 +#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 +#define ROW_ADDR_CHIP_SEL_SHIFT 24 +#define ROW_ADDR_ROW_ADDR3_MASK 0x00FF0000 +#define ROW_ADDR_ROW_ADDR3_SHIFT 16 +#define ROW_ADDR_ROW_ADDR2_MASK 0x0000FF00 +#define ROW_ADDR_ROW_ADDR2_SHIFT 8 +#define ROW_ADDR_ROW_ADDR1_MASK 0x000000FF +#define ROW_ADDR_ROW_ADDR1_SHIFT 0 + +/* NFC_FLASH_COMMAND_REPEAT Field */ +#define COMMAND_REPEAT_MASK 0x0000FFFF +#define COMMAND_REPEAT_SHIFT 0 +#define COMMAND_REPEAT_REPEAT_COUNT_MASK 0x0000FFFF +#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT 0 + +/* NFC_ROW_ADDR_INC Field */ +#define ROW_ADDR_INC_MASK 0x00FFFFFF +#define ROW_ADDR_INC_SHIFT 0 +#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK 0x00FF0000 +#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT 16 +#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK 0x0000FF00 +#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT 8 +#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK 0x000000FF +#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT 0 + +/* NFC_FLASH_STATUS1 Field */ +#define STATUS1_MASK 0xFFFFFFFF +#define STATUS1_SHIFT 0 +#define STATUS1_ID_BYTE1_MASK 0xFF000000 +#define STATUS1_ID_BYTE1_SHIFT 24 +#define STATUS1_ID_BYTE2_MASK 0x00FF0000 +#define STATUS1_ID_BYTE2_SHIFT 16 +#define STATUS1_ID_BYTE3_MASK 0x0000FF00 +#define STATUS1_ID_BYTE3_SHIFT 8 +#define STATUS1_ID_BYTE4_MASK 0x000000FF +#define STATUS1_ID_BYTE4_SHIFT 0 + +/* NFC_FLASH_STATUS2 Field */ +#define STATUS2_MASK 0xFF0000FF +#define STATUS2_SHIFT 0 +#define STATUS2_ID_BYTE5_MASK 0xFF000000 +#define STATUS2_ID_BYTE5_SHIFT 24 +#define STATUS_BYTE1_MASK 0x000000FF +#define STATUS2_STATUS_BYTE1_SHIFT 0 + +/* NFC_DMA1_ADDR Field */ +#define DMA1_ADDR_MASK 0xFFFFFFFF +#define DMA1_ADDR_SHIFT 0 +#define DMA1_ADDR_DMA1_ADDR_MASK 0xFFFFFFFF +#define DMA1_ADDR_DMA1_ADDR_SHIFT 0 + +/* DMA2_ADDR Field */ +#define DMA2_ADDR_MASK 0xFFFFFFFF +#define DMA2_ADDR_SHIFT 0 +#define DMA2_ADDR_DMA2_ADDR_MASK 0xFFFFFFFF +#define DMA2_ADDR_DMA2_ADDR_SHIFT 0 + +/* DMA_CONFIG Field */ +#define DMA_CONFIG_MASK 0xFFFFFFFF +#define DMA_CONFIG_SHIFT 0 +#define DMA_CONFIG_DMA1_CNT_MASK 0xFFF00000 +#define DMA_CONFIG_DMA1_CNT_SHIFT 20 +#define DMA_CONFIG_DMA2_CNT_MASK 0x000FE000 +#define DMA_CONFIG_DMA2_CNT_SHIFT 13 +#define DMA_CONFIG_DMA2_OFFSET_MASK 0x00001FC0 +#define DMA_CONFIG_DMA2_OFFSET_SHIFT 2 +#define DMA_CONFIG_DMA1_ACT_MASK 0x00000002 +#define DMA_CONFIG_DMA1_ACT_SHIFT 1 +#define DMA_CONFIG_DMA2_ACT_MASK 0x00000001 +#define DMA_CONFIG_DMA2_ACT_SHIFT 0 + +/* NFC_CACHE_SWAP Field */ +#define CACHE_SWAP_MASK 0x0FFE0FFE +#define CACHE_SWAP_SHIFT 1 +#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK 0x0FFE0000 +#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT 17 +#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK 0x00000FFE +#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT 1 + +/* NFC_SECTOR_SIZE Field */ +#define SECTOR_SIZE_MASK 0x00001FFF +#define SECTOR_SIZE_SHIFT 0 +#define SECTOR_SIZE_SECTOR_SIZE_MASK 0x00001FFF +#define SECTOR_SIZE_SECTOR_SIZE_SHIFT 0 + +/* NFC_FLASH_CONFIG Field */ +#define CONFIG_MASK 0xFFFFFFFF +#define CONFIG_SHIFT 0 +#define CONFIG_STOP_ON_WERR_MASK 0x80000000 +#define CONFIG_STOP_ON_WERR_SHIFT 31 +#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 +#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 +#define CONFIG_ECC_SRAM_REQ_MASK 0x00200000 +#define CONFIG_ECC_SRAM_REQ_SHIFT 21 +#define CONFIG_DMA_REQ_MASK 0x00100000 +#define CONFIG_DMA_REQ_SHIFT 20 +#define CONFIG_ECC_MODE_MASK 0x000E0000 +#define CONFIG_ECC_MODE_SHIFT 17 +#define CONFIG_FAST_FLASH_MASK 0x00010000 +#define CONFIG_FAST_FLASH_SHIFT 16 +#define CONFIG_ID_COUNT_MASK 0x0000E000 +#define CONFIG_ID_COUNT_SHIFT 13 +#define CONFIG_CMD_TIMEOUT_MASK 0x00001F00 +#define CONFIG_CMD_TIMEOUT_SHIFT 8 +#define CONFIG_16BIT_MASK 0x00000080 +#define CONFIG_16BIT_SHIFT 7 +#define CONFIG_BOOT_MODE_MASK 0x00000040 +#define CONFIG_BOOT_MODE_SHIFT 6 +#define CONFIG_ADDR_AUTO_INCR_MASK 0x00000020 +#define CONFIG_ADDR_AUTO_INCR_SHIFT 5 +#define CONFIG_BUFNO_AUTO_INCR_MASK 0x00000010 +#define CONFIG_BUFNO_AUTO_INCR_SHIFT 4 +#define CONFIG_PAGE_CNT_MASK 0x0000000F +#define CONFIG_PAGE_CNT_SHIFT 0 + +/* NFC_IRQ_STATUS Field */ +#define MASK 0xEFFC003F +#define SHIFT 0 +#define WERR_IRQ_MASK 0x80000000 +#define WERR_IRQ_SHIFT 31 +#define CMD_DONE_IRQ_MASK 0x40000000 +#define CMD_DONE_IRQ_SHIFT 30 +#define IDLE_IRQ_MASK 0x20000000 +#define IDLE_IRQ_SHIFT 29 +#define WERR_STATUS_MASK 0x08000000 +#define WERR_STATUS_SHIFT 27 +#define FLASH_CMD_BUSY_MASK 0x04000000 +#define FLASH_CMD_BUSY_SHIFT 26 +#define RESIDUE_BUSY_MASK 0x02000000 +#define RESIDUE_BUSY_SHIFT 25 +#define ECC_BUSY_MASK 0x01000000 +#define ECC_BUSY_SHIFT 24 +#define DMA_BUSY_MASK 0x00800000 +#define DMA_BUSY_SHIFT 23 +#define WERR_EN_MASK 0x00400000 +#define WERR_EN_SHIFT 22 +#define CMD_DONE_EN_MASK 0x00200000 +#define CMD_DONE_EN_SHIFT 21 +#define IDLE_EN_MASK 0x00100000 +#define IDLE_EN_SHIFT 20 +#define WERR_CLEAR_MASK 0x00080000 +#define WERR_CLEAR_SHIFT 19 +#define CMD_DONE_CLEAR_MASK 0x00040000 +#define CMD_DONE_CLEAR_SHIFT 18 +#define IDLE_CLEAR_MASK 0x00020000 +#define IDLE_CLEAR_SHIFT 17 +#define RESIDUE_BUFF_NO_MASK 0x00000030 +#define RESIDUE_BUFF_NO_SHIFT 4 +#define ECC_BUFF_NO_MASK 0x000000C0 +#define ECC_BUFF_NO_SHIFT 2 +#define DMA_BUFF_NO_MASK 0x00000003 + +#define NFC_CONFIG_VALUE (0x0000a632|(ECC_60_BYTE<<17)) +#endif /* MPC5125_NFC_H */ + diff --git a/include/mpc512x.h b/include/mpc512x.h index 0f022939da..f18c4ffe69 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2006, 2008-2009 Freescale Semiconductor, Inc. All right reserved. * (C) Copyright 2007 DENX Software Engineering * * See file CREDITS for list of people who contributed to this @@ -46,6 +46,7 @@ #define LPCS6AW 0x003C #define LPCA7AW 0x0040 #define SRAMBAR 0x00C4 +#define NFCBAR 0x00C8 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ #define LPC_OFFSET 0x10000 @@ -70,6 +71,7 @@ #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ #define SPR_5121E 0x80180000 +#define SPR_5125 0x80190000 /* SPCR - System Priority Configuration Register */ @@ -211,25 +213,28 @@ #define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) #define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 #define CLOCK_SCCR1_SATA_EN 0x00004000 -#define CLOCK_SCCR1_FEC_EN 0x00002000 +#define CLOCK_SCCR1_FEC1_EN 0x00002000 #define CLOCK_SCCR1_TPR_EN 0x00001000 #define CLOCK_SCCR1_PCI_EN 0x00000800 #define CLOCK_SCCR1_DDR_EN 0x00000400 +#define CLOCK_SCCR1_FEC2_EN 0x00000200 /* System Clock Control Register 2 commands */ #define CLOCK_SCCR2_DIU_EN 0x80000000 #define CLOCK_SCCR2_AXE_EN 0x40000000 #define CLOCK_SCCR2_MEM_EN 0x20000000 -#define CLOCK_SCCR2_USB2_EN 0x10000000 -#define CLOCK_SCCR2_USB1_EN 0x08000000 +#define CLOCK_SCCR2_USB1_EN 0x10000000 +#define CLOCK_SCCR2_USB2_EN 0x08000000 #define CLOCK_SCCR2_I2C_EN 0x04000000 #define CLOCK_SCCR2_BDLC_EN 0x02000000 -#define CLOCK_SCCR2_SDHC_EN 0x01000000 +#define CLOCK_SCCR2_AUTO_EN 0x02000000 +#define CLOCK_SCCR2_SDHC1_EN 0x01000000 #define CLOCK_SCCR2_SPDIF_EN 0x00800000 #define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 #define CLOCK_SCCR2_MBX_EN 0x00200000 #define CLOCK_SCCR2_MBX_3D_EN 0x00100000 #define CLOCK_SCCR2_IIM_EN 0x00080000 +#define CLOCK_SCCR2_SDHC2_EN 0x00020000 /* PSC FIFO Command values */ #define PSC_FIFO_RESET_SLICE 0x80 @@ -291,10 +296,10 @@ #define FIFOC_PSC0_RX_SIZE 0x0 #define FIFOC_PSC0_RX_ADDR 0x0 -#define FIFOC_PSC1_TX_SIZE 0x0 -#define FIFOC_PSC1_TX_ADDR 0x0 -#define FIFOC_PSC1_RX_SIZE 0x0 -#define FIFOC_PSC1_RX_ADDR 0x0 +#define FIFOC_PSC1_TX_SIZE 0x04 +#define FIFOC_PSC1_TX_ADDR 0x00 +#define FIFOC_PSC1_RX_SIZE 0x04 +#define FIFOC_PSC1_RX_ADDR 0x04 #define FIFOC_PSC2_TX_SIZE 0x0 #define FIFOC_PSC2_TX_ADDR 0x0 @@ -302,9 +307,9 @@ #define FIFOC_PSC2_RX_ADDR 0x0 #define FIFOC_PSC3_TX_SIZE 0x04 -#define FIFOC_PSC3_TX_ADDR 0x0 +#define FIFOC_PSC3_TX_ADDR 0x10 #define FIFOC_PSC3_RX_SIZE 0x04 -#define FIFOC_PSC3_RX_ADDR 0x10 +#define FIFOC_PSC3_RX_ADDR 0x14 #define FIFOC_PSC4_TX_SIZE 0x0 #define FIFOC_PSC4_TX_ADDR 0x0 @@ -346,8 +351,271 @@ #define FIFOC_PSC11_RX_SIZE 0x0 #define FIFOC_PSC11_RX_ADDR 0x0 -/* IO Control Register - */ +/* MPC5125 */ +#if (BOARD_TYPE==BOARD_TYPE_5125_MPU) +#define IO_CTRL_MEM 0x00 +#define IO_CTRL_GBOBE 0x01 +#define IO_CTRL_LPC_CLK 0x04 +#define IO_CTRL_LPC_OE_B 0x05 +#define IO_CTRL_LPC_RWB 0x06 +#define IO_CTRL_LPC_CS0_B 0x07 +#define IO_CTRL_LPC_ACK_B 0x08 +#define IO_CTRL_LPC_AX03 0x09 +#define IO_CTRL_EMB_AX02 0x0a +#define IO_CTRL_EMB_AX01 0x0b +#define IO_CTRL_EMB_AX00 0x0c +#define IO_CTRL_EMB_AD31 0x0d +#define IO_CTRL_EMB_AD30 0x0e +#define IO_CTRL_EMB_AD29 0x0f +#define IO_CTRL_EMB_AD28 0x10 +#define IO_CTRL_EMB_AD27 0x11 +#define IO_CTRL_EMB_AD26 0x12 +#define IO_CTRL_EMB_AD25 0x13 +#define IO_CTRL_EMB_AD24 0x14 +#define IO_CTRL_EMB_AD23 0x15 +#define IO_CTRL_EMB_AD22 0x16 +#define IO_CTRL_EMB_AD21 0x17 +#define IO_CTRL_EMB_AD20 0x18 +#define IO_CTRL_EMB_AD19 0x19 +#define IO_CTRL_EMB_AD18 0x1a +#define IO_CTRL_EMB_AD17 0x1b +#define IO_CTRL_EMB_AD16 0x1c +#define IO_CTRL_EMB_AD15 0x1d +#define IO_CTRL_EMB_AD14 0x1e +#define IO_CTRL_EMB_AD13 0x1f +#define IO_CTRL_EMB_AD12 0x20 +#define IO_CTRL_EMB_AD11 0x21 +#define IO_CTRL_EMB_AD10 0x22 +#define IO_CTRL_EMB_AD09 0x23 +#define IO_CTRL_EMB_AD08 0x24 +#define IO_CTRL_EMB_AD07 0x25 +#define IO_CTRL_EMB_AD06 0x26 +#define IO_CTRL_EMB_AD05 0x27 +#define IO_CTRL_EMB_AD04 0x28 +#define IO_CTRL_EMB_AD03 0x29 +#define IO_CTRL_EMB_AD02 0x2a +#define IO_CTRL_EMB_AD01 0x2b +#define IO_CTRL_EMB_AD00 0x2c +#define IO_CTRL_NFC_CE0_B 0x2d +#define IO_CTRL_NFC_RB 0x2e +#define IO_CTRL_DIU_CLK 0x2f +#define IO_CTRL_DIU_DE 0x30 +#define IO_CTRL_DIU_HSYNC 0x31 +#define IO_CTRL_DIU_VSYNC 0x32 +#define IO_CTRL_DIU_LD00 0x33 +#define IO_CTRL_DIU_LD01 0x34 +#define IO_CTRL_DIU_LD02 0x35 +#define IO_CTRL_DIU_LD03 0x36 +#define IO_CTRL_DIU_LD04 0x37 +#define IO_CTRL_DIU_LD05 0x38 +#define IO_CTRL_DIU_LD06 0x39 +#define IO_CTRL_DIU_LD07 0x3a +#define IO_CTRL_DIU_LD08 0x3b +#define IO_CTRL_DIU_LD09 0x3c +#define IO_CTRL_DIU_LD10 0x3d +#define IO_CTRL_DIU_LD11 0x3e +#define IO_CTRL_DIU_LD12 0x3f +#define IO_CTRL_DIU_LD13 0x40 +#define IO_CTRL_DIU_LD14 0x41 +#define IO_CTRL_DIU_LD15 0x42 +#define IO_CTRL_DIU_LD16 0x43 +#define IO_CTRL_DIU_LD17 0x44 +#define IO_CTRL_DIU_LD18 0x45 +#define IO_CTRL_DIU_LD19 0x46 +#define IO_CTRL_DIU_LD20 0x47 +#define IO_CTRL_DIU_LD21 0x48 +#define IO_CTRL_DIU_LD22 0x49 +#define IO_CTRL_DIU_LD23 0x4a +#define IO_CTRL_CAN4_RX 0x4b +#define IO_CTRL_CAN4_TX 0x4c +#define IO_CTRL_CAN1_TX 0x4d +#define IO_CTRL_CAN2_TX 0x4e +#define IO_CTRL_I2C1_SCL 0x4f +#define IO_CTRL_I2C1_SDA 0x50 +#define IO_CTRL_FEC1_TXD_2 0x51 +#define IO_CTRL_FEC1_TXD_3 0x52 +#define IO_CTRL_FEC1_RXD_2 0x53 +#define IO_CTRL_FEC1_RXD_3 0x54 +#define IO_CTRL_FEC1_CRS 0x55 +#define IO_CTRL_FEC1_TX_ER 0x56 +#define IO_CTRL_FEC1_RXD_1 0x57 +#define IO_CTRL_FEC1_TXD_1 0x58 +#define IO_CTRL_FEC1_MDC 0x59 +#define IO_CTRL_FEC1_RX_ER 0x5a +#define IO_CTRL_FEC1_MDIO 0x5b +#define IO_CTRL_FEC1_RXD_0 0x5c +#define IO_CTRL_FEC1_TXD_0 0x5d +#define IO_CTRL_FEC1_TX_CLK 0x5e +#define IO_CTRL_FEC1_RX_CLK 0x5f +#define IO_CTRL_FEC1_RX_DV 0x60 +#define IO_CTRL_FEC1_TX_EN 0x61 +#define IO_CTRL_FEC1_COL 0x62 +#define IO_CTRL_USB1_DATA0 0x63 +#define IO_CTRL_USB1_DATA1 0x64 +#define IO_CTRL_USB1_DATA2 0x65 +#define IO_CTRL_USB1_DATA3 0x66 +#define IO_CTRL_USB1_DATA4 0x67 +#define IO_CTRL_USB1_DATA5 0x68 +#define IO_CTRL_USB1_DATA6 0x69 +#define IO_CTRL_USB1_DATA7 0x6a +#define IO_CTRL_USB1_STOP 0x6b +#define IO_CTRL_USB1_CLK 0x6c +#define IO_CTRL_USB1_NEXT 0x6d +#define IO_CTRL_USB1_DIR 0x6e +#define IO_CTRL_SDHC1_CLK 0x6f +#define IO_CTRL_SDHC1_CMD 0x70 +#define IO_CTRL_SDHC1_D0 0x71 +#define IO_CTRL_SDHC1_D1 0x72 +#define IO_CTRL_SDHC1_D2 0x73 +#define IO_CTRL_SDHC1_D3 0x74 +#define IO_CTRL_PSC_MCLK_IN 0x75 +#define IO_CTRL_PSC0_0 0x76 +#define IO_CTRL_PSC0_1 0x77 +#define IO_CTRL_PSC0_2 0x78 +#define IO_CTRL_PSC0_3 0x79 +#define IO_CTRL_PSC0_4 0x7a +#define IO_CTRL_PSC1_0 0x7b +#define IO_CTRL_PSC1_1 0x7c +#define IO_CTRL_PSC1_2 0x7d +#define IO_CTRL_PSC1_3 0x7e +#define IO_CTRL_PSC1_4 0x7f +#define IO_CTRL_J1850_TX 0x80 +#define IO_CTRL_J1850_RX 0x81 + +#if 1 +#define IOCTL_MEM 0x00 +#define IOCTL_GBOBE 0x01 +#define IOCTL_LPC_CLK 0x04 +#define IOCTL_LPC_OE_B 0x05 +#define IOCTL_LPC_RWB 0x06 +#define IOCTL_LPC_CS0_B 0x07 +#define IOCTL_LPC_ACK_B 0x08 +#define IOCTL_LPC_AX03 0x09 +#define IOCTL_EMB_AX02 0x0a +#define IOCTL_EMB_AX01 0x0b +#define IOCTL_EMB_AX00 0x0c +#define IOCTL_EMB_AD31 0x0d +#define IOCTL_EMB_AD30 0x0e +#define IOCTL_EMB_AD29 0x0f +#define IOCTL_EMB_AD28 0x10 +#define IOCTL_EMB_AD27 0x11 +#define IOCTL_EMB_AD26 0x12 +#define IOCTL_EMB_AD25 0x13 +#define IOCTL_EMB_AD24 0x14 +#define IOCTL_EMB_AD23 0x15 +#define IOCTL_EMB_AD22 0x16 +#define IOCTL_EMB_AD21 0x17 +#define IOCTL_EMB_AD20 0x18 +#define IOCTL_EMB_AD19 0x19 +#define IOCTL_EMB_AD18 0x1a +#define IOCTL_EMB_AD17 0x1b +#define IOCTL_EMB_AD16 0x1c +#define IOCTL_EMB_AD15 0x1d +#define IOCTL_EMB_AD14 0x1e +#define IOCTL_EMB_AD13 0x1f +#define IOCTL_EMB_AD12 0x20 +#define IOCTL_EMB_AD11 0x21 +#define IOCTL_EMB_AD10 0x22 +#define IOCTL_EMB_AD09 0x23 +#define IOCTL_EMB_AD08 0x24 +#define IOCTL_EMB_AD07 0x25 +#define IOCTL_EMB_AD06 0x26 +#define IOCTL_EMB_AD05 0x27 +#define IOCTL_EMB_AD04 0x28 +#define IOCTL_EMB_AD03 0x29 +#define IOCTL_EMB_AD02 0x2a +#define IOCTL_EMB_AD01 0x2b +#define IOCTL_EMB_AD00 0x2c +#define IOCTL_NFC_CE0_B 0x2d +#define IOCTL_NFC_RB 0x2e +#define IOCTL_DIU_CLK 0x2f +#define IOCTL_DIU_DE 0x30 +#define IOCTL_DIU_HSYNC 0x31 +#define IOCTL_DIU_VSYNC 0x32 +#define IOCTL_DIU_LD00 0x33 +#define IOCTL_DIU_LD01 0x34 +#define IOCTL_DIU_LD02 0x35 +#define IOCTL_DIU_LD03 0x36 +#define IOCTL_DIU_LD04 0x37 +#define IOCTL_DIU_LD05 0x38 +#define IOCTL_DIU_LD06 0x39 +#define IOCTL_DIU_LD07 0x3a +#define IOCTL_DIU_LD08 0x3b +#define IOCTL_DIU_LD09 0x3c +#define IOCTL_DIU_LD10 0x3d +#define IOCTL_DIU_LD11 0x3e +#define IOCTL_DIU_LD12 0x3f +#define IOCTL_DIU_LD13 0x40 +#define IOCTL_DIU_LD14 0x41 +#define IOCTL_DIU_LD15 0x42 +#define IOCTL_DIU_LD16 0x43 +#define IOCTL_DIU_LD17 0x44 +#define IOCTL_DIU_LD18 0x45 +#define IOCTL_DIU_LD19 0x46 +#define IOCTL_DIU_LD20 0x47 +#define IOCTL_DIU_LD21 0x48 +#define IOCTL_DIU_LD22 0x49 +#define IOCTL_DIU_LD23 0x4a +#define IOCTL_I2C2_SCL 0x4b +#define IOCTL_I2C2_SDA 0x4c +#define IOCTL_CAN1_TX 0x4d +#define IOCTL_CAN2_TX 0x4e +#define IOCTL_I2C1_SCL 0x4f +#define IOCTL_I2C1_SDA 0x50 +#define IOCTL_FEC1_TXD_2 0x51 +#define IOCTL_FEC1_TXD_3 0x52 +#define IOCTL_FEC1_RXD_2 0x53 +#define IOCTL_FEC1_RXD_3 0x54 +#define IOCTL_FEC1_CRS 0x55 +#define IOCTL_FEC1_TX_ER 0x56 +#define IOCTL_FEC1_RXD_1 0x57 +#define IOCTL_FEC1_TXD_1 0x58 +#define IOCTL_FEC1_MDC 0x59 +#define IOCTL_FEC1_RX_ER 0x5a +#define IOCTL_FEC1_MDIO 0x5b +#define IOCTL_FEC1_RXD_0 0x5c +#define IOCTL_FEC1_TXD_0 0x5d +#define IOCTL_FEC1_TX_CLK 0x5e +#define IOCTL_FEC1_RX_CLK 0x5f +#define IOCTL_FEC1_RX_DV 0x60 +#define IOCTL_FEC1_TX_EN 0x61 +#define IOCTL_FEC1_COL 0x62 +#define IOCTL_USB1_DATA0 0x63 +#define IOCTL_USB1_DATA1 0x64 +#define IOCTL_USB1_DATA2 0x65 +#define IOCTL_USB1_DATA3 0x66 +#define IOCTL_USB1_DATA4 0x67 +#define IOCTL_USB1_DATA5 0x68 +#define IOCTL_USB1_DATA6 0x69 +#define IOCTL_USB1_DATA7 0x6a +#define IOCTL_USB1_STOP 0x6b +#define IOCTL_USB1_CLK 0x6c +#define IOCTL_USB1_NEXT 0x6d +#define IOCTL_USB1_DIR 0x6e +#define IOCTL_SDHC1_CLK 0x6f +#define IOCTL_SDHC1_CMD 0x70 +#define IOCTL_SDHC1_D0 0x71 +#define IOCTL_SDHC1_D1 0x72 +#define IOCTL_SDHC1_D2 0x73 +#define IOCTL_SDHC1_D3 0x74 +#define IOCTL_PSC_MCLK_IN 0x75 +#define IOCTL_PSC0_0 0x76 +#define IOCTL_PSC0_1 0x77 +#define IOCTL_PSC0_2 0x78 +#define IOCTL_PSC0_3 0x79 +#define IOCTL_PSC0_4 0x7a +#define IOCTL_PSC1_0 0x7b +#define IOCTL_PSC1_1 0x7c +#define IOCTL_PSC1_2 0x7d +#define IOCTL_PSC1_3 0x7e +#define IOCTL_PSC1_4 0x7f +#define IOCTL_J1850_TX 0x80 +#define IOCTL_J1850_RX 0x81 +#endif + + +#else +/* MPC5121 */ #define IOCTL_MEM 0x000 #define IOCTL_GP 0x004 #define IOCTL_LPC_CLK 0x008 @@ -545,12 +813,16 @@ #define IOCTL_USB2_VBUS_PWR_FAULT 0x308 #define IOCTL_USB2_VBUS_PWR_SELECT 0x30C #define IOCTL_USB2_PHY_DRVV_BUS 0x310 - +#endif #ifndef __ASSEMBLY__ /* IO pin fields */ +#ifdef CONFIG_ADS5125 +#define IO_PIN_FMUX(v) ((v) << 5) /* pin function */ +#else #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ +#endif #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ #define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ #define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ @@ -561,7 +833,12 @@ typedef struct iopin_t { int p_offset; /* offset from IOCTL_MEM_OFFSET */ int nr_pins; /* number of pins to set this way */ int bit_or; /* or in the value instead of overwrite */ +#ifdef CONFIG_ADS5125 + u_char val; + u_char res0[3]; +#else u_long val; /* value to write or or */ +#endif }iopin_t; void iopin_initialize(iopin_t *,int); @@ -569,7 +846,7 @@ void iopin_initialize(iopin_t *,int); /* Indexes in regs array */ /* Set for DDR */ -#define IOCTRL_MUX_DDR 0x00000036 +#define IOCTRL_MUX_DDR 0x00000000 /* Register Offset Base */ #define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800) diff --git a/lib_ppc/Makefile b/lib_ppc/Makefile index 60ea0c9139..5d8cb392d1 100644 --- a/lib_ppc/Makefile +++ b/lib_ppc/Makefile @@ -37,13 +37,16 @@ COBJS-y += extable.o COBJS-y += interrupts.o COBJS-y += kgdb.o COBJS-y += time.o +COBJS-$(CONFIG_HDMI_CHIP_SIL9022A) +=sil9022init.a SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) - + +sil9022init.a:sil9022init.mtc + cp $< $@ ######################################################################### # defines $(obj).depend target diff --git a/lib_ppc/board.c b/lib_ppc/board.c index f69c5f4f1f..3f75c09f60 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -2,6 +2,9 @@ * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved. + * John Rigby + * * See file CREDITS for list of people who contributed to this * project. * @@ -96,6 +99,15 @@ void doc_init (void); #endif #include #include +/*add*/ +#include + +#define CONFIG_SYS_NO_FLASH +/* +#undef CONFIG_CMD_NAND +*/ +/*#undef CONFIG_CMD_NET*/ +#undef CONFIG_SYS_UPDATE_FLASH_SIZE static char *failed = "*** failed ***\n"; @@ -240,6 +252,7 @@ static int init_func_i2c (void) puts ("I2C: "); i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); puts ("ready\n"); + return (0); } #endif @@ -415,7 +428,7 @@ void board_init_f (ulong bootflag) hang (); } } - + /* * Now that we have DRAM mapped and working, we can * relocate the code and continue running from DRAM. @@ -673,7 +686,11 @@ void board_init_r (gd_t *id, ulong dest_addr) serial_initialize(); #endif +#ifdef CONFIG_CW + printf ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); +#else debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); +#endif WATCHDOG_RESET (); @@ -795,7 +812,6 @@ void board_init_r (gd_t *id, ulong dest_addr) update_flash_size (flash_size); #endif - # if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = TEXT_BASE + flash_size; @@ -836,9 +852,9 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif /* relocate environment function pointers etc. */ - env_relocate (); +// env_relocate (); - /* + /* * Fill in missing fields of bd_info. * We do this here, where we have "normal" access to the * environment; we used to do this still running from ROM, @@ -878,7 +894,7 @@ void board_init_r (gd_t *id, ulong dest_addr) mac_read_from_eeprom(); #endif - s = getenv ("ethaddr"); + s = getenv ("ethaddr"); #if defined (CONFIG_MBX) || \ defined (CONFIG_RPXCLASSIC) || \ defined(CONFIG_IAD210) || \ @@ -990,8 +1006,19 @@ void board_init_r (gd_t *id, ulong dest_addr) /* * Do pci configuration */ +#ifdef CONFIG_FASTBOOT + s = getenv ("skippcicheck"); + if (s && (*s == 'y')) { + extern int pci_init_skipped; + pci_init_skipped = 1; + } + else { + pci_init (); + }; +#else pci_init (); #endif +#endif /** leave this here (after malloc(), environment and PCI are working) **/ /* Initialize devices */ @@ -1007,6 +1034,9 @@ void board_init_r (gd_t *id, ulong dest_addr) /* Initialize the console (after the relocation and devices init) */ console_init_r (); +/* + printf("%s line:%d\n",__func__,__LINE__); +*/ #if defined(CONFIG_CCM) || \ defined(CONFIG_COGENT) || \ @@ -1022,7 +1052,9 @@ void board_init_r (gd_t *id, ulong dest_addr) /* miscellaneous platform dependent initialisations */ misc_init_r (); #endif - +/* + printf("%s line:%d\n",__func__,__LINE__); +*/ #ifdef CONFIG_HERMES if (bd->bi_ethspeed != 0xFFFF) hermes_start_lxt980 ((int) bd->bi_ethspeed); @@ -1033,14 +1065,18 @@ void board_init_r (gd_t *id, ulong dest_addr) puts ("KGDB: "); kgdb_init (); #endif - +/* + printf("%s line:%d\n",__func__,__LINE__); +*/ debug ("U-Boot relocated to %08lx\n", dest_addr); /* * Enable Interrupts */ interrupt_init (); - +/* + printf("%s line:%d\n",__func__,__LINE__); +*/ /* Must happen after interrupts are initialized since * an irq handler gets installed */ @@ -1053,13 +1089,18 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif udelay (20); - +/* + printf("%s line:%d\n",__func__,__LINE__); +*/ set_timer (0); /* Initialize from environment */ if ((s = getenv ("loadaddr")) != NULL) { load_addr = simple_strtoul (s, NULL, 16); } +/* + printf("%s line:%d\n",__func__,__LINE__); +*/ #if defined(CONFIG_CMD_NET) if ((s = getenv ("bootfile")) != NULL) { copy_filename (BootFile, s, sizeof (BootFile)); @@ -1089,13 +1130,31 @@ void board_init_r (gd_t *id, ulong dest_addr) doc_init (); #endif +#if 1 #if defined(CONFIG_CMD_NET) +#if defined(CONFIG_FASTBOOT) +#if defined(CONFIG_NET_MULTI) + WATCHDOG_RESET (); +#endif + + s = getenv ("skipnetcheck"); + if (s && (*s == 'y')) { + extern int eth_init_skipped; + eth_init_skipped = 1; + } + else { + puts ("Net: "); + eth_initialize (bd); + }; + +#else #if defined(CONFIG_NET_MULTI) WATCHDOG_RESET (); puts ("Net: "); #endif eth_initialize (bd); #endif +#endif #if defined(CONFIG_CMD_NET) && ( \ defined(CONFIG_CCM) || \ @@ -1117,6 +1176,7 @@ void board_init_r (gd_t *id, ulong dest_addr) debug ("Reset Ethernet PHY\n"); reset_phy (); #endif +#endif #ifdef CONFIG_POST post_run (NULL, POST_RAM | post_bootmode_get(0)); @@ -1129,20 +1189,38 @@ void board_init_r (gd_t *id, ulong dest_addr) pcmcia_init (); #endif +#ifdef CONFIG_FASTBOOT +#if defined(CONFIG_CMD_IDE) + WATCHDOG_RESET (); + s = getenv ("skipidecheck"); + if (s && (*s == 'y')) { + extern int ide_init_skipped; + ide_init_skipped = 1; + } else { +# ifdef CONFIG_IDE_8xx_PCCARD + puts ("PCMCIA:"); +# else + puts ("IDE: "); +#endif + ide_init (); + } +#endif /* CFG_CMD_IDE */ +#else #if defined(CONFIG_CMD_IDE) WATCHDOG_RESET (); # ifdef CONFIG_IDE_8xx_PCCARD puts ("PCMCIA:"); # else puts ("IDE: "); -#endif +# endif /* CONFIG_IDE_8xx_PCCARD */ #if defined(CONFIG_START_IDE) if (board_start_ide()) ide_init (); #else ide_init (); -#endif -#endif +#endif /* CONFIG_START_IDE */ +#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_FASTBOOT */ #ifdef CONFIG_LAST_STAGE_INIT WATCHDOG_RESET (); @@ -1200,9 +1278,12 @@ void board_init_r (gd_t *id, ulong dest_addr) do_mdm_init = gd->do_mdm_init; } #endif - /* Initialization complete - start the monitor */ - + env_relocate(); +#if (HDMI_CHIP_SELECT==HDMI_CHIP_SIL9022A)//HDMI sil9022a,enable hdmi signal + //TPI_Init(); + //OnHdmiCableConnected(); +#endif /* main_loop() can return to retry autoboot, if so just run it again. */ for (;;) { WATCHDOG_RESET (); diff --git a/lib_ppc/bootm.c b/lib_ppc/bootm.c index e03d763907..be9a9f4ec6 100644 --- a/lib_ppc/bootm.c +++ b/lib_ppc/bootm.c @@ -46,6 +46,10 @@ #endif DECLARE_GLOBAL_DATA_PTR; +#define BOOTM_DEBUG_INFO() do{ \ + unsigned int *buf=0; \ + printf("%s line:%d %08x %08x %08x %08x \n",__func__,__LINE__,*buf++,*buf++,*buf++,*buf++);\ + }while(0) extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern ulong get_effective_memsize(void); @@ -94,6 +98,7 @@ static void boot_jump_linux(bootm_headers_t *images) #endif debug (" Booting using OF flat tree...\n"); + BOOTM_DEBUG_INFO(); (*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0); /* does not return */ diff --git a/lib_ppc/sil9022init.mtc b/lib_ppc/sil9022init.mtc new file mode 100644 index 0000000000..b001ab30c5 Binary files /dev/null and b/lib_ppc/sil9022init.mtc differ diff --git a/nand_flash_program b/nand_flash_program new file mode 100644 index 0000000000..ae84940e16 Binary files /dev/null and b/nand_flash_program differ diff --git a/nand_load_program b/nand_load_program new file mode 100644 index 0000000000..309d6df3b9 Binary files /dev/null and b/nand_load_program differ diff --git a/nand_program_block1_uboot b/nand_program_block1_uboot new file mode 100644 index 0000000000..286e56c751 Binary files /dev/null and b/nand_program_block1_uboot differ diff --git a/nand_spl/board/ads5125/Makefile b/nand_spl/board/ads5125/Makefile new file mode 100644 index 0000000000..7e349665fc --- /dev/null +++ b/nand_spl/board/ads5125/Makefile @@ -0,0 +1,93 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2008 Freescale Semiconductor +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 +PAD_TO := 0xfff00800 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = nandstart.o +COBJS = + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) $(OBJTREE)/nand_spl/board/$(BOARDDIR)/nandload.mtc +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-2k.bin $(nandobj)loader-script-5125.txt + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-2k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)loader-script-5125.txt:$(nandobj)u-boot-spl-2k.bin + $(TOPDIR)/nand_load_program $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +$(ELF): +$(obj)%: $(obj)%.o $(LIB) + $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ + -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ + -L$(gcclibdir) -lgcc + +$(SREC): +$(obj)%.srec: $(obj)% + $(OBJCOPY) -O srec $< $@ 2>/dev/null + +$(BIN): +$(obj)%.bin: $(obj)% + $(OBJCOPY) -O binary $< $@ 2>/dev/null + + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/ads5125/config.mk b/nand_spl/board/ads5125/config.mk new file mode 100644 index 0000000000..5a9334c6f6 --- /dev/null +++ b/nand_spl/board/ads5125/config.mk @@ -0,0 +1,233 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +ifneq ($(OBJTREE),$(SRCTREE)) +ifeq ($(CURDIR),$(SRCTREE)) +dir := +else +dir := $(subst $(SRCTREE)/,,$(CURDIR)) +endif + +obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) +src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) + +$(shell mkdir -p $(obj)) +else +obj := +src := +endif + +# clean the slate ... +PLATFORM_RELFLAGS = +PLATFORM_CPPFLAGS = +PLATFORM_LDFLAGS = + +######################################################################### + +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +HOSTCC = cc +else +HOSTCC = gcc +endif +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer +HOSTSTRIP = strip + +######################################################################### +# +# Option checker (courtesy linux kernel) to ensure +# only supported compiler options are used +# +cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ + > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) + +# +# Include the make variables (CC, etc...) +# +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +LDR = $(CROSS_COMPILE)ldr +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +RANLIB = $(CROSS_COMPILE)RANLIB + +######################################################################### + +# Load generated board configuration +sinclude $(OBJTREE)/include/autoconf.mk + +ifdef ARCH +sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules +endif +ifdef CPU +sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules +endif +ifdef SOC +sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules +endif +ifdef VENDOR +BOARDDIR = $(VENDOR)/$(BOARD) +else +BOARDDIR = $(BOARD) +endif +ifdef BOARD +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules +endif + +######################################################################### + +ifneq (,$(findstring s,$(MAKEFLAGS))) +ARFLAGS = cr +else +ARFLAGS = crv +endif +RELFLAGS= $(PLATFORM_RELFLAGS) +DBGFLAGS= -g # -DDEBUG +OPTFLAGS= -Os #-fomit-frame-pointer +ifndef LDSCRIPT +#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug +ifeq ($(CONFIG_NAND_U_BOOT),y) +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +else +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds +endif +endif +OBJCFLAGS += --gap-fill=0xff + +gccincdir := $(shell $(CC) -print-file-name=include) + +CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ + -D__KERNEL__ +ifneq ($(TEXT_BASE),) +CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) +endif + +ifneq ($(OBJTREE),$(SRCTREE)) +CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include +endif + +CPPFLAGS += -I$(TOPDIR)/include +CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ + -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) + +ifdef BUILD_TAG +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ + -DBUILD_TAG='"$(BUILD_TAG)"' +else +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes +endif + +CFLAGS += $(call cc-option,-fno-stack-protector) + +# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) +# this option have to be placed behind -Wall -- that's why it is here +ifeq ($(ARCH),nios) +ifeq ($(findstring 2.9,$(shell $(CC) --version)),2.9) +CFLAGS := $(CPPFLAGS) -Wall -Wno-trigraphs +endif +endif + +# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g +# option to the assembler. +AFLAGS_DEBUG := + +# turn jbsr into jsr for m68k +ifeq ($(ARCH),m68k) +ifeq ($(findstring 3.4,$(shell $(CC) --version)),3.4) +AFLAGS_DEBUG := -Wa,-gstabs,-S +endif +endif + +AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) + +LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS) +ifneq ($(TEXT_BASE),) +LDFLAGS += -Ttext $(TEXT_BASE) +endif + +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) +# +# So far, this is used only by tools/gdb/Makefile. + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif + +ifeq ($(PCI_CLOCK),PCI_66M) +CFLAGS := $(CFLAGS) -DPCI_66M +endif + +######################################################################### + +export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ + AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ + MAKE +export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS + +######################################################################### + +ifndef REMOTE_BUILD + +%.s: %.S + $(CPP) $(AFLAGS) -o $@ $< +%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $< +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +else + +$(obj)%.s: %.S + $(CPP) $(AFLAGS) -o $@ $< +$(obj)%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $< +$(obj)%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< +endif + +######################################################################### diff --git a/nand_spl/board/ads5125/dram.h b/nand_spl/board/ads5125/dram.h new file mode 100644 index 0000000000..cd26646a08 --- /dev/null +++ b/nand_spl/board/ads5125/dram.h @@ -0,0 +1,101 @@ +/* + * + * (C) Copyright 2009 + * Martha Marx, Silicon Turnkey Express, mmarx@silicontkx.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* these were originally in mpc512x.h */ +#define MDDRC_BASE_OFFSET 0x09000 +#define DDR_LAW_BAR 0x00a0 +#define DDR_LAW_AR 0x00a4 +#define IOCTL_BASE_ADDR 0x0a000 + +/* DRAM Controller Register Offsets */ +#define DDR_SYS_CONFIG 0x00 +#define DDR_TIME_CONFIG0 0x04 +#define DDR_TIME_CONFIG1 0x08 +#define DDR_TIME_CONFIG2 0x0C +#define DDR_COMMAND 0x10 +#define DDR_COMPACT_COMMAND 0x14 +#define DDR_SELF_REFRESH_CMD_0 0x18 +#define DDR_SELF_REFRESH_CMD_1 0x1C +#define DDR_SELF_REFRESH_CMD_2 0x20 +#define DDR_SELF_REFRESH_CMD_3 0x24 +#define DDR_SELF_REFRESH_CMD_4 0x28 +#define DDR_SELF_REFRESH_CMD_5 0x2C +#define DDR_SELF_REFRESH_CMD_6 0x30 +#define DDR_SELF_REFRESH_CMD_7 0x34 +#define DDR_DQS_CONFIG_COUNT 0x38 +#define DDR_DQS_CONFIG_TIME 0x3C +#define DDR_DQS_DELAY_STATUS 0x40 + +/* DRAM Controller Priority Manager Register Offsets */ +#define DRAMPRIOM_PRIOMAN_CONFIG1 0x080 +#define DRAMPRIOM_PRIOMAN_CONFIG2 0x084 +#define DRAMPRIOM_HIPRIO_CONFIG 0x088 +#define DRAMPRIOM_LUT_TABLE0_MAIN_UP 0x08C +#define DRAMPRIOM_LUT_TABLE1_MAIN_UP 0x090 +#define DRAMPRIOM_LUT_TABLE2_MAIN_UP 0x094 +#define DRAMPRIOM_LUT_TABLE3_MAIN_UP 0x098 +#define DRAMPRIOM_LUT_TABLE4_MAIN_UP 0x09C +#define DRAMPRIOM_LUT_TABLE0_MAIN_LOW 0x0A0 +#define DRAMPRIOM_LUT_TABLE1_MAIN_LOW 0x0A4 +#define DRAMPRIOM_LUT_TABLE2_MAIN_LOW 0x0A8 +#define DRAMPRIOM_LUT_TABLE3_MAIN_LOW 0x0AC +#define DRAMPRIOM_LUT_TABLE4_MAIN_LOW 0x0B0 +#define DRAMPRIOM_LUT_TABLE0_ALT_UP 0x0B4 +#define DRAMPRIOM_LUT_TABLE1_ALT_UP 0x0B8 +#define DRAMPRIOM_LUT_TABLE2_ALT_UP 0x0BC +#define DRAMPRIOM_LUT_TABLE3_ALT_UP 0x0C0 +#define DRAMPRIOM_LUT_TABLE4_ALT_UP 0x0C4 +#define DRAMPRIOM_LUT_TABLE0_ALT_LOW 0x0C8 +#define DRAMPRIOM_LUT_TABLE1_ALT_LOW 0x0CC +#define DRAMPRIOM_LUT_TABLE2_ALT_LOW 0x0D0 +#define DRAMPRIOM_LUT_TABLE3_ALT_LOW 0x0D4 +#define DRAMPRIOM_LUT_TABLE4_ALT_LOW 0x0D8 +#define DRAMPRIOM_PERF_MONITOR_CONFIG 0x0DC +#define DRAMPRIOM_EVENT_TIME_COUNTER 0x0E0 +#define DRAMPRIOM_EVENT_TIME_PRESET 0x0E4 +#define DRAMPRIOM_PERF_MNTR1_ADDR_LOW 0x0E8 +#define DRAMPRIOM_PERF_MNTR2_ADDR_LOW 0x0EC +#define DRAMPRIOM_PERF_MNTR1_ADDR_HI 0x0F0 +#define DRAMPRIOM_PERF_MNTR2_ADDR_HI 0x0F4 +#define DRAMPRIOM_PERF_MNTR1_READ_CNTR 0x100 +#define DRAMPRIOM_PERF_MNTR2_READ_CNTR 0x104 +#define DRAMPRIOM_PERF_MNTR1_WRITE_CNTR 0x108 +#define DRAMPRIOM_PERF_MNTR2_WRITE_CNTR 0x10C +#define DRAMPRIOM_GRANTED_ACK_CNTR0 0x110 +#define DRAMPRIOM_GRANTED_ACK_CNTR1 0x114 +#define DRAMPRIOM_GRANTED_ACK_CNTR2 0x118 +#define DRAMPRIOM_GRANTED_ACK_CNTR3 0x11C +#define DRAMPRIOM_GRANTED_ACK_CNTR4 0x120 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR0 0x124 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR1 0x128 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR2 0x12C +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR3 0x130 +#define DRAMPRIOM_CUMULATIVE_WAIT_CNTR4 0x134 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR0 0x138 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR1 0x13C +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR2 0x140 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR3 0x144 +#define DRAMPRIOM_SUMMED_PRIORITY_CNTR4 0x148 + + diff --git a/nand_spl/board/ads5125/nandload.h b/nand_spl/board/ads5125/nandload.h new file mode 100644 index 0000000000..ec5a76e91a --- /dev/null +++ b/nand_spl/board/ads5125/nandload.h @@ -0,0 +1,16 @@ +/* + Provider: LimePC Multimedia Technologies Co., Limited + Date:01/14/2010 + Copyright note: without provider's written consensus by the provider, any release + of provider's code could result in infrigement of provider's intellectural properties. + Autor:Cloudy Chen +*/ +#include +#include +#include +#include +#include +#include +#include +void sram_to_ddr(void); +void nandload(void); \ No newline at end of file diff --git a/nand_spl/board/ads5125/nandload.mtc b/nand_spl/board/ads5125/nandload.mtc new file mode 100644 index 0000000000..182d8a032b Binary files /dev/null and b/nand_spl/board/ads5125/nandload.mtc differ diff --git a/nand_spl/board/ads5125/nandstart.S b/nand_spl/board/ads5125/nandstart.S new file mode 100644 index 0000000000..c61d99cf9b --- /dev/null +++ b/nand_spl/board/ads5125/nandstart.S @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2009 + * Martha Marx, Silicon Turnkey Express, mmarx@silicontkx.com + * + * Based on original start.S done by + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk + * start.S for mpc512x was originally based on the MPC83xx code. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot - NAND Boot Startup Code for MPC5121 Embedded Boards + */ +#define DEBUG + +#include +#include +#include +#include "dram.h" +//#include "nfc.h" + +#define CONFIG_521X 1 /* needed for Linux kernel header files*/ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC512X" +#endif + +/* + * Floating Point enable, Machine Check and Recoverable Interr. + */ +#undef MSR_KERNEL +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* Macros for manipulating CSx_START/STOP */ +#define START_REG(start) ((start) >> 16) +#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) +#define SET_MEM_BASE(r, b) \ + lis r,(b)@h; \ + ori r,r,(b)@l; \ + +#define SET_REG32(r, v, offset, mr) \ + lis r, v@h; \ + ori r, r, v@l; \ + stw r, offset(mr); \ + +#define SET_REG16(r, v, offset, mr) \ + li r, v; \ + sth r, offset(mr); \ + + + .text + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, " " + .ascii "2K NAND BOOT ","\0" + . = EXC_OFF_SYS_RESET + + .globl _start + /* Start from here after reset/power on */ +_start: +boot_cold: + /* Save msr contents */ + mfmsr r5 + lis r4, CONFIG_DEFAULT_IMMR@h + + /* Set IMMR area to our preferred location */ + mfspr r6, MBAR + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + + cmpw r3, r6 + beq 1f /* it has already been set to what we want it to be */ + /* -- nice to chk if coming out of the BDI */ + + + stw r3, IMMRBAR(r4) + mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ + isync +1: lis r4, START_REG(CFG_FLASH_BASE) + ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) + stw r4, LPBAW(r3) + stw r4, LPCS0AW(r3) + isync + /* Initialise the machine */ + bl cpu_early_init + isync + + /* + * The SRAM window has a fixed size (256K), + * so only the start addressis necessary + */ + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 + stw r4, SRAMBAR(r3) + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lwz r4, SRAMBAR(r3) + isync + +#if 0 +#ifdef CONFIG_ADS5125 /* CS2 FUNC MUX must be done before CS is enabled */ + lis r4, (CONFIG_SYS_IOCTRL_ADDR)@h + ori r4, r4, (CONFIG_SYS_IOCTRL_ADDR)@l + li r5, IOCTRL_MUX_CS2 + stb r5, IO_CTRL_LPC_AX03(r4) +/* change the pin muxing on PSC9 here in case it is being used as console*/ + li r5, IOCTRL_MUX_PSC9 + stb r5, IO_CTRL_I2C1_SCL(r4) + stb r5, IO_CTRL_I2C1_SDA(r4) + +#endif +#endif + + /* r3: BOOTFLAG */ + mr r3, r21 + + bl dram_init + + + /* r3: BOOTFLAG */ + mr r3, r21 + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + /*copy sram to ddr*/ + bl sram_to_ddr + /* copy the full U-Boot into DDR */ + /* and jump to it */ +jump_uboot: + SET_MEM_BASE(r10, nandload-CONFIG_SYS_NAND_BASE+CFG_LOADER_DDR_START) + mtlr r10 + isync + blr + + /* NOTREACHED - nand_boot() does not return */ +/* + * This code initialises the machine, + * it expects original MSR contents to be in r5 + */ +cpu_early_init: + /* Initialize machine status; enable machine check interrupt */ + /*-----------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */ +#endif + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ + + lis r3, CFG_IMMR@h + + /* Disable the watchdog */ + /*----------------------*/ + lwz r4, SWCRR(r3) + /* + * Check to see if it's enabled for disabling: once disabled by s/w + * it's not possible to re-enable it + */ + andi. r4, r4, 0x4 + beq 1f + xor r4, r4, r4 + stw r4, SWCRR(r3) +1: + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*------------------------------------------------------*/ + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + blr + +dram_init: + + SET_MEM_BASE(r3, CFG_IMMR + IOCTL_BASE_ADDR) + SET_REG32(r4, (IOCTRL_MUX_DDR<<24), IOCTL_MEM , r3) + + SET_MEM_BASE(r3, CFG_IMMR) + SET_REG32(r4, CFG_DDR_BASE & 0xFFFFF000, DDR_LAW_BAR, r3) + SET_REG32(r4, 0x0000001b, DDR_LAW_AR, r3) + lwz r0, DDR_LAW_AR(r3) + isync + + SET_MEM_BASE(r3, CFG_IMMR + MDDRC_BASE_OFFSET) + SET_REG32(r4, CFG_MDDRC_SYS_CFG_EN, DDR_SYS_CONFIG, r3) + + SET_REG32(r4, CFG_MDDRCGRP_PM_CFG1, DRAMPRIOM_PRIOMAN_CONFIG1, r3) + SET_REG32(r4, CFG_MDDRCGRP_PM_CFG2, DRAMPRIOM_PRIOMAN_CONFIG2, r3) + SET_REG32(r4, CFG_MDDRCGRP_HIPRIO_CFG, DRAMPRIOM_HIPRIO_CONFIG, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_MU, DRAMPRIOM_LUT_TABLE0_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_ML, DRAMPRIOM_LUT_TABLE0_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_MU, DRAMPRIOM_LUT_TABLE1_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_ML, DRAMPRIOM_LUT_TABLE1_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_MU, DRAMPRIOM_LUT_TABLE2_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_ML, DRAMPRIOM_LUT_TABLE2_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_MU, DRAMPRIOM_LUT_TABLE3_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_ML, DRAMPRIOM_LUT_TABLE3_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_MU, DRAMPRIOM_LUT_TABLE4_MAIN_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_ML, DRAMPRIOM_LUT_TABLE4_MAIN_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_AU, DRAMPRIOM_LUT_TABLE0_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT0_AL, DRAMPRIOM_LUT_TABLE0_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_AU, DRAMPRIOM_LUT_TABLE1_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT1_AL, DRAMPRIOM_LUT_TABLE1_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_AU, DRAMPRIOM_LUT_TABLE2_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT2_AL, DRAMPRIOM_LUT_TABLE2_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_AU, DRAMPRIOM_LUT_TABLE3_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT3_AL, DRAMPRIOM_LUT_TABLE3_ALT_LOW, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_AU, DRAMPRIOM_LUT_TABLE4_ALT_UP, r3) + SET_REG32(r4, CFG_MDDRCGRP_LUT4_AL, DRAMPRIOM_LUT_TABLE4_ALT_LOW, r3) + + /* Initialize MDDRC */ + SET_REG32(r4, CFG_MDDRC_SYS_CFG_EN, DDR_SYS_CONFIG, r3) + SET_REG32(r4, CFG_MDDRC_TIME_CFG0, DDR_TIME_CONFIG0, r3) + SET_REG32(r4, CFG_MDDRC_TIME_CFG1, DDR_TIME_CONFIG1, r3) + SET_REG32(r4, CFG_MDDRC_TIME_CFG2, DDR_TIME_CONFIG2, r3) + + + /* Initialize DDR */ + SET_REG32(r4, CFG_MICRON_NOP, DDR_COMMAND, r3) + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + stw r4, DDR_COMMAND(r3); + + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + SET_REG32(r5, CFG_MICRON_NOP, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_RFSH, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_RFSH, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_INIT_DEV_OP, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_EM2, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_EM2, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_EM3, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_EN_DLL, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_INIT_DEV_OP, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_RFSH, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_INIT_DEV_OP, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_OCD_DEFAULT, DDR_COMMAND, r3) + SET_REG32(r4, CFG_MICRON_PCHG_ALL, DDR_COMMAND, r3) + stw r5, DDR_COMMAND(r3); + + /* Start MDDRC */ + SET_REG32(r4, CFG_MDDRC_TIME_CFG0_RUN, DDR_TIME_CONFIG0, r3) + SET_REG32(r4, CFG_MDDRC_SYS_CFG_RUN, DDR_SYS_CONFIG, r3) + isync + blr + diff --git a/nand_spl/board/ads5125/nfc.h b/nand_spl/board/ads5125/nfc.h new file mode 100644 index 0000000000..1406118eba --- /dev/null +++ b/nand_spl/board/ads5125/nfc.h @@ -0,0 +1,122 @@ +/* + * + * (C) Copyright 2009 + * Martha Marx, Silicon Turnkey Express, mmarx@silicontkx.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define TWO_K 0x800 +#define NUMPAGES 137 /* if u-boot grows .. extend this */ + +/* NAND Flash Controller Register Offsets */ +#define NFC_BUF_MAIN1 0x0000 +#define NFC_BUF_MAIN2 0x0200 +#define NFC_BUF_MAIN3 0x0400 +#define NFC_BUF_MAIN4 0x0600 +#define NFC_BUF_MAIN5 0x0800 +#define NFC_BUF_MAIN6 0x0A00 +#define NFC_BUF_MAIN7 0x0C00 +#define NFC_BUF_MAIN8 0x0E00 +#define NFC_BUF_SPARE1 0x1000 +#define NFC_BUF_SPARE2 0x1040 +#define NFC_BUF_SPARE3 0x1080 +#define NFC_BUF_SPARE4 0x10c0 +#define NFC_BUF_SPARE5 0x1100 +#define NFC_BUF_SPARE6 0x1140 +#define NFC_BUF_SPARE7 0x1180 +#define NFC_BUF_SPARE8 0x11c0 + +#define NFC_RAM_BUF_ADDR 0x1e04 +#define NFC_FLASH_ADDR 0x1e06 +#define NFC_FLASH_CMD 0x1e08 +#define NFC_NFC_CFG 0x1e0a +#define NFC_ECC_STATUS1 0x1e0c +#define NFC_ECC_STATUS2 0x1e0e +#define NFC_SPAS 0x1e10 +#define NFC_NF_WR_PROT 0x1e12 +#define NFC_FL_WP_STAT 0x1e18 +#define NFC_NF_CFG1 0x1e1a +#define NFC_NF_CFG2 0x1e1c +#define NFC_UNLOCKSTART_BLKADDR0 0x1E20 +#define NFC_UNLOCKEND_BLKADDR0 0x1E22 +#define NFC_UNLOCKSTART_BLKADDR1 0x1E24 +#define NFC_UNLOCKEND_BLKADDR1 0x1E26 +#define NFC_UNLOCKSTART_BLKADDR2 0x1E28 +#define NFC_UNLOCKEND_BLKADDR2 0x1E2A +#define NFC_UNLOCKSTART_BLKADDR3 0x1E2C +#define NFC_UNLOCKEND_BLKADDR3 0x1E2E + +#define RAM_BUFFER_ADDRESS_RBA_4 0x4 +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 + +/* Bit Definitions */ +#define NFC_INT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLOCKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + + + +#define NAND_CMD_RESET 0xff +#define NFC_ECC_MODE_4 1 +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 +#define NAND_CMD_READ0 0 +#define NAND_CMD_READSTART 0x30 +#define NAND_CMD_READCACHE 0x31 +#define NAND_CMD_READCACHEND 0x34 + diff --git a/nand_spl/board/ads5125/u-boot.lds b/nand_spl/board/ads5125/u-boot.lds new file mode 100644 index 0000000000..832a7c6004 --- /dev/null +++ b/nand_spl/board/ads5125/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + . = ALIGN(16); + *(.rodata*) + *(.eh_frame) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + *(.got2) + __got2_entries = (. - _GOT2_TABLE_) >> 2; + } + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { *(.*bss) } + _end = .; +} +ENTRY(_start) +ASSERT(_end <= 0xfff00800, "NAND bootstrap too big"); diff --git a/net/eth.c b/net/eth.c index 217e8853f5..30cdc5ebc1 100644 --- a/net/eth.c +++ b/net/eth.c @@ -56,6 +56,10 @@ static struct { static unsigned int eth_rcv_current = 0, eth_rcv_last = 0; #endif +#ifdef CONFIG_FASTBOOT +int eth_init_skipped; +#endif + static struct eth_device *eth_devices, *eth_current; struct eth_device *eth_get_dev(void) @@ -330,6 +334,15 @@ int eth_init(bd_t *bis) { struct eth_device* old_current; +#ifdef CONFIG_FASTBOOT + if (eth_init_skipped) { + DECLARE_GLOBAL_DATA_PTR; + eth_init_skipped = 0; + printf("Net: "); + eth_initialize(gd->bd); + } +#endif + if (!eth_current) { puts ("No ethernet found.\n"); return -1; diff --git a/net/net.c b/net/net.c index a55f4d33f9..73217a9677 100644 --- a/net/net.c +++ b/net/net.c @@ -303,6 +303,7 @@ NetInitLoop(proto_t protocol) NetCopyIP(&NetOurIP, &bd->bi_ip_addr); NetOurGatewayIP = getenv_IPaddr ("gatewayip"); NetOurSubnetMask= getenv_IPaddr ("netmask"); + NetServerIP = getenv_IPaddr ("serverip"); NetOurVLAN = getenv_VLAN("vlan"); NetOurNativeVLAN = getenv_VLAN("nvlan"); @@ -312,7 +313,6 @@ NetInitLoop(proto_t protocol) #endif case NETCONS: case TFTP: - NetServerIP = getenv_IPaddr ("serverip"); break; #if defined(CONFIG_CMD_PING) case PING: diff --git a/onenand_ipl/board/apollon/low_levelinit.S b/onenand_ipl/board/apollon/low_levelinit.S deleted file mode 100644 index 205170f7f5..0000000000 --- a/onenand_ipl/board/apollon/low_levelinit.S +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2005-2008 Samsung Electronics - * Kyungmin Park - * - * Derived from board/omap2420h4/platform.S - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#define APOLLON_CS0_BASE 0x00000000 - -#ifdef PRCM_CONFIG_I -#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 -#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 -#define SDRC_RFR_CTRL_0_VAL 0x00044C01 - -/* GPMC */ -#define APOLLON_GPMC_CONFIG1_0 0xe30d1201 -#define APOLLON_GPMC_CONFIG2_0 0x000c1000 -#define APOLLON_GPMC_CONFIG3_0 0x00030400 -#define APOLLON_GPMC_CONFIG4_0 0x0B841006 -#define APOLLON_GPMC_CONFIG5_0 0x020F0C11 -#define APOLLON_GPMC_CONFIG6_0 0x00000000 -#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24)) - -#elif defined(PRCM_CONFIG_II) -#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 -#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C -#define SDRC_RFR_CTRL_0_VAL 0x00030001 - -/* GPMC */ -#define APOLLON_GPMC_CONFIG1_0 0xe30d1201 -#define APOLLON_GPMC_CONFIG2_0 0x00080E81 -#define APOLLON_GPMC_CONFIG3_0 0x00030400 -#define APOLLON_GPMC_CONFIG4_0 0x08041586 -#define APOLLON_GPMC_CONFIG5_0 0x020C090E -#define APOLLON_GPMC_CONFIG6_0 0x00000000 -#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24)) - -#else -#error "Please configure PRCM schecm" -#endif - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - mov r3, r0 /* save skip information */ - - /* Disable watchdog */ - ldr r0, =WD2_BASE - ldr r1, =WD_UNLOCK1 - str r1, [r0, #WSPR] - - ldr r1, =WD_UNLOCK2 - str r1, [r0, #WSPR] - -#ifdef DEBUG_LED - /* LED0 OFF */ - ldr r0, =0x480000E5 /* ball AA10, mode 3 */ - mov r1, #0x0b - strb r1, [r0] -#endif - - /* Pin muxing for SDRC */ - mov r1, #0x00 - ldr r0, =0x480000A1 /* ball C12, mode 0 */ - strb r1, [r0] - - ldr r0, =0x48000032 /* ball D11, mode 0 */ - strb r1, [r0] - - ldr r0, =0x480000A3 /* ball B13, mode 0 */ - strb r1, [r0] - - /* SDRC setting */ - ldr r0, =OMAP2420_SDRC_BASE - ldr r1, =0x00000010 - str r1, [r0, #0x10] - - ldr r1, =0x00000100 - str r1, [r0, #0x44] - - /* SDRC CS0 configuration */ -#ifdef CONFIG_APOLLON_PLUS - ldr r1, =0x01702011 -#else - ldr r1, =0x00d04011 -#endif - str r1, [r0, #0x80] - - ldr r1, =SDRC_ACTIM_CTRLA_0_VAL - str r1, [r0, #0x9C] - - ldr r1, =SDRC_ACTIM_CTRLB_0_VAL - str r1, [r0, #0xA0] - - ldr r1, =SDRC_RFR_CTRL_0_VAL - str r1, [r0, #0xA4] - - ldr r1, =0x00000041 - str r1, [r0, #0x70] - - /* Manual command sequence */ - ldr r1, =0x00000007 - str r1, [r0, #0xA8] - - ldr r1, =0x00000000 - str r1, [r0, #0xA8] - - ldr r1, =0x00000001 - str r1, [r0, #0xA8] - - ldr r1, =0x00000002 - str r1, [r0, #0xA8] - str r1, [r0, #0xA8] - - /* - * CS0 SDRC Mode register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - ldr r1, =0x00000032 - str r1, [r0, #0x84] - - /* Note: You MUST set EMR values */ - /* EMR1 & EMR2 */ - ldr r1, =0x00000000 - str r1, [r0, #0x88] - str r1, [r0, #0x8C] - -#ifdef OLD_SDRC_DLLA_CTRL - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00007306 - str r1, [r0, #0x60] - - ldr r1, =0x00007303 - str r1, [r0, #0x60] -#else - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x60] - - ldr r1, =0x00000503 - str r1, [r0, #0x60] -#endif - -#ifdef __BROKEN_FEATURE__ - /* SDRC_DLLB_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x68] - - ldr r1, =0x00000503 - str r1, [r0, #0x68] -#endif - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b - - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - mov r0, r3 /* pass skip info to s_init */ - - bl s_init /* go setup pll,mux,memory */ - - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK -- cgit v1.2.3