From 2715f5b1512225a774523483bfa61b87447a21d4 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 29 Nov 2013 17:06:18 +0100 Subject: apalis/colibri_t30: add more console uart configurations Add more UART configurations to the device trees allowing easy switching of the console UART port by changing the UART base address of the console node within the device tree e.g. for using UART2 on Apalis T30 as follows: console = "/serial@70006300"; To use it for Linux as well one needs to modify the debug_uartport kernel boot argument e.g. for using UART2 on Apalis T30 as follows: setenv setup 'setenv setupargs gpt gpt_sector=${gptoffset} igb_mac= ${ethaddr} no_console_suspend=1 console=tty1 console=ttyS0,${baudrate}n 8 debug_uartport=lsport,3 ${memargs} fbcon=map:1' --- board/toradex/apalis_t30/apalis_t30.dts | 17 ++++++++++++++++- board/toradex/colibri_t30/colibri_t30.dts | 12 +++++++++++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/board/toradex/apalis_t30/apalis_t30.dts b/board/toradex/apalis_t30/apalis_t30.dts index 1059227e00..d0889b3843 100644 --- a/board/toradex/apalis_t30/apalis_t30.dts +++ b/board/toradex/apalis_t30/apalis_t30.dts @@ -33,7 +33,7 @@ reg = <0x80000000 0x80000000>; }; - serial@70006000 { + uarta: serial@70006000 { status = "ok"; /* * TBD - use CONFIG_SYS_PLLP_BASE_IS_408MHZ somehow here. @@ -42,6 +42,21 @@ clock-frequency = <408000000>; }; + uartb: serial@70006040 { + status = "ok"; + clock-frequency = <408000000>; + }; + + uartc: serial@70006200 { + status = "ok"; + clock-frequency = <408000000>; + }; + + uartd: serial@70006300 { + status = "ok"; + clock-frequency = <408000000>; + }; + /* SD - SDMMC1 */ sdhci@78000000 { status = "ok"; diff --git a/board/toradex/colibri_t30/colibri_t30.dts b/board/toradex/colibri_t30/colibri_t30.dts index 257b80f4fd..4929fbccba 100644 --- a/board/toradex/colibri_t30/colibri_t30.dts +++ b/board/toradex/colibri_t30/colibri_t30.dts @@ -32,7 +32,7 @@ reg = <0x80000000 0xc0000000>; }; - serial@70006000 { + uarta: serial@70006000 { status = "ok"; /* * TBD - use CONFIG_SYS_PLLP_BASE_IS_408MHZ somehow here. @@ -41,6 +41,16 @@ clock-frequency = <408000000>; }; + uartb: serial@70006040 { + status = "ok"; + clock-frequency = <408000000>; + }; + + uartd: serial@70006300 { + status = "ok"; + clock-frequency = <408000000>; + }; + sdhci@78000200 { status = "ok"; width = <4>; /* width of SDIO port */ -- cgit v1.2.3