From 15350ddaccdf14e7e274463db97b72c47a73b10b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 19 Mar 2012 13:12:13 -0700 Subject: x86: Fix TPM driver to work with multiple vendor TPMs - Fix bug in traversal of vendor name list. - Sending "command ready" needs additional logic to handle TPMs that need that bit set twice: once to empty the read FIFOs and once to actualy set command ready. - Certain TPMs need a small delay between requesting locality and attempting to set command ready or they will hang the bus. BUG=chrome-os-partner:8558 TEST=manual Successful boot and suspend/resume with all TPMs listed in the driver vendor/device list. Change-Id: I22021b24f9498c3cafe0e1d5f1c6562ea0be5aad Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/18480 Reviewed-by: Ronald G. Minnich Reviewed-by: Stefan Reinauer --- drivers/tpm/generic_lpc_tpm.c | 85 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 75 insertions(+), 10 deletions(-) diff --git a/drivers/tpm/generic_lpc_tpm.c b/drivers/tpm/generic_lpc_tpm.c index 6600f7600a..323238e0c3 100644 --- a/drivers/tpm/generic_lpc_tpm.c +++ b/drivers/tpm/generic_lpc_tpm.c @@ -102,13 +102,31 @@ struct vendor_name { struct device_name* dev_names; }; +static struct device_name atmel_devices[] = { + {0x3204, "AT97SC3204"}, + {0xffff} +}; + static struct device_name infineon_devices[] = { - {0xb, "SLB9635 TT 1.2"}, - {0} + {0x000b, "SLB9635 TT 1.2"}, + {0xffff} +}; + +static struct device_name nuvoton_devices[] = { + {0x00fe, "NPCT420AA V2"}, + {0xffff} +}; + +static struct device_name stmicro_devices[] = { + {0x0000, "ST33ZP24" }, + {0xffff} }; static const struct vendor_name vendor_names[] = { + {0x1114, "Atmel", atmel_devices}, {0x15d1, "Infineon", infineon_devices}, + {0x1050, "Nuvoton", nuvoton_devices}, + {0x104a, "ST Microelectronics", stmicro_devices}, }; /* @@ -182,6 +200,44 @@ static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) return TPM_TIMEOUT_ERR; } +/* + * PC Client Specific TPM Interface Specification section 11.2.12: + * + * Software must be prepared to send two writes of a "1" to command ready + * field: the first to indicate successful read of all the data, thus + * clearing the data from the ReadFIFO and freeing the TPM's resources, + * and the second to indicate to the TPM it is about to send a new command. + * + * In practice not all TPMs behave the same so it is necessary to be + * flexible when trying to set command ready. + * + * Returns 0 on success if the TPM is ready for transactions. + * Returns TPM_TIMEOUT_ERR if the command ready bit does not get set. + */ +static int tis_command_ready(u8 locality) +{ + u32 status; + + /* 1st attempt to set command ready */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + /* Wait for response */ + status = tpm_read(locality, TIS_REG_STS); + + /* Check if command ready is set yet */ + if (status & TIS_STS_COMMAND_READY) + return 0; + + /* 2nd attempt to set command ready */ + tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + + /* Wait for command ready to get set */ + status = tis_wait_reg(TIS_REG_STS, locality, + TIS_STS_COMMAND_READY, TIS_STS_COMMAND_READY); + + return (status == TPM_TIMEOUT_ERR) ? TPM_TIMEOUT_ERR : 0; +} + /* * Probe the TPM device and try determining its manufacturer/device name. * @@ -190,15 +246,17 @@ static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected) */ static u32 tis_probe(void) { - u32 didvid = tpm_read(0, TIS_REG_DID_VID); - int i; const char *device_name = "unknown"; const char *vendor_name = device_name; + struct device_name *dev; + u32 didvid; u16 vid, did; + int i; if (vendor_dev_id) return 0; /* Already probed. */ + didvid = tpm_read(0, TIS_REG_DID_VID); if (!didvid || (didvid == 0xffffffff)) { printf("%s: No TPM device found\n", __FUNCTION__); return TPM_DRIVER_ERR; @@ -213,11 +271,13 @@ static u32 tis_probe(void) u16 known_did; if (vid == vendor_names[i].vendor_id) { vendor_name = vendor_names[i].vendor_name; + } else { + continue; } - while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) { + dev = &vendor_names[i].dev_names[j]; + while ((known_did = dev->dev_id) != 0xffff) { if (known_did == did) { - device_name = - vendor_names[i].dev_names[j].dev_name; + device_name = dev->dev_name; break; } j++; @@ -225,7 +285,7 @@ static u32 tis_probe(void) break; } /* this will have to be converted into debug printout */ - TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name); + printf("Found TPM %s by %s\n", device_name, vendor_name); return 0; } @@ -421,7 +481,8 @@ static u32 tis_readresponse(u8 *buffer, u32 *len) } /* Tell the TPM that we are done. */ - tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + if (tis_command_ready(locality) == TPM_TIMEOUT_ERR) + return TPM_DRIVER_ERR; *len = offset; return 0; @@ -467,7 +528,11 @@ int tis_open(void) return TPM_DRIVER_ERR; } - tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS); + /* Certain TPMs seem to need some delay here or they hang... */ + udelay(10); + + if (tis_command_ready(locality) == TPM_TIMEOUT_ERR) + return TPM_DRIVER_ERR; return 0; } -- cgit v1.2.3 From 9e84c43e53980d862bba2fbb1095dd8793020743 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Fri, 20 Apr 2012 18:27:23 +0000 Subject: Provide alternative config for netbooting This change allows to build a customized u-boot image, which includes networking capabilities, provides diagnostic commands and supports command line editing. These features are necessary to facilitate the factory flow. This image needs to be clearly distinguishable by ChromeOS. This is achieved by modifying the value presented by the BINF.3 ACPI object. To build this modified image one needs to add BUILD_FACTORY_IMAGE=1 to the make invocation line. BUG=chrome-os-partner:7952 TEST=manual . build the new firmware image as follows: USE='pcserial factory-mode' emerge-link chromeos-u-boot \ chromeos-coreboot chromeos-bootimage . program the new image on the Link target with ChromeOS installed on the SSD and restart it . observe the target stop at u-boot command prompt (boot >) . connect the target to an Ethernet network with a DHCP server using a USB Ethernet dongle . run the following commands at the u-boot prompt boot > usb start (Re)start USB... USB: Register 203007 NbrPorts 7 USB EHCI 1.00 Register 20400b NbrPorts 11 USB EHCI 1.00 8 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found scanning bus for ethernet devices... 1 Ethernet Device(s) found boot > dhcp Waiting for Ethernet connection... done. BOOTP broadcast 1 BOOTP broadcast 2 [a few warnings of unsupported DHCP options] DHCP client bound to address 172.22.75.25 Using asx0 device TFTP from server 172.16.255.7; our IP address is 172.22.75.25; sending through gateway 172.22.75.254 Filename 'pxelinux.0'. Load address: 0x100000 Loading: ## done Bytes transferred = 15840 (3de0 hex) boot > . start ChromeOS on the target by issuing vboot_twostop . once ChromeOS boots check the mainfw_type crossystem reported value localhost ~ # echo $(crossystem mainfw_type) netboot localhost ~ # Change-Id: I1c50517754b6b5f773e432b9adec4b290f303e6f Signed-off-by: Vadim Bendebury Reviewed-on: https://gerrit.chromium.org/gerrit/21071 Reviewed-by: Duncan Laurie --- board/chromebook-x86/coreboot/config.mk | 3 +++ include/configs/coreboot.h | 16 ++++++++++++---- lib/chromeos/crossystem_data.c | 4 ++++ 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk index 857ee8c4b9..627d4cfaf2 100644 --- a/board/chromebook-x86/coreboot/config.mk +++ b/board/chromebook-x86/coreboot/config.mk @@ -36,3 +36,6 @@ HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros LD := $(LD).bfd +ifdef BUILD_FACTORY_IMAGE +PLATFORM_CPPFLAGS += -DFACTORY_IMAGE +endif diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index fd2c0ccf9f..939c79a7ff 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -33,10 +33,19 @@ */ #define CONFIG_SYS_COREBOOT #define CONFIG_SHOW_BOOT_PROGRESS -#define BUILD_CMD_LINE_STUFF 0 #define BUILD_IDE_STUFF 0 -#define BUILD_NETWORK_STUFF 0 -#define BUILD_PART_FS_STUFF 0 + +#ifdef FACTORY_IMAGE +#define BUILD_CMD_LINE_STUFF 1 +#define BUILD_NETWORK_STUFF 1 +#define BUILD_PART_FS_STUFF 1 +#define CONFIG_BOOTDELAY -1 +#else +#define BUILD_CMD_LINE_STUFF 0 +#define BUILD_NETWORK_STUFF 0 +#define BUILD_PART_FS_STUFF 0 +#define CONFIG_BOOTDELAY 0 +#endif /* FDT support */ #define CONFIG_OF_LIBFDT /* Device tree support */ @@ -333,7 +342,6 @@ /* Boot options */ -#define CONFIG_BOOTDELAY 0 /* -1 to disable auto boot */ #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_BOOTARGS "" diff --git a/lib/chromeos/crossystem_data.c b/lib/chromeos/crossystem_data.c index df387c1484..f719a29fee 100644 --- a/lib/chromeos/crossystem_data.c +++ b/lib/chromeos/crossystem_data.c @@ -305,7 +305,11 @@ int crossystem_data_update_acpi(crossystem_data_t *cdata) len = min(ID_LEN, sizeof(acpi_table->vbt6)); memcpy(acpi_table->vbt6, cdata->readonly_firmware_id, len); +#ifdef FACTORY_IMAGE + acpi_table->vbt7 = 3; /* '3' means 'netboot' to crossystem */ +#else acpi_table->vbt7 = cdata->firmware_type; +#endif acpi_table->vbt8 = RECOVERY_REASON_NONE; acpi_table->vbt9 = cdata->fmap_offset; -- cgit v1.2.3 From beb13227f8756d4dcb0fec297398a16d0019f4ab Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Fri, 27 Apr 2012 17:42:54 -0700 Subject: arm: tegra2: seaboard: Enable CRC32 v option The cros_write_firmware has updated flash script command 'crc32' with -v option. To support this change, u-boot needs to be built with CONFIG_CRC32_VERIFY for seaboard. BUG=none TEST=run cros_write_firmware with local build u-boot. Change-Id: I49046ce2424c4624a335af32051421e44bd388bb Signed-off-by: Jimmy Zhang Reviewed-on: https://gerrit.chromium.org/gerrit/21420 Reviewed-by: Simon Glass Reviewed-by: Mark Zhang Reviewed-by: Wei Ni --- include/configs/seaboard.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 5e68faca3f..223beaea77 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -38,6 +38,9 @@ #include "tegra2-common.h" +/* So our flasher can verify that all is well */ +#define CONFIG_CRC32_VERIFY + #ifndef CONFIG_OF_CONTROL /* Things in here are defined by the device tree now. Let it grow! */ -- cgit v1.2.3 From 13f56163c945c3838f84cb449180595d8581d2ee Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Thu, 31 May 2012 11:48:46 +0530 Subject: arm: tegra3: Fix bootup up issue At bootup time device enters in standby state as CLK_RST_CONTROLLER_SCLK_BURST_POLICY is not set correctly. This change correctly sets clock burst policy. BUG = None TEST= Build OK for Seaboard,Cardhu and Waluigi. Tested on Cardhu and waluigi. Device boots up. Change-Id: I598ca7bcfc4a39ecaa68c211d3439ac3569c6e44 Signed-off-by: Puneet Saxena Reviewed-on: https://gerrit.chromium.org/gerrit/24164 Reviewed-by: Varun Wadekar Reviewed-by: Tom Warren Reviewed-by: Jimmy Zhang Tested-by: Tom Warren Commit-Ready: Tom Warren Reviewed-by: Simon Glass --- arch/arm/cpu/armv7/tegra3/warmboot_avp.c | 2 +- arch/arm/include/asm/arch-tegra/clk_rst.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c index 02772d42c1..5281e8f86f 100644 --- a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c +++ b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c @@ -81,7 +81,7 @@ void wb_start(void) reg = SCLK_SWAKE_FIQ_SRC_CLKM | SCLK_SWAKE_IRQ_SRC_CLKM | SCLK_SWAKE_RUN_SRC_CLKM | SCLK_SWAKE_IDLE_SRC_CLKM | - SCLK_SYS_STATE_RUN; + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); writel(reg, &clkrst->crc_sclk_brst_pol); /* Update PLLP output dividers for 408 MHz operation */ diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 6bf9cb6131..d170b3c723 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -275,7 +275,6 @@ enum { #define SUPER_CDIV_ENB (1 << 31) /* CRC_SCLK_BURST_POLICY_0 28h */ -#define SCLK_SYS_STATE_RUN (2 << 28) #define SCLK_SWAKE_FIQ_SRC_CLKM (0 << 12) #define SCLK_SWAKE_IRQ_SRC_CLKM (0 << 8) #define SCLK_SWAKE_RUN_SRC_CLKM (0 << 4) -- cgit v1.2.3 From 48ca7acfd6690b06f7e72a66f5bd741dca36be42 Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Tue, 1 May 2012 16:35:57 -0700 Subject: tegra: config: Change load entry to 0x108000/0x80108000 0x108000/0x80108000 is used as tegra2/tegra3's default boot loader entry address. This change makes u-boot to comply with nvidia standard flash tools. BUG=none TEST=run cros_write_firmware with local build u-boot. Kernel boots up fine. Change-Id: I55e9b5d1847cf7e6a94d362935deef5f6855ba5a Signed-off-by: Jimmy Zhang Reviewed-on: https://gerrit.chromium.org/gerrit/21979 Reviewed-by: Simon Glass --- include/configs/tegra2-common.h | 2 +- include/configs/tegra3-common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 8396dc4d3b..9b8f7242da 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -156,7 +156,7 @@ #define PHYS_SDRAM_1 TEGRA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_TEXT_BASE 0x00E08000 +#define CONFIG_SYS_TEXT_BASE 0x00108000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define BCT_SDRAM_PARAMS_OFFSET (BCT_OFFSET + 0x88) diff --git a/include/configs/tegra3-common.h b/include/configs/tegra3-common.h index ea391c1900..4a42c63e46 100644 --- a/include/configs/tegra3-common.h +++ b/include/configs/tegra3-common.h @@ -131,7 +131,7 @@ #define PHYS_SDRAM_1 TEGRA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GB */ -#define CONFIG_SYS_TEXT_BASE 0x80E08000 +#define CONFIG_SYS_TEXT_BASE 0x80108000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_INITRD_TAG /* enable initrd ATAG */ -- cgit v1.2.3 From b39a120de590a04a6bb7f04cb4cffa5f6aed715e Mon Sep 17 00:00:00 2001 From: Jimmy Zhang Date: Tue, 8 May 2012 15:02:42 -0700 Subject: tegra: fdt: Change load entry to 0x1080000 Change tegra2's entry address to its default address 0x108000. BUG=none TEST=flashed with local built u-boot. Kernel boots up fine. Change-Id: I6ff4ed1f2901df73b21d033fbd191550108e96b5 Signed-off-by: Jimmy Zhang Reviewed-on: https://gerrit.chromium.org/gerrit/22171 Reviewed-by: Simon Glass --- board/nvidia/seaboard/chromeos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/nvidia/seaboard/chromeos.dtsi b/board/nvidia/seaboard/chromeos.dtsi index 0088121556..438af87824 100644 --- a/board/nvidia/seaboard/chromeos.dtsi +++ b/board/nvidia/seaboard/chromeos.dtsi @@ -12,7 +12,7 @@ chromeos-config { twostop; /* Two-stop boot */ twostop-optional; /* One-stop optimization enabled */ - textbase = <0xe08000>; /* Address where U-Boot loads */ + textbase = <0x108000>; /* Address where U-Boot loads */ /* * Device and offset for second-stage firmware, in SPI for now -- cgit v1.2.3