From 6de56c3f6298c831f50b201d7e3cbbb9d4f352db Mon Sep 17 00:00:00 2001 From: Clement Faure Date: Fri, 19 Aug 2022 16:06:27 +0200 Subject: LFOPTEE-177 s400_api: add DEK Blob generation Add ELE_GENERATE_DEK_BLOB API for encrypted boot support. Add CRC message computation. Signed-off-by: Clement Faure --- arch/arm/include/asm/mach-imx/s400_api.h | 4 ++- drivers/misc/sentinel/s400_api.c | 47 +++++++++++++++++++++++++++++++- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h index 9e3c8136df..539b1d16bb 100644 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -25,6 +25,7 @@ #define ELE_RET_LIFECYCLE_UP_REQ (0xA0) #define ELE_GET_EVENTS_REQ (0xA2) #define ELE_START_RNG (0xA3) +#define ELE_GENERATE_DEK_BLOB (0xAF) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) #define ELE_GET_FW_STATUS_REQ (0xC5) @@ -144,5 +145,6 @@ int ahab_get_fw_status(u32 *status, u32 *response); int ahab_release_m33_trout(void); int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response); int ahab_start_rng(void); - +int ahab_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, + u32 max_output_size); #endif diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c index 271d12191d..8ac17890b4 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/sentinel/s400_api.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2020 NXP + * Copyright 2020, 2022 NXP * */ @@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR; +static uint32_t compute_crc(const struct sentinel_msg *msg) +{ + u32 crc = 0; + size_t i = 0; + u32 *data = (u32 *)msg; + + for (i = 0; i < (msg->size - 1); i++) + crc ^= data[i]; + + return crc; +} + int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response) { struct udevice *dev = gd->arch.s400_dev; @@ -516,3 +528,36 @@ int ahab_start_rng(void) return ret; } + +int ahab_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, + u32 max_output_size) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 8; + msg.command = ELE_GENERATE_DEK_BLOB; + msg.data[0] = key_id; + msg.data[1] = 0x0; + msg.data[2] = src_paddr; + msg.data[3] = 0x0; + msg.data[4] = dst_paddr; + msg.data[5] = max_output_size; + msg.data[6] = compute_crc(&msg); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret 0x%x, response 0x%x\n", + __func__, ret, msg.data[0]); + + return ret; +} -- cgit v1.2.3 From bf07f5166bff8b1981c9b4e54eaa7764f1e2ffbf Mon Sep 17 00:00:00 2001 From: Clement Faure Date: Fri, 19 Aug 2022 16:09:02 +0200 Subject: LFOPTEE-177 imx: cmd_dek: add ELE DEK Blob generation support Add ELE DEK Blob generation for the cmd_dek command. Signed-off-by: Clement Faure --- arch/arm/mach-imx/Kconfig | 7 ++++ arch/arm/mach-imx/cmd_dek.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0616b05a05..9976ab78d0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -109,6 +109,7 @@ config CMD_DEKBLOB select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M select IMX_SECO_DEK_ENCAP if ARCH_IMX8 + select IMX_ELE_DEK_ENCAP if ARCH_IMX8ULP || ARCH_IMX9 help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and @@ -137,6 +138,12 @@ config IMX_SECO_DEK_ENCAP This enabled the DEK blob encapsulation with the SECO API. This option is only available on imx8. +config IMX_ELE_DEK_ENCAP + bool "Support the DEK blob encapsulation with ELE" + help + This enabled the DEK blob encapsulation with the ELE API. This option + is only available on imx8ulp and imx9. + config CMD_PRIBLOB bool "Support the set_priblob_bitfield command" depends on HAS_CAAM && IMX_HAB diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 701bf516df..5ff8a4e55d 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2015 Freescale Semiconductor, Inc. + * Copyright 2022 NXP * * Command for encapsulating DEK blob */ @@ -20,6 +21,11 @@ #include #include #endif +#ifdef CONFIG_IMX_ELE_DEK_ENCAP +#include +#include +#endif + #include /** @@ -284,6 +290,84 @@ error: } #endif /* CONFIG_IMX_SECO_DEK_ENCAP */ +#ifdef CONFIG_IMX_ELE_DEK_ENCAP + +#define DEK_BLOB_HDR_SIZE 8 +#define AHAB_PRIVATE_KEY 0x81 +#define AHAB_DEK_BLOB 0x01 +#define AHAB_ALG_AES 0x03 +#define AHAB_128_AES_KEY 0x10 +#define AHAB_192_AES_KEY 0x18 +#define AHAB_256_AES_KEY 0x20 + +static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) +{ + u8 in_size, out_size; + u8 *src_ptr, *dst_ptr; + struct generate_key_blob_hdr hdr; + + /* Set sizes */ + in_size = sizeof(struct generate_key_blob_hdr) + len / 8; + out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE; + + /* Get src and dst virtual addresses */ + src_ptr = map_sysmem(src_addr, in_size); + dst_ptr = map_sysmem(dst_addr, out_size); + + /* Check addr input */ + if (!(src_ptr && dst_ptr)) { + debug("src_addr or dst_addr invalid\n"); + return -1; + } + + /* Build key header */ + hdr.version = 0x0; + hdr.length_lsb = in_size; + hdr.length_msb = 0x00; + hdr.tag = AHAB_PRIVATE_KEY; + hdr.flags = AHAB_DEK_BLOB; + hdr.algorithm = AHAB_ALG_AES; + hdr.mode = 0x0; /* Not used by the ELE */ + + switch (len) { + case 128: + hdr.size = AHAB_128_AES_KEY; + break; + case 192: + hdr.size = AHAB_192_AES_KEY; + break; + case 256: + hdr.size = AHAB_256_AES_KEY; + break; + default: + /* Not supported */ + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + /* Move input key and append blob header */ + memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)), + (void *)src_ptr, len / 8); + memcpy((void *)src_ptr, (void *)&hdr, + sizeof(struct generate_key_blob_hdr)); + + /* Flush the cache */ + flush_dcache_range(src_addr, src_addr + in_size); + flush_dcache_range(dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + /* Call ELE */ + if (ahab_generate_dek_blob(0x00, src_addr, dst_addr, out_size)) + return -1; + + /* Invalidate output buffer */ + invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + return 0; +} +#endif /* CONFIG_IMX_ELE_DEK_ENCAP */ + /** * do_dek_blob() - Handle the "dek_blob" command-line command * @cmdtp: Command data struct pointer -- cgit v1.2.3 From f0721d67f036d5902dacba2a98ed5bffa448ac76 Mon Sep 17 00:00:00 2001 From: Clement Faure Date: Fri, 19 Aug 2022 16:11:26 +0200 Subject: LFOPTEE-177 imx8ulp: enable cmd_dek command Enable cmd_dek command for DEK Blob generation. Signed-off-by: Clement Faure --- configs/imx8ulp_evk_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index 98ed956a20..f6cd629a36 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -138,3 +138,6 @@ CONFIG_POWER_DOMAIN=y CONFIG_DM_THERMAL=y CONFIG_SCMI_THERMAL=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y -- cgit v1.2.3 From 9710cc4840e1d70ced569b41196ba31be01e9bbc Mon Sep 17 00:00:00 2001 From: Clement Faure Date: Mon, 22 Aug 2022 13:51:42 +0200 Subject: LFOPTEE-177 imx93evk: enable cmd_dek command Enable cmd_dek command for DEK Blob generation. Signed-off-by: Clement Faure --- configs/imx93_11x11_evk_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 9ea7b851af..0d2d135b6a 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -170,3 +170,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_CMD_BMP=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y -- cgit v1.2.3 From 48b1d6e34fd462830bbabd390a4ec4c369dc2059 Mon Sep 17 00:00:00 2001 From: "faqiang.zhu" Date: Mon, 16 May 2022 12:41:44 +0800 Subject: MA-20149 set fs type of android partitions The usedata partition fs type is switched to be f2fs. Set it uboot for the return result of "fastboot getvar" command, and the "fastboot format userdata" can automatically format the userdata partition as f2fs. For read-only partitions with android rootfs images, the fs type is switched to be erofs. Althrough these partitions are dynamic partitions which cannot be recognized by uboot, set their types still. Signed-off-by: faqiang.zhu --- drivers/fastboot/fb_fsl/fb_fsl_partitions.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c index 237ae875ab..0cad38e993 100644 --- a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c +++ b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c @@ -118,15 +118,16 @@ static int _fastboot_parts_add_ptable_entry(int ptable_index, !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_A) || !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_A) || !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_B) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_B) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_B)) #else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || !strcmp((const char *)info.name, FASTBOOT_PARTITION_DEVICE) || - !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE)) #endif - !strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA)) + strcpy(ptable[ptable_index].fstype, "erofs"); + else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA)) + strcpy(ptable[ptable_index].fstype, "f2fs"); + else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA)) strcpy(ptable[ptable_index].fstype, "ext4"); else strcpy(ptable[ptable_index].fstype, "raw"); -- cgit v1.2.3 From 60555c4a445c9bae25456d1d2335a7eac5ea06cd Mon Sep 17 00:00:00 2001 From: Kshitiz Varshney Date: Wed, 7 Sep 2022 09:16:46 +0200 Subject: PLATSEC-1781-1 mx6ull:Add config CONFIG_OF_SYSTEM_SETUP This commit enables CONFIG_OF_SYSTEM_SETUP for making modification to the flat device tree before handing it off to the kernel. This causes ft_system_setup() to be called before booting the kernel. Signed-off-by: Kshitiz Varshney --- configs/mx6ull_14x14_evk_defconfig | 1 + configs/mx6ull_14x14_evk_emmc_defconfig | 1 + configs/mx6ull_14x14_evk_nand_defconfig | 1 + configs/mx6ull_14x14_evk_optee_defconfig | 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + configs/mx6ull_14x14_evk_qspi1_defconfig | 1 + configs/mx6ull_9x9_evk_defconfig | 1 + configs/mx6ull_9x9_evk_plugin_defconfig | 1 + configs/mx6ull_9x9_evk_qspi1_defconfig | 1 + 9 files changed, 9 insertions(+) diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 79964b3ccf..b81047f845 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -103,3 +103,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig index f4bcc40544..b6925f0282 100644 --- a/configs/mx6ull_14x14_evk_emmc_defconfig +++ b/configs/mx6ull_14x14_evk_emmc_defconfig @@ -103,3 +103,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig index 1931293bc6..0bbd9b9e59 100644 --- a/configs/mx6ull_14x14_evk_nand_defconfig +++ b/configs/mx6ull_14x14_evk_nand_defconfig @@ -110,3 +110,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig index ba1c8e02a4..e5ca8d808c 100644 --- a/configs/mx6ull_14x14_evk_optee_defconfig +++ b/configs/mx6ull_14x14_evk_optee_defconfig @@ -104,3 +104,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 9c1354981e..19dcf4abee 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -104,3 +104,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig index 13a1eec75e..54266facb0 100644 --- a/configs/mx6ull_14x14_evk_qspi1_defconfig +++ b/configs/mx6ull_14x14_evk_qspi1_defconfig @@ -106,3 +106,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig index 3f73c5e697..7b88d47678 100644 --- a/configs/mx6ull_9x9_evk_defconfig +++ b/configs/mx6ull_9x9_evk_defconfig @@ -108,3 +108,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig index 41468f2d38..526d2b3f1d 100644 --- a/configs/mx6ull_9x9_evk_plugin_defconfig +++ b/configs/mx6ull_9x9_evk_plugin_defconfig @@ -108,3 +108,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig index f1446ef8e0..4ffc639da2 100644 --- a/configs/mx6ull_9x9_evk_qspi1_defconfig +++ b/configs/mx6ull_9x9_evk_qspi1_defconfig @@ -110,3 +110,4 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y +CONFIG_OF_SYSTEM_SETUP=y -- cgit v1.2.3 From 8789f3ca3e400caa4c4acabfabf80b0441909bc6 Mon Sep 17 00:00:00 2001 From: Kshitiz Varshney Date: Wed, 7 Sep 2022 09:57:59 +0200 Subject: PLATSEC-1781-2 MX6: Device tree fix-up This commit fixes up the device tree with 16 byte randomly generated (each) otp_crypto_key, otp_unique_key handles inside dcp crypto node. Signed-off-by: Kshitiz Varshney --- arch/arm/mach-imx/mx6/module_fuse.c | 47 +++++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index c24d8279ed..6e3cc8b46c 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2022 NXP */ #include @@ -10,6 +10,11 @@ #include #include #include +#include +#include +#include +#include +#include static struct fuse_entry_desc mx6_fuse_descs[] = { #if defined(CONFIG_MX6ULL) @@ -300,7 +305,45 @@ add_status: } } - return 0; + /*Random number generation through RNG driver*/ + struct udevice *dev; + void *buf; + char keys[2][16] = {"otp_crypto_key", "otp_unique_key"}; + int ret = 0; + int nodeoff = fdt_path_offset(blob, "/soc/bus@2200000/crypto@2280000"); + + if (nodeoff < 0) { + printf("node to update the SoC serial number is not found.\n"); + return nodeoff; + } + rc = uclass_get_device(UCLASS_RNG, 0, &dev); + if (rc || !dev) { + printf("No RNG device\n"); + return rc; + } + + buf = malloc(16); + if (!buf) { + printf("Out of memory\n"); + return -ENOMEM; + } + + for (int i = 0; i < 2; i++) { + ret = dm_rng_read(dev, buf, 16); + if (ret) { + printf("Reading RNG failed\n"); + goto err; + } + + ret = fdt_setprop(blob, nodeoff, keys[i], buf, 16); + if (ret < 0) { + printf("WARNING: could not set %s key handle %s.\n", keys[i], fdt_strerror(ret)); + goto err; + } + } +err: + free(buf); + return ret; } #endif -- cgit v1.2.3 From 0a6297a290e09b0f856a6cf1f4db7bc3d0c60eb6 Mon Sep 17 00:00:00 2001 From: Ji Luo Date: Wed, 21 Sep 2022 20:56:39 +0800 Subject: MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default on A1 chip, when DBD_EN is fused and HAB closed, the TRDC was owned by S400 and the ATF space (SSRAM) would be locked (RW only) before HAB verify, which would cause boot hang if we don't enable CONFIG_AHAB_BOOT by default. This commit enables CONFIG_AHAB_BOOT by default, so the execution permission on SSRAM would be added on HAB closed board. Signed-off-by: Ji Luo --- configs/imx8ulp_9x9_evk_android_defconfig | 1 + configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig | 1 + configs/imx8ulp_9x9_evk_android_uuu_defconfig | 1 + configs/imx8ulp_evk_android_defconfig | 1 + configs/imx8ulp_evk_android_dual_defconfig | 1 + configs/imx8ulp_evk_android_trusty_defconfig | 1 + configs/imx8ulp_evk_android_trusty_dual_defconfig | 1 + configs/imx8ulp_evk_android_uuu_defconfig | 1 + 8 files changed, 8 insertions(+) diff --git a/configs/imx8ulp_9x9_evk_android_defconfig b/configs/imx8ulp_9x9_evk_android_defconfig index 939de54bac..7f326aacf1 100644 --- a/configs/imx8ulp_9x9_evk_android_defconfig +++ b/configs/imx8ulp_9x9_evk_android_defconfig @@ -148,3 +148,4 @@ CONFIG_ANDROID_AB_SUPPORT=y CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig index 2154d9ad67..6dc7a0d6cf 100644 --- a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig @@ -155,3 +155,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_9x9_evk_android_uuu_defconfig b/configs/imx8ulp_9x9_evk_android_uuu_defconfig index d816b90bb9..860e5f1d36 100644 --- a/configs/imx8ulp_9x9_evk_android_uuu_defconfig +++ b/configs/imx8ulp_9x9_evk_android_uuu_defconfig @@ -143,3 +143,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_defconfig b/configs/imx8ulp_evk_android_defconfig index b944e8cc6b..df603245f0 100644 --- a/configs/imx8ulp_evk_android_defconfig +++ b/configs/imx8ulp_evk_android_defconfig @@ -148,3 +148,4 @@ CONFIG_ANDROID_AB_SUPPORT=y CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_dual_defconfig b/configs/imx8ulp_evk_android_dual_defconfig index 84f31a638d..1fef689c74 100644 --- a/configs/imx8ulp_evk_android_dual_defconfig +++ b/configs/imx8ulp_evk_android_dual_defconfig @@ -149,3 +149,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_trusty_defconfig b/configs/imx8ulp_evk_android_trusty_defconfig index c6e2378b82..5e54aca9d7 100644 --- a/configs/imx8ulp_evk_android_trusty_defconfig +++ b/configs/imx8ulp_evk_android_trusty_defconfig @@ -154,3 +154,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp" CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_trusty_dual_defconfig b/configs/imx8ulp_evk_android_trusty_dual_defconfig index 1f345e8d1f..93ca30df1d 100644 --- a/configs/imx8ulp_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_evk_android_trusty_dual_defconfig @@ -155,3 +155,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_uuu_defconfig b/configs/imx8ulp_evk_android_uuu_defconfig index 966f40d169..e8e5f12685 100644 --- a/configs/imx8ulp_evk_android_uuu_defconfig +++ b/configs/imx8ulp_evk_android_uuu_defconfig @@ -143,3 +143,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_AHAB_BOOT=y -- cgit v1.2.3 From 167f65006fb23442c0e020919515ba3c979732f2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 5 Sep 2022 09:19:13 +0800 Subject: MLK-26021 imx93: add 9x9 qsb lpddr4 board Add i.MX93 9x9 QSB board support, the left feature is splash screen for now. Reviewed-by: Ye Li Signed-off-by: Peng Fan (cherry picked from commit 7af2a3c29b05007f6e6a47990997ed415f3dad24) --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi | 178 ++++ arch/arm/dts/imx93-9x9-qsb.dts | 603 +++++++++++ arch/arm/mach-imx/imx9/Kconfig | 6 + board/freescale/imx93_qsb/Kconfig | 14 + board/freescale/imx93_qsb/Makefile | 12 + board/freescale/imx93_qsb/imx93_qsb.c | 245 +++++ board/freescale/imx93_qsb/lpddr4_timing.c | 1575 +++++++++++++++++++++++++++++ board/freescale/imx93_qsb/spl.c | 132 +++ configs/imx93_9x9_qsb_defconfig | 157 +++ include/configs/imx93_qsb.h | 200 ++++ 11 files changed, 3124 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi create mode 100644 arch/arm/dts/imx93-9x9-qsb.dts create mode 100644 board/freescale/imx93_qsb/Kconfig create mode 100644 board/freescale/imx93_qsb/Makefile create mode 100644 board/freescale/imx93_qsb/imx93_qsb.c create mode 100644 board/freescale/imx93_qsb/lpddr4_timing.c create mode 100644 board/freescale/imx93_qsb/spl.c create mode 100644 configs/imx93_9x9_qsb_defconfig create mode 100644 include/configs/imx93_qsb.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 37be88c70e..f036e54186 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1004,7 +1004,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-kontron-pitx-imx8m.dtb dtb-$(CONFIG_ARCH_IMX9) += \ - imx93-11x11-evk.dtb + imx93-11x11-evk.dtb \ + imx93-9x9-qsb.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi new file mode 100644 index 0000000000..06935ce1e4 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + u-boot,dm-spl; +}; + +&lpi2c2 { + u-boot,dm-spl; +}; + +&lpi2c3 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c1 { + u-boot,dm-spl; +}; + +&pinctrl_lpi2c2 { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&s4muap { + u-boot,dm-spl; + status = "okay"; +}; + +&clk { + u-boot,dm-pre-reloc; + u-boot,dm-spl; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + +&osc_32k { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&osc_24m { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk_ext1 { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <400000000>, <133333334>; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb.dts b/arch/arm/dts/imx93-9x9-qsb.dts new file mode 100644 index 0000000000..29c244ad5b --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb.dts @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + model = "NXP i.MX93 9x9 Quick Start Board"; + compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + cm33: imx93-cm33 { + compatible = "fsl,imx93-cm33"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1 + &mu1 1 1 + &mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + fsl,startup-delay-ms = <500>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-micfil"; + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + rtl821x,aldps-disable; + rtl821x,clkout-disable; + }; + }; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; + +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + fsl,sdio-async-interrupt-enabled; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; +}; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index c709448411..d4dca5fd95 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -27,9 +27,15 @@ config TARGET_IMX93_11X11_EVK bool "imx93_11x11_evk" select IMX93 +config TARGET_IMX93_9X9_QSB + bool "imx93_9x9_qsb" + select IMX93 + select IMX9_LPDDR4X + endchoice source "board/freescale/imx93_evk/Kconfig" +source "board/freescale/imx93_qsb/Kconfig" endif diff --git a/board/freescale/imx93_qsb/Kconfig b/board/freescale/imx93_qsb/Kconfig new file mode 100644 index 0000000000..47eab96b70 --- /dev/null +++ b/board/freescale/imx93_qsb/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX93_9X9_QSB + +config SYS_BOARD + default "imx93_qsb" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx93_qsb" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx93_qsb/Makefile b/board/freescale/imx93_qsb/Makefile new file mode 100644 index 0000000000..b4aca9bf1d --- /dev/null +++ b/board/freescale/imx93_qsb/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_qsb.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += lpddr4_timing.o +endif diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c new file mode 100644 index 0000000000..9d6115afd8 --- /dev/null +++ b/board/freescale/imx93_qsb/imx93_qsb.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2) +#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(LPUART1_CLK_ROOT); + + return 0; +} + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port portpd; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(0, 0x71); + } else + return -EINVAL; +} + +struct tcpc_port_config portpd_config = { + .i2c_bus = 0, /*i2c1*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 15000, + .op_snk_mv = 9000, +}; + +struct tcpc_port_config port1_config = { + .i2c_bus = 0, /*i2c1*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, + .disable_pd = true, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port pd\n"); + ret = tcpc_init(&portpd, portpd_config, NULL); + if (ret) { + printf("%s: tcpc portpd init failed, err=%d\n", + __func__, ret); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + struct tcpc_port *port_ptr; + + debug("board_usb_init %d, type %d\n", index, init); + + port_ptr = &port1; + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + + if (init == USB_INIT_HOST) + ret = tcpc_disable_src_vbus(&port1); + + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + debug("%s %d\n", __func__, dev_seq(dev)); + + port_ptr = &port1; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + + tcpc_print_log(port_ptr); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_eqos(void) +{ + struct blk_ctrl_wakeupmix_regs *bctrl = + (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&bctrl->eqos_gpr, + BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, + BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); + + return set_clk_eqos(ENET_125MHZ); +} + +int board_init(void) +{ +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) + setup_eqos(); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "(9X9_QSB"); + env_set("board_rev", "iMX93"); +#endif + return 0; +} + diff --git a/board/freescale/imx93_qsb/lpddr4_timing.c b/board/freescale/imx93_qsb/lpddr4_timing.c new file mode 100644 index 0000000000..9eec154724 --- /dev/null +++ b/board/freescale/imx93_qsb/lpddr4_timing.c @@ -0,0 +1,1575 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from IMX_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44140001 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000512 }, + { 0x4e300084, 0x0 }, + { 0x4e300114, 0x2 }, + { 0x4e300260, 0x0 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300104, 0xaaee001b }, + { 0x4e300108, 0x626ee273 }, + { 0x4e30010c, 0x5e18b }, + { 0x4e300100, 0x25ab321b }, + { 0x4e300160, 0x9002 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300250, 0x2b }, + { 0x4e300254, 0x15b015b }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x26522613 }, + { 0x4e300304, 0x15b2217 }, + { 0x4e300308, 0xa380e3c }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300124, 0x1c770000 }, + { 0x4e300800, 0x43930002 }, + { 0x4e300804, 0x1f1f1f1f }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0xb }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x12007d, 0x212 }, + { 0x12007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x1004d, 0x600 }, + { 0x1014d, 0x600 }, + { 0x1104d, 0x600 }, + { 0x1114d, 0x600 }, + { 0x11004d, 0x600 }, + { 0x11014d, 0x600 }, + { 0x11104d, 0x600 }, + { 0x11114d, 0x600 }, + { 0x10049, 0xe3f }, + { 0x10149, 0xe3f }, + { 0x11049, 0xe3f }, + { 0x11149, 0xe3f }, + { 0x110049, 0xe3f }, + { 0x110149, 0xe3f }, + { 0x111049, 0xe3f }, + { 0x111149, 0xe3f }, + { 0x43, 0x7f }, + { 0x1043, 0x7f }, + { 0x2043, 0x7f }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x11 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x3a5 }, + { 0x120008, 0x1d3 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x1200b2, 0x10c }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x1200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x20021, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4808 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4808 }, + { 0x54024, 0x4 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x848 }, + { 0x54036, 0x48 }, + { 0x54037, 0x400 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x848 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4808 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4808 }, + { 0x54024, 0x4 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x331b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x848 }, + { 0x54036, 0x48 }, + { 0x54037, 0x400 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x331b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x848 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4808 }, + { 0x5401e, 0x4 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4808 }, + { 0x54024, 0x4 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x848 }, + { 0x54036, 0x48 }, + { 0x54037, 0x400 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x848 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x400 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x0 }, + { 0x2000b, 0x419 }, + { 0x2000c, 0xe9 }, + { 0x2000d, 0x91c }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x20c }, + { 0x12000c, 0x74 }, + { 0x12000d, 0x48e }, + { 0x12000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, }, +}; diff --git a/board/freescale/imx93_qsb/spl.c b/board/freescale/imx93_qsb/spl.c new file mode 100644 index 0000000000..0b7b88f01a --- /dev/null +++ b/board/freescale/imx93_qsb/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* 0.9v: for LPDDR4X 3722 */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + + /* 1.1v for LPDDR4 */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_early_init_f(); + + spl_early_init(); + + preloader_console_init(); + + ret = arch_cpu_init_dm(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + printf("SOC: 0x%x\n", gd->arch.soc_rev); + printf("LC: 0x%x\n", gd->arch.lifecycle); + } + power_init_board(); + + /* Increase ARM clock to 1.7Ghz */ + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, 1700000000); /* 1.7Ghz */ + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig new file mode 100644 index 0000000000..2a4611d8cf --- /dev/null +++ b/configs/imx93_9x9_qsb_defconfig @@ -0,0 +1,157 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-9x9-qsb" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_9X9_QSB=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h new file mode 100644 index 0000000000..7a0600fd76 --- /dev/null +++ b/include/configs/imx93_qsb.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __IMX93_QSB_H +#define __IMX93_QSB_H + +#include +#include +#include +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (SZ_64M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x2051ddd0 +#define CONFIG_SPL_BSS_START_ADDR 0x2051e000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x83200000 /* Need disable simple malloc where still uses malloc_f area */ +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) + +#include +#else +#define BOOTENV +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + BOOTENV \ + AHAB_ENV \ + "scriptaddr=0x83500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "splashimage=0x90000000\0" \ + "console=ttyLP0,115200 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;" \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi;" + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" + +#define DWC_NET_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#endif -- cgit v1.2.3 From 65287dc074dd30b011b170348fb8a2dd970bf632 Mon Sep 17 00:00:00 2001 From: "Oliver F. Brown" Date: Thu, 8 Sep 2022 17:14:48 -0500 Subject: LF-7055: video: imx: Add set_parent calls to LVDS initialization The set_parent calls for the LVDS Pixel and Phy clock must be add. The default parent from the System firmware may no longer be expected to be set to "bypass". Signed-off-by: Oliver F. Brown Reviewed-by: Liu Ying (cherry picked from commit cb6d090fd2f4283a428d65f17ddc9fa1c08f8960) --- drivers/video/nxp/imx/imx8_lvds.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/video/nxp/imx/imx8_lvds.c b/drivers/video/nxp/imx/imx8_lvds.c index d9162dbbc2..87b0108838 100644 --- a/drivers/video/nxp/imx/imx8_lvds.c +++ b/drivers/video/nxp/imx/imx8_lvds.c @@ -80,6 +80,20 @@ static int imx8_ldb_soc_setup(struct udevice *dev, sc_pm_clock_rate_t pixel_cloc return -EIO; } + err = sc_pm_set_clock_parent(-1, lvds_rsrc, SC_PM_CLK_PER, SC_PM_PARENT_BYPS); + if (err) { + printf("LVDS set SC_PM_CLK_PER parent failed! (error = %d)\n", + err); + return -EIO; + } + + err = sc_pm_set_clock_parent(-1, lvds_rsrc, SC_PM_CLK_PHY, SC_PM_PARENT_BYPS); + if (err) { + printf("LVDS set SC_PM_CLK_PHY parent failed! (error = %d)\n", + err); + return -EIO; + } + err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_PER, &pixel_clock); if (err) { printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); -- cgit v1.2.3 From 88132ed0b4ee31a0940be96d13b1a65ac030869e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Sep 2022 16:05:02 +0800 Subject: LFU-396-1 video: simple_panel: make backlight optional Somes boards may default enable backlight and not able to set brightness, so make it optional. Signed-off-by: Peng Fan Reviewed-by: Ye Li (cherry picked from commit 928d56fcb5c540e5d8937473a74189a46f701ce3) --- drivers/video/simple_panel.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index c8f7022ea6..f9281d5e83 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -23,12 +23,14 @@ static int simple_panel_enable_backlight(struct udevice *dev) struct simple_panel_priv *priv = dev_get_priv(dev); int ret; - debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name); dm_gpio_set_value(&priv->enable, 1); - ret = backlight_enable(priv->backlight); - debug("%s: done, ret = %d\n", __func__, ret); - if (ret) - return ret; + if (priv->backlight) { + debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name); + ret = backlight_enable(priv->backlight); + debug("%s: done, ret = %d\n", __func__, ret); + if (ret) + return ret; + } return 0; } @@ -40,10 +42,12 @@ static int simple_panel_set_backlight(struct udevice *dev, int percent) debug("%s: start, backlight = '%s'\n", __func__, priv->backlight->name); dm_gpio_set_value(&priv->enable, 1); - ret = backlight_set_brightness(priv->backlight, percent); - debug("%s: done, ret = %d\n", __func__, ret); - if (ret) - return ret; + if (priv->backlight) { + ret = backlight_set_brightness(priv->backlight, percent); + debug("%s: done, ret = %d\n", __func__, ret); + if (ret) + return ret; + } return 0; } @@ -66,9 +70,10 @@ static int simple_panel_of_to_plat(struct udevice *dev) ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, "backlight", &priv->backlight); if (ret) { - debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); - return log_ret(ret); + printf("%s: Cannot get backlight: ret=%d\n", __func__, ret); + priv->backlight = NULL; } + ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, GPIOD_IS_OUT); if (ret) { -- cgit v1.2.3 From 21eb66fe1f81909d3f72940fdeb7085a06427118 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 16 Sep 2022 13:38:34 +0800 Subject: LFU-396-2 video: nxp: imx: dsi: force DISPLAY_FLAGS_HSYNC_HIGH & DISPLAY_FLAGS_VSYNC_HIGH To i.MX93/8MP, the VSYNC/HSYNC Polarities are high, so set the timing flag: DISPLAY_FLAGS_HSYNC_HIGH & DISPLAY_FLAGS_VSYNC_HIGH in check_timing callback. Signed-off-by: Peng Fan Reviewed-by: Ye Li (cherry picked from commit 15eba93f742cb427a8808a05f9e800c1b2922f0e) --- drivers/video/nxp/imx/dw_dsi_imx.c | 4 ++++ drivers/video/nxp/imx/sec_dsim_imx.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/video/nxp/imx/dw_dsi_imx.c b/drivers/video/nxp/imx/dw_dsi_imx.c index cf65ec02e5..6bdd382621 100644 --- a/drivers/video/nxp/imx/dw_dsi_imx.c +++ b/drivers/video/nxp/imx/dw_dsi_imx.c @@ -349,6 +349,10 @@ static int dw_dsi_imx_check_timing(struct udevice *dev, struct display_timing *t return -ENOTCONN; } + /* DSI force the Polarities as high */ + priv->adj.flags &= ~(DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW); + priv->adj.flags |= DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH; + *timing = priv->adj; return 0; diff --git a/drivers/video/nxp/imx/sec_dsim_imx.c b/drivers/video/nxp/imx/sec_dsim_imx.c index 2e6aa467f7..9c6e7d2bca 100644 --- a/drivers/video/nxp/imx/sec_dsim_imx.c +++ b/drivers/video/nxp/imx/sec_dsim_imx.c @@ -32,6 +32,7 @@ struct imx_sec_dsim_priv { struct reset_ctl_bulk soft_resetn; struct reset_ctl_bulk clk_enable; struct reset_ctl_bulk mipi_reset; + struct display_timing adj; }; #if IS_ENABLED(CONFIG_DM_RESET) @@ -120,6 +121,8 @@ static int imx_sec_dsim_attach(struct udevice *dev) return ret; } + priv->adj = timings; + ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host); if (ret) { dev_err(dev, "No video dsi host detected %d\n", ret); @@ -209,9 +212,23 @@ static int imx_sec_dsim_remove(struct udevice *dev) return 0; } +static int imx_sec_dsim_check_timing(struct udevice *dev, struct display_timing *timing) +{ + struct imx_sec_dsim_priv *priv = dev_get_priv(dev); + + /* DSI force the Polarities as high */ + priv->adj.flags &= ~(DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW); + priv->adj.flags |= DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH; + + *timing = priv->adj; + + return 0; +} + struct video_bridge_ops imx_sec_dsim_ops = { .attach = imx_sec_dsim_attach, .set_backlight = imx_sec_dsim_set_backlight, + .check_timing = imx_sec_dsim_check_timing, }; static const struct udevice_id imx_sec_dsim_ids[] = { -- cgit v1.2.3 From 5f414738a5fbaa7a4a49a2d55c4e19851fdc3627 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Sep 2022 16:06:16 +0800 Subject: LFU-396-3 video: nxp: imx_lcdifv3: support VSYNC/HSYNC active low Default is active high, but some settings requires active low, so according to timing flags to set mode sync. If flags have DISPLAY_FLAGS_HSYNC_LOW and DISPLAY_FLAGS_VSYNC_LOW set, mode.sync will clear FB_SYNC_HOR_HIGH_ACT and FB_SYNC_VERT_HIGH_ACT, then INV_VS and INV_HS will be set to 1 Signed-off-by: Peng Fan Reviewed-by: Ye Li (cherry picked from commit 6f225600790b201c6c6f45a2ec640daed8dfe310) --- drivers/video/nxp/imx/imx_lcdifv3.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/video/nxp/imx/imx_lcdifv3.c b/drivers/video/nxp/imx/imx_lcdifv3.c index 8313e09848..66e6ad6a86 100644 --- a/drivers/video/nxp/imx/imx_lcdifv3.c +++ b/drivers/video/nxp/imx/imx_lcdifv3.c @@ -99,8 +99,15 @@ static void lcdifv3_set_mode(struct lcdifv3_priv *priv, writel(ctrldescl0_1, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_1)); /* Polarities */ - writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); - writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + if (mode->sync & FB_SYNC_VERT_HIGH_ACT) + writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + else + writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_SET)); + + if (mode->sync & FB_SYNC_HOR_HIGH_ACT) + writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + else + writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_SET)); /* SEC MIPI DSI specific */ writel(CTRL_INV_PXCK, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); @@ -316,7 +323,6 @@ static void lcdifv3_of_parse_thres(struct udevice *dev) } } - static int lcdifv3_video_probe(struct udevice *dev) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); @@ -377,6 +383,13 @@ static int lcdifv3_video_probe(struct udevice *dev) mode.hsync_len = timings.hsync_len.typ; mode.vsync_len = timings.vsync_len.typ; mode.pixclock = HZ2PS(timings.pixelclock.typ); + mode.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT; + + if (timings.flags & DISPLAY_FLAGS_HSYNC_LOW ) + mode.sync &= ~FB_SYNC_HOR_HIGH_ACT; + + if (timings.flags & DISPLAY_FLAGS_VSYNC_LOW ) + mode.sync &= ~FB_SYNC_VERT_HIGH_ACT; lcdifv3_init(dev, &mode, GDF_32BIT_X888RGB); -- cgit v1.2.3 From ef6a3d9cc38ec8e2635f0d8c000962ffbf76f9ac Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Sep 2022 16:13:44 +0800 Subject: LFU-396-4 video: nxp: imx: add Add i.MX93 parallel display format encoder driver i.MX93 MediaMix GPR contains the display_mux register to control parallel display format configuration. Add a video bridge driver for it. Signed-off-by: Peng Fan Reviewed-by: Ye Li (cherry picked from commit c8084a583054d439314d0cf2b9fa957cd6eb3352) --- drivers/video/nxp/imx/Kconfig | 7 + drivers/video/nxp/imx/Makefile | 1 + drivers/video/nxp/imx/imx93-parallel-disp-fmt.c | 166 ++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 drivers/video/nxp/imx/imx93-parallel-disp-fmt.c diff --git a/drivers/video/nxp/imx/Kconfig b/drivers/video/nxp/imx/Kconfig index 49455fac49..1824b969fb 100644 --- a/drivers/video/nxp/imx/Kconfig +++ b/drivers/video/nxp/imx/Kconfig @@ -123,3 +123,10 @@ config VIDEO_IMX_DCNANO help Support for i.MX8ULP DCNANO LCD controller. +config VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT + bool "Support for i.MX93 parallel display format" + select VIDEO_BRIDGE + select VIDEO_LINK + help + Choose this to enable the internal parallel display format + configuration found on i.MX93 processors. diff --git a/drivers/video/nxp/imx/Makefile b/drivers/video/nxp/imx/Makefile index 1d2035c63a..019789fe0c 100644 --- a/drivers/video/nxp/imx/Makefile +++ b/drivers/video/nxp/imx/Makefile @@ -15,4 +15,5 @@ obj-$(CONFIG_VIDEO_NW_MIPI_DSI) += mipi_dsi_northwest.o obj-$(CONFIG_VIDEO_IMX_NW_DSI) += nw_dsi_imx.o obj-$(CONFIG_VIDEO_IMX_DW_DSI) += dw_dsi_imx.o obj-$(CONFIG_VIDEO_IMX_DCNANO) += dcnano.o +obj-$(CONFIG_VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT) += imx93-parallel-disp-fmt.o obj-y += hdmi/ diff --git a/drivers/video/nxp/imx/imx93-parallel-disp-fmt.c b/drivers/video/nxp/imx/imx93-parallel-disp-fmt.c new file mode 100644 index 0000000000..72af93873f --- /dev/null +++ b/drivers/video/nxp/imx/imx93-parallel-disp-fmt.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DISPLAY_MUX_CTRL 0x60 +#define PARALLEL_DISP_FORMAT 0x700 + +enum imx93_pdf_format { + RGB888_TO_RGB888 = 0x0, + RGB888_TO_RGB666 = 0x1 << 8, + RGB565_TO_RGB565 = 0x2 << 8, +}; + +struct imx93_pdf_priv { + struct udevice *panel; + struct display_timing adj; + enum imx93_pdf_format format; + void *__iomem addr; +}; + +static int imx93_pdf_attach(struct udevice *dev) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + struct display_timing timings; + int ret; + + priv->panel = video_link_get_next_device(dev); + if (!priv->panel || + device_get_uclass_id(priv->panel) != UCLASS_PANEL) { + dev_err(dev, "get panel device error\n"); + return -ENODEV; + } + + ret = video_link_get_display_timings(&timings); + if (ret) { + dev_err(dev, "decode display timing error %d\n", ret); + return ret; + } + + priv->adj = timings; + + writel(priv->format, priv->addr + DISPLAY_MUX_CTRL); + + return 0; +} + +static int imx93_pdf_check_timing(struct udevice *dev, struct display_timing *timing) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + + /* Ensure the bridge device attached to panel */ + if (!priv->panel) { + dev_err(dev, "%s No panel device attached\n", __func__); + return -ENOTCONN; + } + + *timing = priv->adj; + + return 0; +} + +static int imx93_pdf_probe(struct udevice *dev) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + const char *fmt; + u32 bus_format; + int ret; + + priv->addr = (void __iomem *)dev_read_addr(dev_get_parent(dev)); + if ((fdt_addr_t)priv->addr == FDT_ADDR_T_NONE) { + dev_err(dev, "not able to get addr\n"); + return -EINVAL; + } + + ret = ofnode_read_string_index(dev_ofnode(dev), "fsl,interface-pix-fmt", 0, &fmt); + if (!ret) { + if (!strcmp(fmt, "rgb565")) + bus_format = MEDIA_BUS_FMT_RGB565_1X16; + else if (!strcmp(fmt, "rgb666")) + bus_format = MEDIA_BUS_FMT_RGB666_1X18; + else if (!strcmp(fmt, "rgb888")) + bus_format = MEDIA_BUS_FMT_RGB888_1X24; + + } + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB565_1X16: + priv->format = RGB565_TO_RGB565; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + priv->format = RGB888_TO_RGB666; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + priv->format = RGB888_TO_RGB888; + break; + default: + dev_dbg(dev, "invalid bus format 0x%x\n", bus_format); + return -EINVAL; + } + + + return 0; +} + +static int imx93_pdf_remove(struct udevice *dev) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + + if (priv->panel) + device_remove(priv->panel, DM_REMOVE_NORMAL); + + return 0; +} + +static int imx93_pdf_set_backlight(struct udevice *dev, int percent) +{ + struct imx93_pdf_priv *priv = dev_get_priv(dev); + int ret; + + ret = panel_enable_backlight(priv->panel); + if (ret) { + dev_err(dev, "panel %s enable backlight error %d\n", priv->panel->name, ret); + return ret; + } + + return 0; +} + +struct video_bridge_ops imx93_pdf_ops = { + .attach = imx93_pdf_attach, + .check_timing = imx93_pdf_check_timing, + .set_backlight = imx93_pdf_set_backlight, +}; + +static const struct udevice_id imx93_pdf_ids[] = { + { .compatible = "fsl,imx93-parallel-display-format" }, + { } +}; + +U_BOOT_DRIVER(imx93_pdf_driver) = { + .name = "imx93_pdf_driver", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = imx93_pdf_ids, + .bind = dm_scan_fdt_dev, + .remove = imx93_pdf_remove, + .probe = imx93_pdf_probe, + .ops = &imx93_pdf_ops, + .priv_auto = sizeof(struct imx93_pdf_priv), +}; -- cgit v1.2.3 From fffc330cf1a1309c552c8b84660a6e5de8ebe901 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 19 Sep 2022 11:22:35 +0800 Subject: LFU-396-5 imx9: clock: add 300MHz fracn pll table Add 300MHz freq for lower video pll settings Signed-off-by: Peng Fan Reviewed-by: Ye Li (cherry picked from commit 03ccdbf58acf3333801afe110c8371819346fdbb) --- arch/arm/mach-imx/imx9/clock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 7dc33941a9..6e31999fc0 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -39,6 +39,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ + FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), }; /* return in khz */ -- cgit v1.2.3 From 60e0e629f99b385f40d81389c0dc8d3141939028 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Sep 2022 16:17:34 +0800 Subject: LFU-396-6 arm: dts: add imx93 9x9 ontat panel dts Update SoC dtsi to include parrel display fmt Add lcdif pinmux Add new board dts Signed-off-by: Peng Fan Reviewed-by: Ye Li (cherry picked from commit 947b648496737e4dddde3a93e3d21fefc7d9c401) --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts | 65 +++++++++++++++++++++++++ arch/arm/dts/imx93-9x9-qsb.dts | 27 ++++++++++ arch/arm/dts/imx93.dtsi | 24 +++++++++ 4 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f036e54186..fada5f1275 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1005,7 +1005,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ dtb-$(CONFIG_ARCH_IMX9) += \ imx93-11x11-evk.dtb \ - imx93-9x9-qsb.dtb + imx93-9x9-qsb.dtb \ + imx93-9x9-qsb-ontat-wvga-panel.dts dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts new file mode 100644 index 0000000000..6eb09ec9e3 --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-ontat-wvga-panel.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + */ + +#include "imx93-9x9-qsb.dts" +#include "imx93-9x9-qsb-u-boot.dtsi" + +/ { + panel { + compatible = "ontat,kd50g21-40nt-a1", "simple-panel"; + enable-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <48>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + + vsync-active = <0>; + hsync-active = <0>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; + /*assigned-clock-rates = <150000000>, <30000000>, <400000000>, <133333333>;*/ +}; + +¶llel_disp_fmt { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + fsl,interface-pix-fmt = "rgb666"; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +/* pin conflicts */ +&sai3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx93-9x9-qsb.dts b/arch/arm/dts/imx93-9x9-qsb.dts index 29c244ad5b..cfb91c9884 100644 --- a/arch/arm/dts/imx93-9x9-qsb.dts +++ b/arch/arm/dts/imx93-9x9-qsb.dts @@ -600,4 +600,31 @@ MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e >; }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; }; diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi index 59a09b5ec5..8314ca4c1b 100644 --- a/arch/arm/dts/imx93.dtsi +++ b/arch/arm/dts/imx93.dtsi @@ -1332,6 +1332,25 @@ power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>; status = "disabled"; }; + + parallel_disp_fmt: dpi { + compatible = "fsl,imx93-parallel-display-format"; + /* power-domains = <&mediamix>; [Not enable for U-Boot], otherwise driver probe fail */ + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_to_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dpi>; + }; + }; + }; + }; }; ldb: ldb@4ac10020 { @@ -1447,6 +1466,11 @@ reg = <1>; remote-endpoint = <&ldb_ch0>; }; + + lcdif_to_dpi: endpoint@2 { + reg = <2>; + remote-endpoint = <&dpi_to_lcdif>; + }; }; }; -- cgit v1.2.3 From 4881ba99fa4efa2edd8a7b8f95f85ea48d9858ba Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 15 Sep 2022 16:18:57 +0800 Subject: LFU-396-7 imx93_9x9_qsp_defconfig: support splash screen Enable video config to support splash screen Signed-off-by: Peng Fan Reviewed-by: Ye Li (cherry picked from commit 919d29f2bd0264e84abed6b40d9363a7b24eb7d3) --- configs/imx93_9x9_qsb_defconfig | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 2a4611d8cf..16dd825ce3 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -14,7 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_IMX_CONFIG="" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-9x9-qsb" +CONFIG_DEFAULT_DEVICE_TREE="imx93-9x9-qsb-ontat-wvga-panel" CONFIG_SPL_TEXT_BASE=0x2049A000 CONFIG_USB_TCPC=y CONFIG_TARGET_IMX93_9X9_QSB=y @@ -153,5 +153,18 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_POWER_DOMAIN=y CONFIG_IMX93_BLK_CTRL=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SIMPLE_PANEL=y +CONFIG_VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT=y + CONFIG_CMD_DEKBLOB=y CONFIG_IMX_ELE_DEK_ENCAP=y -- cgit v1.2.3 From fab973fe1dfcb514793e0653a897e022add4f33a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 20 Sep 2022 12:24:34 +0800 Subject: LFU-397 imx8m: clock: not configure reserved SRC register i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it. Reviewed-by: Ye Li Signed-off-by: Peng Fan (cherry picked from commit 78d7ccda83f729d7f7b5f4b731a6d35764cdc402) --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d6be307e6e..203c52d1d3 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -83,7 +83,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) case ANATOP_DRAM_PLL: setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7); setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5); - writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004); pll_base = &ana_pll->dram_pll_gnrl_ctl; break; -- cgit v1.2.3 From c45c4fb791b0de7059c38a4447716edf399dda7f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 14:06:40 +0800 Subject: LFU-398-1 DTS: imx93: Update flexspi node in DTSi Update flexspi clocks relevant properties and add alias for flexspi Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 271d114e751814488cad885be17da313d8a9079d) --- arch/arm/dts/imx93.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi index 8314ca4c1b..1ace98274b 100644 --- a/arch/arm/dts/imx93.dtsi +++ b/arch/arm/dts/imx93.dtsi @@ -36,6 +36,7 @@ serial5 = &lpuart6; serial6 = &lpuart7; serial7 = &lpuart8; + spi0 = &flexspi; isi0 = &isi_0; i2c0 = &lpi2c1; i2c1 = &lpi2c2; @@ -498,7 +499,7 @@ #thermal-sensor-cells = <0>; status = "disabled"; }; - + micfil: micfil@44520000 { compatible = "fsl,imx93-micfil"; reg = <0x44520000 0x10000>; @@ -848,9 +849,11 @@ reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; status = "disabled"; }; -- cgit v1.2.3 From b6cbe6b1416d9baced047597d186bd9d71ddd838 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 14:08:14 +0800 Subject: LFU-398-2 DTS: imx93-11x11-evk: Enable and update flexspi NOR Enable the flexspi NOR in DTS, and correct the NOR flash and pinctrl settings to adapt M.2 QSPI NOR board design which uses 4 I/O data pins. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 8f1cedf1ecc36622d310ba26b401ed0f5530dbe1) --- arch/arm/dts/imx93-11x11-evk.dts | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts index 38bf2aeb99..c82e5a9c67 100644 --- a/arch/arm/dts/imx93-11x11-evk.dts +++ b/arch/arm/dts/imx93-11x11-evk.dts @@ -458,16 +458,16 @@ &flexspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi>; - status = "disabled"; + status = "okay"; - flash0: flash@0 { + flash0: mt25qu512a@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; @@ -485,17 +485,11 @@ pinctrl_flexspi: flexspigrp { fsl,pins = < MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 - MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42 MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 - MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42 MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 - MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42 - MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42 - MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42 - MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42 >; }; -- cgit v1.2.3 From c56f2132d53b4a6fbbafd27e54bb07c79f5e3a9e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 14:12:00 +0800 Subject: LFU-398-3 imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST VPCIe_3V3 is used to supply the power to M.2 card, we must enable it before using the flash. The SD3_nRST is connected to reset pin of flash, must deassert (pull up) it. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit cbd24cd503366f7c657afbaab03b0c85610298e2) --- board/freescale/imx93_evk/imx93_evk.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index e8db920200..02eaffe396 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -19,6 +19,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -251,6 +252,36 @@ static int setup_eqos(void) return set_clk_eqos(ENET_125MHZ); } +static void board_gpio_init(void) +{ + struct gpio_desc desc; + int ret; + + /* Enable EXT1_PWREN for PCIE_3.3V */ + ret = dm_gpio_lookup_name("gpio@22_13", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "EXT1_PWREN"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); + + /* Deassert SD3_nRST */ + ret = dm_gpio_lookup_name("gpio@22_12", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "SD3_nRST"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); +} + int board_init(void) { #ifdef CONFIG_USB_TCPC @@ -263,6 +294,8 @@ int board_init(void) if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) setup_eqos(); + board_gpio_init(); + return 0; } -- cgit v1.2.3 From d9f563336f7df8571d57de2dcd1560af4f73c031 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 16:58:16 +0800 Subject: LFU-398-4 imx93_11x11_evk: Enable Flexspi NOR support Enable flexspi drivers and relevant configs to support FSPI NOR Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 2c61cee4236a5d50d076627d32b4e3ce484ead0f) --- configs/imx93_11x11_evk_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 0d2d135b6a..3b869101dd 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -87,6 +87,14 @@ CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + CONFIG_CMD_FASTBOOT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_UUU_SUPPORT=y -- cgit v1.2.3 From ba4f72198f500ace451f714ee90ccb50e8ba6b9f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 17:31:29 +0800 Subject: LFU-398-5 DTS: imx93-9x9-qsb: Add flexspi NOR nodes and pinctrl Add the flexspi NOR node and its pinctrl setting to 9x9 QSB DTS to support M.2 QSPI NOR card. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit e56a523df5372ab432a58a9f0383086cbec27ba0) --- arch/arm/dts/imx93-9x9-qsb.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/dts/imx93-9x9-qsb.dts b/arch/arm/dts/imx93-9x9-qsb.dts index cfb91c9884..accb295c03 100644 --- a/arch/arm/dts/imx93-9x9-qsb.dts +++ b/arch/arm/dts/imx93-9x9-qsb.dts @@ -178,6 +178,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: mt25qu512a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &lpi2c1 { #address-cells = <1>; #size-cells = <0>; @@ -487,6 +503,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42 + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42 + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42 + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42 + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42 + >; + }; + pinctrl_lpi2c1: lpi2c1grp { fsl,pins = < MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e -- cgit v1.2.3 From 1f500a5967001ddfa72680b2711b6ae2b0110006 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 17:33:37 +0800 Subject: LFU-398-6 imx93_qsb: Enable M.2 VPCIe_3V3 and deassert SD3_nRST VPCIe_3V3 is used to supply the power to M.2 card, we must enable it before using the flash. The SD3_nRST is connected to reset pin of flash, must deassert (pull up) it. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit de9747a36721c2bb19a3f5ac5c3da3e580c78010) --- board/freescale/imx93_qsb/imx93_qsb.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c index 9d6115afd8..b5cb2709fc 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.c +++ b/board/freescale/imx93_qsb/imx93_qsb.c @@ -19,6 +19,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -213,6 +214,36 @@ static int setup_eqos(void) return set_clk_eqos(ENET_125MHZ); } +static void board_gpio_init(void) +{ + struct gpio_desc desc; + int ret; + + /* Enable EXT1_PWREN for PCIE_3.3V */ + ret = dm_gpio_lookup_name("gpio@22_13", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "EXT1_PWREN"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); + + /* Deassert SD3_nRST */ + ret = dm_gpio_lookup_name("gpio@22_12", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "SD3_nRST"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); +} + int board_init(void) { #ifdef CONFIG_USB_TCPC @@ -222,6 +253,8 @@ int board_init(void) if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) setup_eqos(); + board_gpio_init(); + return 0; } -- cgit v1.2.3 From d8760a747935588255c9bacce635d348ce800754 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 17:34:45 +0800 Subject: LFU-398-7 imx93_9x9_qsb: Enable Flexspi NOR support Enable flexspi drivers and relevant configs to support FSPI NOR Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 0843cc8c9a508d2cf8be61e6f728c6e7b71c60ff) --- configs/imx93_9x9_qsb_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 16dd825ce3..6d990e22fa 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -87,6 +87,14 @@ CONFIG_SYSCON=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + CONFIG_CMD_FASTBOOT=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_UUU_SUPPORT=y -- cgit v1.2.3 From 48a2221acc9fd03de1373d5f44a75c9b8b3ac00a Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 14 Sep 2022 17:18:02 +0800 Subject: LFU-395 imx93: Add fused parts support According to datasheet, iMX93 has fused parts with CORE1 or NPU or both disabled. Update the SOC codes to support such parts and disable/remove nodes from kernel DTB for fused modules. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit d23f6cda69a572c42d9cc480787ad70a129d1a2e) --- arch/arm/include/asm/arch-imx/cpu.h | 7 ++ arch/arm/include/asm/mach-imx/sys_proto.h | 11 +- arch/arm/mach-imx/imx9/soc.c | 161 +++++++++++++++++++++++++++++- 3 files changed, 176 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index f326c90312..36f51e0792 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -62,6 +62,13 @@ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_CPU_IMX93 0xC1 /* dummy ID */ +#define MXC_CPU_IMX9351 0xC2 /* dummy ID */ +#define MXC_CPU_IMX9332 0xC3 /* dummy ID */ +#define MXC_CPU_IMX9331 0xC4 /* dummy ID */ +#define MXC_CPU_IMX9322 0xC5 /* dummy ID */ +#define MXC_CPU_IMX9321 0xC6 /* dummy ID */ +#define MXC_CPU_IMX9312 0xC7 /* dummy ID */ +#define MXC_CPU_IMX9311 0xC8 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 57557db715..04505d948c 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -84,7 +84,16 @@ struct bd_info; #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL)) -#define is_imx93() (is_cpu_type(MXC_CPU_IMX93)) +#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \ + is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || is_cpu_type(MXC_CPU_IMX9322) || \ + is_cpu_type(MXC_CPU_IMX9321) || is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311)) +#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351)) +#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332)) +#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331)) +#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322)) +#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321)) +#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312)) +#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311)) #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 66200dbe3c..03b9018739 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -160,10 +160,33 @@ static void set_cpu_info(struct sentinel_get_info_data *info) memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); } +static u32 get_cpu_variant_type(u32 type) +{ + /* word 19 */ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2)); + bool npu_disable = !!(val & BIT(13)); + bool core1_disable = !!(val & BIT(15)); + u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24); + + if ((val2 & pack_9x9_fused) == pack_9x9_fused) + type = MXC_CPU_IMX9322; + + if (npu_disable && core1_disable) + return type + 3; + else if (npu_disable) + return type + 2; + else if (core1_disable) + return type + 1; + + return type; +} + u32 get_cpu_rev(void) { u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; - return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev); + return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) | + (CHIP_REV_1_0 + rev); } #define UNLOCK_WORD 0xD928C520 /* unlock word */ @@ -315,13 +338,38 @@ err: printf("%s: fuse read err: %d\n", __func__, ret); } +const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX93: + return "93(52)";/* iMX93 Dual core with NPU */ + case MXC_CPU_IMX9351: + return "93(51)";/* iMX93 Single core with NPU */ + case MXC_CPU_IMX9332: + return "93(32)";/* iMX93 Dual core without NPU */ + case MXC_CPU_IMX9331: + return "93(31)";/* iMX93 Single core without NPU */ + case MXC_CPU_IMX9322: + return "93(22)";/* iMX93 9x9 Dual core */ + case MXC_CPU_IMX9321: + return "93(21)";/* iMX93 9x9 Single core */ + case MXC_CPU_IMX9312: + return "93(12)";/* iMX93 9x9 Dual core without NPU */ + case MXC_CPU_IMX9311: + return "93(11)";/* iMX93 9x9 Single core without NPU */ + default: + return "??"; + } +} + int print_cpuinfo(void) { u32 cpurev; cpurev = get_cpu_rev(); - printf("CPU: i.MX93 rev%d.%d at %d MHz\n", + printf("CPU: i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0x1FF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); @@ -333,8 +381,117 @@ int arch_misc_init(void) return 0; } +static int delete_fdt_nodes(void *blob, const char *const nodes_path[], int size_array) +{ + int i = 0; + int rc; + int nodeoff; + + for (i = 0; i < size_array; i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path[i]); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path[i], fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path[i]); + } + } + + return 0; +} + +static int disable_npu_nodes(void *blob) +{ + static const char * const nodes_path_npu[] = { + "/ethosu", + "/reserved-memory/ethosu_region@C0000000" + }; + + return delete_fdt_nodes(blob, nodes_path_npu, ARRAY_SIZE(nodes_path_npu)); +} + +static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores) +{ + static const char * const thermal_path[] = { + "/thermal-zones/cpu-thermal/cooling-maps/map0" + }; + + int nodeoff, cnt, i, ret, j; + u32 cooling_dev[6]; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 6); + if (cnt < 0) + continue; + + if (cnt != 6) + printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt); + + for (j = 0; j < cnt; j++) + cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]); + + ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, + sizeof(u32) * (6 - disabled_cores * 3)); + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + continue; + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static int disable_cpu_nodes(void *blob, u32 disabled_cores) +{ + u32 i = 0; + int rc; + int nodeoff; + char nodes_path[32]; + + for (i = 1; i <= disabled_cores; i++) { + + sprintf(nodes_path, "/cpus/cpu@%u00", i); + + nodeoff = fdt_path_offset(blob, nodes_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path, fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path); + } + } + + disable_thermal_cpu_nodes(blob, disabled_cores); + + return 0; +} + int ft_system_setup(void *blob, struct bd_info *bd) { + if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311()) + disable_cpu_nodes(blob, 1); + + if (is_imx9332() || is_imx9331() || is_imx9312() || is_imx9311()) + disable_npu_nodes(blob); + + return ft_add_optee_node(blob, bd); } -- cgit v1.2.3 From 53f06207782013e9dc36a5bd25810628fe66a419 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 15:39:40 +0800 Subject: LFU-399 imx8ulp: Reconfigure MRC3 for SRAM0 access Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode access only for boot purpose. Since SW will reuse the SRAM0 as SCMI buffer and SPL container loading buffer, need to reconfigure MRC3. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit ebfac7540de520b97724d3fd2d5918b4b56327b1) --- arch/arm/mach-imx/imx8ulp/rdc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index 66225c0a6a..f5423ec7b9 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -276,6 +276,21 @@ void xrdc_init_mda(void) void xrdc_init_mrc(void) { + /* Re-config MRC3 for SRAM0 in case protected by S400 */ + xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000); + xrdc_config_mrc_dx_perm(3, 0, 0, 1); + xrdc_config_mrc_dx_perm(3, 0, 1, 1); + xrdc_config_mrc_dx_perm(3, 0, 4, 1); + xrdc_config_mrc_dx_perm(3, 0, 5, 1); + xrdc_config_mrc_dx_perm(3, 0, 6, 1); + xrdc_config_mrc_dx_perm(3, 0, 7, 1); + xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF); + + /* Clear other 3 regions of MRC3 to invalid */ + xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0); + xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0); + xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0); + /* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */ xrdc_config_mrc_w0_w1(4, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); xrdc_config_mrc_dx_perm(4, 0, 1, 1); -- cgit v1.2.3 From 432a4af96087cf9e71543bb3d9fc01be12989cd7 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 20 Sep 2022 16:19:09 +0800 Subject: LFU-400 imx8ulp: clock: Clear dividers in PLL3DIV_PFD registers At present, in cgc1_pll3_init we don't set the pll3pfd div values, just use the default 0. But when MROM-3029 is applied, ROM will set PLL3 pfd1div2 to 1 and pfd2div1 to 3. This finally causes some clocks' rate decreased, for example USDHC. So clear the PLL3DIV_PFD dividers to get correct rate. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 91eb5a47b996b531c5fda5e421d35f54f486c548) --- arch/arm/mach-imx/imx8ulp/cgc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index 3913b17051..d3c0e64cd6 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq) while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30))) ; + clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f); + clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f); + clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23)); -- cgit v1.2.3 From e4722baa5afdac1cf63db78c02553389175943fd Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 21 Sep 2022 10:08:49 +0800 Subject: LFU-402-1 iMX93: soc: Get market segment and speed grading Get the chip's market segment and speed grading from fuse and print them in boot log like other i.MX series. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 1226b8cbd8da7b3e2520db9bac0197886725bec2) --- arch/arm/mach-imx/imx9/soc.c | 84 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 80 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 03b9018739..55550bd109 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -32,6 +32,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -153,6 +154,56 @@ int board_usb_gadget_port_auto(void) } #endif +u32 get_cpu_speed_grade_hz(void) +{ + u32 speed, max_speed; + u32 grade; + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + val >>= 6; + val &= 0xf; + + speed = 2300000000 - val * 100000000; + + if (is_imx93()) { + grade = get_cpu_temp_grade(NULL, NULL); + if (grade == TEMP_INDUSTRIAL) + max_speed = 1500000000; + else + max_speed = 1700000000; + + /* In case the fuse of speed grade not programmed */ + if (speed > max_speed) + speed = max_speed; + } + + return speed; +} + +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2)); + + val >>= 4; + val &= 0x3; + + if (minc && maxc) { + if (val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + *minc = -20; + *maxc = 105; + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} + static void set_cpu_info(struct sentinel_get_info_data *info) { gd->arch.soc_rev = info->soc; @@ -364,14 +415,39 @@ const char *get_imx_type(u32 imxtype) int print_cpuinfo(void) { - u32 cpurev; + u32 cpurev, max_freq; + int minc, maxc; cpurev = get_cpu_rev(); - printf("CPU: i.MX%s rev%d.%d at %d MHz\n", + printf("CPU: i.MX%s rev%d.%d", get_imx_type((cpurev & 0x1FF000) >> 12), - (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, - mxc_get_clock(MXC_ARM_CLK) / 1000000); + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); + + max_freq = get_cpu_speed_grade_hz(); + if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) { + printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000); + } else { + printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + } + + puts("CPU: "); + switch (get_cpu_temp_grade(&minc, &maxc)) { + case TEMP_AUTOMOTIVE: + puts("Automotive temperature grade "); + break; + case TEMP_INDUSTRIAL: + puts("Industrial temperature grade "); + break; + case TEMP_EXTCOMMERCIAL: + puts("Extended Consumer temperature grade "); + break; + default: + puts("Consumer temperature grade "); + break; + } + printf("(%dC to %dC)\n", minc, maxc); return 0; } -- cgit v1.2.3 From 401b9824f92e2ab772caf048757ce1176b1dfaca Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 21 Sep 2022 10:11:59 +0800 Subject: LFU-402-2 iMX93: clock: Add API to set max ARM core clock Add a new API to set max ARM core clock that should be aligned with speed grading. For iMX93, the max speed is 1.7Ghz for Consumer and Auto, 1.5Ghz for Industrial. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 318a1354e3392075b5be6db7bd0cd642027c8daf) --- arch/arm/include/asm/arch-imx9/clock.h | 1 + arch/arm/mach-imx/imx9/clock.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index 5cb762d429..758ee26ff2 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -217,6 +217,7 @@ u32 mxc_get_clock(enum mxc_clock clk); void dram_pll_init(ulong pll_val); void dram_enable_bypass(ulong clk_val); void dram_disable_bypass(void); +void set_arm_core_max_clk(void); int configure_intpll(enum ccm_clk_src pll, u32 freq); diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 6e31999fc0..62f2f1b93b 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; static struct imx_intpll_rate_table imx9_intpll_tbl[] = { INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */ INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */ + INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */ INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */ INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */ INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */ @@ -540,6 +541,18 @@ u32 get_arm_core_clk(void) return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT); } +void set_arm_core_max_clk(void) +{ + u32 speed; + + /* Increase ARM clock to max rate according to speed grade */ + speed = get_cpu_speed_grade_hz(); + + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, speed); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { -- cgit v1.2.3 From 78749666dd336b14e53abe824b26f41b8e45cb90 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 21 Sep 2022 10:17:05 +0800 Subject: LFU-402-3 imx93_evk/qsb: Use API to set max ARM clock Replace the codes with the new API to set max ARM clock. The API will align the max clock with speed grading fuse. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 6f41fcc451448dc607d70314a45c6bb29f637fb3) --- board/freescale/imx93_evk/spl.c | 5 +---- board/freescale/imx93_qsb/spl.c | 5 +---- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index e0a9df1e5a..8a9fd6c0cd 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -107,10 +107,7 @@ void board_init_f(ulong dummy) } power_init_board(); - /* Increase ARM clock to 1.7Ghz */ - ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); - configure_intpll(ARM_PLL_CLK, 1700000000); /* 1.7Ghz */ - ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); + set_arm_core_max_clk(); /* Init power of mix */ soc_power_init(); diff --git a/board/freescale/imx93_qsb/spl.c b/board/freescale/imx93_qsb/spl.c index 0b7b88f01a..a91bdabc4a 100644 --- a/board/freescale/imx93_qsb/spl.c +++ b/board/freescale/imx93_qsb/spl.c @@ -109,10 +109,7 @@ void board_init_f(ulong dummy) } power_init_board(); - /* Increase ARM clock to 1.7Ghz */ - ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); - configure_intpll(ARM_PLL_CLK, 1700000000); /* 1.7Ghz */ - ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); + set_arm_core_max_clk(); /* Init power of mix */ soc_power_init(); -- cgit v1.2.3 From 91e711a565ccbceab63811e53c5ec5f7211448c2 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 21 Sep 2022 10:58:24 +0800 Subject: LFU-403-1 thermal: imx_tmu: Update TMU driver to support iMX93 The TMU used on iMX93 is IP revision 2.1 which is different with previous revision used on iMX8MQ. So add a new FLAG V4 for this revision to distinguish the operations. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 761ab8136adbb1201b1e72a1d9e915d3069ff5cf) --- drivers/thermal/Kconfig | 6 +-- drivers/thermal/imx_tmu.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 8666d67483..6274640c41 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -27,10 +27,10 @@ config IMX_SCU_THERMAL trip is crossed config IMX_TMU - bool "Thermal Management Unit driver for NXP i.MX8M" - depends on ARCH_IMX8M + bool "Thermal Management Unit driver for NXP i.MX8M and iMX93" + depends on ARCH_IMX8M || IMX93 help - Support for Temperature sensors on NXP i.MX8M. + Support for Temperature sensors on NXP i.MX8M and iMX93. It supports one critical trip point and one passive trip point. The boot is hold to the cool device to throttle CPUs when the passive trip is crossed diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index ca45abbb8e..893e674455 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -24,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SITES_MAX 16 #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 +#define FLAGS_VER4 0x4 #define TMR_DISABLE 0x0 #define TMR_ME 0x80000000 @@ -75,6 +76,46 @@ struct imx_tmu_regs { u32 ttr3cr; /* Temperature Range 3 Control Register */ }; +struct imx_tmu_regs_v4 { + u32 tmr; /* Mode Register */ + u32 tsr; /* Status Register */ + u32 tmsr; /* Monitor Site Register */ + u32 tmtmir; /* Temperature measurement interval Register */ + u8 res0[0x10]; + u32 tier; /* Interrupt Enable Register */ + u32 tidr; /* Interrupt Detect Register */ + u8 res1[0x8]; + u32 tiiscr; /* Interrupt Immediate Site Capture Register */ + u32 tiascr; /* Interrupt Average Site Capture Register */ + u32 ticscr; /* Interrupt Critical Site Capture Register */ + u8 res2[0x4]; + u32 tmhtcr; /* Monitor High Temperature Capture Register */ + u32 tmltcr; /* MonitorLow Temperature Capture Register */ + u32 tmrtrcr; /* Monitor Rising Temperature Rate Capture Register */ + u32 tmftrcr; /* Monitor Falling Temperature Rate Capture Register */ + u32 tmhtitr; /* Monitor High Temperature Immediate Threshold */ + u32 tmhtatr; /* Monitor High Temperature Average Threshold */ + u32 tmhtactr; /* Monitor High Temperature Average Crit Threshold */ + u8 res3[0x4]; + u32 tmltitr; /* Monitor Low Temperature Immediate Threshold */ + u32 tmltatr; /* Monitor Low Temperature Average Threshold */ + u32 tmltactr; /* Monitor Low Temperature Average Crit Threshold */ + u8 res4[0x4]; + u32 tmrtrctr; /* Monitor Rising Temperature Rate Critical Threshold Register */ + u32 tmftrctr; /* Monitor Falling Temperature Rate Critical Threshold Register */ + u8 res5[0x8]; + u32 ttcfgr; /* Temperature Configuration Register */ + u32 tscfgr; /* Sensor Configuration Register */ + u8 res6[0x78]; + u32 tritsr0; /* Immediate Temperature Site Register */ + u32 tratsr0; /* Average Temperature Site Register */ + u8 res7[0xdf8]; + u32 tcmcfg; /* Central Module Configuration */ + u8 res8[0xc]; + u32 ttrcr[16]; /* Temperature Range Control Register */ +}; + + struct imx_tmu_regs_v2 { u32 ter; /* TMU enable Register */ u32 tsr; /* Status Register */ @@ -114,6 +155,7 @@ union tmu_regs { struct imx_tmu_regs regs_v1; struct imx_tmu_regs_v2 regs_v2; struct imx_tmu_regs_v3 regs_v3; + struct imx_tmu_regs_v4 regs_v4; }; struct imx_tmu_plat { @@ -147,6 +189,9 @@ static int read_temperature(struct udevice *dev, int *temp) * only reflects the RAW uncalibrated data */ valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1; + } else if (drv_data & FLAGS_VER4) { + val = readl(&pdata->regs->regs_v4.tritsr0); + valid = val & 0x80000000; } else { val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr); valid = val & 0x80000000; @@ -164,6 +209,13 @@ static int read_temperature(struct udevice *dev, int *temp) return -EINVAL; *temp *= 1000; + } else if (drv_data & FLAGS_VER4) { + *temp = (val & 0x1ff) * 1000; + if (val & 0x200) + *temp += 500; + + /* Convert Kelvin to Celsius */ + *temp -= 273000; } else { *temp = (val & 0xff) * 1000; } @@ -215,6 +267,26 @@ static int imx_tmu_calibration(struct udevice *dev) if (drv_data & (FLAGS_VER2 | FLAGS_VER3)) return 0; + if (drv_data & FLAGS_VER4) { + int index; + calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len); + if (!calibration || len % 8 || len > 128) { + printf("TMU: invalid calibration data.\n"); + return -ENODEV; + } + + for (i = 0; i < len; i += 8, calibration += 2) { + index = i / 8; + writel(index, &pdata->regs->regs_v4.ttcfgr); + val = fdt32_to_cpu(*calibration); + writel(val, &pdata->regs->regs_v4.tscfgr); + val = fdt32_to_cpu(*(calibration + 1)); + writel((1 << 31) | val, &pdata->regs->regs_v4.ttrcr[index]); + } + + return 0; + } + ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4); if (ret) { printf("TMU: missing calibration range, ret = %d.\n", ret); @@ -267,6 +339,15 @@ static void imx_tmu_init(struct udevice *dev) /* Disable interrupt, using polling instead */ writel(0x0, &pdata->regs->regs_v2.tier); + } else if (drv_data & FLAGS_VER4) { + /* Disable monitoring */ + writel(TMR_DISABLE, &pdata->regs->regs_v4.tmr); + + /* Disable interrupt, using polling instead */ + writel(TIER_DISABLE, &pdata->regs->regs_v4.tier); + + /* Set update_interval */ + writel(TMTMIR_DEFAULT, &pdata->regs->regs_v4.tmtmir); } else { /* Disable monitoring */ writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr); @@ -319,6 +400,22 @@ static int imx_tmu_enable_msite(struct udevice *dev) /* Enable monitor */ reg |= TER_EN; writel(reg, &pdata->regs->regs_v2.ter); + } else if (drv_data & FLAGS_VER4) { + reg = readl(&pdata->regs->regs_v4.tcmcfg); + reg |= (1 << 30) | (1 << 28); + reg &= ~0xF000; /* set SAR clk = IPG clk /16 */ + writel(reg, &pdata->regs->regs_v4.tcmcfg); + + /* Set ALPF*/ + reg = readl(&pdata->regs->regs_v4.tmr); + reg |= TMR_ALPF; + writel(reg, &pdata->regs->regs_v4.tmr); + + writel(1, &pdata->regs->regs_v4.tmsr); + + /* Enable ME */ + reg |= TMR_ME; + writel(reg, &pdata->regs->regs_v4.tmr); } else { /* Clear the ME before setting MSITE and ALPF*/ reg = readl(&pdata->regs->regs_v1.tmr); @@ -460,6 +557,7 @@ static const struct udevice_id imx_tmu_ids[] = { { .compatible = "fsl,imx8mq-tmu", }, { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, }, { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, }, + { .compatible = "fsl,imx93-tmu", .data = FLAGS_VER4, }, { } }; -- cgit v1.2.3 From 050a94e6365e5dba5aa8456a71559b13663dd29e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 21 Sep 2022 11:19:16 +0800 Subject: LFU-403-2 DTS: imx93: Update TMU node to sync with kernel Enable the TMU node, update calibration data and remove iMX8MQ compatible string since the TMU revision is different and not compatble. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit f417c996eabe1727a9c190b0b5e3f3298591f2c7) --- arch/arm/dts/imx93.dtsi | 56 ++++++++----------------------------------------- 1 file changed, 9 insertions(+), 47 deletions(-) diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi index 1ace98274b..be4626d5e7 100644 --- a/arch/arm/dts/imx93.dtsi +++ b/arch/arm/dts/imx93.dtsi @@ -448,56 +448,18 @@ }; tmu: tmu@44482000 { - compatible = "fsl,imx93-tmu", "fsl,imx8mq-tmu"; - little-endian; + compatible = "fsl,imx93-tmu"; reg = <0x44482000 0x1000>; clocks = <&clk IMX93_CLK_TMC_GATE>; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000035 - 0x00000004 0x0000003d - 0x00000005 0x00000043 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005f - 0x0000000a 0x00000067 - 0x0000000b 0x0000006f - - 0x00010000 0x0000001b - 0x00010001 0x00000023 - 0x00010002 0x0000002b - 0x00010003 0x00000033 - 0x00010004 0x0000003b - 0x00010005 0x00000043 - 0x00010006 0x0000004b - 0x00010007 0x00000055 - 0x00010008 0x0000005d - 0x00010009 0x00000067 - 0x0001000a 0x00000070 - - 0x00020000 0x00000017 - 0x00020001 0x00000023 - 0x00020002 0x0000002d - 0x00020003 0x00000037 - 0x00020004 0x00000041 - 0x00020005 0x0000004b - 0x00020006 0x00000057 - 0x00020007 0x00000063 - 0x00020008 0x0000006f - - 0x00030000 0x00000015 - 0x00030001 0x00000021 - 0x00030002 0x0000002d - 0x00030003 0x00000039 - 0x00030004 0x00000045 - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; + little-endian; + fsl,tmu-calibration = <0x0000000e 0x800000da + 0x00000029 0x800000e9 + 0x00000056 0x80000102 + 0x000000a2 0x8000012a + 0x00000116 0x80000166 + 0x00000195 0x800001a7 + 0x000001b2 0x800001b6>; #thermal-sensor-cells = <0>; - status = "disabled"; }; micfil: micfil@44520000 { -- cgit v1.2.3 From e1703ec06a487c682291d79bf5a465b7a24b093d Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 21 Sep 2022 11:21:58 +0800 Subject: LFU-403-3 iMX93: soc: print current CPU temperature Probe the TMU device and print CPU temperature in boot log Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit 81c0d42a590abaffc9dc7bee570c5d14803d820b) --- arch/arm/mach-imx/imx9/soc.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 55550bd109..8d7780a71e 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -33,6 +33,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -447,7 +448,25 @@ int print_cpuinfo(void) puts("Consumer temperature grade "); break; } - printf("(%dC to %dC)\n", minc, maxc); + printf("(%dC to %dC)", minc, maxc); + +#if defined(CONFIG_IMX_TMU) + struct udevice *udev; + int ret, temp; + + ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal", &udev); + if (!ret) { + ret = thermal_get_temp(udev, &temp); + + if (!ret) + printf(" at %dC", temp); + else + debug(" - invalid sensor data\n"); + } else { + debug(" - invalid sensor device\n"); + } +#endif + puts("\n"); return 0; } -- cgit v1.2.3 From 19c3fdebf8d179cbdedd7b4ce72943d6e8525b3a Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 21 Sep 2022 11:26:04 +0800 Subject: LFU-403-4 imx93_evk/qsb: Enable TMU sensor driver Enable TMU sensor driver on iMX93 boards' defconfigs Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit de014b071446cd1479255549e37d81ef642626c0) --- configs/imx93_11x11_evk_defconfig | 2 ++ configs/imx93_9x9_qsb_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 3b869101dd..d023253959 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -181,3 +181,5 @@ CONFIG_CMD_BMP=y CONFIG_CMD_DEKBLOB=y CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 6d990e22fa..7177527f4a 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -176,3 +176,5 @@ CONFIG_VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT=y CONFIG_CMD_DEKBLOB=y CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y -- cgit v1.2.3 From a95afe08769db2773637ef115d06227f015cd0e0 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 27 Sep 2022 15:39:41 +0800 Subject: LF-7238 imx9: soc: Remove OPTEE memory from DRAM bank and MMU Since OPTEE memory will be protected by ATF to secure access only. We need to remove it from u-boot DRAM banks and MMU table, then the memory will not be used by both u-boot and kernel. Signed-off-by: Ye Li Reviewed-by: Peng Fan (cherry picked from commit c140827845b2ee1de2c2aa6f7df77d2825062996) --- arch/arm/mach-imx/imx9/soc.c | 150 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 8d7780a71e..11220799ae 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -337,13 +337,161 @@ static struct mm_region imx93_mem_map[] = { struct mm_region *mem_map = imx93_mem_map; +static unsigned int imx9_find_dram_entry_in_mem_map(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx93_mem_map); i++) + if (imx93_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + return i; + + hang(); /* Entry not found, this must never happen. */ +} + +void enable_caches(void) +{ + /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch + * If OPTEE does not run, still update the MMU table according to dram banks structure + * to set correct dram size from board_phys_sdram_size + */ + int i = 0; + /* + * please make sure that entry initial value matches + * imx93_mem_map for DRAM1 + */ + int entry = imx9_find_dram_entry_in_mem_map(); + u64 attrs = imx93_mem_map[entry].attrs; + + while (i < CONFIG_NR_DRAM_BANKS && + entry < ARRAY_SIZE(imx93_mem_map)) { + if (gd->bd->bi_dram[i].start == 0) + break; + imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; + imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].attrs = attrs; + debug("Added memory mapping (%d): %llx %llx\n", entry, + imx93_mem_map[entry].phys, imx93_mem_map[entry].size); + i++; entry++; + } + + icache_enable(); + dcache_enable(); +} + +__weak int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = PHYS_SDRAM_SIZE; + +#ifdef PHYS_SDRAM_2_SIZE + *size += PHYS_SDRAM_2_SIZE; +#endif + return 0; +} + int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; + phys_size_t sdram_size; + int ret; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = sdram_size - rom_pointer[1]; + else + gd->ram_size = sdram_size; + + return 0; +} + +int dram_init_banksize(void) +{ + int bank = 0; + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size, sdram_b2_size; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x80000000; + sdram_b2_size = sdram_size - 0x80000000; + } else { + sdram_b1_size = sdram_size; + sdram_b2_size = 0; + } + + gd->bd->bi_dram[bank].start = PHYS_SDRAM; + if (rom_pointer[1]) { + phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; + phys_size_t optee_size = (size_t)rom_pointer[1]; + + gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough\n"); + return -1; + } + + gd->bd->bi_dram[bank].start = optee_start + optee_size; + gd->bd->bi_dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->bd->bi_dram[bank].start; + } + } else { + gd->bd->bi_dram[bank].size = sdram_b1_size; + } + + if (sdram_b2_size) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); + return -1; + } + gd->bd->bi_dram[bank].start = 0x100000000UL; + gd->bd->bi_dram[bank].size = sdram_b2_size; + } return 0; } +phys_size_t get_effective_memsize(void) +{ + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size; + ret = board_phys_sdram_size(&sdram_size); + if (!ret) { + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x80000000; + } else { + sdram_b1_size = sdram_size; + } + + if (rom_pointer[1]) { + /* We will relocate u-boot to Top of dram1. Tee position has two cases: + * 1. At the top of dram1, Then return the size removed optee size. + * 2. In the middle of dram1, return the size of dram1. + */ + if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size)) + return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); + } + + return sdram_b1_size; + } else { + return PHYS_SDRAM_SIZE; + } +} + + void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { u32 val[2] = {}; -- cgit v1.2.3 From 8731024fe7e5c1db85a8da728661577200b95044 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Thu, 29 Sep 2022 12:32:29 +0800 Subject: LFU-406 mx6ul/mx6ulz: Fix build break caused by RNG patch Fix build break of issue "undefined reference to `dm_rng_read'" on 6UL and 6ULZ. which is introduced by commit 8789f3c (PLATSEC-1781-2 MX6: Device tree fix-up) Signed-off-by: Ye Li Reviewed-by: Kshitiz Varshney --- arch/arm/mach-imx/mx6/module_fuse.c | 70 ++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 6e3cc8b46c..19780b64a5 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -305,45 +305,49 @@ add_status: } } - /*Random number generation through RNG driver*/ - struct udevice *dev; - void *buf; - char keys[2][16] = {"otp_crypto_key", "otp_unique_key"}; - int ret = 0; - int nodeoff = fdt_path_offset(blob, "/soc/bus@2200000/crypto@2280000"); + if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) { + /*Random number generation through RNG driver*/ + struct udevice *dev; + void *buf; + char keys[2][16] = {"otp_crypto_key", "otp_unique_key"}; + int ret = 0; + int nodeoff = fdt_path_offset(blob, "/soc/bus@2200000/crypto@2280000"); - if (nodeoff < 0) { - printf("node to update the SoC serial number is not found.\n"); - return nodeoff; - } - rc = uclass_get_device(UCLASS_RNG, 0, &dev); - if (rc || !dev) { - printf("No RNG device\n"); - return rc; - } - - buf = malloc(16); - if (!buf) { - printf("Out of memory\n"); - return -ENOMEM; - } + if (nodeoff < 0) { + printf("node to update the SoC serial number is not found.\n"); + return nodeoff; + } + rc = uclass_get_device(UCLASS_RNG, 0, &dev); + if (rc || !dev) { + printf("No RNG device\n"); + return rc; + } - for (int i = 0; i < 2; i++) { - ret = dm_rng_read(dev, buf, 16); - if (ret) { - printf("Reading RNG failed\n"); - goto err; + buf = malloc(16); + if (!buf) { + printf("Out of memory\n"); + return -ENOMEM; } - ret = fdt_setprop(blob, nodeoff, keys[i], buf, 16); - if (ret < 0) { - printf("WARNING: could not set %s key handle %s.\n", keys[i], fdt_strerror(ret)); - goto err; + for (int i = 0; i < 2; i++) { + ret = dm_rng_read(dev, buf, 16); + if (ret) { + printf("Reading RNG failed\n"); + goto err; + } + + ret = fdt_setprop(blob, nodeoff, keys[i], buf, 16); + if (ret < 0) { + printf("WARNING: could not set %s key handle %s.\n", keys[i], fdt_strerror(ret)); + goto err; + } } - } err: - free(buf); - return ret; + free(buf); + return ret; + } + + return 0; } #endif -- cgit v1.2.3 From a8fef10ab929dcaf736b413b6f8f04213cd070e6 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 4 Jul 2022 10:29:12 +0800 Subject: LFU-407-01 configs: imx93: Update spl stack & bss base address As the ddr timing info will be saved at the last 16KB of the OCRAM, spl stack & bss base should be updated to avoid conflict. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Reviewed-by: Ye Li --- include/configs/imx93_evk.h | 4 ++-- include/configs/imx93_qsb.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 31ee667ee6..0816a50df6 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -18,8 +18,8 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x2051ddd0 -#define CONFIG_SPL_BSS_START_ADDR 0x2051e000 +#define CONFIG_SPL_STACK 0x20519dd0 +#define CONFIG_SPL_BSS_START_ADDR 0x2051a000 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x83200000 /* Need disable simple malloc where still uses malloc_f area */ #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h index 7a0600fd76..4a6a321568 100644 --- a/include/configs/imx93_qsb.h +++ b/include/configs/imx93_qsb.h @@ -18,8 +18,8 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x2051ddd0 -#define CONFIG_SPL_BSS_START_ADDR 0x2051e000 +#define CONFIG_SPL_STACK 0x20519dd0 +#define CONFIG_SPL_BSS_START_ADDR 0x2051a000 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x83200000 /* Need disable simple malloc where still uses malloc_f area */ #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ -- cgit v1.2.3 From 25e38cb476274678877b98d407566e81a8f2838e Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Wed, 29 Jun 2022 10:18:51 +0800 Subject: LFU-407-02 ddr: imx9: Change the saved ddr data base to 0x2051c000 change the ddr saved info to the last 16KB of the OCRAM. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Reviewed-by: Ye Li --- drivers/ddr/imx/imx9/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index 123ad173cf..b1795eec35 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -22,6 +22,6 @@ config SAVED_DRAM_TIMING_BASE help after DRAM is trained, need to save the dram related timming info into memory for low power use. - default 0x204DC000 + default 0x2051C000 endmenu -- cgit v1.2.3 From bb45dd592dbb50fe522e5e70bc8cd8c722418ba3 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 29 Sep 2022 01:31:41 +0800 Subject: LFU-408 imx93evk: config the pmic standby voltage for buck1 Per the datasheet, the VDD_SOC voltage can be set to typical 0.65V when system enter sys_sleep mode(PMIC_standby signal HIGH), so add this support. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Reviewed-by: Ye Li --- board/freescale/imx93_evk/spl.c | 6 ++++++ board/freescale/imx93_qsb/spl.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 8a9fd6c0cd..2d2900c6e0 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -67,11 +67,17 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + /* 0.9v */ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + /* set standby voltage to 0.65v */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + /* I2C_LT_EN*/ pmic_reg_write(dev, 0xa, 0x3); diff --git a/board/freescale/imx93_qsb/spl.c b/board/freescale/imx93_qsb/spl.c index a91bdabc4a..952854cc65 100644 --- a/board/freescale/imx93_qsb/spl.c +++ b/board/freescale/imx93_qsb/spl.c @@ -67,10 +67,16 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + /* 0.9v: for LPDDR4X 3722 */ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + /* set standby voltage to 0.65v */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + /* 1.1v for LPDDR4 */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); -- cgit v1.2.3 From beb5e5e330337e2beb015e72fd61ce566e76c5ae Mon Sep 17 00:00:00 2001 From: Ji Luo Date: Wed, 21 Sep 2022 20:56:39 +0800 Subject: MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default on A1 chip, when DBD_EN is fused and HAB closed, the TRDC was owned by S400 and the ATF space (SSRAM) would be locked (RW only) before HAB verify, which would cause boot hang if we don't enable CONFIG_AHAB_BOOT by default. This commit enables CONFIG_AHAB_BOOT by default, so the execution permission on SSRAM would be added on HAB closed board. Signed-off-by: Ji Luo --- configs/imx8ulp_9x9_evk_android_defconfig | 1 + configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig | 1 + configs/imx8ulp_9x9_evk_android_uuu_defconfig | 1 + configs/imx8ulp_evk_android_defconfig | 1 + configs/imx8ulp_evk_android_dual_defconfig | 1 + configs/imx8ulp_evk_android_trusty_defconfig | 1 + configs/imx8ulp_evk_android_trusty_dual_defconfig | 1 + configs/imx8ulp_evk_android_uuu_defconfig | 1 + 8 files changed, 8 insertions(+) diff --git a/configs/imx8ulp_9x9_evk_android_defconfig b/configs/imx8ulp_9x9_evk_android_defconfig index 939de54bac..7f326aacf1 100644 --- a/configs/imx8ulp_9x9_evk_android_defconfig +++ b/configs/imx8ulp_9x9_evk_android_defconfig @@ -148,3 +148,4 @@ CONFIG_ANDROID_AB_SUPPORT=y CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig index 2154d9ad67..6dc7a0d6cf 100644 --- a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig @@ -155,3 +155,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_9x9_evk_android_uuu_defconfig b/configs/imx8ulp_9x9_evk_android_uuu_defconfig index d816b90bb9..860e5f1d36 100644 --- a/configs/imx8ulp_9x9_evk_android_uuu_defconfig +++ b/configs/imx8ulp_9x9_evk_android_uuu_defconfig @@ -143,3 +143,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_defconfig b/configs/imx8ulp_evk_android_defconfig index b944e8cc6b..df603245f0 100644 --- a/configs/imx8ulp_evk_android_defconfig +++ b/configs/imx8ulp_evk_android_defconfig @@ -148,3 +148,4 @@ CONFIG_ANDROID_AB_SUPPORT=y CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_dual_defconfig b/configs/imx8ulp_evk_android_dual_defconfig index 84f31a638d..1fef689c74 100644 --- a/configs/imx8ulp_evk_android_dual_defconfig +++ b/configs/imx8ulp_evk_android_dual_defconfig @@ -149,3 +149,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_trusty_defconfig b/configs/imx8ulp_evk_android_trusty_defconfig index c6e2378b82..5e54aca9d7 100644 --- a/configs/imx8ulp_evk_android_trusty_defconfig +++ b/configs/imx8ulp_evk_android_trusty_defconfig @@ -154,3 +154,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp" CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_trusty_dual_defconfig b/configs/imx8ulp_evk_android_trusty_dual_defconfig index 1f345e8d1f..93ca30df1d 100644 --- a/configs/imx8ulp_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_evk_android_trusty_dual_defconfig @@ -155,3 +155,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8ulp_evk_android_uuu_defconfig b/configs/imx8ulp_evk_android_uuu_defconfig index 966f40d169..e8e5f12685 100644 --- a/configs/imx8ulp_evk_android_uuu_defconfig +++ b/configs/imx8ulp_evk_android_uuu_defconfig @@ -143,3 +143,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_AHAB_BOOT=y -- cgit v1.2.3 From 32965eb52f780e55ea1a46697ac95b4fbe011c89 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 13 Sep 2022 14:15:22 +0800 Subject: LFU-392 imx8ulp: upower: replace magic number with macro The swton indicates the logic switch, magic number 0xfff80 is hard to understand, so use macro. Some board design may not have MIPI_CSI/DSI voltage input connected per data sheet. In that case, the upower power on api may dead loop mu to wait response, however there is no response. So remove MIPI_CSI/DSI here, let linux power domain driver to runtime enable the power domain. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c index 87152ca818..7770beeecb 100644 --- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c @@ -14,6 +14,24 @@ #define UPOWER_AP_MU1_ADDR 0x29280000 +#define PS_RTD BIT(0) +#define PS_DSP BIT(1) +#define PS_A35_0 BIT(2) +#define PS_A35_1 BIT(3) +#define PS_L2 BIT(4) +#define PS_FAST_NIC BIT(5) +#define PS_APD_PERIPH BIT(6) +#define PS_GPU3D BIT(7) +#define PS_HIFI4 BIT(8) +#define PS_DDR GENMASK(12, 9) +#define PS_PXP_EPDC BIT(13) +#define PS_MIPI_DSI BIT(14) +#define PS_MIPI_CSI BIT(15) +#define PS_NIC_LPAV BIT(16) +#define PS_FUSION_AO BIT(17) +#define PS_FUSE BIT(18) +#define PS_UPOWER BIT(19) + static struct MU_tag *muptr = (struct MU_tag *)UPOWER_AP_MU1_ADDR; extern void upwr_txrx_isr(void); @@ -156,7 +174,8 @@ int upower_init(void) } } while(0); - swton = 0xfff80; + swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR | + PS_HIFI4 | PS_GPU3D; ret = upwr_pwm_power_on(&swton, NULL /* no memories */, NULL /* no callback */); if (ret) printf("Turn on switches fail %d\n", ret); -- cgit v1.2.3 From 5703d3ae37e0cb9f23b117d915610b736b2fa97f Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 9 Oct 2022 14:28:57 +0800 Subject: LFU-411 imx8ulp: Always enable MIPI_DSI power switch Due to the errata ERR051067, the MIPI DSI power switch must be on for HIFI4. ATF has set ALWAYS_ON flag to DSI PS as workaround, so we must enable it in SPL, otherwise DSI PS can't be enabled by SCMI PD calling. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c index 7770beeecb..965a444e77 100644 --- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c @@ -175,7 +175,7 @@ int upower_init(void) } while(0); swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR | - PS_HIFI4 | PS_GPU3D; + PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI; ret = upwr_pwm_power_on(&swton, NULL /* no memories */, NULL /* no callback */); if (ret) printf("Turn on switches fail %d\n", ret); -- cgit v1.2.3 From 266dddae454a9cc95f0ee08da423f63c030f9d64 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 Oct 2022 09:32:43 +0800 Subject: LFU-412 configs: imx93_evk: shrink mem= for jailhouse After remove the optee memory bank, there is an 32MB hole. So mem=1280MB should decrease to mem=1248MB. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- include/configs/imx93_evk.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 0816a50df6..ea89c10c78 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -51,11 +51,11 @@ #define JAILHOUSE_ENV \ "jh_mmcboot=setenv fdtfile imx93-11x11-evk-root.dtb; " \ - "setenv jh_clk clk_ignore_unused mem=1280MB kvm-arm.mode=nvhe; " \ + "setenv jh_clk clk_ignore_unused mem=1248MB kvm-arm.mode=nvhe; " \ "if run loadimage; then run mmcboot;" \ "else run jh_netboot; fi; \0" \ "jh_netboot=setenv fdtfile imx93-11x11-evk-root.dtb; " \ - "setenv jh_clk clk_ignore_unused mem=1280MB kvm-arm.mode=nvhe; run netboot; \0 " + "setenv jh_clk clk_ignore_unused mem=1248MB kvm-arm.mode=nvhe; run netboot; \0 " #define CONFIG_MFG_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS_DEFAULT \ -- cgit v1.2.3 From 63d0579f39778e835bdf13da8e42fceb929f5604 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 5 Sep 2022 13:14:00 +0800 Subject: LFU-410 imx: ele_ahab: Add ahab_sec_fuse_prog command Add ahab_sec_fuse_prog command to support burn secure fuse, for example the system ROM patch. Before running the command, user needs to sign the fuse container in format mentioned in ELE API and have loaded the container to specified address passed to ahab_sec_fuse_prog Signed-off-by: Ye Li Acked-by: Peng Fan --- arch/arm/include/asm/mach-imx/s400_api.h | 2 ++ arch/arm/mach-imx/ele_ahab.c | 39 ++++++++++++++++++++++++++++++++ drivers/misc/sentinel/s400_api.c | 31 +++++++++++++++++++++++++ 3 files changed, 72 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h index 539b1d16bb..3862c5a39b 100644 --- a/arch/arm/include/asm/mach-imx/s400_api.h +++ b/arch/arm/include/asm/mach-imx/s400_api.h @@ -147,4 +147,6 @@ int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response); int ahab_start_rng(void); int ahab_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size); +int ahab_write_secure_fuse(ulong signed_msg_blk, u32 *response); + #endif diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 6daa7a96a0..192f90e6b1 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -568,6 +568,39 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr; + u32 header, response; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + header = *(u32 *)addr; + + if ((header & 0xff0000ff) != 0x89000000) { + printf("Wrong Signed message block format, header 0x%x\n", header); + return CMD_RET_FAILURE; + } + + header = (header & 0xffff00) >> 8; + + printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header); + flush_dcache_range(addr, addr + header - 1); + + if (ahab_write_secure_fuse(addr, &response)) { + printf("Program secure fuse failed, response 0x%x\n", response); + return CMD_RET_FAILURE; + } + + printf("Program secure fuse completed, response 0x%x\n", response); + + return CMD_RET_SUCCESS; +} + + U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, "autenticate OS container via AHAB", "addr\n" @@ -588,3 +621,9 @@ U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status, "display AHAB lifecycle only", "" ); + +U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog, + "Program secure fuse via signed message block", + "addr\n" + "addr - Signed message block for secure fuse\n" +); diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c index 8ac17890b4..baab9b2c9b 100644 --- a/drivers/misc/sentinel/s400_api.c +++ b/drivers/misc/sentinel/s400_api.c @@ -561,3 +561,34 @@ int ahab_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, return ret; } + +int ahab_write_secure_fuse(ulong signed_msg_blk, u32 *response) +{ + struct udevice *dev = gd->arch.s400_dev; + int size = sizeof(struct sentinel_msg); + struct sentinel_msg msg; + int ret; + + if (!dev) { + printf("s400 dev is not initialized\n"); + return -ENODEV; + } + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 3; + msg.command = ELE_WRITE_SECURE_FUSE_REQ; + + msg.data[0] = upper_32_bits(signed_msg_blk); + msg.data[1] = lower_32_bits(signed_msg_blk); + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x, failed fuse row index %u\n", + __func__, ret, msg.data[0], msg.data[1]); + + if (response) + *response = msg.data[0]; + + return ret; +} -- cgit v1.2.3 From aa4ebb661997ebe2db491693ee4a690adf20402c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 10 Oct 2022 14:40:22 +0800 Subject: LFU-414 imx8ulp: clock: Update clocks to meet max rate restrictions Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency restrictions. Detail clock rate changes in the patch: PLL3 PFD2: 389M -> 324M PLL3 PFD3: 336M -> 389M PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD) PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD) PLL4 PFD0: 792M -> 594M PLL4 PFD2: 792M -> 316.8M NIC_AP: 96M (ND) -> 192M, 48M (LD) -> 96M NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M USDHC0: PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD) USDHC1: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) USDHC2: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/cgc.c | 69 +++++++++++++++++++++------------------ arch/arm/mach-imx/imx8ulp/clock.c | 50 +++++++++++----------------- 2 files changed, 57 insertions(+), 62 deletions(-) diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index d3c0e64cd6..b19268c822 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -136,42 +136,34 @@ void cgc1_pll3_init(ulong freq) clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7)); clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F); - - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0); - clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */ - } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0); - clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */ - } else { - setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */ - } - + setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* PFD0 324M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8); - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8); + setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8); /* PFD1 389M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16); - setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16); + setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 16); /* PFD2 324M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22))) ; clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24); - setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24); + setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 24); /* PFD3 389M */ clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31)); while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30))) ; clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f); - clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f); - + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) + clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x03010000); /* Set PFD3 DIV1 to 194M, PFD3 DIV2 to 97M */ + else + clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x01000000); /* Set PFD3 DIV1 to 389M, PFD3 DIV2 to 194M */ clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15)); clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23)); @@ -182,6 +174,17 @@ void cgc1_pll3_init(ulong freq) clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23)); clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31)); + /* NIC_AP: + * OD source PLL3 PFD0, 324M + * ND source FRO192, 192M + * LD source FRO192, 96M + */ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); + } else { + clrbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21)); + } + if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28)); /* nicclk select pll3 pfd0 */ while (!(readl(&cgc1_regs->nicclk) & BIT(27))) @@ -221,18 +224,9 @@ void cgc2_pll4_init(bool pll4_reset) /* Enable all 4 PFDs */ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */ - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21); /* 99Mhz for NIC_LPAV */ - } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21); /* 198Mhz for NIC_LPAV */ - } else { - setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */ - clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21)); - } - setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */ - setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 16); /* 316.8Mhz */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396Mhz */ clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31)); @@ -244,9 +238,22 @@ void cgc2_pll4_init(bool pll4_reset) clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31)); clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31)); - clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28)); - while (!(readl(&cgc2_regs->niclpavclk) & BIT(27))) - ; + /* NIC_LPAV: + * OD source PLL4 PFD1, 316.8M + * ND source FRO192, 192M + * LD source FRO192, 96M + */ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21); + } else { + clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21)); + } + + if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { + clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28)); + while (!(readl(&cgc2_regs->niclpavclk) & BIT(27))) + ; + } } void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd) diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 2898c8b96c..17dff404fb 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -183,37 +183,20 @@ void clock_init_late(void) */ cgc1_pll3_init(540672000); - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2); - pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); - } else { - pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); - - pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); - } + pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD3_DIV1); /* 389M for OD, 194M for LD/ND*/ + pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND */ + pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND*/ + pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); /* enable MU0_MUB clock before access the register of MU0_MUB */ pcc_clock_enable(3, MU0_B_PCC3_SLOT, true); @@ -432,6 +415,8 @@ void reset_lcdclk(void) pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true); } +/* PLL4 PFD0 max frequency */ +#define PLL4_PFD0_MAX_RATE 600000 /*khz*/ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) { u8 pcd, best_pcd = 0; @@ -450,6 +435,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) for (div = 1; div <= 64; div++) { parent_rate = pll4_rate; parent_rate = parent_rate * 18 / pfd; + if (parent_rate > PLL4_PFD0_MAX_RATE) + continue; + parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) { -- cgit v1.2.3 From 97fc905e7f7344fb9c2ca3c861348b2b110a51d6 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Thu, 29 Sep 2022 16:03:47 -0500 Subject: LFU-409: imx8dxl: fix the i.MX8DXL ddr3l NAND DQS iomux setting The DQS signal for NAND on i.MX8DXL ddr3l should come from USDHC1_CD_B rather than EMMC0_CMD. The information on A1 schematic is wrong. Signed-off-by: Han Xu Reviewed-by: Frank Li (cherry picked from commit 611d71fa8de07ae6a99c7d3bf809091236ceac27) --- arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts | 2 +- board/freescale/imx8dxl_evk/imx8dxl_evk.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts index 040e52912e..3fe19b9848 100644 --- a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts +++ b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts @@ -100,8 +100,8 @@ SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c - SC_P_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c SC_P_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c SC_P_USDHC1_WP_CONN_NAND_ALE 0x0e00004c SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c diff --git a/board/freescale/imx8dxl_evk/imx8dxl_evk.c b/board/freescale/imx8dxl_evk/imx8dxl_evk.c index 55f1e1ee77..2acfd5dc96 100644 --- a/board/freescale/imx8dxl_evk/imx8dxl_evk.c +++ b/board/freescale/imx8dxl_evk/imx8dxl_evk.c @@ -69,8 +69,8 @@ static iomux_cfg_t gpmi_nand_pads[] = { SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), - SC_P_EMMC0_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_USDHC1_RESET_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_USDHC1_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), -- cgit v1.2.3 From 933a3b25fe32be454a79f58376e3b54ef8ffb96b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 26 Sep 2022 14:20:53 -0500 Subject: LF-7234 enable CONFIG_CMD_CRC32 and CONFIG_CRC32_VERIFY uuu can use crc command check burned image integrity Signed-off-by: Frank Li Reviewed-by: Ye Li (cherry picked from commit 44278536f1ddc9f6fca4e753c9f739c2aae77b0e) --- configs/imx8dx_17x17_val_defconfig | 3 ++- configs/imx8dx_mek_defconfig | 3 ++- configs/imx8dx_mek_fspi_defconfig | 3 ++- configs/imx8dxl_ddr3l_evk_defconfig | 3 ++- configs/imx8dxl_ddr3l_evk_fspi_defconfig | 3 ++- configs/imx8dxl_ddr3l_evk_nand_defconfig | 3 ++- configs/imx8dxl_evk_defconfig | 3 ++- configs/imx8dxl_evk_fspi_defconfig | 3 ++- configs/imx8dxl_evk_lcd_defconfig | 3 ++- configs/imx8dxl_phantom_mek_defconfig | 3 ++- configs/imx8dxl_phantom_mek_fspi_defconfig | 3 ++- configs/imx8mm_ddr3l_val_defconfig | 3 ++- configs/imx8mm_ddr4_ab2_defconfig | 3 ++- configs/imx8mm_ddr4_evk_defconfig | 3 ++- configs/imx8mm_ddr4_evk_nand_defconfig | 3 ++- configs/imx8mm_ddr4_val_defconfig | 3 ++- configs/imx8mm_evk_defconfig | 3 ++- configs/imx8mm_evk_fspi_defconfig | 3 ++- configs/imx8mn_ab2_defconfig | 3 ++- configs/imx8mn_ddr3l_ab2_defconfig | 3 ++- configs/imx8mn_ddr3l_evk_defconfig | 3 ++- configs/imx8mn_ddr4_ab2_defconfig | 3 ++- configs/imx8mn_ddr4_evk_defconfig | 3 ++- configs/imx8mn_ddr4_evk_ld_defconfig | 3 ++- configs/imx8mn_evk_defconfig | 3 ++- configs/imx8mn_evk_ld_defconfig | 3 ++- configs/imx8mp_ddr4_evk_defconfig | 3 ++- configs/imx8mp_ddr4_evk_inline_ecc_defconfig | 3 ++- configs/imx8mp_ddr4_evk_nand_defconfig | 3 ++- configs/imx8mp_evk_defconfig | 3 ++- configs/imx8mp_evk_inline_ecc_defconfig | 3 ++- configs/imx8mp_evk_ndm_defconfig | 3 ++- configs/imx8mq_ddr3l_val_defconfig | 3 ++- configs/imx8mq_ddr4_val_defconfig | 3 ++- configs/imx8mq_ddr4_val_nand_defconfig | 3 ++- configs/imx8mq_evk_defconfig | 3 ++- configs/imx8qm_ddr4_val_defconfig | 3 ++- configs/imx8qm_lpddr4_val_defconfig | 3 ++- configs/imx8qm_lpddr4_val_fspi_defconfig | 3 ++- configs/imx8qm_mek_cockpit_a53_defconfig | 3 ++- configs/imx8qm_mek_defconfig | 3 ++- configs/imx8qm_mek_fspi_defconfig | 3 ++- configs/imx8qm_mek_trusty_xen_defconfig | 3 ++- configs/imx8qxp_17x17_val_defconfig | 3 ++- configs/imx8qxp_ddr3_val_defconfig | 3 ++- configs/imx8qxp_lpddr4_val_defconfig | 3 ++- configs/imx8qxp_lpddr4_val_fspi_defconfig | 3 ++- configs/imx8qxp_lpddr4_val_nand_defconfig | 3 ++- configs/imx8qxp_mek_defconfig | 3 ++- configs/imx8qxp_mek_fspi_defconfig | 3 ++- configs/imx8ulp_9x9_evk_defconfig | 1 + configs/imx8ulp_9x9_evk_i3c_defconfig | 1 + configs/imx8ulp_evk_defconfig | 1 + configs/imx8ulp_evk_i3c_defconfig | 1 + configs/imx8ulp_evk_nd_defconfig | 1 + configs/imx93_11x11_evk_defconfig | 3 ++- configs/imx93_9x9_qsb_defconfig | 3 ++- configs/mx6dlsabreauto_defconfig | 2 ++ configs/mx6dlsabreauto_eimnor_defconfig | 2 ++ configs/mx6dlsabreauto_nand_defconfig | 2 ++ configs/mx6dlsabreauto_optee_defconfig | 2 ++ configs/mx6dlsabreauto_plugin_defconfig | 2 ++ configs/mx6dlsabreauto_spinor_defconfig | 2 ++ configs/mx6dlsabresd_defconfig | 2 ++ configs/mx6dlsabresd_epdc_defconfig | 2 ++ configs/mx6dlsabresd_optee_defconfig | 2 ++ configs/mx6dlsabresd_plugin_defconfig | 2 ++ configs/mx6qpsabreauto_defconfig | 2 ++ configs/mx6qpsabreauto_eimnor_defconfig | 2 ++ configs/mx6qpsabreauto_nand_defconfig | 2 ++ configs/mx6qpsabreauto_optee_defconfig | 2 ++ configs/mx6qpsabreauto_plugin_defconfig | 2 ++ configs/mx6qpsabreauto_sata_defconfig | 2 ++ configs/mx6qpsabreauto_spinor_defconfig | 2 ++ configs/mx6qpsabresd_defconfig | 2 ++ configs/mx6qpsabresd_optee_defconfig | 2 ++ configs/mx6qpsabresd_sata_defconfig | 2 ++ configs/mx6qsabreauto_defconfig | 2 ++ configs/mx6qsabreauto_eimnor_defconfig | 2 ++ configs/mx6qsabreauto_nand_defconfig | 2 ++ configs/mx6qsabreauto_optee_defconfig | 2 ++ configs/mx6qsabreauto_plugin_defconfig | 2 ++ configs/mx6qsabreauto_sata_defconfig | 2 ++ configs/mx6qsabreauto_spinor_defconfig | 2 ++ configs/mx6qsabrelite_defconfig | 2 ++ configs/mx6qsabresd_defconfig | 2 ++ configs/mx6qsabresd_optee_defconfig | 2 ++ configs/mx6qsabresd_plugin_defconfig | 2 ++ configs/mx6qsabresd_sata_defconfig | 2 ++ configs/mx6sabreauto_defconfig | 2 ++ configs/mx6sabresd_defconfig | 2 ++ configs/mx6slevk_defconfig | 2 ++ configs/mx6slevk_epdc_defconfig | 2 ++ configs/mx6slevk_optee_defconfig | 2 ++ configs/mx6slevk_plugin_defconfig | 2 ++ configs/mx6slevk_spinor_defconfig | 2 ++ configs/mx6slevk_spl_defconfig | 2 ++ configs/mx6sll_lpddr2_val_defconfig | 2 ++ configs/mx6sll_lpddr3_val_defconfig | 2 ++ configs/mx6sll_lpddr3_val_epdc_defconfig | 2 ++ configs/mx6sll_lpddr3_val_plugin_defconfig | 2 ++ configs/mx6sll_lpddr3_val_spinor_defconfig | 2 ++ configs/mx6sllevk_defconfig | 2 ++ configs/mx6sllevk_epdc_defconfig | 2 ++ configs/mx6sllevk_optee_defconfig | 2 ++ configs/mx6sllevk_plugin_defconfig | 2 ++ configs/mx6solosabreauto_defconfig | 2 ++ configs/mx6solosabreauto_eimnor_defconfig | 2 ++ configs/mx6solosabreauto_nand_defconfig | 2 ++ configs/mx6solosabreauto_optee_defconfig | 2 ++ configs/mx6solosabreauto_spinor_defconfig | 2 ++ configs/mx6solosabresd_defconfig | 2 ++ configs/mx6solosabresd_optee_defconfig | 2 ++ configs/mx6sx_14x14_lpddr2_val_defconfig | 2 ++ configs/mx6sx_14x14_lpddr2_val_nand_defconfig | 2 ++ configs/mx6sx_14x14_lpddr2_val_plugin_defconfig | 2 ++ configs/mx6sx_17x17_val_defconfig | 2 ++ configs/mx6sx_17x17_val_eimnor_defconfig | 2 ++ configs/mx6sx_17x17_val_nand_defconfig | 2 ++ configs/mx6sx_17x17_val_plugin_defconfig | 2 ++ configs/mx6sx_17x17_val_qspi2_defconfig | 2 ++ configs/mx6sx_17x17_val_spinor_defconfig | 2 ++ configs/mx6sx_17x17wp_val_defconfig | 2 ++ configs/mx6sx_19x19_ddr3_val_defconfig | 2 ++ configs/mx6sx_19x19_ddr3_val_eimnor_defconfig | 2 ++ configs/mx6sx_19x19_ddr3_val_nand_defconfig | 2 ++ configs/mx6sx_19x19_ddr3_val_plugin_defconfig | 2 ++ configs/mx6sx_19x19_ddr3_val_qspi2_defconfig | 2 ++ configs/mx6sx_19x19_ddr3_val_spinor_defconfig | 2 ++ configs/mx6sx_19x19_lpddr2_val_defconfig | 2 ++ configs/mx6sx_19x19_lpddr2_val_plugin_defconfig | 2 ++ configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig | 2 ++ configs/mx6sxsabreauto_defconfig | 2 ++ configs/mx6sxsabreauto_nand_defconfig | 2 ++ configs/mx6sxsabreauto_optee_defconfig | 2 ++ configs/mx6sxsabreauto_plugin_defconfig | 2 ++ configs/mx6sxsabreauto_qspi1_defconfig | 2 ++ configs/mx6sxsabresd_defconfig | 2 ++ configs/mx6sxsabresd_emmc_defconfig | 2 ++ configs/mx6sxsabresd_m4fastup_defconfig | 2 ++ configs/mx6sxsabresd_optee_defconfig | 2 ++ configs/mx6sxsabresd_plugin_defconfig | 2 ++ configs/mx6sxsabresd_qspi2_defconfig | 2 ++ configs/mx6ul_14x14_ddr3_val_defconfig | 2 ++ configs/mx6ul_14x14_ddr3_val_eimnor_defconfig | 2 ++ configs/mx6ul_14x14_ddr3_val_emmc_defconfig | 2 ++ configs/mx6ul_14x14_ddr3_val_nand_defconfig | 2 ++ configs/mx6ul_14x14_ddr3_val_plugin_defconfig | 2 ++ configs/mx6ul_14x14_ddr3_val_qspi1_defconfig | 2 ++ configs/mx6ul_14x14_ddr3_val_spinor_defconfig | 2 ++ configs/mx6ul_14x14_evk_defconfig | 2 ++ configs/mx6ul_14x14_evk_emmc_defconfig | 2 ++ configs/mx6ul_14x14_evk_nand_defconfig | 2 ++ configs/mx6ul_14x14_evk_optee_defconfig | 2 ++ configs/mx6ul_14x14_evk_plugin_defconfig | 2 ++ configs/mx6ul_14x14_evk_qspi1_defconfig | 2 ++ configs/mx6ul_14x14_evk_spl_defconfig | 2 ++ configs/mx6ul_14x14_lpddr2_val_defconfig | 2 ++ configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig | 2 ++ configs/mx6ul_9x9_evk_defconfig | 2 ++ configs/mx6ul_9x9_evk_optee_defconfig | 2 ++ configs/mx6ul_9x9_evk_plugin_defconfig | 2 ++ configs/mx6ul_9x9_evk_qspi1_defconfig | 2 ++ configs/mx6ul_9x9_evk_spl_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_emmc_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_epdc_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_nand_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_plugin_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_qspi1_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_spinor_defconfig | 2 ++ configs/mx6ull_14x14_ddr3_val_tsc_defconfig | 2 ++ configs/mx6ull_14x14_evk_defconfig | 2 ++ configs/mx6ull_14x14_evk_emmc_defconfig | 2 ++ configs/mx6ull_14x14_evk_nand_defconfig | 2 ++ configs/mx6ull_14x14_evk_optee_defconfig | 2 ++ configs/mx6ull_14x14_evk_plugin_defconfig | 2 ++ configs/mx6ull_14x14_evk_qspi1_defconfig | 2 ++ configs/mx6ull_9x9_evk_defconfig | 2 ++ configs/mx6ull_9x9_evk_plugin_defconfig | 2 ++ configs/mx6ull_9x9_evk_qspi1_defconfig | 2 ++ configs/mx6ulz_14x14_evk_defconfig | 3 ++- configs/mx6ulz_14x14_evk_emmc_defconfig | 3 ++- configs/mx6ulz_14x14_evk_nand_defconfig | 3 ++- configs/mx6ulz_14x14_evk_optee_defconfig | 3 ++- configs/mx6ulz_14x14_evk_qspi1_defconfig | 2 ++ 186 files changed, 367 insertions(+), 56 deletions(-) diff --git a/configs/imx8dx_17x17_val_defconfig b/configs/imx8dx_17x17_val_defconfig index 882905225a..f46b604f58 100644 --- a/configs/imx8dx_17x17_val_defconfig +++ b/configs/imx8dx_17x17_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dx_mek_defconfig b/configs/imx8dx_mek_defconfig index 083b819777..e193c7de16 100644 --- a/configs/imx8dx_mek_defconfig +++ b/configs/imx8dx_mek_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dx_mek_fspi_defconfig b/configs/imx8dx_mek_fspi_defconfig index df26f991e7..d939c86a89 100644 --- a/configs/imx8dx_mek_fspi_defconfig +++ b/configs/imx8dx_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_ddr3l_evk_defconfig b/configs/imx8dxl_ddr3l_evk_defconfig index 421d3e1181..36b0b83a5d 100644 --- a/configs/imx8dxl_ddr3l_evk_defconfig +++ b/configs/imx8dxl_ddr3l_evk_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_ddr3l_evk_fspi_defconfig b/configs/imx8dxl_ddr3l_evk_fspi_defconfig index 9f4856954e..cea4f6d331 100644 --- a/configs/imx8dxl_ddr3l_evk_fspi_defconfig +++ b/configs/imx8dxl_ddr3l_evk_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_ddr3l_evk_nand_defconfig b/configs/imx8dxl_ddr3l_evk_nand_defconfig index 7a92c318ce..92dab96d27 100644 --- a/configs/imx8dxl_ddr3l_evk_nand_defconfig +++ b/configs/imx8dxl_ddr3l_evk_nand_defconfig @@ -43,7 +43,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_evk_defconfig b/configs/imx8dxl_evk_defconfig index 4341d7f919..36a056e2e9 100644 --- a/configs/imx8dxl_evk_defconfig +++ b/configs/imx8dxl_evk_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_evk_fspi_defconfig b/configs/imx8dxl_evk_fspi_defconfig index 8248dcd839..f7fe652cdf 100644 --- a/configs/imx8dxl_evk_fspi_defconfig +++ b/configs/imx8dxl_evk_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_evk_lcd_defconfig b/configs/imx8dxl_evk_lcd_defconfig index f2091fed79..59222826c0 100644 --- a/configs/imx8dxl_evk_lcd_defconfig +++ b/configs/imx8dxl_evk_lcd_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_phantom_mek_defconfig b/configs/imx8dxl_phantom_mek_defconfig index 87eb60cf59..90c17f7417 100644 --- a/configs/imx8dxl_phantom_mek_defconfig +++ b/configs/imx8dxl_phantom_mek_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8dxl_phantom_mek_fspi_defconfig b/configs/imx8dxl_phantom_mek_fspi_defconfig index 25a666c8fd..17f1671013 100644 --- a/configs/imx8dxl_phantom_mek_fspi_defconfig +++ b/configs/imx8dxl_phantom_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mm_ddr3l_val_defconfig b/configs/imx8mm_ddr3l_val_defconfig index 9b84bd1bec..3178976fe8 100644 --- a/configs/imx8mm_ddr3l_val_defconfig +++ b/configs/imx8mm_ddr3l_val_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_ddr4_ab2_defconfig b/configs/imx8mm_ddr4_ab2_defconfig index 5d4357c8cd..84857b04a1 100644 --- a/configs/imx8mm_ddr4_ab2_defconfig +++ b/configs/imx8mm_ddr4_ab2_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_ddr4_evk_defconfig b/configs/imx8mm_ddr4_evk_defconfig index a70a951992..4f020d7c19 100644 --- a/configs/imx8mm_ddr4_evk_defconfig +++ b/configs/imx8mm_ddr4_evk_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_ddr4_evk_nand_defconfig b/configs/imx8mm_ddr4_evk_nand_defconfig index f4e93d0ab0..4a648a7ea5 100644 --- a/configs/imx8mm_ddr4_evk_nand_defconfig +++ b/configs/imx8mm_ddr4_evk_nand_defconfig @@ -45,7 +45,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_ddr4_val_defconfig b/configs/imx8mm_ddr4_val_defconfig index 6a369e750a..f163c4b2c2 100644 --- a/configs/imx8mm_ddr4_val_defconfig +++ b/configs/imx8mm_ddr4_val_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index ca1c4a268a..1d86997236 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -44,7 +44,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index cef425149f..d92c66f4e1 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -45,7 +45,8 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ab2_defconfig b/configs/imx8mn_ab2_defconfig index 3bf4cf2a36..1cfda9e150 100644 --- a/configs/imx8mn_ab2_defconfig +++ b/configs/imx8mn_ab2_defconfig @@ -53,7 +53,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx8mn_ddr3l_ab2_defconfig b/configs/imx8mn_ddr3l_ab2_defconfig index db6236f242..ac939df584 100644 --- a/configs/imx8mn_ddr3l_ab2_defconfig +++ b/configs/imx8mn_ddr3l_ab2_defconfig @@ -50,7 +50,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig index fef1be5027..81ed94d8ae 100644 --- a/configs/imx8mn_ddr3l_evk_defconfig +++ b/configs/imx8mn_ddr3l_evk_defconfig @@ -50,7 +50,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ddr4_ab2_defconfig b/configs/imx8mn_ddr4_ab2_defconfig index dd4bd5fcda..63b77093cd 100644 --- a/configs/imx8mn_ddr4_ab2_defconfig +++ b/configs/imx8mn_ddr4_ab2_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 097ff4f5f1..9db46d225d 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_ddr4_evk_ld_defconfig b/configs/imx8mn_ddr4_evk_ld_defconfig index 0db9422123..8fe4b7d861 100644 --- a/configs/imx8mn_ddr4_evk_ld_defconfig +++ b/configs/imx8mn_ddr4_evk_ld_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 20c2ff2a52..07a03b0e01 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -53,7 +53,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx8mn_evk_ld_defconfig b/configs/imx8mn_evk_ld_defconfig index b2d30247ab..5772625672 100644 --- a/configs/imx8mn_evk_ld_defconfig +++ b/configs/imx8mn_evk_ld_defconfig @@ -50,7 +50,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_ddr4_evk_defconfig b/configs/imx8mp_ddr4_evk_defconfig index 028a5b82d3..686c2b299f 100644 --- a/configs/imx8mp_ddr4_evk_defconfig +++ b/configs/imx8mp_ddr4_evk_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_ddr4_evk_inline_ecc_defconfig b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig index 920fa8ee06..ad516ea1f4 100644 --- a/configs/imx8mp_ddr4_evk_inline_ecc_defconfig +++ b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_ddr4_evk_nand_defconfig b/configs/imx8mp_ddr4_evk_nand_defconfig index 8aaf3fad38..7286989a12 100644 --- a/configs/imx8mp_ddr4_evk_nand_defconfig +++ b/configs/imx8mp_ddr4_evk_nand_defconfig @@ -46,7 +46,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 393e9b8aba..2dc3ebc5b9 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -51,7 +51,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx8mp_evk_inline_ecc_defconfig b/configs/imx8mp_evk_inline_ecc_defconfig index b8a82849ab..e07340744e 100644 --- a/configs/imx8mp_evk_inline_ecc_defconfig +++ b/configs/imx8mp_evk_inline_ecc_defconfig @@ -48,7 +48,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8mp_evk_ndm_defconfig b/configs/imx8mp_evk_ndm_defconfig index ae66220d74..84049e7fe1 100644 --- a/configs/imx8mp_evk_ndm_defconfig +++ b/configs/imx8mp_evk_ndm_defconfig @@ -52,7 +52,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx8mq_ddr3l_val_defconfig b/configs/imx8mq_ddr3l_val_defconfig index d655205f7f..6096880d6c 100644 --- a/configs/imx8mq_ddr3l_val_defconfig +++ b/configs/imx8mq_ddr3l_val_defconfig @@ -46,7 +46,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mq_ddr4_val_defconfig b/configs/imx8mq_ddr4_val_defconfig index 8daa255b14..f912ba647d 100644 --- a/configs/imx8mq_ddr4_val_defconfig +++ b/configs/imx8mq_ddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mq_ddr4_val_nand_defconfig b/configs/imx8mq_ddr4_val_nand_defconfig index 8aea657047..f8485cc2d7 100644 --- a/configs/imx8mq_ddr4_val_nand_defconfig +++ b/configs/imx8mq_ddr4_val_nand_defconfig @@ -45,7 +45,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index dc2c5003f2..51f24980cc 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -49,7 +49,8 @@ CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y diff --git a/configs/imx8qm_ddr4_val_defconfig b/configs/imx8qm_ddr4_val_defconfig index 3ad81fc695..6e433b77d4 100644 --- a/configs/imx8qm_ddr4_val_defconfig +++ b/configs/imx8qm_ddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_lpddr4_val_defconfig b/configs/imx8qm_lpddr4_val_defconfig index ff7855d1a0..eba7ee5769 100644 --- a/configs/imx8qm_lpddr4_val_defconfig +++ b/configs/imx8qm_lpddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_lpddr4_val_fspi_defconfig b/configs/imx8qm_lpddr4_val_fspi_defconfig index 4da05191c1..b77c3b8c2d 100644 --- a/configs/imx8qm_lpddr4_val_fspi_defconfig +++ b/configs/imx8qm_lpddr4_val_fspi_defconfig @@ -53,7 +53,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_cockpit_a53_defconfig b/configs/imx8qm_mek_cockpit_a53_defconfig index a7d7fd4d1e..b4d1f531ac 100644 --- a/configs/imx8qm_mek_cockpit_a53_defconfig +++ b/configs/imx8qm_mek_cockpit_a53_defconfig @@ -39,7 +39,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 29e9d796a6..d575904063 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_fspi_defconfig b/configs/imx8qm_mek_fspi_defconfig index 5284194138..0a8502d7b1 100644 --- a/configs/imx8qm_mek_fspi_defconfig +++ b/configs/imx8qm_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qm_mek_trusty_xen_defconfig b/configs/imx8qm_mek_trusty_xen_defconfig index 0cd969bb52..cacd625916 100644 --- a/configs/imx8qm_mek_trusty_xen_defconfig +++ b/configs/imx8qm_mek_trusty_xen_defconfig @@ -45,7 +45,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_17x17_val_defconfig b/configs/imx8qxp_17x17_val_defconfig index 181a6696eb..a75ab18161 100644 --- a/configs/imx8qxp_17x17_val_defconfig +++ b/configs/imx8qxp_17x17_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_ddr3_val_defconfig b/configs/imx8qxp_ddr3_val_defconfig index d2cc47f630..acaf40ddd0 100644 --- a/configs/imx8qxp_ddr3_val_defconfig +++ b/configs/imx8qxp_ddr3_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_lpddr4_val_defconfig b/configs/imx8qxp_lpddr4_val_defconfig index fcc6f7a275..186e467f94 100644 --- a/configs/imx8qxp_lpddr4_val_defconfig +++ b/configs/imx8qxp_lpddr4_val_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_lpddr4_val_fspi_defconfig b/configs/imx8qxp_lpddr4_val_fspi_defconfig index aba96c898b..b900b36e0e 100644 --- a/configs/imx8qxp_lpddr4_val_fspi_defconfig +++ b/configs/imx8qxp_lpddr4_val_fspi_defconfig @@ -53,7 +53,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_lpddr4_val_nand_defconfig b/configs/imx8qxp_lpddr4_val_nand_defconfig index 7e3c606619..0cee3d8613 100644 --- a/configs/imx8qxp_lpddr4_val_nand_defconfig +++ b/configs/imx8qxp_lpddr4_val_nand_defconfig @@ -44,7 +44,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index eda9d2cc00..0e9b0b1890 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -46,7 +46,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8qxp_mek_fspi_defconfig b/configs/imx8qxp_mek_fspi_defconfig index 56e3334828..7fa22d10ef 100644 --- a/configs/imx8qxp_mek_fspi_defconfig +++ b/configs/imx8qxp_mek_fspi_defconfig @@ -52,7 +52,8 @@ CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_CLK=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y diff --git a/configs/imx8ulp_9x9_evk_defconfig b/configs/imx8ulp_9x9_evk_defconfig index 48e8892417..0927a46e1f 100644 --- a/configs/imx8ulp_9x9_evk_defconfig +++ b/configs/imx8ulp_9x9_evk_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/imx8ulp_9x9_evk_i3c_defconfig b/configs/imx8ulp_9x9_evk_i3c_defconfig index c5a53008a7..45a1f77e33 100644 --- a/configs/imx8ulp_9x9_evk_i3c_defconfig +++ b/configs/imx8ulp_9x9_evk_i3c_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index f6cd629a36..fabc6c15c7 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/imx8ulp_evk_i3c_defconfig b/configs/imx8ulp_evk_i3c_defconfig index ce6e7d14ee..7eeeb0668b 100644 --- a/configs/imx8ulp_evk_i3c_defconfig +++ b/configs/imx8ulp_evk_i3c_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/imx8ulp_evk_nd_defconfig b/configs/imx8ulp_evk_nd_defconfig index 800f2c26c7..a5b099c25e 100644 --- a/configs/imx8ulp_evk_nd_defconfig +++ b/configs/imx8ulp_evk_nd_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_READ=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CRC32_VERIFY=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index d023253959..4bf4aac854 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -43,7 +43,8 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 7177527f4a..c928b5aa82 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -43,7 +43,8 @@ CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_ERASEENV=y CONFIG_CMD_NVEDIT_EFI=y -# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index d469fa1462..347302bc9c 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_eimnor_defconfig b/configs/mx6dlsabreauto_eimnor_defconfig index 2c9180c86d..d775d189a1 100644 --- a/configs/mx6dlsabreauto_eimnor_defconfig +++ b/configs/mx6dlsabreauto_eimnor_defconfig @@ -100,3 +100,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_nand_defconfig b/configs/mx6dlsabreauto_nand_defconfig index 7990e0a32b..ef5cbcafe1 100644 --- a/configs/mx6dlsabreauto_nand_defconfig +++ b/configs/mx6dlsabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_optee_defconfig b/configs/mx6dlsabreauto_optee_defconfig index a50f156465..65a4497c98 100644 --- a/configs/mx6dlsabreauto_optee_defconfig +++ b/configs/mx6dlsabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_plugin_defconfig b/configs/mx6dlsabreauto_plugin_defconfig index 78b0d346cf..47b1a6402f 100644 --- a/configs/mx6dlsabreauto_plugin_defconfig +++ b/configs/mx6dlsabreauto_plugin_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabreauto_spinor_defconfig b/configs/mx6dlsabreauto_spinor_defconfig index 162a98dde0..3f5280f898 100644 --- a/configs/mx6dlsabreauto_spinor_defconfig +++ b/configs/mx6dlsabreauto_spinor_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index b23a524fb2..f91b23218c 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_epdc_defconfig b/configs/mx6dlsabresd_epdc_defconfig index 79d5742e1e..853e5c5ef5 100644 --- a/configs/mx6dlsabresd_epdc_defconfig +++ b/configs/mx6dlsabresd_epdc_defconfig @@ -102,3 +102,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_optee_defconfig b/configs/mx6dlsabresd_optee_defconfig index aca36d95df..4cc87f3161 100644 --- a/configs/mx6dlsabresd_optee_defconfig +++ b/configs/mx6dlsabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6dlsabresd_plugin_defconfig b/configs/mx6dlsabresd_plugin_defconfig index 417607a291..6f35ff8b56 100644 --- a/configs/mx6dlsabresd_plugin_defconfig +++ b/configs/mx6dlsabresd_plugin_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig index 553bc99c71..bd83071583 100644 --- a/configs/mx6qpsabreauto_defconfig +++ b/configs/mx6qpsabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_eimnor_defconfig b/configs/mx6qpsabreauto_eimnor_defconfig index 8bd43ffb72..0dceadbcf1 100644 --- a/configs/mx6qpsabreauto_eimnor_defconfig +++ b/configs/mx6qpsabreauto_eimnor_defconfig @@ -100,3 +100,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_nand_defconfig b/configs/mx6qpsabreauto_nand_defconfig index 7eebfcab1e..be87a9b515 100644 --- a/configs/mx6qpsabreauto_nand_defconfig +++ b/configs/mx6qpsabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_optee_defconfig b/configs/mx6qpsabreauto_optee_defconfig index a53cac34e8..6b618c4966 100644 --- a/configs/mx6qpsabreauto_optee_defconfig +++ b/configs/mx6qpsabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_plugin_defconfig b/configs/mx6qpsabreauto_plugin_defconfig index 6075500b55..51e32a7f9f 100644 --- a/configs/mx6qpsabreauto_plugin_defconfig +++ b/configs/mx6qpsabreauto_plugin_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_sata_defconfig b/configs/mx6qpsabreauto_sata_defconfig index 472eb10c8e..407981dd25 100644 --- a/configs/mx6qpsabreauto_sata_defconfig +++ b/configs/mx6qpsabreauto_sata_defconfig @@ -102,3 +102,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabreauto_spinor_defconfig b/configs/mx6qpsabreauto_spinor_defconfig index 229494f00e..b64d4f0eb5 100644 --- a/configs/mx6qpsabreauto_spinor_defconfig +++ b/configs/mx6qpsabreauto_spinor_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabresd_defconfig b/configs/mx6qpsabresd_defconfig index ba36499910..eb386c720a 100644 --- a/configs/mx6qpsabresd_defconfig +++ b/configs/mx6qpsabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabresd_optee_defconfig b/configs/mx6qpsabresd_optee_defconfig index 77978c9561..4ba3890b95 100644 --- a/configs/mx6qpsabresd_optee_defconfig +++ b/configs/mx6qpsabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qpsabresd_sata_defconfig b/configs/mx6qpsabresd_sata_defconfig index 19e72e2b17..f9a057339f 100644 --- a/configs/mx6qpsabresd_sata_defconfig +++ b/configs/mx6qpsabresd_sata_defconfig @@ -111,3 +111,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index c2e92a947e..978fe14826 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_eimnor_defconfig b/configs/mx6qsabreauto_eimnor_defconfig index 8205860865..38b3f974c1 100644 --- a/configs/mx6qsabreauto_eimnor_defconfig +++ b/configs/mx6qsabreauto_eimnor_defconfig @@ -100,3 +100,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_nand_defconfig b/configs/mx6qsabreauto_nand_defconfig index d1479557f0..3281cab0eb 100644 --- a/configs/mx6qsabreauto_nand_defconfig +++ b/configs/mx6qsabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_optee_defconfig b/configs/mx6qsabreauto_optee_defconfig index 7ba7d641d7..f594feb87a 100644 --- a/configs/mx6qsabreauto_optee_defconfig +++ b/configs/mx6qsabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_plugin_defconfig b/configs/mx6qsabreauto_plugin_defconfig index 5d90ecde91..29c0d38bbc 100644 --- a/configs/mx6qsabreauto_plugin_defconfig +++ b/configs/mx6qsabreauto_plugin_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_sata_defconfig b/configs/mx6qsabreauto_sata_defconfig index 9b71e45b16..e132390287 100644 --- a/configs/mx6qsabreauto_sata_defconfig +++ b/configs/mx6qsabreauto_sata_defconfig @@ -102,3 +102,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabreauto_spinor_defconfig b/configs/mx6qsabreauto_spinor_defconfig index 5c51939b4f..3ac3d004ab 100644 --- a/configs/mx6qsabreauto_spinor_defconfig +++ b/configs/mx6qsabreauto_spinor_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 6817c6f88a..c2a8bbe1e9 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -90,3 +90,5 @@ CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 986fab886d..bef2e54c6b 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_optee_defconfig b/configs/mx6qsabresd_optee_defconfig index 93187e1f41..33e036803c 100644 --- a/configs/mx6qsabresd_optee_defconfig +++ b/configs/mx6qsabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_plugin_defconfig b/configs/mx6qsabresd_plugin_defconfig index f2e85177b9..cb68cabdc1 100644 --- a/configs/mx6qsabresd_plugin_defconfig +++ b/configs/mx6qsabresd_plugin_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6qsabresd_sata_defconfig b/configs/mx6qsabresd_sata_defconfig index 11c7c1d8da..b0c166c1ed 100644 --- a/configs/mx6qsabresd_sata_defconfig +++ b/configs/mx6qsabresd_sata_defconfig @@ -111,3 +111,5 @@ CONFIG_IMX_AHCI=y CONFIG_DM_SCSI=y CONFIG_SCSI=y CONFIG_CMD_SCSI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index fe3ec76748..81251995bb 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -117,3 +117,5 @@ CONFIG_VIDEO_IPUV3=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index d2f5f8df15..f1a7ae6f18 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -122,3 +122,5 @@ CONFIG_VIDEO_IPUV3=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 2cc16e2110..e0dbd22866 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -90,3 +90,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_epdc_defconfig b/configs/mx6slevk_epdc_defconfig index 638afd5208..5f7ee6188f 100644 --- a/configs/mx6slevk_epdc_defconfig +++ b/configs/mx6slevk_epdc_defconfig @@ -95,3 +95,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_optee_defconfig b/configs/mx6slevk_optee_defconfig index 779b1a4771..422ccb9152 100644 --- a/configs/mx6slevk_optee_defconfig +++ b/configs/mx6slevk_optee_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_plugin_defconfig b/configs/mx6slevk_plugin_defconfig index 642543e142..df1b60a7d0 100644 --- a/configs/mx6slevk_plugin_defconfig +++ b/configs/mx6slevk_plugin_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 3f8a2ddd3d..0c432a46e5 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -92,3 +92,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index 09d71ae905..9ae103d3a3 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -82,3 +82,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr2_val_defconfig b/configs/mx6sll_lpddr2_val_defconfig index 2b1f0434b7..4f01034a44 100644 --- a/configs/mx6sll_lpddr2_val_defconfig +++ b/configs/mx6sll_lpddr2_val_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_defconfig b/configs/mx6sll_lpddr3_val_defconfig index 5cad2d7775..4b4fa344c6 100644 --- a/configs/mx6sll_lpddr3_val_defconfig +++ b/configs/mx6sll_lpddr3_val_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_epdc_defconfig b/configs/mx6sll_lpddr3_val_epdc_defconfig index 497480d9e9..1921e086bb 100644 --- a/configs/mx6sll_lpddr3_val_epdc_defconfig +++ b/configs/mx6sll_lpddr3_val_epdc_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_plugin_defconfig b/configs/mx6sll_lpddr3_val_plugin_defconfig index a88e1e403e..d016b013be 100644 --- a/configs/mx6sll_lpddr3_val_plugin_defconfig +++ b/configs/mx6sll_lpddr3_val_plugin_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sll_lpddr3_val_spinor_defconfig b/configs/mx6sll_lpddr3_val_spinor_defconfig index 4590d781eb..8087eaeec8 100644 --- a/configs/mx6sll_lpddr3_val_spinor_defconfig +++ b/configs/mx6sll_lpddr3_val_spinor_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y CONFIG_DM_ETH=y CONFIG_PHYLIB=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 56e5755223..fab5c0d822 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_epdc_defconfig b/configs/mx6sllevk_epdc_defconfig index 87ace8ad3e..2d66343059 100644 --- a/configs/mx6sllevk_epdc_defconfig +++ b/configs/mx6sllevk_epdc_defconfig @@ -87,3 +87,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_optee_defconfig b/configs/mx6sllevk_optee_defconfig index 7978739bf3..02b18d66de 100644 --- a/configs/mx6sllevk_optee_defconfig +++ b/configs/mx6sllevk_optee_defconfig @@ -92,3 +92,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 602cb48baa..2f7c12f820 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -92,3 +92,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_defconfig b/configs/mx6solosabreauto_defconfig index bdf5103638..d3192e32dc 100644 --- a/configs/mx6solosabreauto_defconfig +++ b/configs/mx6solosabreauto_defconfig @@ -96,3 +96,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_eimnor_defconfig b/configs/mx6solosabreauto_eimnor_defconfig index dc764a2f1a..e7ac350237 100644 --- a/configs/mx6solosabreauto_eimnor_defconfig +++ b/configs/mx6solosabreauto_eimnor_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_nand_defconfig b/configs/mx6solosabreauto_nand_defconfig index 8f6816c0f7..86add3582c 100644 --- a/configs/mx6solosabreauto_nand_defconfig +++ b/configs/mx6solosabreauto_nand_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_optee_defconfig b/configs/mx6solosabreauto_optee_defconfig index d18fc606d8..b4cce2f6bb 100644 --- a/configs/mx6solosabreauto_optee_defconfig +++ b/configs/mx6solosabreauto_optee_defconfig @@ -97,3 +97,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabreauto_spinor_defconfig b/configs/mx6solosabreauto_spinor_defconfig index 4de754b0b6..5382813bc2 100644 --- a/configs/mx6solosabreauto_spinor_defconfig +++ b/configs/mx6solosabreauto_spinor_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabresd_defconfig b/configs/mx6solosabresd_defconfig index 9b5843a13d..f41a900cfb 100644 --- a/configs/mx6solosabresd_defconfig +++ b/configs/mx6solosabresd_defconfig @@ -107,3 +107,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6solosabresd_optee_defconfig b/configs/mx6solosabresd_optee_defconfig index 731e6f28d0..2face9926d 100644 --- a/configs/mx6solosabresd_optee_defconfig +++ b/configs/mx6solosabresd_optee_defconfig @@ -108,3 +108,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_14x14_lpddr2_val_defconfig b/configs/mx6sx_14x14_lpddr2_val_defconfig index bea729b6d9..687c52b152 100644 --- a/configs/mx6sx_14x14_lpddr2_val_defconfig +++ b/configs/mx6sx_14x14_lpddr2_val_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_14x14_lpddr2_val_nand_defconfig b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig index 04ea9c8bd2..06b3ccae00 100644 --- a/configs/mx6sx_14x14_lpddr2_val_nand_defconfig +++ b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig index f2a56d271e..fd0e3e1755 100644 --- a/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig +++ b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig @@ -80,3 +80,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_defconfig b/configs/mx6sx_17x17_val_defconfig index 8427cc704d..9bb0187ecb 100644 --- a/configs/mx6sx_17x17_val_defconfig +++ b/configs/mx6sx_17x17_val_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_eimnor_defconfig b/configs/mx6sx_17x17_val_eimnor_defconfig index 092e73a7c2..4ae90d9f8a 100644 --- a/configs/mx6sx_17x17_val_eimnor_defconfig +++ b/configs/mx6sx_17x17_val_eimnor_defconfig @@ -72,3 +72,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_nand_defconfig b/configs/mx6sx_17x17_val_nand_defconfig index 1478027ece..16f0185251 100644 --- a/configs/mx6sx_17x17_val_nand_defconfig +++ b/configs/mx6sx_17x17_val_nand_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_plugin_defconfig b/configs/mx6sx_17x17_val_plugin_defconfig index 454aec8da6..7c95d28299 100644 --- a/configs/mx6sx_17x17_val_plugin_defconfig +++ b/configs/mx6sx_17x17_val_plugin_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_qspi2_defconfig b/configs/mx6sx_17x17_val_qspi2_defconfig index d614d181b4..6b32679f73 100644 --- a/configs/mx6sx_17x17_val_qspi2_defconfig +++ b/configs/mx6sx_17x17_val_qspi2_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17_val_spinor_defconfig b/configs/mx6sx_17x17_val_spinor_defconfig index 3e4ab08a61..e579d02481 100644 --- a/configs/mx6sx_17x17_val_spinor_defconfig +++ b/configs/mx6sx_17x17_val_spinor_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_17x17wp_val_defconfig b/configs/mx6sx_17x17wp_val_defconfig index c4f9ff3fa8..d79ef92e72 100644 --- a/configs/mx6sx_17x17wp_val_defconfig +++ b/configs/mx6sx_17x17wp_val_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_defconfig b/configs/mx6sx_19x19_ddr3_val_defconfig index 365c4266e9..a371c401c8 100644 --- a/configs/mx6sx_19x19_ddr3_val_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_defconfig @@ -77,3 +77,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig index ea6389c6f6..9b85e58043 100644 --- a/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig @@ -71,3 +71,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_nand_defconfig b/configs/mx6sx_19x19_ddr3_val_nand_defconfig index 57b57efbae..2f74fb0901 100644 --- a/configs/mx6sx_19x19_ddr3_val_nand_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_nand_defconfig @@ -80,3 +80,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_plugin_defconfig b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig index 8568c358e6..ed21966a28 100644 --- a/configs/mx6sx_19x19_ddr3_val_plugin_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig index cccdbc8d13..fa497fc511 100644 --- a/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_ddr3_val_spinor_defconfig b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig index b3439bc3a7..32bbe2a499 100644 --- a/configs/mx6sx_19x19_ddr3_val_spinor_defconfig +++ b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig @@ -81,3 +81,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_lpddr2_val_defconfig b/configs/mx6sx_19x19_lpddr2_val_defconfig index 79ae5deebd..d4de70cc1a 100644 --- a/configs/mx6sx_19x19_lpddr2_val_defconfig +++ b/configs/mx6sx_19x19_lpddr2_val_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig index 0e16c6ae68..2a353e731e 100644 --- a/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig +++ b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig index a515ad6673..491e07c7f7 100644 --- a/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig +++ b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig @@ -82,3 +82,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 3cd1254f8f..89b3548977 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_nand_defconfig b/configs/mx6sxsabreauto_nand_defconfig index 0dc30d8475..a32d0d312b 100644 --- a/configs/mx6sxsabreauto_nand_defconfig +++ b/configs/mx6sxsabreauto_nand_defconfig @@ -117,3 +117,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_optee_defconfig b/configs/mx6sxsabreauto_optee_defconfig index b246eff6d9..add640ec30 100644 --- a/configs/mx6sxsabreauto_optee_defconfig +++ b/configs/mx6sxsabreauto_optee_defconfig @@ -113,3 +113,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_plugin_defconfig b/configs/mx6sxsabreauto_plugin_defconfig index 8c4a158a7d..7e81e7b3cc 100644 --- a/configs/mx6sxsabreauto_plugin_defconfig +++ b/configs/mx6sxsabreauto_plugin_defconfig @@ -113,3 +113,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabreauto_qspi1_defconfig b/configs/mx6sxsabreauto_qspi1_defconfig index 0878827593..9b0b725dbd 100644 --- a/configs/mx6sxsabreauto_qspi1_defconfig +++ b/configs/mx6sxsabreauto_qspi1_defconfig @@ -117,3 +117,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 7d2a7995e0..ccd084a4ff 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -111,3 +111,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_emmc_defconfig b/configs/mx6sxsabresd_emmc_defconfig index 5b41f86a30..3fa8f151be 100644 --- a/configs/mx6sxsabresd_emmc_defconfig +++ b/configs/mx6sxsabresd_emmc_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_m4fastup_defconfig b/configs/mx6sxsabresd_m4fastup_defconfig index fbcb906692..04b8e656b1 100644 --- a/configs/mx6sxsabresd_m4fastup_defconfig +++ b/configs/mx6sxsabresd_m4fastup_defconfig @@ -87,3 +87,5 @@ CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_IMX_BOOTAUX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_optee_defconfig b/configs/mx6sxsabresd_optee_defconfig index 572ab0cebb..8801dbd7b2 100644 --- a/configs/mx6sxsabresd_optee_defconfig +++ b/configs/mx6sxsabresd_optee_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_plugin_defconfig b/configs/mx6sxsabresd_plugin_defconfig index c7ae5c7e4c..1f6a5f63d0 100644 --- a/configs/mx6sxsabresd_plugin_defconfig +++ b/configs/mx6sxsabresd_plugin_defconfig @@ -112,3 +112,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6sxsabresd_qspi2_defconfig b/configs/mx6sxsabresd_qspi2_defconfig index a5e1fcedb4..5fdab1f758 100644 --- a/configs/mx6sxsabresd_qspi2_defconfig +++ b/configs/mx6sxsabresd_qspi2_defconfig @@ -116,3 +116,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_defconfig b/configs/mx6ul_14x14_ddr3_val_defconfig index ad0cc2698e..011dd23469 100644 --- a/configs/mx6ul_14x14_ddr3_val_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_defconfig @@ -75,3 +75,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig index a75a381f8a..7ffe1d36d8 100644 --- a/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig @@ -64,3 +64,5 @@ CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_MMC=n +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_emmc_defconfig b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig index 0d68ad1298..e6d2980a47 100644 --- a/configs/mx6ul_14x14_ddr3_val_emmc_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig @@ -67,3 +67,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_nand_defconfig b/configs/mx6ul_14x14_ddr3_val_nand_defconfig index 8f1483cd05..d727d78fc3 100644 --- a/configs/mx6ul_14x14_ddr3_val_nand_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_nand_defconfig @@ -75,3 +75,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_plugin_defconfig b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig index fdd8315a67..ad9c14f8d3 100644 --- a/configs/mx6ul_14x14_ddr3_val_plugin_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig @@ -76,3 +76,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig index 15c0e6e3b1..b843458073 100644 --- a/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig @@ -77,3 +77,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_ddr3_val_spinor_defconfig b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig index a82bed66e2..4788727d34 100644 --- a/configs/mx6ul_14x14_ddr3_val_spinor_defconfig +++ b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig @@ -78,3 +78,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 1aa455f120..687d7362fe 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -101,3 +101,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_emmc_defconfig b/configs/mx6ul_14x14_evk_emmc_defconfig index 19baa475e0..ce6b7afb70 100644 --- a/configs/mx6ul_14x14_evk_emmc_defconfig +++ b/configs/mx6ul_14x14_evk_emmc_defconfig @@ -101,3 +101,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_nand_defconfig b/configs/mx6ul_14x14_evk_nand_defconfig index 7b99e89be6..61d49d2f51 100644 --- a/configs/mx6ul_14x14_evk_nand_defconfig +++ b/configs/mx6ul_14x14_evk_nand_defconfig @@ -105,3 +105,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_optee_defconfig b/configs/mx6ul_14x14_evk_optee_defconfig index 885f25e7b2..d5621b59a2 100644 --- a/configs/mx6ul_14x14_evk_optee_defconfig +++ b/configs/mx6ul_14x14_evk_optee_defconfig @@ -102,3 +102,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_plugin_defconfig b/configs/mx6ul_14x14_evk_plugin_defconfig index 6555f224b3..97b032d000 100644 --- a/configs/mx6ul_14x14_evk_plugin_defconfig +++ b/configs/mx6ul_14x14_evk_plugin_defconfig @@ -102,3 +102,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_qspi1_defconfig b/configs/mx6ul_14x14_evk_qspi1_defconfig index 608bd156f3..260183a57c 100644 --- a/configs/mx6ul_14x14_evk_qspi1_defconfig +++ b/configs/mx6ul_14x14_evk_qspi1_defconfig @@ -104,3 +104,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_evk_spl_defconfig b/configs/mx6ul_14x14_evk_spl_defconfig index dfc1bc2fd4..b21aa2b976 100644 --- a/configs/mx6ul_14x14_evk_spl_defconfig +++ b/configs/mx6ul_14x14_evk_spl_defconfig @@ -100,3 +100,5 @@ CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_lpddr2_val_defconfig b/configs/mx6ul_14x14_lpddr2_val_defconfig index 6a80b0e6d4..740ea1b6ee 100644 --- a/configs/mx6ul_14x14_lpddr2_val_defconfig +++ b/configs/mx6ul_14x14_lpddr2_val_defconfig @@ -66,3 +66,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig index 22b88418ca..41dc2ad821 100644 --- a/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig +++ b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig @@ -67,3 +67,5 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 7afd445694..6d2b998e8f 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -103,3 +103,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_optee_defconfig b/configs/mx6ul_9x9_evk_optee_defconfig index bfb3cb6c75..4d71c0e644 100644 --- a/configs/mx6ul_9x9_evk_optee_defconfig +++ b/configs/mx6ul_9x9_evk_optee_defconfig @@ -104,3 +104,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_plugin_defconfig b/configs/mx6ul_9x9_evk_plugin_defconfig index 3ca556a36f..7c2dc45f37 100644 --- a/configs/mx6ul_9x9_evk_plugin_defconfig +++ b/configs/mx6ul_9x9_evk_plugin_defconfig @@ -104,3 +104,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_qspi1_defconfig b/configs/mx6ul_9x9_evk_qspi1_defconfig index 55f5efb465..b5abc8c051 100644 --- a/configs/mx6ul_9x9_evk_qspi1_defconfig +++ b/configs/mx6ul_9x9_evk_qspi1_defconfig @@ -106,3 +106,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ul_9x9_evk_spl_defconfig b/configs/mx6ul_9x9_evk_spl_defconfig index a121e96603..66ef7428ba 100644 --- a/configs/mx6ul_9x9_evk_spl_defconfig +++ b/configs/mx6ul_9x9_evk_spl_defconfig @@ -90,3 +90,5 @@ CONFIG_VIDEO_MXS=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_defconfig b/configs/mx6ull_14x14_ddr3_val_defconfig index 18879920ac..d545f2771d 100644 --- a/configs/mx6ull_14x14_ddr3_val_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_emmc_defconfig b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig index c7f75c035a..568b55908c 100644 --- a/configs/mx6ull_14x14_ddr3_val_emmc_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig @@ -67,3 +67,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_epdc_defconfig b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig index ac06caeffe..1be63ac379 100644 --- a/configs/mx6ull_14x14_ddr3_val_epdc_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig @@ -79,3 +79,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_nand_defconfig b/configs/mx6ull_14x14_ddr3_val_nand_defconfig index 2ccdd61e4a..fddaaeb267 100644 --- a/configs/mx6ull_14x14_ddr3_val_nand_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_nand_defconfig @@ -75,3 +75,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_plugin_defconfig b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig index 77a643e560..05913c6a3c 100644 --- a/configs/mx6ull_14x14_ddr3_val_plugin_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig @@ -76,3 +76,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig index e04d76179a..f41f5c1f13 100644 --- a/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig @@ -77,3 +77,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_spinor_defconfig b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig index 36eb157659..6dafce4fd9 100644 --- a/configs/mx6ull_14x14_ddr3_val_spinor_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig @@ -78,3 +78,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_ddr3_val_tsc_defconfig b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig index 5b266463cf..782ea09914 100644 --- a/configs/mx6ull_14x14_ddr3_val_tsc_defconfig +++ b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig @@ -76,3 +76,5 @@ CONFIG_USB_STORAGE=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index b81047f845..06193017f4 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -104,3 +104,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig index b6925f0282..4b81d0ea72 100644 --- a/configs/mx6ull_14x14_evk_emmc_defconfig +++ b/configs/mx6ull_14x14_evk_emmc_defconfig @@ -104,3 +104,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig index 0bbd9b9e59..efca82d619 100644 --- a/configs/mx6ull_14x14_evk_nand_defconfig +++ b/configs/mx6ull_14x14_evk_nand_defconfig @@ -111,3 +111,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig index e5ca8d808c..51e1bd8fde 100644 --- a/configs/mx6ull_14x14_evk_optee_defconfig +++ b/configs/mx6ull_14x14_evk_optee_defconfig @@ -105,3 +105,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 19dcf4abee..ffdcc93819 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -105,3 +105,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig index 54266facb0..69db8b7ec7 100644 --- a/configs/mx6ull_14x14_evk_qspi1_defconfig +++ b/configs/mx6ull_14x14_evk_qspi1_defconfig @@ -107,3 +107,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig index 7b88d47678..e96c202f4d 100644 --- a/configs/mx6ull_9x9_evk_defconfig +++ b/configs/mx6ull_9x9_evk_defconfig @@ -109,3 +109,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig index 526d2b3f1d..cd7a5505e1 100644 --- a/configs/mx6ull_9x9_evk_plugin_defconfig +++ b/configs/mx6ull_9x9_evk_plugin_defconfig @@ -109,3 +109,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig index 4ffc639da2..4168573e03 100644 --- a/configs/mx6ull_9x9_evk_qspi1_defconfig +++ b/configs/mx6ull_9x9_evk_qspi1_defconfig @@ -111,3 +111,5 @@ CONFIG_DM_RNG=y CONFIG_CMD_RNG=y CONFIG_FSL_DCP_RNG=y CONFIG_OF_SYSTEM_SETUP=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 438af0a065..ee911af30a 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -87,4 +87,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y \ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_emmc_defconfig b/configs/mx6ulz_14x14_evk_emmc_defconfig index 7595c54ee8..44881ee749 100644 --- a/configs/mx6ulz_14x14_evk_emmc_defconfig +++ b/configs/mx6ulz_14x14_evk_emmc_defconfig @@ -87,4 +87,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y \ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_nand_defconfig b/configs/mx6ulz_14x14_evk_nand_defconfig index 6526b17200..44a69b350c 100644 --- a/configs/mx6ulz_14x14_evk_nand_defconfig +++ b/configs/mx6ulz_14x14_evk_nand_defconfig @@ -91,4 +91,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y \ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_optee_defconfig b/configs/mx6ulz_14x14_evk_optee_defconfig index ebb71c0684..12a2973b7b 100644 --- a/configs/mx6ulz_14x14_evk_optee_defconfig +++ b/configs/mx6ulz_14x14_evk_optee_defconfig @@ -88,4 +88,5 @@ CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y -CONFIG_EFI_PARTITION=y \ No newline at end of file +CONFIG_EFI_PARTITION=yCONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y diff --git a/configs/mx6ulz_14x14_evk_qspi1_defconfig b/configs/mx6ulz_14x14_evk_qspi1_defconfig index d6af77381f..a19528a293 100644 --- a/configs/mx6ulz_14x14_evk_qspi1_defconfig +++ b/configs/mx6ulz_14x14_evk_qspi1_defconfig @@ -91,3 +91,5 @@ CONFIG_FASTBOOT_BUF_ADDR=0x83800000 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 CONFIG_FASTBOOT_FLASH=y CONFIG_EFI_PARTITION=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y -- cgit v1.2.3 From aaead5a2b8dace60b5a511453269be2853522a48 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 11 Oct 2022 12:19:45 +0800 Subject: LFU-416 imx: cmd_dek: Fix build warning in blob_encap_dek MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix below build warning introduced by commit bf07f51 (LFOPTEE-177 imx: cmd_dek: add ELE DEK Blob generation support) In file included from ./arch/arm/include/asm/io.h:341, from include/fsl_sec.h:13, from arch/arm/mach-imx/cmd_dek.c:16: include/cpu_func.h:68:39: note: expected ‘long unsigned int’ but argument is of type ‘u8 *’ {aka ‘unsigned char *’} 68 | void flush_dcache_range(unsigned long start, unsigned long stop); Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/cmd_dek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 5ff8a4e55d..9e69f2c505 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -353,7 +353,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len) /* Flush the cache */ flush_dcache_range(src_addr, src_addr + in_size); - flush_dcache_range(dst_ptr, (ulong)(dst_ptr + + flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + roundup(out_size, ARCH_DMA_MINALIGN))); /* Call ELE */ -- cgit v1.2.3 From a555a21be6916ac7238c84bf1fb70aa10cb44be2 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 11 Oct 2022 12:24:48 +0800 Subject: LFU-413 imx8ulp_evk: Remove CONFIG_BOOTDELAY=0 from ND defconfig Remove CONFIG_BOOTDELAY=0, use default 2s boot delay Signed-off-by: Ye Li Reviewed-by: Peng Fan --- configs/imx8ulp_evk_nd_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/imx8ulp_evk_nd_defconfig b/configs/imx8ulp_evk_nd_defconfig index a5b099c25e..b886326571 100644 --- a/configs/imx8ulp_evk_nd_defconfig +++ b/configs/imx8ulp_evk_nd_defconfig @@ -25,7 +25,6 @@ CONFIG_REMAKE_ELF=y CONFIG_SYS_LOAD_ADDR=0x80400000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb" CONFIG_BOARD_EARLY_INIT_F=y -- cgit v1.2.3 From 026521c7d6553ecc50b24bea61dba33ba7a5168d Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 11 Oct 2022 14:21:04 +0800 Subject: LFU-417-1 ddr: imx: imx9: Add DDR inline ECC support Support DDR inline ECC feature for i.MX9 DDR driver. It uses top 1/8 DDR size for ECC data. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx9/ddr.h | 4 ++++ drivers/ddr/imx/imx9/Kconfig | 6 ++++++ drivers/ddr/imx/imx9/ddr_init.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index 83983ed391..af5e6b5764 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -13,11 +13,15 @@ #define DDR_PHY_BASE 0x4E100000 #define DDRMIX_BLK_CTRL_BASE 0x4E010000 +#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0) +#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8) #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) #define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_SDRAM_CFG2 (DDR_CTL_BASE + 0x114) #define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) +#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000) #define SRC_BASE_ADDR (0x44460000) #define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index b1795eec35..0c2ee89c31 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -17,6 +17,12 @@ config IMX9_DRAM_PM_COUNTER help Enable DDR controller performance monitor counter for reference events. +config IMX9_DRAM_INLINE_ECC + bool "Enable DDR INLINE ECC feature" + default n + help + Select to enable DDR INLINE ECC feature + config SAVED_DRAM_TIMING_BASE hex "Define the base address for saved dram timing" help diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c index 7cf1142f9a..17b4b259ac 100644 --- a/drivers/ddr/imx/imx9/ddr_init.c +++ b/drivers/ddr/imx/imx9/ddr_init.c @@ -197,6 +197,37 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num) writel(tmp_t, REG_DDR_TIMING_CFG_4); } +void update_inline_ecc_setting(void) +{ + u32 val, sa, ea; + + val = readl(REG_DDR_CS0_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS0_BNDS); + } + + val = readl(REG_DDR_CS1_BNDS); + if (val != 0) { + sa = (val >> 16) & 0xff; + ea = val & 0xff; + + /* 1/8 size is used for inline ecc */ + ea = ea - ((ea + 1 - sa) >> 3); + writel((sa << 16) | ea, REG_DDR_CS1_BNDS); + } + + /* Enable Inline ECC */ + setbits_le32(REG_DDR_ERR_EN, BIT(31) | BIT(30)); + + /* Enable data initialization */ + setbits_le32(REG_DDR_SDRAM_CFG2, BIT(4)); +} + int ddr_init(struct dram_timing_info *dram_timing) { unsigned int initial_drate; @@ -233,6 +264,10 @@ int ddr_init(struct dram_timing_info *dram_timing) update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); +#ifdef CONFIG_IMX9_DRAM_INLINE_ECC + update_inline_ecc_setting(); +#endif + #ifdef CONFIG_IMX9_DRAM_PM_COUNTER writel(0x200000, REG_DDR_DEBUG_19); #endif -- cgit v1.2.3 From c244bdfd76c524a0fbaab25138ebd86e2be033a5 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 11 Oct 2022 14:23:43 +0800 Subject: LFU-417-2 imx93_evk/qsb: Enable DDR inline ECC feature Add new defconfig to enable DDR inline ECC. 256MB DDR size is occupied by ECC data, so total DDR size is 1.792GB Signed-off-by: Ye Li Reviewed-by: Peng Fan --- configs/imx93_11x11_evk_inline_ecc_defconfig | 187 +++++++++++++++++++++++++++ configs/imx93_9x9_qsb_inline_ecc_defconfig | 182 ++++++++++++++++++++++++++ include/configs/imx93_evk.h | 4 + include/configs/imx93_qsb.h | 4 + 4 files changed, 377 insertions(+) create mode 100644 configs/imx93_11x11_evk_inline_ecc_defconfig create mode 100644 configs/imx93_9x9_qsb_inline_ecc_defconfig diff --git a/configs/imx93_11x11_evk_inline_ecc_defconfig b/configs/imx93_11x11_evk_inline_ecc_defconfig new file mode 100644 index 0000000000..8fc62d1988 --- /dev/null +++ b/configs/imx93_11x11_evk_inline_ecc_defconfig @@ -0,0 +1,187 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_11X11_EVK=y +CONFIG_IMX9_DRAM_INLINE_ECC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_ADP5585_GPIO=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y +CONFIG_PHY=y +CONFIG_PHY_IMX93_MIPI_DPHY=y +CONFIG_MIPI_DPHY_HELPERS=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_DW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig new file mode 100644 index 0000000000..593c6c17c8 --- /dev/null +++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig @@ -0,0 +1,182 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-9x9-qsb-ontat-wvga-panel" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_9X9_QSB=y +CONFIG_IMX9_DRAM_INLINE_ECC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y + +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SIMPLE_PANEL=y +CONFIG_VIDEO_IMX93_PARALLEL_DISPLAY_FORMAT=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index ea89c10c78..11caf14fd9 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -176,7 +176,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 +#ifdef CONFIG_IMX9_DRAM_INLINE_ECC +#define PHYS_SDRAM_SIZE 0x70000000 /* 1/8 DDR is used by ECC */ +#else #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h index 4a6a321568..ed17090c54 100644 --- a/include/configs/imx93_qsb.h +++ b/include/configs/imx93_qsb.h @@ -167,7 +167,11 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 +#ifdef CONFIG_IMX9_DRAM_INLINE_ECC +#define PHYS_SDRAM_SIZE 0x70000000 /* 1/8 DDR is used by ECC */ +#else #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 -- cgit v1.2.3 From 320096439b63134c293092b835454bac10cffb40 Mon Sep 17 00:00:00 2001 From: Ji Luo Date: Mon, 10 Oct 2022 19:13:53 +0800 Subject: MA-20738 imx8ulp: bumps CONFIG_LMB_MAX_REGIONS defualt reserved memory region limit (8) is not enough after adding ramoops reserved memory node, this commit bumps the CONFIG_LMB_MAX_REGIONS. Change-Id: Iba5113dcd5b81e70a75342d7aaf8d68140ed29e4 Signed-off-by: Ji Luo --- configs/imx8ulp_9x9_evk_android_defconfig | 1 + configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig | 1 + configs/imx8ulp_evk_android_defconfig | 1 + configs/imx8ulp_evk_android_dual_defconfig | 1 + configs/imx8ulp_evk_android_trusty_defconfig | 1 + configs/imx8ulp_evk_android_trusty_dual_defconfig | 1 + configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig | 1 + configs/imx8ulp_watch_android_defconfig | 1 + configs/imx8ulp_watch_android_dual_defconfig | 1 + configs/imx8ulp_watch_android_trusty_dual_defconfig | 1 + 10 files changed, 10 insertions(+) diff --git a/configs/imx8ulp_9x9_evk_android_defconfig b/configs/imx8ulp_9x9_evk_android_defconfig index 7f326aacf1..0fcdcad4bb 100644 --- a/configs/imx8ulp_9x9_evk_android_defconfig +++ b/configs/imx8ulp_9x9_evk_android_defconfig @@ -149,3 +149,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig index 6dc7a0d6cf..99c61f4228 100644 --- a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig @@ -156,3 +156,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_evk_android_defconfig b/configs/imx8ulp_evk_android_defconfig index df603245f0..57fa5ff1a8 100644 --- a/configs/imx8ulp_evk_android_defconfig +++ b/configs/imx8ulp_evk_android_defconfig @@ -149,3 +149,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_evk_android_dual_defconfig b/configs/imx8ulp_evk_android_dual_defconfig index 1fef689c74..e7050ab71c 100644 --- a/configs/imx8ulp_evk_android_dual_defconfig +++ b/configs/imx8ulp_evk_android_dual_defconfig @@ -150,3 +150,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_DUAL_BOOTLOADER=y CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_evk_android_trusty_defconfig b/configs/imx8ulp_evk_android_trusty_defconfig index 5e54aca9d7..f624bedc72 100644 --- a/configs/imx8ulp_evk_android_trusty_defconfig +++ b/configs/imx8ulp_evk_android_trusty_defconfig @@ -155,3 +155,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_evk_android_trusty_dual_defconfig b/configs/imx8ulp_evk_android_trusty_dual_defconfig index 93ca30df1d..8e7d7797bd 100644 --- a/configs/imx8ulp_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_evk_android_trusty_dual_defconfig @@ -156,3 +156,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig b/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig index 1693cc577c..b6b358546d 100644 --- a/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig +++ b/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig @@ -157,3 +157,4 @@ CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_watch_android_defconfig b/configs/imx8ulp_watch_android_defconfig index 3d7a8c2a56..1197272579 100644 --- a/configs/imx8ulp_watch_android_defconfig +++ b/configs/imx8ulp_watch_android_defconfig @@ -136,3 +136,4 @@ CONFIG_ANDROID_AB_SUPPORT=y CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_watch_android_dual_defconfig b/configs/imx8ulp_watch_android_dual_defconfig index c268a330de..60dffc0c15 100644 --- a/configs/imx8ulp_watch_android_dual_defconfig +++ b/configs/imx8ulp_watch_android_dual_defconfig @@ -137,3 +137,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_DUAL_BOOTLOADER=y +CONFIG_LMB_MAX_REGIONS=9 diff --git a/configs/imx8ulp_watch_android_trusty_dual_defconfig b/configs/imx8ulp_watch_android_trusty_dual_defconfig index 80b5d52c1b..ab439b3943 100644 --- a/configs/imx8ulp_watch_android_trusty_dual_defconfig +++ b/configs/imx8ulp_watch_android_trusty_dual_defconfig @@ -143,3 +143,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="watch_8ulp" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="WATCH_8ULP" CONFIG_DUAL_BOOTLOADER=y +CONFIG_LMB_MAX_REGIONS=9 -- cgit v1.2.3 From 4998fef38a58037e35bd3d6ed0c47295768c21aa Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 Oct 2022 11:22:46 +0800 Subject: Revert "MLK-25478-3 workaround: disable verify time of signer and signee." SR-IR-2.0 not need this patch This reverts commit 2bcca1ad5625388b631122593b3c54c43a9af7eb. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- lib/crypto/pkcs7_verify.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/crypto/pkcs7_verify.c b/lib/crypto/pkcs7_verify.c index 54c677bcad..82c5c745d4 100644 --- a/lib/crypto/pkcs7_verify.c +++ b/lib/crypto/pkcs7_verify.c @@ -529,6 +529,7 @@ static int pkcs7_verify_one(struct pkcs7_message *pkcs7, if (sinfo->signing_time < sinfo->signer->valid_from || sinfo->signing_time > sinfo->signer->valid_to) { pr_warn("Message signed outside of X.509 validity window\n"); + return -EKEYREJECTED; } } -- cgit v1.2.3 From e1ed0611b5e8a54690c5fd2711e1cfd04e857672 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 Oct 2022 11:23:16 +0800 Subject: Revert "MLK-25478-2 efi: clean memory and reset MemoryOverwriteRequestControl" SR-IR-2.0 not need this patch This reverts commit 88068edd5f50462970aad47e0f53b463fc94b60e. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- lib/efi_loader/efi_setup.c | 37 +------------------------------------ 1 file changed, 1 insertion(+), 36 deletions(-) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 366c219f53..617f4fda9d 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -8,16 +8,12 @@ #define LOG_CATEGORY LOGC_EFI #include -#include #include #include #include -#include #define OBJ_LIST_NOT_INITIALIZED 1 -DECLARE_GLOBAL_DATA_PTR; - efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED; /* @@ -193,43 +189,12 @@ static efi_status_t efi_init_memory_only_reset_control(void) efi_status_t ret; efi_uintn_t data_size = 0; - data_size = sizeof(memory_only_reset_control); ret = efi_get_variable_int(L"MemoryOverwriteRequestControl", &efi_memory_only_reset_control_guid, NULL, &data_size, &memory_only_reset_control, NULL); - if (ret == EFI_SUCCESS) { - if (memory_only_reset_control & 0x01) { - struct bd_info *bd = gd->bd; - int i; - void *start, *buf; - ulong count; - - memory_only_reset_control = memory_only_reset_control & (~(0x01)); - ret = efi_set_variable_int(L"MemoryOverwriteRequestControl", - &efi_memory_only_reset_control_guid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS | - EFI_VARIABLE_NON_VOLATILE, - sizeof(memory_only_reset_control), - &memory_only_reset_control, 0); - - for (i = CONFIG_NR_DRAM_BANKS - 1; i > 0; --i) { - count = bd->bi_dram[i].size; - if (!count) - continue; - start = map_sysmem(bd->bi_dram[i].start, count); - buf = start; - while (count > 0) { - *((u8 *)buf) = 0; - buf += 1; - count--; - } - unmap_sysmem(start); - } - } + if (ret == EFI_SUCCESS) return ret; - } ret = efi_set_variable_int(L"MemoryOverwriteRequestControl", &efi_memory_only_reset_control_guid, -- cgit v1.2.3 From 361b23b98ed8675abce0bb2680118863aa954852 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 Oct 2022 11:23:22 +0800 Subject: Revert "MLK-25478-1 efi: add Platform-Reset-Attack variables" SR-IR-2.0 not need this patch This reverts commit 7781c5a2b964a42c3057f4ebcb936e4bea83f530. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- include/efi_api.h | 4 ---- include/efi_loader.h | 2 -- lib/efi_loader/efi_image_loader.c | 1 - lib/efi_loader/efi_setup.c | 36 ------------------------------------ 4 files changed, 43 deletions(-) diff --git a/include/efi_api.h b/include/efi_api.h index 0227bdcfae..83c01085fd 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -226,10 +226,6 @@ enum efi_reset_type { EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \ 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a) -#define EFI_MEMORY_ONLY_RESET_CONTROL_GUID \ - EFI_GUID(0xe20939be, 0x32d4, 0x41be, 0xa1, 0x50, \ - 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29) - struct efi_capsule_header { efi_guid_t capsule_guid; u32 header_size; diff --git a/include/efi_loader.h b/include/efi_loader.h index 6f03a912f4..c52ea59ec7 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -312,8 +312,6 @@ extern const efi_guid_t efi_guid_firmware_management_protocol; extern const efi_guid_t efi_esrt_guid; /* GUID of the SMBIOS table */ extern const efi_guid_t smbios_guid; -/* GUID of memory only reset control */ -extern const efi_guid_t efi_memory_only_reset_control_guid; extern char __efi_runtime_start[], __efi_runtime_stop[]; extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[]; diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index b7b9aea6d3..9611398885 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -27,7 +27,6 @@ const efi_guid_t efi_guid_loaded_image_device_path = const efi_guid_t efi_simple_file_system_protocol_guid = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID; -const efi_guid_t efi_memory_only_reset_control_guid = EFI_MEMORY_ONLY_RESET_CONTROL_GUID; static int machines[] = { #if defined(__aarch64__) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 617f4fda9d..eee54e4878 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -175,37 +175,6 @@ static efi_status_t efi_init_os_indications(void) } -/** - * efi_init_memory_only_reset_control() - indicate supported features for - * OS requests - * - * Set the MemoryOverwriteRequestControl variable. - * - * Return: status code - */ -static efi_status_t efi_init_memory_only_reset_control(void) -{ - u8 memory_only_reset_control = 0; - efi_status_t ret; - efi_uintn_t data_size = 0; - - ret = efi_get_variable_int(L"MemoryOverwriteRequestControl", - &efi_memory_only_reset_control_guid, - NULL, &data_size, - &memory_only_reset_control, NULL); - if (ret == EFI_SUCCESS) - return ret; - - ret = efi_set_variable_int(L"MemoryOverwriteRequestControl", - &efi_memory_only_reset_control_guid, - EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS | - EFI_VARIABLE_NON_VOLATILE, - sizeof(memory_only_reset_control), - &memory_only_reset_control, 0); - return ret; -} - /** * efi_init_obj_list() - Initialize and populate EFI object list * @@ -257,11 +226,6 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; - /* Platform Reset Attack features */ - ret = efi_init_memory_only_reset_control(); - if (ret != EFI_SUCCESS) - goto out; - /* Initialize system table */ ret = efi_initialize_system_table(); if (ret != EFI_SUCCESS) -- cgit v1.2.3 From 957bdd9c9250c4d27087bb984a60738829a25c28 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 11 Oct 2022 15:37:09 +0800 Subject: LFU-418 imx8ulp: upower_hal: make code cleaner Align format Check err_code Add more log Detail the memory magic number Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 101 ++++++++++++++++++++++---- 1 file changed, 85 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c index 965a444e77..ee215a4c76 100644 --- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c @@ -142,6 +142,7 @@ int upower_init(void) u32 fw_major, fw_minor, fw_vfixes; u32 soc_id; int status; + upwr_resp_t err_code; uint32_t swton; uint64_t memon; @@ -180,22 +181,86 @@ int upower_init(void) if (ret) printf("Turn on switches fail %d\n", ret); else - printf("Turn on switches ok\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + printf("Turning on switches...\n"); + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Turn on switches faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Turn on switches ok\n"); - memon = 0x3FFFFFFFFFFFFCUL; + /* + * Ascending Order -> bit [0:54) + * CA35 Core 0 L1 cache + * CA35 Core 1 L1 cache + * L2 Cache 0 + * L2 Cache 1 + * L2 Cache victim/tag + * CAAM Secure RAM + * DMA1 RAM + * FlexSPI2 FIFO, Buffer + * SRAM0 + * AD ROM + * USB0 TX/RX RAM + * uSDHC0 FIFO RAM + * uSDHC1 FIFO RAM + * uSDHC2 FIFO and USB1 TX/RX RAM + * GIC RAM + * ENET TX FIXO + * Reserved(Brainshift) + * DCNano Tile2Linear and RGB Correction + * DCNano Cursor and FIFO + * EPDC LUT + * EPDC FIFO + * DMA2 RAM + * GPU2D RAM Group 1 + * GPU2D RAM Group 2 + * GPU3D RAM Group 1 + * GPU3D RAM Group 2 + * HIFI4 Caches, IRAM, DRAM + * ISI Buffers + * MIPI-CSI FIFO + * MIPI-DSI FIFO + * PXP Caches, Buffers + * SRAM1 + * Casper RAM + * DMA0 RAM + * FlexCAN RAM + * FlexSPI0 FIFO, Buffer + * FlexSPI1 FIFO, Buffer + * CM33 Cache + * PowerQuad RAM + * ETF RAM + * Sentinel PKC, Data RAM1, Inst RAM0/1 + * Sentinel ROM + * uPower IRAM/DRAM + * uPower ROM + * CM33 ROM + * SSRAM Partition 0 + * SSRAM Partition 1 + * SSRAM Partition 2,3,4 + * SSRAM Partition 5 + * SSRAM Partition 6 + * SSRAM Partition 7_a(128KB) + * SSRAM Partition 7_b(64KB) + * SSRAM Partition 7_c(64KB) + * Sentinel Data RAM0, Inst RAM2 + */ + /* MIPI-CSI FIFO BIT28 not set */ + memon = 0x3FFFFFEFFFFFFCUL; ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon /* no memories */, NULL /* no callback */); if (ret) printf("Turn on memories fail %d\n", ret); else - printf("Turn on memories ok\n"); - upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + printf("Turning on memories...\n"); + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Turn on memories faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Turn on memories ok\n"); mdelay(1); @@ -203,13 +268,14 @@ int upower_init(void) if (ret) printf("Clear DDR retention fail %d\n", ret); else - printf("Clear DDR retention ok\n"); + printf("Clearing DDR retention...\n"); upower_wait_resp(); - - ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, &ret_val, 1000); + ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Clear DDR retention fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Clear DDR retention ok\n"); if (is_soc_rev(CHIP_REV_1_0)) { /* Enable AFBB for AP domain */ @@ -220,12 +286,15 @@ int upower_init(void) if (ret) printf("Enable AFBB for APD bias fail %d\n", ret); else - printf("Enable AFBB for APD bias ok\n"); + printf("Enabling AFBB for APD bias...\n"); upower_wait_resp(); - ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000); if (ret != UPWR_REQ_OK) - printk("Faliure %d\n", ret); + printf("Enable AFBB fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + else + printf("Enable AFBB for APD bias ok\n"); + } return 0; -- cgit v1.2.3 From 4e7c44e1f33efeb22d6633d92097b2ff1d417497 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 11 Oct 2022 17:48:21 +0800 Subject: LFU-419 arm: dts: imx8mp: fix flexspi nand reg The address/reg should be 1 cell, so fix it. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/dts/imx8mp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index 2876b94b2a..4662d53183 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -979,7 +979,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mp-fspi-nand"; - reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; reg-names = "FlexSPI", "FlexSPI-memory"; status = "disabled"; }; -- cgit v1.2.3 From f824cd019558e90f74d328a4ef3cd09ebab76ab6 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 12 Oct 2022 13:56:58 +0800 Subject: LFU-415 net: fec_mxc: Skip recv packet process when fec is halted After FEC is halted by calling fec_halt callback, we should not continue receiving packet. Otherwise it will process previous pending interrupts on EIR register and uses wrong rbd index as this has been reset to 0. The GRA interrupt which is triggered by issuing graceful stop command to FEC transmitter in fec_halt is processed in this case. It causes wrong receive buffer desciptors be used by FEC in next time. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- drivers/net/fec_mxc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 84fbc43a37..b67569b7cd 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -884,6 +884,9 @@ static int fec_recv(struct eth_device *dev) ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); #endif + if (!(readl(&fec->eth->ecntrl) & FEC_ECNTRL_ETHER_EN)) + return 0; + /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); writel(ievent, &fec->eth->ievent); -- cgit v1.2.3 From 53689e4f7db578fc6e476a3af9a123f7dd3806c3 Mon Sep 17 00:00:00 2001 From: "faqiang.zhu" Date: Wed, 28 Sep 2022 16:57:54 +0800 Subject: MA-20667 set metadata partition of type f2fs The metadata partition needs to be formated as f2fs with the configuration of i.MX Android 13. Signed-off-by: faqiang.zhu --- drivers/fastboot/fb_fsl/fb_fsl_partitions.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c index 0cad38e993..a43c70db93 100644 --- a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c +++ b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c @@ -125,10 +125,9 @@ static int _fastboot_parts_add_ptable_entry(int ptable_index, !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE)) #endif strcpy(ptable[ptable_index].fstype, "erofs"); - else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA)) + else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA)) strcpy(ptable[ptable_index].fstype, "f2fs"); - else if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA)) - strcpy(ptable[ptable_index].fstype, "ext4"); else strcpy(ptable[ptable_index].fstype, "raw"); return 0; -- cgit v1.2.3 From d9f477625d34a0ea9d8cfe3115d677c3c549d995 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Tue, 11 Oct 2022 12:54:00 +0530 Subject: LF-7332 armv8: SHA-256 using ARMv8 Crypto Extensions added support for SHA-256 hash algorithms using the ARM v8 SHA-256 instructions. Signed-off-by: Gaurav Jain --- arch/arm/Kconfig | 2 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/crypto/Kconfig | 6 ++ arch/arm/cpu/armv8/crypto/Makefile | 4 + arch/arm/cpu/armv8/crypto/sha2-ce-core.S | 157 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/crypto/sha2-ce-glue.c | 66 +++++++++++++ arch/arm/include/asm/macro.h | 40 ++++++++ arch/arm/mach-imx/imx8/Kconfig | 1 + include/crypto/sha2.h | 50 ++++++++++ include/crypto/sha256_base.h | 87 +++++++++++++++++ 10 files changed, 414 insertions(+) create mode 100644 arch/arm/cpu/armv8/crypto/Kconfig create mode 100644 arch/arm/cpu/armv8/crypto/Makefile create mode 100644 arch/arm/cpu/armv8/crypto/sha2-ce-core.S create mode 100644 arch/arm/cpu/armv8/crypto/sha2-ce-glue.c create mode 100644 include/crypto/sha2.h create mode 100644 include/crypto/sha256_base.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4e07fc88f6..39b6a2b1b5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2213,6 +2213,8 @@ source "arch/arm/cpu/armv7/Kconfig" source "arch/arm/cpu/armv8/Kconfig" +source "arch/arm/cpu/armv8/crypto/Kconfig" + source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-nexell/Kconfig" diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 85fe0475c8..6e1498b470 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ +obj-$(CONFIG_CRYPTO_SHA2_ARM64_CE) += crypto/ diff --git a/arch/arm/cpu/armv8/crypto/Kconfig b/arch/arm/cpu/armv8/crypto/Kconfig new file mode 100644 index 0000000000..379c673343 --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/Kconfig @@ -0,0 +1,6 @@ +if ARM64 + +config CRYPTO_SHA2_ARM64_CE + tristate "SHA-224/SHA-256 digest algorithm (ARMv8 Crypto Extensions)" + +endif diff --git a/arch/arm/cpu/armv8/crypto/Makefile b/arch/arm/cpu/armv8/crypto/Makefile new file mode 100644 index 0000000000..8b23b166ed --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CRYPTO_SHA2_ARM64_CE) += sha2-ce.o +sha2-ce-y := sha2-ce-glue.o sha2-ce-core.o diff --git a/arch/arm/cpu/armv8/crypto/sha2-ce-core.S b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S new file mode 100644 index 0000000000..ad76362dff --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/sha2-ce-core.S @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions + * + * Copyright (C) 2014 Linaro Ltd + * Copyright 2022 NXP + */ + +#include +#include + + .text + .arch armv8-a+crypto + + dga .req q20 + dgav .req v20 + dgb .req q21 + dgbv .req v21 + + t0 .req v22 + t1 .req v23 + + dg0q .req q24 + dg0v .req v24 + dg1q .req q25 + dg1v .req v25 + dg2q .req q26 + dg2v .req v26 + + .macro add_only, ev, rc, s0 + mov dg2v.16b, dg0v.16b + .ifeq \ev + add t1.4s, v\s0\().4s, \rc\().4s + sha256h dg0q, dg1q, t0.4s + sha256h2 dg1q, dg2q, t0.4s + .else + .ifnb \s0 + add t0.4s, v\s0\().4s, \rc\().4s + .endif + sha256h dg0q, dg1q, t1.4s + sha256h2 dg1q, dg2q, t1.4s + .endif + .endm + + .macro add_update, ev, rc, s0, s1, s2, s3 + sha256su0 v\s0\().4s, v\s1\().4s + add_only \ev, \rc, \s1 + sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s + .endm + + /* + * The SHA-256 round constants + */ + .section ".rodata", "a" + .align 4 +.Lsha2_rcon: + .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5 + .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5 + .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3 + .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174 + .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc + .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da + .word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7 + .word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967 + .word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13 + .word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85 + .word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3 + .word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070 + .word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5 + .word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3 + .word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208 + .word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 + + /* + * void sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src, + * int blocks) + */ + .text +ENTRY(sha2_ce_transform) + /* load round constants */ + adr_l x8, .Lsha2_rcon + ld1 { v0.4s- v3.4s}, [x8], #64 + ld1 { v4.4s- v7.4s}, [x8], #64 + ld1 { v8.4s-v11.4s}, [x8], #64 + ld1 {v12.4s-v15.4s}, [x8] + + /* load state */ + ld1 {dgav.4s, dgbv.4s}, [x0] + + /* load sha256_ce_state::finalize */ + ldr_l w4, sha256_ce_offsetof_finalize, x4 + ldr w4, [x0, x4] + + /* load input */ +0: ld1 {v16.4s-v19.4s}, [x1], #64 + sub w2, w2, #1 + +CPU_LE( rev32 v16.16b, v16.16b ) +CPU_LE( rev32 v17.16b, v17.16b ) +CPU_LE( rev32 v18.16b, v18.16b ) +CPU_LE( rev32 v19.16b, v19.16b ) + +1: add t0.4s, v16.4s, v0.4s + mov dg0v.16b, dgav.16b + mov dg1v.16b, dgbv.16b + + add_update 0, v1, 16, 17, 18, 19 + add_update 1, v2, 17, 18, 19, 16 + add_update 0, v3, 18, 19, 16, 17 + add_update 1, v4, 19, 16, 17, 18 + + add_update 0, v5, 16, 17, 18, 19 + add_update 1, v6, 17, 18, 19, 16 + add_update 0, v7, 18, 19, 16, 17 + add_update 1, v8, 19, 16, 17, 18 + + add_update 0, v9, 16, 17, 18, 19 + add_update 1, v10, 17, 18, 19, 16 + add_update 0, v11, 18, 19, 16, 17 + add_update 1, v12, 19, 16, 17, 18 + + add_only 0, v13, 17 + add_only 1, v14, 18 + add_only 0, v15, 19 + add_only 1 + + /* update state */ + add dgav.4s, dgav.4s, dg0v.4s + add dgbv.4s, dgbv.4s, dg1v.4s + + /* handled all input blocks? */ + cbz w2, 2f + b 0b + + /* + * Final block: add padding and total bit count. + * Skip if the input size was not a round multiple of the block size, + * the padding is handled by the C code in that case. + */ +2: cbz x4, 3f + ldr_l w4, sha256_ce_offsetof_count, x4 + ldr x4, [x0, x4] + movi v17.2d, #0 + mov x8, #0x80000000 + movi v18.2d, #0 + ror x7, x4, #29 // ror(lsl(x4, 3), 32) + fmov d16, x8 + mov x4, #0 + mov v19.d[0], xzr + mov v19.d[1], x7 + b 1b + + /* store new state */ +3: st1 {dgav.4s, dgbv.4s}, [x0] + mov w0, w2 + ret +ENDPROC(sha2_ce_transform) diff --git a/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c b/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c new file mode 100644 index 0000000000..31e436ef1d --- /dev/null +++ b/arch/arm/cpu/armv8/crypto/sha2-ce-glue.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha2-ce-glue.c - SHA-256 using ARMv8 Crypto Extensions + * + * Copyright (C) 2014 - 2017 Linaro Ltd + * Copyright 2022 NXP + */ + +#include +#include +#include + +struct sha256_ce_state { + struct sha256_state sst; + u32 finalize; +}; + +extern const u32 sha256_ce_offsetof_count; +extern const u32 sha256_ce_offsetof_finalize; + +asmlinkage int sha2_ce_transform(struct sha256_ce_state *sst, u8 const *src, + int blocks); + +static void __sha2_ce_transform(struct sha256_state *sst, u8 const *src, + int blocks) +{ + while (blocks) { + int rem; + + rem = sha2_ce_transform(container_of(sst, struct sha256_ce_state, + sst), src, blocks); + src += (blocks - rem) * SHA256_BLOCK_SIZE; + blocks = rem; + } +} + +const u32 sha256_ce_offsetof_count = offsetof(struct sha256_ce_state, + sst.count); +const u32 sha256_ce_offsetof_finalize = offsetof(struct sha256_ce_state, + finalize); + +static void sha256_ce_update(struct sha256_ce_state *sctx, const u8 *data, + unsigned int len) +{ + sctx->finalize = 0; + sha256_base_do_update(&sctx->sst, data, len, __sha2_ce_transform); +} + +static void sha256_ce_final(struct sha256_ce_state *sctx, u8 *out) +{ + sctx->finalize = 0; + sha256_base_do_finalize(&sctx->sst, __sha2_ce_transform); + sha256_base_finish(&sctx->sst, out); +} + +/* + * Output = SHA-256( input buffer ). + */ +void sha256_ce(const unsigned char *input, unsigned int ilen, unsigned char *output) +{ + struct sha256_ce_state sctx; + + sha256_init(&sctx.sst); + sha256_ce_update(&sctx, input, ilen); + sha256_ce_final(&sctx, output); +} diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index ec0171e0e6..4e982892f8 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -3,6 +3,7 @@ * include/asm-arm/macro.h * * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * Copyright 2022 NXP */ #ifndef __ASM_ARM_MACRO_H__ @@ -356,6 +357,45 @@ lr .req x30 .endm #endif +/* + * Select code when configured for LE. + */ +#ifdef CONFIG_CPU_BIG_ENDIAN +#define CPU_LE(code...) +#else +#define CPU_LE(code...) code +#endif + +/* + * Pseudo-ops for PC-relative adr/ldr , where + * is within the range +/- 4 GB of the PC. + */ + /* + * @dst: destination register (64 bit wide) + * @sym: name of the symbol + */ + .macro adr_l, dst, sym + adrp \dst, \sym + add \dst, \dst, :lo12:\sym + .endm + + /* + * @dst: destination register (32 or 64 bit wide) + * @sym: name of the symbol + * @tmp: optional 64-bit scratch register to be used if is a + * 32-bit wide register, in which case it cannot be used to hold + * the address + */ + .macro ldr_l, dst, sym, tmp= + .ifb \tmp + adrp \dst, \sym + ldr \dst, [\dst, :lo12:\sym] + .else + adrp \tmp, \sym + ldr \dst, [\tmp, :lo12:\sym] + .endif + .endm + #endif /* CONFIG_ARM64 */ #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index a2f29ffa90..df383fe9b9 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -181,6 +181,7 @@ config TARGET_IMX8DXL_EVK bool "Support i.MX8DXL EVK board" select BOARD_LATE_INIT select IMX8DXL + select CRYPTO_SHA2_ARM64_CE select FSL_CAAM select FSL_BLOB select ARCH_MISC_INIT diff --git a/include/crypto/sha2.h b/include/crypto/sha2.h new file mode 100644 index 0000000000..1d787e16d9 --- /dev/null +++ b/include/crypto/sha2.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common values for SHA-2 algorithms + * + * Copyright 2022 NXP + */ + +#ifndef _CRYPTO_SHA2_H +#define _CRYPTO_SHA2_H + +#include + +#define SHA256_DIGEST_SIZE 32 +#define SHA256_BLOCK_SIZE 64 + +#define SHA256_H0 0x6a09e667UL +#define SHA256_H1 0xbb67ae85UL +#define SHA256_H2 0x3c6ef372UL +#define SHA256_H3 0xa54ff53aUL +#define SHA256_H4 0x510e527fUL +#define SHA256_H5 0x9b05688cUL +#define SHA256_H6 0x1f83d9abUL +#define SHA256_H7 0x5be0cd19UL + +struct sha256_state { + uint32_t state[SHA256_DIGEST_SIZE / 4]; + uint64_t count; + uint8_t buf[SHA256_BLOCK_SIZE]; +}; + +/* + * Stand-alone implementation of the SHA256 algorithm. + */ + +static inline void sha256_init(struct sha256_state *sctx) +{ + sctx->state[0] = SHA256_H0; + sctx->state[1] = SHA256_H1; + sctx->state[2] = SHA256_H2; + sctx->state[3] = SHA256_H3; + sctx->state[4] = SHA256_H4; + sctx->state[5] = SHA256_H5; + sctx->state[6] = SHA256_H6; + sctx->state[7] = SHA256_H7; + sctx->count = 0; +} + +void sha256_ce(const unsigned char *data, unsigned int ilen, unsigned char *output); + +#endif /* _CRYPTO_SHA2_H */ diff --git a/include/crypto/sha256_base.h b/include/crypto/sha256_base.h new file mode 100644 index 0000000000..f36a7929b3 --- /dev/null +++ b/include/crypto/sha256_base.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha256_base.h - core logic for SHA-256 implementations + * + * Copyright (C) 2015 Linaro Ltd + * Copyright 2022 NXP + */ + +#ifndef _CRYPTO_SHA256_BASE_H +#define _CRYPTO_SHA256_BASE_H + +#include +#include +#include +#include + +typedef void (sha256_block_fn)(struct sha256_state *sst, u8 const *src, + int blocks); + +static inline void sha256_base_do_update(struct sha256_state *sctx, + const u8 *data, + unsigned int len, + sha256_block_fn *block_fn) +{ + unsigned int partial = sctx->count % SHA256_BLOCK_SIZE; + + sctx->count += len; + + if ((partial + len) >= SHA256_BLOCK_SIZE) { + int blocks; + + if (partial) { + int p = SHA256_BLOCK_SIZE - partial; + + memcpy(sctx->buf + partial, data, p); + data += p; + len -= p; + + block_fn(sctx, sctx->buf, 1); + } + + blocks = len / SHA256_BLOCK_SIZE; + len %= SHA256_BLOCK_SIZE; + + if (blocks) { + block_fn(sctx, data, blocks); + data += blocks * SHA256_BLOCK_SIZE; + } + partial = 0; + } + if (len) + memcpy(sctx->buf + partial, data, len); +} + +static inline void sha256_base_do_finalize(struct sha256_state *sctx, + sha256_block_fn *block_fn) +{ + const int bit_offset = SHA256_BLOCK_SIZE - sizeof(__be64); + __be64 *bits = (__be64 *)(sctx->buf + bit_offset); + unsigned int partial = sctx->count % SHA256_BLOCK_SIZE; + + sctx->buf[partial++] = 0x80; + if (partial > bit_offset) { + memset(sctx->buf + partial, 0x0, SHA256_BLOCK_SIZE - partial); + partial = 0; + + block_fn(sctx, sctx->buf, 1); + } + + memset(sctx->buf + partial, 0x0, bit_offset - partial); + *bits = cpu_to_be64(sctx->count << 3); + block_fn(sctx, sctx->buf, 1); +} + +static inline void sha256_base_finish(struct sha256_state *sctx, u8 *out) +{ + unsigned int digest_size = SHA256_DIGEST_SIZE; + __be32 *digest = (__be32 *)out; + int i; + + for (i = 0; digest_size > 0; i++, digest_size -= sizeof(__be32)) + put_unaligned_be32(sctx->state[i], digest++); + + memset(sctx, 0x0, sizeof(*sctx)); +} + +#endif /* _CRYPTO_SHA256_BASE_H */ -- cgit v1.2.3 From 032fab5e1275422559b81bb79af44218c3faa3c2 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 12 Oct 2022 18:06:29 +0800 Subject: LFU-421 imx93_evk: Add imx93 low drive mode support on 11x11 EVK Add a static u-boot config for i.MX93 low drive mode support. When low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks, A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet max frequencies in low drive mode. The patch also updates kernel's DTB for the media AXI clock and USDHC root clocks. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx9/Kconfig | 5 + arch/arm/mach-imx/imx9/clock.c | 65 +- arch/arm/mach-imx/imx9/soc.c | 87 ++ board/freescale/imx93_evk/Makefile | 4 + board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1498 +++++++++++++++++++++++++ board/freescale/imx93_evk/spl.c | 19 +- configs/imx93_11x11_evk_ld_defconfig | 189 ++++ 7 files changed, 1855 insertions(+), 12 deletions(-) create mode 100644 board/freescale/imx93_evk/lpddr4x_timing_ld.c create mode 100644 configs/imx93_11x11_evk_ld_defconfig diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index d4dca5fd95..f4fc1ac5ce 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -5,6 +5,11 @@ config AHAB_BOOT help This option enables the support for AHAB secure boot. +config IMX9_LOW_DRIVE_MODE + bool "Configure to i.MX9 low drive mode" + help + This option enables the settings for iMX9 low drive mode. + config IMX9 bool select ARCH_EARLY_INIT_R diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 62f2f1b93b..909a770e1c 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -553,6 +553,13 @@ void set_arm_core_max_clk(void) ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); } +void set_arm_core_low_drive_clk(void) +{ + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, 900000000); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -625,21 +632,26 @@ void init_uart_clk(u32 index) void init_clk_usdhc(u32 index) { - /* 400 Mhz */ + u32 div; + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + div = 3; /* 266.67 Mhz */ + else + div = 2; /* 400 Mhz */ + switch (index) { case 0: ccm_lpcg_on(CCGR_USDHC1, 0); - ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div); ccm_lpcg_on(CCGR_USDHC1, 1); break; case 1: ccm_lpcg_on(CCGR_USDHC2, 0); - ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div); ccm_lpcg_on(CCGR_USDHC2, 1); break; case 2: ccm_lpcg_on(CCGR_USDHC3, 0); - ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2); + ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div); ccm_lpcg_on(CCGR_USDHC3, 1); break; default: @@ -698,7 +710,36 @@ void dram_disable_bypass(void) } #endif -int clock_init(void) +void bus_clock_init_low_drive(void) +{ + /* Set A55 clk to 500M */ + ccm_clk_root_cfg(ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2); + /* Set A55 periphal to 200M */ + ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4); + /* Set A55 mtr bus to 133M */ + ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + + /* Sentinel to 133M */ + ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_wakeup to 133M */ + ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* Bus_AON to 133M */ + ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 to 133M */ + ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* WAKEUP_AXI to 200M */ + ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4); + /* SWO TRACE to 133M */ + ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); + /* NIC to 250M */ + ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD0, 4); + /* NIC_APB to 133M */ + ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); +} + +void bus_clock_init(void) { /* Set A55 periphal to 333M */ ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); @@ -717,12 +758,22 @@ int clock_init(void) ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); /* SWO TRACE to 133M */ ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); - /* M33 systetick to 133M */ - ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); + /* M33 systetick to 24M */ + ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); /* NIC to 400M */ ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); /* NIC_APB to 133M */ ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); +} + +int clock_init(void) +{ + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + bus_clock_init_low_drive(); + set_arm_core_low_drive_clk(); + } else { + bus_clock_init(); + } /* allow for non-secure access */ int i; diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 11220799ae..6f2613d5bf 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -726,6 +726,91 @@ static int disable_cpu_nodes(void *blob, u32 disabled_cores) return 0; } +struct low_drive_freq_entry { + const char *node_path; + u32 clk; + u32 new_rate; +}; + +static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32 new_rate) +{ +#define MAX_ASSIGNED_CLKS 8 + int cnt, j; + u32 assignedclks[MAX_ASSIGNED_CLKS]; /* max 8 clocks*/ + + cnt = fdtdec_get_int_array_count(fdt, node_off, "assigned-clock-rates", + assignedclks, MAX_ASSIGNED_CLKS); + if (cnt > 0) { + if (cnt <= clk_index) + return -ENOENT; + + if (assignedclks[clk_index] <= new_rate) + return 0; + + assignedclks[clk_index] = new_rate; + for (j = 0; j < cnt; j++) + assignedclks[j] = cpu_to_fdt32(assignedclks[j]); + + return fdt_setprop(fdt, node_off, "assigned-clock-rates", &assignedclks, cnt * sizeof(u32)); + } + + return -ENOENT; +} + +static int low_drive_freq_update(void *blob) +{ + int nodeoff, ret; + int i; + + /* Update kernel dtb clocks for low drive mode */ + struct low_drive_freq_entry table[] = { + {"/soc@0/lcd-controller@4ae30000", 2, 200000000}, + {"/soc@0/bus@42800000/camera/isi@4ae40000", 0, 200000000}, + {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, + }; + + for (i = 0; i < ARRAY_SIZE(table); i++) { + nodeoff = fdt_path_offset(blob, table[i].node_path); + if (nodeoff >= 0) { + ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk, table[i].new_rate); + if (!ret) + printf("%s freq updated\n", table[i].node_path); + } + } + + return 0; +} + +#ifdef CONFIG_OF_BOARD_FIXUP +#ifndef CONFIG_SPL_BUILD +int board_fix_fdt(void *fdt) +{ + /* Update u-boot dtb clocks for low drive mode */ + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + int nodeoff; + int i; + + struct low_drive_freq_entry table[] = { + {"/soc@0/lcd-controller@4ae30000", 0, 200000000}, + {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, + {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, + }; + + for (i = 0; i < ARRAY_SIZE(table); i++) { + nodeoff = fdt_path_offset(fdt, table[i].node_path); + if (nodeoff >= 0) + low_drive_fdt_fix_clock(fdt, nodeoff, table[i].clk, table[i].new_rate); + } + } + + return 0; +} +#endif +#endif + int ft_system_setup(void *blob, struct bd_info *bd) { if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311()) @@ -734,6 +819,8 @@ int ft_system_setup(void *blob, struct bd_info *bd) if (is_imx9332() || is_imx9331() || is_imx9312() || is_imx9311()) disable_npu_nodes(blob); + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + low_drive_freq_update(blob); return ft_add_optee_node(blob, bd); } diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile index 575f8e9460..17956d24bf 100644 --- a/board/freescale/imx93_evk/Makefile +++ b/board/freescale/imx93_evk/Makefile @@ -8,5 +8,9 @@ obj-y += imx93_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +ifdef CONFIG_IMX9_LOW_DRIVE_MODE +obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o +else obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o endif +endif diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c b/board/freescale/imx93_evk/lpddr4x_timing_ld.c new file mode 100644 index 0000000000..78d40cd6d9 --- /dev/null +++ b/board/freescale/imx93_evk/lpddr4x_timing_ld.c @@ -0,0 +1,1498 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from IMX_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44140001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000512 }, + { 0x4e300084, 0x0 }, + { 0x4e300114, 0x2 }, + { 0x4e300260, 0x0 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300104, 0xaa77000e }, + { 0x4e300108, 0x1816b1aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300100, 0x12552100 }, + { 0x4e300160, 0x9002 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0xaa00aa }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x11281109 }, + { 0x4e300304, 0xaa110a }, + { 0x4e300308, 0x620071e }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x5ff }, + { 0x1015f, 0x5ff }, + { 0x1105f, 0x5ff }, + { 0x1115f, 0x5ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x10049, 0xe00 }, + { 0x10149, 0xe00 }, + { 0x11049, 0xe00 }, + { 0x11149, 0xe00 }, + { 0x43, 0x60 }, + { 0x1043, 0x60 }, + { 0x2043, 0x60 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x1d3 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x20021, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x74a }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x1bb4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1f46 }, + { 0x5401c, 0x1708 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x1bb4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1f46 }, + { 0x54022, 0x1708 }, + { 0x54024, 0x6 }, + { 0x54032, 0xb400 }, + { 0x54033, 0x321b }, + { 0x54034, 0x4600 }, + { 0x54035, 0x81f }, + { 0x54036, 0x17 }, + { 0x54037, 0x600 }, + { 0x54038, 0xb400 }, + { 0x54039, 0x321b }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x81f }, + { 0x5403c, 0x17 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x0 }, + { 0x2000b, 0x20c }, + { 0x2000c, 0x74 }, + { 0x2000d, 0x48e }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 1866mts 2D */ + .drate = 1866, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1866, }, +}; + diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 2d2900c6e0..9a041af30e 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -70,10 +70,17 @@ int power_init_board(void) /* enable DVS control through PMIC_STBY_REQ */ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - /* 0.9v - */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + /* 0.75v for Low drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); + } else { + /* 0.9v for Over drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + } /* set standby voltage to 0.65v */ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); @@ -111,9 +118,11 @@ void board_init_f(ulong dummy) printf("SOC: 0x%x\n", gd->arch.soc_rev); printf("LC: 0x%x\n", gd->arch.lifecycle); } + power_init_board(); - set_arm_core_max_clk(); + if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_core_max_clk(); /* Init power of mix */ soc_power_init(); diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig new file mode 100644 index 0000000000..aa1c4984a0 --- /dev/null +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -0,0 +1,189 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_USB_TCPC=y +CONFIG_TARGET_IMX93_11X11_EVK=y +CONFIG_IMX9_LOW_DRIVE_MODE=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CRC32=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y + +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_USB_PORT_AUTO=y + +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_IMX_RGPIO2P=y +CONFIG_HUSH_PARSER=y +CONFIG_CLK_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_ADP5585_GPIO=y + +CONFIG_POWER_DOMAIN=y +CONFIG_IMX93_BLK_CTRL=y +CONFIG_PHY=y +CONFIG_PHY_IMX93_MIPI_DPHY=y +CONFIG_MIPI_DPHY_HELPERS=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_DW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_VIDEO_LOGO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_DEKBLOB=y +CONFIG_IMX_ELE_DEK_ENCAP=y +CONFIG_IMX_TMU=y +CONFIG_DM_THERMAL=y + +CONFIG_OF_BOARD_FIXUP=y -- cgit v1.2.3 From c6c06de038ff0f10b80e9c0cc40d5645aed95162 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 17 Oct 2022 16:58:10 +0800 Subject: LFU-422-1 mtd: spi-nor: Add GigaDevice GD25LX256E NOR flash Add the NOR flash id for GD25LX256E which has 32MB size, supports 4 Bytes address mode and OCTAL I/O Signed-off-by: Ye Li Reviewed-by: Peng Fan --- drivers/mtd/spi/spi-nor-ids.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7524337746..86a1c4c81b 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -136,6 +136,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- cgit v1.2.3 From 0a99627b60e9e7ea8b798602425749e62be127d6 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 17 Oct 2022 17:02:37 +0800 Subject: LFU-422-2 imx8ulp_evk: Enable the GD25LX256E support Due to the EOL of ATXP032, i.MX8ULP EVK board will change to use GD25LX256E flash at flexspi0 for RTD. As u-boot is used for UUU to burn the RTD image, so update defconfig to support the new flash. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- configs/imx8ulp_9x9_evk_defconfig | 1 + configs/imx8ulp_9x9_evk_i3c_defconfig | 1 + configs/imx8ulp_evk_defconfig | 1 + configs/imx8ulp_evk_i3c_defconfig | 1 + configs/imx8ulp_evk_nd_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/configs/imx8ulp_9x9_evk_defconfig b/configs/imx8ulp_9x9_evk_defconfig index 0927a46e1f..f1f5a3cf24 100644 --- a/configs/imx8ulp_9x9_evk_defconfig +++ b/configs/imx8ulp_9x9_evk_defconfig @@ -71,6 +71,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y diff --git a/configs/imx8ulp_9x9_evk_i3c_defconfig b/configs/imx8ulp_9x9_evk_i3c_defconfig index 45a1f77e33..5011a6f812 100644 --- a/configs/imx8ulp_9x9_evk_i3c_defconfig +++ b/configs/imx8ulp_9x9_evk_i3c_defconfig @@ -72,6 +72,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index fabc6c15c7..b5c76f8129 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -71,6 +71,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y diff --git a/configs/imx8ulp_evk_i3c_defconfig b/configs/imx8ulp_evk_i3c_defconfig index 7eeeb0668b..2f70101317 100644 --- a/configs/imx8ulp_evk_i3c_defconfig +++ b/configs/imx8ulp_evk_i3c_defconfig @@ -73,6 +73,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y diff --git a/configs/imx8ulp_evk_nd_defconfig b/configs/imx8ulp_evk_nd_defconfig index b886326571..bd454f3cb2 100644 --- a/configs/imx8ulp_evk_nd_defconfig +++ b/configs/imx8ulp_evk_nd_defconfig @@ -71,6 +71,7 @@ CONFIG_NXP_FSPI=y CONFIG_SPI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_PHYLIB=y -- cgit v1.2.3 From ae396d343a39374269b28fc572daf04d86b9589c Mon Sep 17 00:00:00 2001 From: WeiLu Date: Tue, 18 Oct 2022 11:10:11 +0800 Subject: LF-6627: nand drvier fixups in nandboot on ls1043ardb-pd Signed-off-by: WeiLu --- board/freescale/ls1043ardb/ls1043ardb.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index c6d2b85e55..1ac86b6904 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -368,7 +368,20 @@ void nand_fixup() csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224; #ifdef CONFIG_TFABOOT - set_ifc_csor(IFC_CS1, csor); + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x25) + set_ifc_csor(IFC_CS1, csor); + else if (cfg_rcw_src == 0x118) + set_ifc_csor(IFC_CS0, csor); + else + printf("Invalid setting\n"); #else #ifdef CONFIG_NAND_BOOT set_ifc_csor(IFC_CS0, csor); -- cgit v1.2.3 From 58ba744cbad09fd307f73425eb4e4c2310db28cc Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 18 Oct 2022 17:16:29 +0800 Subject: MLK-26034 imx6: Disable LCDIF clock before jumping to kernel Disable LCDIF axi clock and pix clock CCGR before jumping to kernel to avoid potential MUX glitch issue on CSCDR2 LCDIF_PRE_CLK_SEL mux. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- board/freescale/mx6sllevk/mx6sllevk.c | 7 +++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 8 ++++++++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 8 ++++++++ board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 7 +++++++ board/freescale/mx6ullevk/mx6ullevk.c | 7 +++++++ 5 files changed, 37 insertions(+) diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index 22e43dffe7..f6467d40fc 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -408,3 +408,10 @@ int checkboard(void) return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(MX6SLL_LCDIF_BASE_ADDR, 0); +#endif +} diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 9c355e4e23..4460117380 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -458,3 +458,11 @@ int checkboard(void) return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(MX6SX_LCDIF1_BASE_ADDR, 0); + enable_lcdif_clock(LCDIF2_BASE_ADDR, 0); +#endif +} diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 7e1c538677..8e725ff882 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -794,3 +794,11 @@ int checkboard(void) #endif return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(MX6SX_LCDIF1_BASE_ADDR, 0); + enable_lcdif_clock(LCDIF2_BASE_ADDR, 0); +#endif +} diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 221a1ba791..96d40af5da 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -446,6 +446,13 @@ void board_preboot_os(void) gpio_set_value(IMX_GPIO_NR(5, 9), 0); } +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(LCDIF1_BASE_ADDR, 0); +#endif +} + #ifdef CONFIG_SPL_BUILD #include #include diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index 72e4898ae8..23dbc67107 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -367,3 +367,10 @@ int checkboard(void) return 0; } + +void board_quiesce_devices(void) +{ +#if defined(CONFIG_VIDEO_MXS) + enable_lcdif_clock(LCDIF1_BASE_ADDR, 0); +#endif +} -- cgit v1.2.3 From 330e2634143a540cf9de07ef94343144b0429fb8 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 18 Oct 2022 16:07:26 +0800 Subject: LFU-423: usb: cdns3: gadget: Avoid using usb_ss after null check Fix Coverity Issue 22852965, in select_ep(), usb_ss pointer is used after the null check, here use printf instead dev_err to avoid using usb_ss after null check. Signed-off-by: Sherry Sun Reviewed-by: Ye Li --- drivers/usb/cdns3/gadget.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 5bd80cf986..730454c66e 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -55,7 +55,7 @@ static struct usb_request *next_request(struct list_head *list) static void select_ep(struct usb_ss_dev *usb_ss, u32 ep) { if (!usb_ss || !usb_ss->regs) { - dev_err(&usb_ss->dev, "Failed to select endpoint!\n"); + printf("Failed to select endpoint!\n"); return; } -- cgit v1.2.3 From f3b75e3317d17180009af5c866b9a85a855a79be Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Wed, 12 Oct 2022 14:29:20 +0530 Subject: LF-7332 imx8/ahab: sha256: enable image verification using ARMv8 crypto extention add support for SHA-256 secure hash algorithm using the ARM v8 SHA-256 instructions for verifying image hash. Signed-off-by: Gaurav Jain --- arch/arm/mach-imx/imx8/ahab.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 3c3c4cdc4f..deb18a3bb2 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2022 NXP */ #include @@ -16,6 +16,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; #define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x60000000UL) #define SECO_PT 2U +#define AHAB_HASH_TYPE_MASK 0x00000700 +#define AHAB_HASH_TYPE_SHA256 0 int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { @@ -130,6 +133,9 @@ int authenticate_os_container(ulong addr) u16 length; struct boot_img_t *img; unsigned long s, e; +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + u8 hash_value[SHA256_DIGEST_SIZE]; +#endif if (addr % 4) { puts("Error: Image's address is not 4 byte aligned\n"); @@ -179,9 +185,23 @@ int authenticate_os_container(ulong addr) flush_dcache_range(s, e); +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + if (((img->hab_flags & AHAB_HASH_TYPE_MASK) >> 8) == AHAB_HASH_TYPE_SHA256) { + sha256_ce((void *)img->dst, img->size, hash_value); + err = memcmp(&img->hash, &hash_value, SHA256_DIGEST_SIZE); + if (err) { + printf("img %d hash comparison failed, error %d\n", i, err); + ret = -EIO; + goto exit; + } + } else { +#endif ret = ahab_verify_cntr_image(img, i); if (ret) goto exit; +#ifdef CONFIG_CRYPTO_SHA2_ARM64_CE + } +#endif } exit: -- cgit v1.2.3 From 15b1ebb00cc05eab9a13ac1ff790b0d4ac4b4d35 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 18 Oct 2022 12:06:19 +0800 Subject: LFU-393 imx93: Add reset cause print Add reset cause print to u-boot log on i.MX93. Since the SRC GENERAL registers are read only for non-secure mode. We have to clear SRSR in secure mode (SPL) and pass the value to non-secure mode via GPR1 register. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx9/soc.c | 55 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 6f2613d5bf..94351f8cb8 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -562,10 +562,59 @@ const char *get_imx_type(u32 imxtype) } } +#define SRC_SRSR_RESET_CAUSE_NUM 16 +const char *reset_cause[SRC_SRSR_RESET_CAUSE_NUM] = { + "POR ", + "JTAG ", + "IPP USER ", + "WDOG1 ", + "WDOG2 ", + "WDOG3 ", + "WDOG4 ", + "WDOG5 ", + "TEMPSENSE ", + "CSU ", + "JTAG_SW ", + "M33_REQ ", + "M33_LOCKUP " + "UNK ", + "UNK ", + "UNK ", +}; + +static void save_reset_cause(void) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr = readl(&src->srsr); + writel(srsr, &src->srsr); /* clear srsr in sec mode */ + + /* Save value to GPR1 to pass to nonsecure */ + writel(srsr, &src->gpr[0]); +} + +static const char *get_reset_cause(u32 *srsr_ret) +{ + struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE; + u32 srsr; + u32 i; + + srsr = readl(&src->gpr[0]); + if (srsr_ret) + *srsr_ret = srsr; + + for (i = SRC_SRSR_RESET_CAUSE_NUM; i > 0; i--) { + if (srsr & (1 << (i - 1))) + return reset_cause[i - 1]; + } + + return "unknown reset"; +} + int print_cpuinfo(void) { u32 cpurev, max_freq; int minc, maxc; + u32 ssrs_ret; cpurev = get_cpu_rev(); @@ -616,6 +665,9 @@ int print_cpuinfo(void) #endif puts("\n"); + printf("Reset cause: %s", get_reset_cause(&ssrs_ret)); + printf("(0x%x)\n", ssrs_ret); + return 0; } @@ -845,6 +897,9 @@ int arch_cpu_init(void) clock_init(); trdc_early_init(); + + /* Save SRC SRSR to GPR1 and clear it */ + save_reset_cause(); } return 0; -- cgit v1.2.3 From 6933487b4df3fb864214a64bd6b1b33dfe26c98c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 19 Oct 2022 10:55:56 +0800 Subject: LFU-427 imx93: Print ELE FW version Print ELE FW version in uboot log for debug purpose Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx9/soc.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 94351f8cb8..02edced9aa 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -34,6 +34,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -671,8 +673,36 @@ int print_cpuinfo(void) return 0; } +void build_info(void) +{ + u32 fw_version, sha1, res, status; + int ret; + + printf("\nBuildInfo:\n"); + + ret = ahab_get_fw_status(&status, &res); + if (ret) { + printf(" - ELE firmware status failed %d, 0x%x\n", ret, res); + } else if ((status & 0xff) == 1) { + ret = ahab_get_fw_version(&fw_version, &sha1, &res); + if (ret) { + printf(" - ELE firmware version failed %d, 0x%x\n", ret, res); + } else { + printf(" - ELE firmware version %u.%u.%u-%x", + (fw_version & (0x00ff0000)) >> 16, + (fw_version & (0x0000ff00)) >> 8, + (fw_version & (0x000000ff)), sha1); + ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); + } + } else { + printf(" - ELE firmware not included\n"); + } + puts("\n"); +} + int arch_misc_init(void) { + build_info(); return 0; } -- cgit v1.2.3 From 94c5bb2eb83b09845ecefdc75797bdcde100c412 Mon Sep 17 00:00:00 2001 From: Ji Luo Date: Thu, 20 Oct 2022 17:06:16 +0800 Subject: MA-20507-7 trusty: fix dereference null return value This fixes the coverity issue: 22852960 Dereference null return value. Change-Id: I8186b49eb7f248476c4b8d3c773fbd2680da8367 Signed-off-by: Ji Luo --- lib/trusty/ql-tipc/keymaster.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/trusty/ql-tipc/keymaster.c b/lib/trusty/ql-tipc/keymaster.c index 3d026b0a23..282cb53cdb 100644 --- a/lib/trusty/ql-tipc/keymaster.c +++ b/lib/trusty/ql-tipc/keymaster.c @@ -690,6 +690,11 @@ int trusty_set_boot_patch_level(uint32_t boot_patch_level) int rc; req = trusty_calloc(4, 1); // 4 bytes should be enough. + if (!req) { + trusty_error("trusty_calloc memory failed!\n"); + return -1; + } + memcpy(req, &boot_patch_level, sizeof(uint32_t)); req_size = sizeof(uint32_t); -- cgit v1.2.3 From 676831be672105d08115b6827b6697b5b41cff9c Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Wed, 19 Oct 2022 16:37:11 +0800 Subject: LF-7369-1 clk: imx: implement a clock gate driver for i.MX93 Add a clock gate driver for i.MX93. Bit0 of LPCG_DIRECT controls the ON/OFF of LPCG when LPCG is in direct control mode. Bit[2:0] of LPCG_LPM_CUR controls the ON/OFF of LPCG when LPCG is already in CPULPM mode. Signed-off-by: Alice Guo Reviewed-by: Ye Li --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-gate-93.c | 146 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 3 + 3 files changed, 150 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-gate-93.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 2e44b249cb..4eebc34092 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -20,4 +20,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o +obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o clk-gate-93.o diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c new file mode 100644 index 0000000000..7b43f18e6e --- /dev/null +++ b/drivers/clk/imx/clk-gate-93.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Author: Alice Guo + */ + +#include +#include +#include +#include +#include + +#include "clk.h" + +#define LPCG_DIRECT 0x0 +#define LPCG_LPM_CUR 0x1c +#define LPM_SETTING_OFF 0x0 +#define LPM_SETTING_ON 0x4 +#define LPCG_AUTHEN 0x30 +#define WHITE_LIST_DM0 16 +#define DOMAIN_ID_A55 3 +#define TZ_NS BIT(9) +#define CPULPM_MOD BIT(2) + +struct imx93_clk_gate { + struct clk clk; + void __iomem *reg_base; + u8 lpcg_on_offset; + u8 lpcg_on_ctrl; + u8 lpcg_on_mask; + ulong flags; +}; + +#define to_imx93_clk_gate(_clk) container_of(_clk, struct imx93_clk_gate, clk) + +static bool imx93_clk_gate_check_authen(void __iomem *reg_base) +{ + u32 authen; + + authen = readl(reg_base + LPCG_AUTHEN); + if (!(authen & TZ_NS) || !(authen & BIT(WHITE_LIST_DM0 + DOMAIN_ID_A55))) + return false; + + return true; +} + +static void imx93_clk_gate_ctrl_hw(struct clk *clk, bool enable) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + u32 v; + + v = readl(gate->reg_base + LPCG_AUTHEN); + if (v & CPULPM_MOD) { + v = enable ? LPM_SETTING_ON : LPM_SETTING_OFF; + writel(v, gate->reg_base + LPCG_LPM_CUR); + } else { + v = readl(gate->reg_base + LPCG_DIRECT); + v &= ~(gate->lpcg_on_mask << gate->lpcg_on_offset); + if (enable) + v |= (gate->lpcg_on_ctrl & gate->lpcg_on_mask) << gate->lpcg_on_offset; + writel(v, gate->reg_base + LPCG_DIRECT); + } +} + +static int imx93_clk_gate_enable(struct clk *clk) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + + if (!imx93_clk_gate_check_authen(gate->reg_base)) + return -EINVAL; + + imx93_clk_gate_ctrl_hw(clk, true); + + return 0; +} + +static int imx93_clk_gate_disable(struct clk *clk) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + + if (!imx93_clk_gate_check_authen(gate->reg_base)) + return -EINVAL; + + imx93_clk_gate_ctrl_hw(clk, false); + + return 0; +} + +static ulong imx93_clk_gate_set_rate(struct clk *clk, ulong rate) +{ + struct clk *parent = clk_get_parent(clk); + + if (parent) + return clk_set_rate(parent, rate); + + return -ENODEV; +} + +static const struct clk_ops imx93_clk_gate_ops = { + .set_rate = imx93_clk_gate_set_rate, + .enable = imx93_clk_gate_enable, + .disable = imx93_clk_gate_disable, + .get_rate = clk_generic_get_rate, +}; + +static struct clk *register_clk_gate(const char *name, const char *parent_name, + void __iomem *reg_base, u8 lpcg_on_offset, + u8 lpcg_on_ctrl, u8 lpcg_on_mask, ulong flags) +{ + struct imx93_clk_gate *gate; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg_base = reg_base; + gate->lpcg_on_offset = lpcg_on_offset; + gate->lpcg_on_ctrl = lpcg_on_ctrl; + gate->lpcg_on_mask = lpcg_on_mask; + gate->flags = flags; + + ret = clk_register(&gate->clk, "imx93_clk_gate", name, parent_name); + if (ret) { + kfree(gate); + return ERR_PTR(ret); + } + + return &gate->clk; +} + +struct clk *clk_register_imx93_clk_gate(const char *name, const char *parent_name, + void __iomem *reg_base, u8 lpcg_on_offset, + ulong flags) +{ + return register_clk_gate(name, parent_name, reg_base, lpcg_on_offset, 1, + 1, flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); +} + +U_BOOT_DRIVER(imx93_clk_gate) = { + .name = "imx93_clk_gate", + .id = UCLASS_CLK, + .ops = &imx93_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index dd4df82125..e690756150 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -52,6 +52,9 @@ struct imx93_pll_fracn_gp { struct clk *clk_register_imx93_pll(const char *name, const char *parent_name, void __iomem *reg); +struct clk *clk_register_imx93_clk_gate(const char *name, const char *parent_name, + void __iomem *reg_base, u8 lpcg_on_offset, + ulong flags); struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, -- cgit v1.2.3 From f405551dcc12ef332c06da91ae30095f279015ef Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Thu, 20 Oct 2022 18:26:08 +0800 Subject: LF-7369-2 clk: imx93: update LPCG control API Use i.MX93 specific LPCG control API. Signed-off-by: Alice Guo Reviewed-by: Ye Li --- drivers/clk/imx/clk-imx93.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 87ba829841..f0d7f49a1f 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -407,8 +407,8 @@ static int imx93_clk_probe(struct udevice *dev) for (int i = 0; i < ARRAY_SIZE(clk_ccgrs); i++) { ccgr = &clk_ccgrs[i]; - clk = imx_clk_gate4_flags(ccgr->name, ccgr->parent_names, - ccm_base + ccgr->off, 0, ccgr->flags); + clk = clk_register_imx93_clk_gate(ccgr->name, ccgr->parent_names, + ccm_base + ccgr->off, 0, ccgr->flags); clk_dm(ccgr->clk_id, clk); } -- cgit v1.2.3 From 205680f9f4baabc030050ae14e7b2bb700a3ae70 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 24 Oct 2022 10:25:42 +0800 Subject: LFU-428 imx8ulp: Add warning for CAAM non-secure state failure When booting from OEM closed part, due to OTPMK not programmed correctly, CAAM is in non-secure state. Add a warning in SPL to indicate the problem to users. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- board/freescale/imx8ulp_evk/spl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index 40555f45be..0cbce593fd 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -169,6 +169,8 @@ void spl_board_init(void) /* Asks S400 to release CAAM for A35 core */ ret = ahab_release_caam(7, &res); if (!ret) { + if (((res >> 8) & 0xff) == ELE_NON_SECURE_STATE_FAILURE_IND) + printf("Warning: CAAM is in non-secure state, 0x%x\n", res); /* Only two UCLASS_MISC devicese are present on the platform. There * are MU and CAAM. Here we initialize CAAM once it's released by -- cgit v1.2.3 From e91a047f54f74061fa15d995c3ecceb940c45ada Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 24 Oct 2022 16:45:36 -0400 Subject: LF-7382: fastboot: improve emmc write speed tested at iMX8MM platfrom reduce almost half write time. (499s vs 1000s). About 1/4 improve at 8DXL platform. 100*512 = 51k, which small than emmc erase block size 64k, which may cause more page management in emmc. Increase to 4096, about 2M write to emmc each time. Signed-off-by: Frank Li Reviewed-by: Ye Li --- lib/image-sparse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/image-sparse.c b/lib/image-sparse.c index b255d3acc0..a90d51624e 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -55,7 +55,7 @@ static lbaint_t write_sparse_chunk_raw(struct sparse_storage *info, void *data, char *response) { - lbaint_t n = blkcnt, write_blks, blks = 0, aligned_buf_blks = 100; + lbaint_t n = blkcnt, write_blks, blks = 0, aligned_buf_blks = 4096; uint32_t *aligned_buf = NULL; if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { -- cgit v1.2.3 From 413b08f841f0366e42ffe57b1ff5e5053e6555b7 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Mon, 24 Oct 2022 16:48:17 -0500 Subject: MLK-25850: imx8dxl_ddr3l_evk: change the default fdt file name change the fdt file name with rpmsg postfix as the default. Signed-off-by: Han Xu Reviewed-by: Ye Li --- board/freescale/imx8dxl_evk/imx8dxl_evk.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/imx8dxl_evk/imx8dxl_evk.c b/board/freescale/imx8dxl_evk/imx8dxl_evk.c index 2acfd5dc96..eaf8b8e0d8 100644 --- a/board/freescale/imx8dxl_evk/imx8dxl_evk.c +++ b/board/freescale/imx8dxl_evk/imx8dxl_evk.c @@ -328,7 +328,10 @@ int board_late_init(void) if (fdt_file && !strcmp(fdt_file, "undefined")) { #if defined(CONFIG_TARGET_IMX8DXL_DDR3_EVK) - env_set("fdt_file", "imx8dxl-ddr3l-evk.dtb"); + if (m4_booted) + env_set("fdt_file", "imx8dxl-ddr3l-evk-rpmsg.dtb"); + else + env_set("fdt_file", "imx8dxl-ddr3l-evk.dtb"); #else if (m4_booted) env_set("fdt_file", "imx8dxl-evk-rpmsg.dtb"); -- cgit v1.2.3 From d23cfa097679acc00f2c28587c3473e8369e5227 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Tue, 25 Oct 2022 11:14:39 -0500 Subject: LFU-426: qspihdr: Coverity Issue: unchecked return value fix the unchecked return value(CWE-252) issue in qspihdr tool. Signed-off-by: Han Xu Reviewed-by: Ye Li --- arch/arm/mach-imx/cmd_qspihdr.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/cmd_qspihdr.c b/arch/arm/mach-imx/cmd_qspihdr.c index 6e2758664f..ef4a3cf113 100644 --- a/arch/arm/mach-imx/cmd_qspihdr.c +++ b/arch/arm/mach-imx/cmd_qspihdr.c @@ -235,6 +235,7 @@ static int do_qspihdr_check(int argc, char * const argv[], int flag) unsigned long addr; char *endp; void *tmp; + int ret; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) int off = QSPI_HDR_OFF + QSPI_HDR_TAG_OFF; @@ -266,7 +267,11 @@ static int do_qspihdr_check(int argc, char * const argv[], int flag) return 1; } } else { - spi_flash_read(flash, off, 4, &buf); + ret = spi_flash_read(flash, off, 4, &buf); + if (ret) { + printf("flash read failed, ret: %d\n", ret); + return -1; + } if (buf == tag) { if (flag & FLAG_VERBOSE) @@ -398,6 +403,7 @@ static int do_qspihdr_dump(int argc, char * const argv[]) char *endp; void *tmp; void *buf; + int ret; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) int off = QSPI_HDR_OFF; @@ -431,7 +437,11 @@ static int do_qspihdr_dump(int argc, char * const argv[]) return 0; } - spi_flash_read(flash, off, HDR_LEN, buf); + ret = spi_flash_read(flash, off, HDR_LEN, buf); + if (ret) { + printf("flash read failed, ret: %d\n", ret); + return -1; + } hdr_dump(buf); free(buf); -- cgit v1.2.3 From a6762e28bf07c1ebca51e7c366fa1a900e375996 Mon Sep 17 00:00:00 2001 From: WeiLu Date: Wed, 26 Oct 2022 11:44:51 +0800 Subject: LF-6627: nand drvier fixups in sdboot on ls1043ardb-pd Signed-off-by: WeiLu --- board/freescale/ls1043ardb/ls1043ardb.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 1ac86b6904..16cd8273c8 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -368,6 +368,7 @@ void nand_fixup() csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224; #ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); u8 cfg_rcw_src1, cfg_rcw_src2; u16 cfg_rcw_src; cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); @@ -380,8 +381,12 @@ void nand_fixup() set_ifc_csor(IFC_CS1, csor); else if (cfg_rcw_src == 0x118) set_ifc_csor(IFC_CS0, csor); - else - printf("Invalid setting\n"); + else { + if (src == BOOT_SOURCE_SD_MMC) + set_ifc_csor(IFC_CS1, csor); + else + printf("Invalid setting\n"); + } #else #ifdef CONFIG_NAND_BOOT set_ifc_csor(IFC_CS0, csor); -- cgit v1.2.3 From ed2c3cbd6ace10985f67642c6fa009346371ee0e Mon Sep 17 00:00:00 2001 From: Maximus Sun Date: Thu, 27 Oct 2022 21:06:55 +0800 Subject: MA-20814 add fastboot command to erase u-boot env Add fastboot command "fastboot oem erase_uboot_env" to support erase u-boot env. Signed-off-by: Maximus Sun --- configs/imx8mm_ddr4_evk_android_defconfig | 1 + configs/imx8mm_ddr4_evk_android_uuu_defconfig | 1 + configs/imx8mm_evk_1g_ddr_android_defconfig | 1 + configs/imx8mm_evk_4g_android_defconfig | 1 + configs/imx8mm_evk_4g_android_trusty_defconfig | 1 + configs/imx8mm_evk_4g_android_uuu_defconfig | 1 + configs/imx8mm_evk_android_defconfig | 1 + configs/imx8mm_evk_android_dual_defconfig | 1 + configs/imx8mm_evk_android_trusty_defconfig | 1 + configs/imx8mm_evk_android_trusty_dual_defconfig | 1 + ...mm_evk_android_trusty_secure_unlock_dual_defconfig | 1 + configs/imx8mm_evk_android_uuu_defconfig | 1 + configs/imx8mq_evk_android_defconfig | 1 + configs/imx8mq_evk_android_dual_defconfig | 1 + configs/imx8mq_evk_android_trusty_defconfig | 1 + configs/imx8mq_evk_android_trusty_dual_defconfig | 1 + ...mq_evk_android_trusty_secure_unlock_dual_defconfig | 1 + configs/imx8mq_evk_android_uuu_defconfig | 1 + configs/imx8qm_mek_android_defconfig | 1 + configs/imx8qm_mek_android_dual_defconfig | 1 + configs/imx8qm_mek_android_hdmi_defconfig | 1 + configs/imx8qm_mek_android_trusty_defconfig | 1 + configs/imx8qm_mek_android_trusty_dual_defconfig | 1 + ...qm_mek_android_trusty_secure_unlock_dual_defconfig | 1 + configs/imx8qm_mek_android_uuu_defconfig | 1 + configs/imx8qm_mek_androidauto2_trusty_defconfig | 1 + configs/imx8qm_mek_androidauto2_trusty_md_defconfig | 1 + configs/imx8qm_mek_androidauto_trusty_defconfig | 1 + ...8qm_mek_androidauto_trusty_secure_unlock_defconfig | 1 + configs/imx8qxp_mek_android_defconfig | 1 + configs/imx8qxp_mek_android_dual_defconfig | 1 + configs/imx8qxp_mek_android_trusty_dual_defconfig | 1 + ...xp_mek_android_trusty_secure_unlock_dual_defconfig | 1 + configs/imx8qxp_mek_android_uuu_defconfig | 1 + configs/imx8qxp_mek_androidauto2_trusty_defconfig | 1 + configs/imx8qxp_mek_androidauto_trusty_defconfig | 1 + ...qxp_mek_androidauto_trusty_secure_unlock_defconfig | 1 + configs/imx8ulp_9x9_evk_android_defconfig | 1 + configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig | 1 + configs/imx8ulp_9x9_evk_android_uuu_defconfig | 1 + configs/imx8ulp_evk_android_defconfig | 1 + configs/imx8ulp_evk_android_dual_defconfig | 1 + configs/imx8ulp_evk_android_trusty_defconfig | 1 + configs/imx8ulp_evk_android_trusty_dual_defconfig | 1 + ...lp_evk_android_trusty_secure_unlock_dual_defconfig | 1 + configs/imx8ulp_evk_android_uuu_defconfig | 1 + configs/imx8ulp_watch_android_defconfig | 1 + configs/imx8ulp_watch_android_dual_defconfig | 1 + configs/imx8ulp_watch_android_uuu_defconfig | 1 + drivers/fastboot/fb_fsl/fb_fsl_command.c | 19 ++++++++++++++++++- include/fb_fsl.h | 1 + 51 files changed, 68 insertions(+), 1 deletion(-) diff --git a/configs/imx8mm_ddr4_evk_android_defconfig b/configs/imx8mm_ddr4_evk_android_defconfig index 80e0d93775..7fd463fa19 100644 --- a/configs/imx8mm_ddr4_evk_android_defconfig +++ b/configs/imx8mm_ddr4_evk_android_defconfig @@ -170,3 +170,4 @@ CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_ddr4_evk_android_uuu_defconfig b/configs/imx8mm_ddr4_evk_android_uuu_defconfig index d6c5cb11d1..b39916c30c 100644 --- a/configs/imx8mm_ddr4_evk_android_uuu_defconfig +++ b/configs/imx8mm_ddr4_evk_android_uuu_defconfig @@ -165,3 +165,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_1g_ddr_android_defconfig b/configs/imx8mm_evk_1g_ddr_android_defconfig index 5133f38cd3..94dd53eeca 100644 --- a/configs/imx8mm_evk_1g_ddr_android_defconfig +++ b/configs/imx8mm_evk_1g_ddr_android_defconfig @@ -204,3 +204,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_IMX8M_1G_MEMORY=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_4g_android_defconfig b/configs/imx8mm_evk_4g_android_defconfig index 7f2882c5a6..e6d3407e23 100644 --- a/configs/imx8mm_evk_4g_android_defconfig +++ b/configs/imx8mm_evk_4g_android_defconfig @@ -204,3 +204,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_IMX8M_4G_LPDDR4=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_4g_android_trusty_defconfig b/configs/imx8mm_evk_4g_android_trusty_defconfig index bf48059cc7..52c0e4b8df 100644 --- a/configs/imx8mm_evk_4g_android_trusty_defconfig +++ b/configs/imx8mm_evk_4g_android_trusty_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mm" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_4g_android_uuu_defconfig b/configs/imx8mm_evk_4g_android_uuu_defconfig index bbe331da0a..ec8b3bb827 100644 --- a/configs/imx8mm_evk_4g_android_uuu_defconfig +++ b/configs/imx8mm_evk_4g_android_uuu_defconfig @@ -199,3 +199,4 @@ CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n CONFIG_IMX8M_4G_LPDDR4=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_defconfig b/configs/imx8mm_evk_android_defconfig index d7ffc14bec..32e7a71742 100644 --- a/configs/imx8mm_evk_android_defconfig +++ b/configs/imx8mm_evk_android_defconfig @@ -203,3 +203,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_dual_defconfig b/configs/imx8mm_evk_android_dual_defconfig index adad43db54..b5e3853d6c 100644 --- a/configs/imx8mm_evk_android_dual_defconfig +++ b/configs/imx8mm_evk_android_dual_defconfig @@ -204,3 +204,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0x320 CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_trusty_defconfig b/configs/imx8mm_evk_android_trusty_defconfig index e5023f7521..ca516701a3 100644 --- a/configs/imx8mm_evk_android_trusty_defconfig +++ b/configs/imx8mm_evk_android_trusty_defconfig @@ -209,3 +209,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mm" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_trusty_dual_defconfig b/configs/imx8mm_evk_android_trusty_dual_defconfig index a609d53ff3..852cff0bd4 100644 --- a/configs/imx8mm_evk_android_trusty_dual_defconfig +++ b/configs/imx8mm_evk_android_trusty_dual_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_trusty_secure_unlock_dual_defconfig b/configs/imx8mm_evk_android_trusty_secure_unlock_dual_defconfig index 1c871fd964..1f9bbc2da1 100644 --- a/configs/imx8mm_evk_android_trusty_secure_unlock_dual_defconfig +++ b/configs/imx8mm_evk_android_trusty_secure_unlock_dual_defconfig @@ -212,3 +212,4 @@ CONFIG_ATTESTATION_ID_MODEL="EVK_8MM" CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_IMX_HAB=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mm_evk_android_uuu_defconfig b/configs/imx8mm_evk_android_uuu_defconfig index 7a6c245d17..479346249d 100644 --- a/configs/imx8mm_evk_android_uuu_defconfig +++ b/configs/imx8mm_evk_android_uuu_defconfig @@ -198,3 +198,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_defconfig b/configs/imx8mq_evk_android_defconfig index b74492e9f9..9d5dc1de40 100644 --- a/configs/imx8mq_evk_android_defconfig +++ b/configs/imx8mq_evk_android_defconfig @@ -167,3 +167,4 @@ CONFIG_AVB_WARNING_LOGO_ROWS=0x60 CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_dual_defconfig b/configs/imx8mq_evk_android_dual_defconfig index 4c428fc569..917e83e850 100644 --- a/configs/imx8mq_evk_android_dual_defconfig +++ b/configs/imx8mq_evk_android_dual_defconfig @@ -168,3 +168,4 @@ CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_trusty_defconfig b/configs/imx8mq_evk_android_trusty_defconfig index 075e9e887d..a9740ecda9 100644 --- a/configs/imx8mq_evk_android_trusty_defconfig +++ b/configs/imx8mq_evk_android_trusty_defconfig @@ -173,3 +173,4 @@ CONFIG_ATTESTATION_ID_DEVICE="evk_8mq" CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ" +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_trusty_dual_defconfig b/configs/imx8mq_evk_android_trusty_dual_defconfig index 4763648ba7..648b77bfc5 100644 --- a/configs/imx8mq_evk_android_trusty_dual_defconfig +++ b/configs/imx8mq_evk_android_trusty_dual_defconfig @@ -172,3 +172,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ" CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_trusty_secure_unlock_dual_defconfig b/configs/imx8mq_evk_android_trusty_secure_unlock_dual_defconfig index e53b1eb416..f406981aa3 100644 --- a/configs/imx8mq_evk_android_trusty_secure_unlock_dual_defconfig +++ b/configs/imx8mq_evk_android_trusty_secure_unlock_dual_defconfig @@ -176,3 +176,4 @@ CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ" CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_IMX_HAB=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8mq_evk_android_uuu_defconfig b/configs/imx8mq_evk_android_uuu_defconfig index ed696565b7..460db0b7dc 100644 --- a/configs/imx8mq_evk_android_uuu_defconfig +++ b/configs/imx8mq_evk_android_uuu_defconfig @@ -161,3 +161,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_defconfig b/configs/imx8qm_mek_android_defconfig index 4ae8b05fcf..9cb61da220 100644 --- a/configs/imx8qm_mek_android_defconfig +++ b/configs/imx8qm_mek_android_defconfig @@ -206,3 +206,4 @@ CONFIG_PSCI_BOARD_REBOOT=y CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_dual_defconfig b/configs/imx8qm_mek_android_dual_defconfig index 7e465d0e03..6637225097 100644 --- a/configs/imx8qm_mek_android_dual_defconfig +++ b/configs/imx8qm_mek_android_dual_defconfig @@ -207,3 +207,4 @@ CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_hdmi_defconfig b/configs/imx8qm_mek_android_hdmi_defconfig index 0551b0826c..b7fb8cd751 100644 --- a/configs/imx8qm_mek_android_hdmi_defconfig +++ b/configs/imx8qm_mek_android_hdmi_defconfig @@ -208,3 +208,4 @@ CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_trusty_defconfig b/configs/imx8qm_mek_android_trusty_defconfig index ea93c9ce76..c40d236c07 100644 --- a/configs/imx8qm_mek_android_trusty_defconfig +++ b/configs/imx8qm_mek_android_trusty_defconfig @@ -213,3 +213,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_SHA256=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_trusty_dual_defconfig b/configs/imx8qm_mek_android_trusty_dual_defconfig index 7a8a7a3c1c..97d1f554b5 100644 --- a/configs/imx8qm_mek_android_trusty_dual_defconfig +++ b/configs/imx8qm_mek_android_trusty_dual_defconfig @@ -214,3 +214,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_SHA256=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_trusty_secure_unlock_dual_defconfig b/configs/imx8qm_mek_android_trusty_secure_unlock_dual_defconfig index 5b2b3903c8..0b2ce5f1f2 100644 --- a/configs/imx8qm_mek_android_trusty_secure_unlock_dual_defconfig +++ b/configs/imx8qm_mek_android_trusty_secure_unlock_dual_defconfig @@ -216,3 +216,4 @@ CONFIG_SHA256=y CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_android_uuu_defconfig b/configs/imx8qm_mek_android_uuu_defconfig index 6a558b16aa..9239ef02f9 100644 --- a/configs/imx8qm_mek_android_uuu_defconfig +++ b/configs/imx8qm_mek_android_uuu_defconfig @@ -200,3 +200,4 @@ CONFIG_CMD_BMP=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto2_trusty_defconfig b/configs/imx8qm_mek_androidauto2_trusty_defconfig index 0cd969bb52..d11d032f81 100644 --- a/configs/imx8qm_mek_androidauto2_trusty_defconfig +++ b/configs/imx8qm_mek_androidauto2_trusty_defconfig @@ -211,3 +211,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_LOAD_KEY_FROM_RPMB=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto2_trusty_md_defconfig b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig index de51e6e666..36251bdc10 100644 --- a/configs/imx8qm_mek_androidauto2_trusty_md_defconfig +++ b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig @@ -212,3 +212,4 @@ CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_LOAD_KEY_FROM_RPMB=n CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto_trusty_defconfig b/configs/imx8qm_mek_androidauto_trusty_defconfig index 9fcbc53e44..c557926ec4 100644 --- a/configs/imx8qm_mek_androidauto_trusty_defconfig +++ b/configs/imx8qm_mek_androidauto_trusty_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig index 2010ba1aa2..e91ddffbaf 100644 --- a/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig +++ b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig @@ -212,3 +212,4 @@ CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_defconfig b/configs/imx8qxp_mek_android_defconfig index ef8f3fffb9..033daa7ad7 100644 --- a/configs/imx8qxp_mek_android_defconfig +++ b/configs/imx8qxp_mek_android_defconfig @@ -204,3 +204,4 @@ CONFIG_PSCI_BOARD_REBOOT=y CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_dual_defconfig b/configs/imx8qxp_mek_android_dual_defconfig index 119c94f049..f904654d3d 100644 --- a/configs/imx8qxp_mek_android_dual_defconfig +++ b/configs/imx8qxp_mek_android_dual_defconfig @@ -205,3 +205,4 @@ CONFIG_VIRTUAL_AB_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_trusty_dual_defconfig b/configs/imx8qxp_mek_android_trusty_dual_defconfig index 6363bc47a5..91718b0707 100644 --- a/configs/imx8qxp_mek_android_trusty_dual_defconfig +++ b/configs/imx8qxp_mek_android_trusty_dual_defconfig @@ -212,3 +212,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_DUAL_BOOTLOADER=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_trusty_secure_unlock_dual_defconfig b/configs/imx8qxp_mek_android_trusty_secure_unlock_dual_defconfig index 6af0b69475..9de24b5d85 100644 --- a/configs/imx8qxp_mek_android_trusty_secure_unlock_dual_defconfig +++ b/configs/imx8qxp_mek_android_trusty_secure_unlock_dual_defconfig @@ -214,3 +214,4 @@ CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_android_uuu_defconfig b/configs/imx8qxp_mek_android_uuu_defconfig index 80ff2f8cec..45ee29db70 100644 --- a/configs/imx8qxp_mek_android_uuu_defconfig +++ b/configs/imx8qxp_mek_android_uuu_defconfig @@ -198,3 +198,4 @@ CONFIG_CMD_BMP=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_androidauto2_trusty_defconfig b/configs/imx8qxp_mek_androidauto2_trusty_defconfig index 1a9ecc8849..d932149a87 100644 --- a/configs/imx8qxp_mek_androidauto2_trusty_defconfig +++ b/configs/imx8qxp_mek_androidauto2_trusty_defconfig @@ -210,3 +210,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_LOAD_KEY_FROM_RPMB=n +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_androidauto_trusty_defconfig b/configs/imx8qxp_mek_androidauto_trusty_defconfig index bae4378391..e5912f8585 100644 --- a/configs/imx8qxp_mek_androidauto_trusty_defconfig +++ b/configs/imx8qxp_mek_androidauto_trusty_defconfig @@ -209,3 +209,4 @@ CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig index 10989c26c5..a4b7c9a747 100644 --- a/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig +++ b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig @@ -211,3 +211,4 @@ CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q" CONFIG_ANDROID_AUTO_SUPPORT=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_9x9_evk_android_defconfig b/configs/imx8ulp_9x9_evk_android_defconfig index 0fcdcad4bb..23ff269937 100644 --- a/configs/imx8ulp_9x9_evk_android_defconfig +++ b/configs/imx8ulp_9x9_evk_android_defconfig @@ -150,3 +150,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_AHAB_BOOT=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig index 99c61f4228..d929c04e91 100644 --- a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig @@ -157,3 +157,4 @@ CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y CONFIG_AHAB_BOOT=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_9x9_evk_android_uuu_defconfig b/configs/imx8ulp_9x9_evk_android_uuu_defconfig index 860e5f1d36..3308c0b76a 100644 --- a/configs/imx8ulp_9x9_evk_android_uuu_defconfig +++ b/configs/imx8ulp_9x9_evk_android_uuu_defconfig @@ -144,3 +144,4 @@ CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_defconfig b/configs/imx8ulp_evk_android_defconfig index 57fa5ff1a8..d5b8b93006 100644 --- a/configs/imx8ulp_evk_android_defconfig +++ b/configs/imx8ulp_evk_android_defconfig @@ -150,3 +150,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_AHAB_BOOT=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_dual_defconfig b/configs/imx8ulp_evk_android_dual_defconfig index e7050ab71c..a2ab29cab8 100644 --- a/configs/imx8ulp_evk_android_dual_defconfig +++ b/configs/imx8ulp_evk_android_dual_defconfig @@ -151,3 +151,4 @@ CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_DUAL_BOOTLOADER=y CONFIG_AHAB_BOOT=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_trusty_defconfig b/configs/imx8ulp_evk_android_trusty_defconfig index f624bedc72..9e56ac6b48 100644 --- a/configs/imx8ulp_evk_android_trusty_defconfig +++ b/configs/imx8ulp_evk_android_trusty_defconfig @@ -156,3 +156,4 @@ CONFIG_ATTESTATION_ID_MANUFACTURER="nxp" CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_AHAB_BOOT=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_trusty_dual_defconfig b/configs/imx8ulp_evk_android_trusty_dual_defconfig index 8e7d7797bd..8be797977a 100644 --- a/configs/imx8ulp_evk_android_trusty_dual_defconfig +++ b/configs/imx8ulp_evk_android_trusty_dual_defconfig @@ -157,3 +157,4 @@ CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP" CONFIG_DUAL_BOOTLOADER=y CONFIG_AHAB_BOOT=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig b/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig index b6b358546d..a92d3e6b11 100644 --- a/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig +++ b/configs/imx8ulp_evk_android_trusty_secure_unlock_dual_defconfig @@ -158,3 +158,4 @@ CONFIG_DUAL_BOOTLOADER=y CONFIG_SECURE_UNLOCK=y CONFIG_AHAB_BOOT=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_evk_android_uuu_defconfig b/configs/imx8ulp_evk_android_uuu_defconfig index e8e5f12685..7078836de1 100644 --- a/configs/imx8ulp_evk_android_uuu_defconfig +++ b/configs/imx8ulp_evk_android_uuu_defconfig @@ -144,3 +144,4 @@ CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n CONFIG_AHAB_BOOT=y +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_watch_android_defconfig b/configs/imx8ulp_watch_android_defconfig index 1197272579..8ae1851dc1 100644 --- a/configs/imx8ulp_watch_android_defconfig +++ b/configs/imx8ulp_watch_android_defconfig @@ -137,3 +137,4 @@ CONFIG_AVB_WARNING_LOGO=y CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_watch_android_dual_defconfig b/configs/imx8ulp_watch_android_dual_defconfig index 60dffc0c15..833c1b657c 100644 --- a/configs/imx8ulp_watch_android_dual_defconfig +++ b/configs/imx8ulp_watch_android_dual_defconfig @@ -138,3 +138,4 @@ CONFIG_AVB_WARNING_LOGO_COLS=0xC8 CONFIG_AVB_WARNING_LOGO_ROWS=0xC0 CONFIG_DUAL_BOOTLOADER=y CONFIG_LMB_MAX_REGIONS=9 +CONFIG_CMD_ERASEENV=y diff --git a/configs/imx8ulp_watch_android_uuu_defconfig b/configs/imx8ulp_watch_android_uuu_defconfig index d1307293ae..5d5799855f 100644 --- a/configs/imx8ulp_watch_android_uuu_defconfig +++ b/configs/imx8ulp_watch_android_uuu_defconfig @@ -131,3 +131,4 @@ CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y CONFIG_ANDROID_SUPPORT=y CONFIG_ANDROID_AB_SUPPORT=y CONFIG_CMD_BOOTA=n +CONFIG_CMD_ERASEENV=y diff --git a/drivers/fastboot/fb_fsl/fb_fsl_command.c b/drivers/fastboot/fb_fsl/fb_fsl_command.c index 11224728a8..61b1a9d580 100644 --- a/drivers/fastboot/fb_fsl/fb_fsl_command.c +++ b/drivers/fastboot/fb_fsl/fb_fsl_command.c @@ -472,6 +472,16 @@ static bool endswith(char* s, char* subs) { return true; } +static bool erase_uboot_env(void) { + FbLockState status; + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) { + printf("can not erase env when device is in locked state\n"); + return false; + } else + return env_erase() ? false : true; +} + static void flashing(char *cmd, char *response) { FbLockState status; @@ -726,7 +736,14 @@ static void flashing(char *cmd, char *response) } #endif /* !CONFIG_AVB_ATX */ #endif /* CONFIG_IMX_TRUSTY_OS */ - else if (endswith(cmd, "unlock_critical")) { + else if (endswith(cmd, ERASE_UBOOT_ENV)) { + if(erase_uboot_env()) + strcpy(response, "OKAY"); + else { + printf("ERROR erase uboot environment variable failed!"); + strcpy(response, "FAILerase uboot environment variable failed!"); + } + } else if (endswith(cmd, "unlock_critical")) { strcpy(response, "OKAY"); } else if (endswith(cmd, "unlock")) { printf("flashing unlock.\n"); diff --git a/include/fb_fsl.h b/include/fb_fsl.h index 7c2d6fbc89..080ea0e44b 100644 --- a/include/fb_fsl.h +++ b/include/fb_fsl.h @@ -51,6 +51,7 @@ #endif #define FASTBOOT_PARTITION_METADATA "metadata" +#define ERASE_UBOOT_ENV "erase_uboot_env" #ifdef CONFIG_ANDROID_AB_SUPPORT #define FASTBOOT_PARTITION_BOOT_A "boot_a" -- cgit v1.2.3 From 918dbf78bbb299829025c25737005a776c50dda6 Mon Sep 17 00:00:00 2001 From: Zhipeng Wang Date: Mon, 7 Nov 2022 09:49:40 +0800 Subject: MA-20872 Revert "MA-18775 system will hang about 3s when boot up kernel" The problem of the system hanging for about 3 seconds when booting the kernel is gone, so enable the 8mp early console. This reverts commit 8f897bce4cce75e7599a8ea952271eab37b1dc51. Change-Id: I5a4c32f22fc93393610f3ae99fb3ca8e0643990a --- arch/arm/dts/imx8mp-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index 0df546dfd0..61e8a70196 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -13,7 +13,7 @@ compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; chosen { - bootargs = "console=ttymxc1,115200"; + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; stdout-path = &uart2; }; -- cgit v1.2.3 From b35420da607480d13334acd485d1e20954a14b58 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 29 Apr 2022 15:34:44 +0200 Subject: crypto: fsl_hash: Remove unnecessary alignment check in caam_hash() While working on an LX2160 based board and updating to latest mainline I noticed problems using the HW accelerated hash functions on this platform, when trying to boot a FIT Kernel image. Here the resulting error message: Using 'conf-freescale_lx2160a.dtb' configuration Trying 'kernel-1' kernel subimage Verifying Hash Integrity ... sha256Error: Address arguments are not aligned CAAM was not setup properly or it is faulty error! Bad hash value for 'hash-1' hash node in 'kernel-1' image node Bad Data Hash ERROR: can't get kernel image! Testing and checking with Gaurav Jain from NXP has revealed, that this alignment check is not necessary here at all. So let's remove this check completely. Signed-off-by: Stefan Roese Cc: Gaurav Jain Cc: dullfire@yahoo.com Reviewed-by: Gaurav Jain --- drivers/crypto/fsl/fsl_hash.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 66249f2707..226e4be51d 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -186,13 +186,6 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, uint32_t *desc; unsigned int size; - if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) || - !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) { - puts("Error: Address arguments are not aligned\n"); - return -EINVAL; - } - - debug("\ncaam hash\n"); desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); -- cgit v1.2.3 From 62ad7799b6cad795f73acacc28bf3711fc83a886 Mon Sep 17 00:00:00 2001 From: Kshitiz Varshney Date: Fri, 11 Nov 2022 13:06:03 +0100 Subject: LF-7602: Device tree fixup based on compatible string Updated otp_crypto_key & otp_unique_key device tree fix up. Earlier, device tree fix up was based on hardcoded address, but now it's based on compatible string of crypto node:- "fsl,imx28-dcp" Signed-off-by: Kshitiz Varshney --- arch/arm/mach-imx/mx6/module_fuse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 19780b64a5..a171e7b54d 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -311,7 +311,7 @@ add_status: void *buf; char keys[2][16] = {"otp_crypto_key", "otp_unique_key"}; int ret = 0; - int nodeoff = fdt_path_offset(blob, "/soc/bus@2200000/crypto@2280000"); + int nodeoff = fdt_node_offset_by_compatible(blob, -1, "fsl,imx28-dcp"); if (nodeoff < 0) { printf("node to update the SoC serial number is not found.\n"); -- cgit v1.2.3 From 14b6c8f3e3b222f6c508b49cba319a08d207e8f4 Mon Sep 17 00:00:00 2001 From: Maximus Sun Date: Tue, 15 Nov 2022 13:41:15 +0800 Subject: MA-20886 imx8ulp: Boot from recovery mode when pressing key MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make system enter recovery mode when user pressing "sw2" when i.MX 8ULP EVK and i.MX 8ULP EVK 9×9 board are powered on. Signed-off-by: Maximus Sun Change-Id: Ifc13c37fff4f6c7352161b6ad7d6014aeeafcc6d --- arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h | 2 +- board/freescale/imx8ulp_evk/imx8ulp_evk.c | 32 +++++++++++++++++++++++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h index 3638f0db53..cdea5d6f3c 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h @@ -73,6 +73,6 @@ enum { IMX8ULP_PAD_PTF5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0A6C, 0x2, 0), IMX8ULP_PAD_PTF0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0A68, 0x2, 0), IMX8ULP_PAD_PTF1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0A64, 0x2, 0), - + IMX8ULP_PAD_PTF7__PTF7 = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0), }; #endif /* __ASM_ARCH_IMX8ULP_PINS_H__ */ diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c index 3b0c57e497..3a6bd1da5a 100644 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -210,9 +210,39 @@ int board_late_init(void) #ifdef CONFIG_FSL_FASTBOOT #ifdef CONFIG_ANDROID_RECOVERY +static iomux_cfg_t const recovery_pad[] = { + IMX8ULP_PAD_PTF7__PTF7 | MUX_PAD_CTRL(PAD_CTL_IBE_ENABLE), +}; int is_recovery_key_pressing(void) { - return 0; /*TODO*/ + int ret; + struct gpio_desc desc; + + imx8ulp_iomux_setup_multiple_pads(recovery_pad, ARRAY_SIZE(recovery_pad)); + + ret = dm_gpio_lookup_name("GPIO3_7", &desc); + if (ret) { + printf("%s lookup GPIO3_7 failed ret = %d\n", __func__, ret); + return 0; + } + + ret = dm_gpio_request(&desc, "recovery"); + if (ret) { + printf("%s request recovery pad failed ret = %d\n", __func__, ret); + return 0; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + ret = dm_gpio_get_value(&desc); + if (ret < 0) { + printf("%s error in retrieving GPIO value ret = %d\n", __func__, ret); + return 0; + } + + dm_gpio_free(desc.dev, &desc); + + return !ret; } #endif /*CONFIG_ANDROID_RECOVERY*/ #endif /*CONFIG_FSL_FASTBOOT*/ -- cgit v1.2.3