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2012-10-30Merge branch 'colibri' of git://git.toradex.com/u-boot-toradex.git into colibriMax Krummenacher
2012-10-30Merge branch 'chromeos-v2011.06' into colibriMarcel Ziswiler
Conflicts: arch/arm/cpu/armv7/tegra3/warmboot_avp.c arch/arm/include/asm/arch-tegra/clk_rst.h
2012-10-29Merge branch 'colibri' of git://git.toradex.com/u-boot-toradex.git into colibriMax Krummenacher
2012-10-29tegra: add enterrcm commandStephen Warren
tegra: add enterrcm command Tegra's boot ROM supports a mode whereby code may be downloaded and flash programmed over a USB connection. On dev boards, this is typically entered by holding down a "force recovery" button and resetting the CPU. However, not all boards have such a button (one example is the Compulab Trimslice), so a method to enter RCM from software is useful. This change implements the command "enterrcm" to do this, and enables it for all Tegra boards by default. Even on boards other than Trimslice, controlling this over a UART may be useful, e.g. to allow simple remote control without the need for mechanical button actuators, or hooking up relays/... to the button. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-10-26Merge branch 'colibri' of git://git.toradex.com/u-boot-toradex.git into colibritrdx
2012-10-25colibri_t20: fix SD bootMarcel Ziswiler
As the kernel recently passed the 4 MB size limit simply copying 4 MB won't quite cut it. Increase to 8 MB for now. In the future properly parsing the SD card's partition table would be the way to go.
2012-10-24colibri_t30: fix buildMarcel Ziswiler
Fix build issues introduced with NVIDIA partition table parsing integration.
2012-10-18Merge branch 'colibri' of git://git.toradex.com/u-boot-toradex into colibritrdx
2012-10-18colibri_t20: fix SD bootT20_LinuxImageV2.0Alpha2_20121019Marcel Ziswiler
If booting from SD card BCT contains information specific to SD card partition layout which is bogus if used for NAND partition parsing. Simply fall back to default offset just like in recovery BCT case. Note: in the future we could parse SD partition table as well to more generically support SD booting from various card densities.
2012-10-18colibri_t20: nand: change offset handlingMarcel Ziswiler
Rather than relying on hard-coded offsets actually make use of partition table parsing implementation.
2012-10-18colibri_t20: nand: integrate NVIDIA partition table parsingMarcel Ziswiler
NVIDIA's NAND layout includes a partition table that can be used to generically construct the mtdparts kernel boot argument. As an added benefit this is completely independent of the underlying NAND part used which differs with various module versions. It further allows our customer easy adoption to their own custom partition layout. Initial partition table parsing courtesy of Mitja Špes from LXNAV.
2012-10-18colibri_t20: fix SD bootMarcel Ziswiler
If booting from SD card BCT contains information specific to SD card partition layout which is bogus if used for NAND partition parsing. Simply fall back to default offset just like in recovery BCT case. Note: in the future we could parse SD partition table as well to more generically support SD booting from various card densities.
2012-10-18colibri_t20: nand: change offset handlingMarcel Ziswiler
Rather than relying on hard-coded offsets actually make use of partition table parsing implementation.
2012-10-18colibri_t20: nand: integrate NVIDIA partition table parsingMarcel Ziswiler
NVIDIA's NAND layout includes a partition table that can be used to generically construct the mtdparts kernel boot argument. As an added benefit this is completely independent of the underlying NAND part used which differs with various module versions. It further allows our customer easy adoption to their own custom partition layout. Initial partition table parsing courtesy of Mitja Špes from LXNAV.
2012-10-18colibri_t20: fix SD boot bootdeviceMarcel Ziswiler
Change SD boot bootdevice in environment variable sdargs from mmcblk3p1 to mmcblk0p1 due to later kernels using a different numbering scheme. While at it clean-up some white space indentation stuff.
2012-10-18colibri_t20: add sanity check to board_query_sdram_size()Marcel Ziswiler
Colibri T20 does not use OdmData but rather relies on memory controller configuration done by boot ROM based on BCT information. Unfortunately it is possible to at least boot a 256 MB module with a 512 MB BCT therefore double check whether we really do have that.
2012-10-18tegra 30: PMIC init commentMarcel Ziswiler
Add comment concerning PMIC initialisation of VDD_CPU via VDDCtrl.
2012-10-16colibri_t20: modify order of console boot argumentMarcel Ziswiler
User space tools like init just use last console kernel boot argument as their one and only console. Re-order them in order to output boot messages on serial debug console.
2012-10-15Examples: Properly append LDFLAGS to LD commandMarek Vasut
Examples: Properly append LDFLAGS to LD command The LD command in examples/standalone/Makefile ignored platform specific LDFLAGS setup. Pass these LDFLAGS to the command. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de>
2012-09-26colibri_t20: activate backlight gpioMarcel Ziswiler
Activate BL_ON backlight GPIO PT4 on SODIMM pin 71. While at it add commented out XGA 1024x768 display timing values as well.
2012-08-22Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808Marcel Ziswiler
2012-07-18tegra: fdt: Change load entry to 0x1080000Jimmy Zhang
Change tegra2's entry address to its default address 0x108000. BUG=none TEST=flashed with local built u-boot. Kernel boots up fine. Change-Id: I6ff4ed1f2901df73b21d033fbd191550108e96b5 Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/22171 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-07-18tegra: config: Change load entry to 0x108000/0x80108000Jimmy Zhang
0x108000/0x80108000 is used as tegra2/tegra3's default boot loader entry address. This change makes u-boot to comply with nvidia standard flash tools. BUG=none TEST=run cros_write_firmware with local build u-boot. Kernel boots up fine. Change-Id: I55e9b5d1847cf7e6a94d362935deef5f6855ba5a Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/21979 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-06-05arm: tegra3: Fix bootup up issuePuneet Saxena
At bootup time device enters in standby state as CLK_RST_CONTROLLER_SCLK_BURST_POLICY is not set correctly. This change correctly sets clock burst policy. BUG = None TEST= Build OK for Seaboard,Cardhu and Waluigi. Tested on Cardhu and waluigi. Device boots up. Change-Id: I598ca7bcfc4a39ecaa68c211d3439ac3569c6e44 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/24164 Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Tested-by: Tom Warren <twarren@nvidia.com> Commit-Ready: Tom Warren <twarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2012-04-30arm: tegra2: seaboard: Enable CRC32 v optionJimmy Zhang
The cros_write_firmware has updated flash script command 'crc32' with -v option. To support this change, u-boot needs to be built with CONFIG_CRC32_VERIFY for seaboard. BUG=none TEST=run cros_write_firmware with local build u-boot. Change-Id: I49046ce2424c4624a335af32051421e44bd388bb Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/21420 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mark Zhang <markz@nvidia.com> Reviewed-by: Wei Ni <wni@nvidia.com>
2012-04-25Provide alternative config for netbootingVadim Bendebury
This change allows to build a customized u-boot image, which includes networking capabilities, provides diagnostic commands and supports command line editing. These features are necessary to facilitate the factory flow. This image needs to be clearly distinguishable by ChromeOS. This is achieved by modifying the value presented by the BINF.3 ACPI object. To build this modified image one needs to add BUILD_FACTORY_IMAGE=1 to the make invocation line. BUG=chrome-os-partner:7952 TEST=manual . build the new firmware image as follows: USE='pcserial factory-mode' emerge-link chromeos-u-boot \ chromeos-coreboot chromeos-bootimage . program the new image on the Link target with ChromeOS installed on the SSD and restart it . observe the target stop at u-boot command prompt (boot >) . connect the target to an Ethernet network with a DHCP server using a USB Ethernet dongle . run the following commands at the u-boot prompt boot > usb start (Re)start USB... USB: Register 203007 NbrPorts 7 USB EHCI 1.00 Register 20400b NbrPorts 11 USB EHCI 1.00 8 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found scanning bus for ethernet devices... 1 Ethernet Device(s) found boot > dhcp Waiting for Ethernet connection... done. BOOTP broadcast 1 BOOTP broadcast 2 [a few warnings of unsupported DHCP options] DHCP client bound to address 172.22.75.25 Using asx0 device TFTP from server 172.16.255.7; our IP address is 172.22.75.25; sending through gateway 172.22.75.254 Filename 'pxelinux.0'. Load address: 0x100000 Loading: ## done Bytes transferred = 15840 (3de0 hex) boot > . start ChromeOS on the target by issuing vboot_twostop . once ChromeOS boots check the mainfw_type crossystem reported value localhost ~ # echo $(crossystem mainfw_type) netboot localhost ~ # Change-Id: I1c50517754b6b5f773e432b9adec4b290f303e6f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/21071 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-10x86: Fix TPM driver to work with multiple vendor TPMsDuncan Laurie
- Fix bug in traversal of vendor name list. - Sending "command ready" needs additional logic to handle TPMs that need that bit set twice: once to empty the read FIFOs and once to actualy set command ready. - Certain TPMs need a small delay between requesting locality and attempting to set command ready or they will hang the bus. BUG=chrome-os-partner:8558 TEST=manual Successful boot and suspend/resume with all TPMs listed in the driver vendor/device list. Change-Id: I22021b24f9498c3cafe0e1d5f1c6562ea0be5aad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18480 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
2012-03-29Make u-boot recognize full range of PPT LPC controllersVadim Bendebury
The full range of LPC controllers should be accepted by u-boot when looking for the SPI controller. The values come from Intel's Panther_Point_EDS_v072.pdf (document #472178). BUG=chrome-os-partner:7734 TEST=manual . program the new image on the target . reboot it and observe coming up to ChromeOS login screen Change-Id: Id8f7068c3b48885f868a1f30e7927e678d2154b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/19147 Reviewed-by: Jon Salz <jsalz@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/19310 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
2012-03-21Increase size of MRC cache on LinkStefan Reinauer
Link's MRC produces significantly more training data than the one used on Stumpy/Lumpy. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none TEST=boot tested on Link Change-Id: I9310c3bcc77fb4318db0635b97b115ab0eb7e5ec Reviewed-on: https://gerrit.chromium.org/gerrit/18748 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-03-20spi: Atmel: Add support for AT25DFTom Warren
Cardhu boards can use Atmel and Winbond SPI flash parts - support both in one binary. BUG=chromium-os:23496 TEST=build all OK, test on Cardhu. 'sf probe 0' returns: SF: Detected AT25DF321A with page size 256, total 4 MiB. sf read/write/erase all work OK. Signed-off-by: Tom Warren <twarren@nvidia.com> Change-Id: I7df3abb030a49b572e1172ca77227cd4d63e0c21 Reviewed-on: https://gerrit.chromium.org/gerrit/18539 Reviewed-by: Mike Frysinger <vapier@chromium.org>
2012-03-19x86: Make RW unused section labels uniqueDuncan Laurie
BUG=none TEST=check fmap on generated binary for unique names Change-Id: Id1ac5cf223ec6a333fc8f4c587e972afd087f90d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18435 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2012-03-16Reduce RW BIOS data sections to 512K from 976KDuncan Laurie
This saves 500ms in the RW BIOS path and still leaves 130K overhead from the current U-boot size (372K) which should be more than enough for any future updates on stumpy/lumpy. This should be re-visited if/when vboot is smart enough to just read+validate the actual binary within the section. BUG=chrome-os-partner:8518 TEST=boot lumpy/stumpy through RW BIOS path and gather timestamps to see 500ms improvement. Change-Id: Ia714b4b95245f02f6e781247f820ca915bb403f5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18372 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2012-03-16Remove code that disabled cache in _x86boot_startDuncan Laurie
When U-boot is loaded via verified boot it starts at the _x86boot_start entry point and promptly disables caching, resulting in about a 500ms hit to boot time. BUG=chrome-os-partner:8518 TEST=boot on lumpy with RW BIOS and gather timestamps to observe 500ms less time spent in u-boot init. Change-Id: I4eb1ad5ebcb20a156fef77452030e47a5e510115 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18371 Reviewed-by: Stefan Reinauer <reinauer@google.com>
2012-03-15Use keyboard controller for hard reset instead of CF9Vadim Bendebury
For some still unknown reason writes to localtion 0xcf9 do not cause the Link to reboot, they cause it to shut down instead. While this will have to be investigated and fixed, this change modifies the code to use the keyboard controller (implemented by the EC on Link) to restart the system. Once the 0xcf9 problem is resolved, this change could be reverted. BUG=chrome-os-partner:8397 TEST=manual . when u-boot tires restarting the system it now reboots. before this change it would just shut down. Change-Id: I8076f897304f705e20ec8f2e30cce17d7fdd31c4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/18332 Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2012-03-15gen: Get disk/part_dos.c to compile when CONFIG_SYS_64BIT_LBA is turned onGabe Black
The code in this file tries to print an LBA using the format specifier "%10ld", but when CONFIG_SYS_64BIT_LBA is turned on, the argument passed in this position is a 64 bit value and isn't compatible. This change selects the appropriate format specifier, the original or "10lld", based on whether CONFIG_SYS_64BIT_LBA is turned on. BUG=chrome-os-partner:8180 TEST=Built for Stumpy with BUILD_PART_FS_STUFF turned on and CONFIG_SYS_64BIT_LBA enabled and disable, and saw the compile errors go away. Change-Id: Ib80b1567ce07673aea2b47dfba9b3526b32f9de5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18219 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-03-15arm: Tegra3: pass board id through the dts filesVarun Wadekar
BUG=chromium-os:23496 TEST=build on Waluigi, Seaboard, Cardhu Change-Id: I9ccd3085fb551e9887815592e9b518b6944beda7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14474 Reviewed-by: Simon Glass <sjg@chromium.org>
2012-03-14gen: Make the AHCI code find the capacity of disks > 128 GB properlyGabe Black
In the structure returned by the ATA identify device command, there are two fields which describe the device capacity. One is a 32 bit data type which reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs, the small value is the only value with the correct size. If it supports more, if the number of sectors is small enough to fit into 28 bits, both fields reflect the correct value. If it's too large, the smaller field has 28 bits of 1s, 0xfffffff, and the other field has the correct value. The AHCI driver is implemented by attaching to the generic SCSI code and translating on the fly between SCSI binary data structures and AHCI data structures. It responds to requests to execute specific SCSI commands by executing the equivalent AHCI commands and then crafting a response which matches what a SCSI disk would send. The AHCI driver now considers both fields and chooses the correct one when implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands. BUG=chrome-os-partner:8180 TEST=Built and booted to ChromeOS with this code on a CRB with a 250 GB drive and a Stumpy with a 16 GB drive. Checked the serial output to make sure U-Boot reported the correct size. Forced the READ CAPACITY (10) command to saturate so that the READ CAPACITY (16) command would be used and verified that that also booted correctly on a CRB. Change-Id: I31b662498f4c9657d70bb90400032c83e9d9c8da Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18061 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-03-13gen: Make the SCSI command aware of READ CAPACITY (16) and how to use itGabe Black
The generic SCSI code in U-Boot was only aware of the READ CAPACITY (10) SCSI command which can detect the size of disks up to 2TB in size. If that size is exceeded, it should then try the READ CAPACITY (16) command which returns a 64 bit block count value. BUG=chrome-os-partner:8180 TEST=In conjunction with the next change, built and booted into ChromeOS on the Emerald Lake 2 CRB with a 250 GB SSD. Did the same but forced the READ CAPACITY (10) command to saturate and the code to fall back to READ CAPACITY (16). Note that this code has not be tested with a real SCSI disk, just the AHCI code pretending to be a SCSI disk as it historically has. Change-Id: Ia0ee3fa1264649f25065658d5d368101d39ce614 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18060 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-03-13x86: config: Turn on the CONFIG_SYS_64BIT_LBA option for corebootGabe Black
BUG=chrome-os-partner:8180 TEST=Built and booted on emeraldlake2 and Stumpy. Change-Id: If14ff4930015fae36d421fd30ab5bd126c464db9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18059 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2012-03-13gen: Make the SCSI and USB drivers compile with the CONFIG_SYS_64BIT_LBA optionGabe Black
These drivers wouldn't compile when the CONFIG_SYS_64BIT_LBA option is turned on because the used fixed size data types in their exported functions when they should have used lbaint_t for the block count parameter. That meant that when the sizes happened to be the same, when using a 28 bit LBA, the driver would build, but when it wasn't, a 48 bit LBA, things broke. This change adjusts the signatures to use the right type and makes small adjustments in the affected functions. BUG=chrome-os-partner:8180 TEST=Built for emeraldlake2 with the CONFIG_SYS_64BIT_LBA option enabled and saw its compile errors go away. Change-Id: I7443b5976d3d06b82070344011fba46a28bd77de Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18058 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
2012-03-13x86: Add an emeraldlake2 device treeGabe Black
BUG=chrome-os-partner:8180 TEST=Built u-boot for emeraldlake2. Change-Id: Iae62f047ddc102fbf530e1f8f9af34939971a6a3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/18057 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2012-03-08tegra: Remove keyboard support from fdtSimon Glass
This uses a format which is not supported by the upstream dtc, so remove this. BUG=chromium-os:23249 TEST=emerge-tegra2_kaen chromeos-u-boot with new dtc Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I18b9420dbee20c2d115cc5ff1b13425faffe2a3e Reviewed-on: https://gerrit.chromium.org/gerrit/17630
2012-02-28Print firmware version in tab screenStefan Reinauer
In bug reports with screen shots of the firmware screens with tab pressed, it would be extremely useful to see the version of the currently running firmware and the read-only firmware, so output this information. BUG=none TEST=press TAB at dev screen, see firmware versions printed on the screen. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: If91d4b1da8a7f69ff797b0b00c507248139601cd Reviewed-on: https://gerrit.chromium.org/gerrit/17002 Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
2012-02-28Don't ever return from cold_reboot() functionStefan Reinauer
cold_reboot() should wait until the reset kicks in, instead of returning and continuing in an undefined code path. Without this patch, vboot_twostop will return, and secure_boot() will start printing an error message, which results in a sporadic # on the screen when pressing space or ESC on the dev screen in order to go to recovery mode. BUG=chrome-os-partner:7683 TEST=boot to dev screen on lumpy, press ESC or space. Observe there is no # character printed before going to recovery mode. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ic2ee570032686e48603f0fb3b1ec9cbfae9451bc Reviewed-on: https://gerrit.chromium.org/gerrit/17007 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
2012-02-27Add flag fast-developer-mode to make default developer mode time on x86 2sStefan Reinauer
This will trigger setting gbb.flags to 1 in cros_bundle_firmware so the factory time is reduced. GBB.flags will be changed in the factory process. Also needs https://gerrit.chromium.org/gerrit/#change,16845 BUG=chrome-os-partner:7671 TEST=manual emerge-stumpy chromeos-bootimage gbb_utility -g --flags /build/stumpy/firmware/image.bin Should report "flags: 0x00000001" Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie05433ad737005bd5dcca2f88232b0a5bbd00df9 Reviewed-on: https://gerrit.chromium.org/gerrit/16113 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
2012-02-27tegra: configs: enable warm boot on CardhuVarun Wadekar
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT BUG=chromium-os:23496 TEST=build and boot on Cardhu Change-Id: If21303468193c7f5f6ba1c0c0b7cd0ccb5a08c0e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13801
2012-02-27tegra: configs: enable warm boot on WaluigiVarun Wadekar
enable CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT BUG=chromium-os:23496 TEST=build and boot on Waluigi Change-Id: I622d228d02767954ffa7e101ad6f5f5fb1146702 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13802
2012-02-27arm: tegra3: add warmboot code needed for LP0Varun Wadekar
BUG=chromium-os:23496 TEST=build and boot on Waluigi, Cardhu by enabling CONFIG_TEGRA_LP0 and CONFIG_TEGRA3_WARMBOOT. odification of the work done by: a. Jimmy Zhang <jimmzhang@nvidia.com> b. Yen Lin <yelin@nvidia.com> c. Wei Ni <wni@nvidia.com> Change-Id: If2fa63ccd23341694955bca25fb5cfc4a8a805ad Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/13800
2012-02-24arm: tegra: move warmboot_avp.h over to common locationVarun Wadekar
warmboot_avp.h needs to be present in include/arch-tegra in order to use it for Tegra3. BUG=chromium-os:23496 TEST=build for Seaboard Change-Id: I3f369194e4002e8257c9d2ff37253bc20733138d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/15394
2012-02-24arm: tegra3: header file for the MC/EMC registersVarun Wadekar
BUG=chromium-os:23496 TEST=build for Cardhu, Waluigi and Seaboard Change-Id: I6d26502d1ecc393b266ffe06b540f59c595e19ae Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/14811
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