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The i.MX 7 detection taken from upstream U-Boot adds a new macro
MXC_CPU_MX7S. The downstream U-Boot still has one runtime occurence
which currently checks for MXC_CPU_MX7D only. Fix this SoC detection
to detect MXC_CPU_MX7S too.
Note: While the GPT timer is available on i.MX 7, it is currently
not configured (CONFIG_GPT_TIMER). Instead, the CPU internal
syscounter timer is currently used (CONFIG_SYSCOUNTER_TIMER).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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For mx7 the code needn't make provisions, we can use the simple
variant of fuse_bank_physical. Also U-Boot does not allow multi-
platform (MX6/MX7) configurations, hence we can use compile time
defines which select the simpler variant for MX7 always.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Remove code which does not change anything. This also synchronizes
this function with the upstream variant of it.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Just release TPS65911 GPIO1 (EN_CORE_DVFS_N) connected to TPS62362
VSEL1 to switch VDD_CORE back to boot set 1 defaulting to 1.200V.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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On i.MX 6 and i.MX 7 U-Boot does wait until the measured SOC temperature
is below a certain limit.
On i.MX 6 this was 80°C, on i.MX7 85°C.
Put this consistently to 90°C to allow the extended/industrial temperature
rated modules to boot at elevated temperatures.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Due to an undefined pin muxing function being used for CAM_MCLK_PCC0
that pin got locked and did no more allow for the Linux kernel and/or
our GPIOConfig tool to make any further modifications.
On Apalis T30 this pin is used as camera master clock CAM1_MCLK which
was impossible to do due to it being locked while on Colibri T30 this
pin is just multiplexed with the SD/MMC card clock MM_CLK which is
tri-stated by default anyway.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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'run setupdate' tries a number of update media to find an update script
and then sources it.
Each media is probed by its own run set<media>update, however if a script
is found it is not sourced immediately but this task is delegated to
'run setupdate'. Thus one cannot just do a 'run setethupdate' to only
try to update over Ethernet.
This also unifies the functionality with Colibri VF and Colibri iMX7
were it has been implemented like this for a while now.
While at it use consistently ${loadaddr}.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Create a variable to boot the Cortex-M4 core. By default, the command
is not doing anything. Flash a firmware into the UBI volume using:
Colibri iMX7 # ubi part ubi
Colibri iMX7 # fatload ${interface} 0:1 ${loadaddr} hello_world.bin
Colibri iMX7 # ubi write ${loadaddr} m4firmware ${filesize}
And set the command to boot the firmware automatically:
Colibri iMX7 # setenv m4boot 'ubi read 0x7F8000 m4firmware && bootaux 0x7F8000'
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Ethernet packages with IEEE 802.1Q VLAN support may be up to 1522
bytes long. Increase the default size used to allocate packet
storage by 4 bytes.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Change file and other names resp. strings to apalis-tk1 rather than
apalis_tk1 due to upstream Linux kernel device tree maintainers no
longer allowing any underscores to be used in any such.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Synchronize initramfs related configuration options and improve
memory layout. The memory layout with an offset of 16MiB allows
to boot bigger kernels. With AUTO_ZRELADDR, which is pretty much
the standard nowadays, the kernel relacates itself to PC masked
with 0xf8000000 plus a text offset of 0x8000 (hence 0x80008000 for
Vybrid/i.MX 7 or 0x10008000 for i.MX 6). To avoid that the kernel
overwrites itself during uncompress, move the kernel further away
from its decompressed location. With a 16MiB offset from the start
of memory and a 16MiB distance to the device-tree, we allow kernel
up to ~16MiB.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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With the next release our update scripts write the kernel and
device tree in seperate UBI volumes. This allows to use a lot
less UBI/UBIFS support in U-Boot, which should lower the risk
of hitting bugs in this area.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Regular HDA mode requires the TK1 SoC being the master to drive the
DAP1_BIT_CLK and DAP1_SYNC pins therefore do not tristate their
outputs. Further more despite the level shifter direction of those pins
being called Shift_CTRL_Dir_In[2] those need to be configured as output
for regular HDA mode.
Note: If connecting to a I2S codec operating in master mode (e.g. as on
our i.MX 6 designs) the later would have to be changed to inputs again.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Use the exact SoC information from the soc environment variable to
load the device tree file for the Colibri iMX7S or iMX7D.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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This can be useful if the same U-Boot binary is used for boards
available with a i.MX 7Solo and i.MX 7Dual.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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To properly reset a Colibri iMX7 the PMIC reset capabilities need
to be used.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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The command usb reset potentially requires to deregister USB keyboards,
hence enable it if USB Keyboards are enabled.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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The i.MX 7Solo only has one USB controller. Do not enable USB_PEN
but return a -ENODEV return code instead. This allows "usb start"
to work properly on Colibri iMX7S modules.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Read the number of cores in the fuses to distinguish between
the dual and solo versions.
Tested on a mx7d sabresd and on a mx7solo warp7.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit e25a0656bac63c5fcd20ef4313dc09c409fc512d)
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Enabled RDC (resource domain controller) to isolate peripherals between
the A7(s) and M4 core.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only.
CM4 image will set the M4 to domain 1 only.
This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and
setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the peripherals/masters definitions and registers base addresses
for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC.
Signed-off-by: Ye.Li <B37916@freescale.com>
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We can rely on finish bit for temperature reading for TO1.1.
Also introduce CHIP_REV_xx macros for 7D.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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i.MX7D TO1.1 changes DDR retension mode control to IOMUXC_GPR,
add support to this change for LPSR which needs to exit from
DDR retension mode.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
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U-Boot on Apalis iMX6 has a known problem:
Apparently Apalis iMX6 does not works with Gigabit switches...
Limiting speed to 10/100Mbps, and setting master mode, seems to
be the only way to have a successful PHY auto negotiation.
How to fix: Understand why Linux kernel do not have this issue.
However, the current work around did not take effect since the
generic phy config function (which gets called after the board
level work-around) reenabled gigabit advertisment again.
Use the newly introduced environment variable to disable gigabit
Ethernet advertisement.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Disable Gigabit ethernet advertisment when the environment variable
"disable_giga" is set. This feature is already present in the KSZ9023,
this patch implements the same functionality as part of phylib.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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The four level shifter output enables Shift_CTRL_OE[0 to 2 and 4] were
wrongly pulled up therefore disabling the respective pin's input resp.
output capabilities.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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With the next release our update scripts write the kernel and
device tree in seperate UBI volumes. This allows to use a lot
less UBI/UBIFS support in U-Boot, which should lower the risk
of hitting bugs in this area. Boot times are also slightly
faster (measurements showed an improvement of ~150ms).
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Implement optional PCIe EvalBoard initialisation which properly reset the PLX
(now Avago) PEX 8605 PCIe switch plus PCIe devices on the Apalis Evaluation
carrier board.
Please note that you will have to enable the second PCIe port in the dts as well
e.g.:
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index be4f4d6..321c7d6 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -59,6 +59,7 @@
};
pci@2,0 {
+ status = "okay";
nvidia,num-lanes = <1>;
};
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Make sure the Intel i210 gigabit Ethernet controller gets properly enabled by
disabling DEV_OFF_N in the initialisation sequence.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Fix PCIe gigabit Ethernet initialisation by explicitly
controlling +V3.3_ETH provided by LDO9 and LDO10.
Note: For this to work an assembly option needs to be
patched on the current prototypes.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Newer U-Boot changed the DCD alignment with the effect that the
MMDCx_MDCTL reg/val pair moved 4 bytes.
Move away from a hardcoded offset and parse the IVT and DCD table
to find the correct location.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Get rid of the noatime mount option as L4T resp. Ubuntu does not seem to like
that one at all and rather fails booting as follows:
* Starting NVIDIA specific init script [fail]
...
* Starting NSM status monitor [ OK ]
The disk drive for / is not ready yet or not present.
keys:Continue to wait, or Press S to skip mounting or M for manual recovery
* Starting NSM status monitor [ OK ]
...
* Starting NSM status monitor [fail]
* Stopping NSM status monitor [ OK ]
* Starting Bridge socket events into upstart [ OK ]
The mount now defaults to relatime.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Adding command availability check for update fusing command useful for
update scripts.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Adding update fusing command to assist in updating modules to the fast
boot mode as per the following article on our developer website:
http://developer.toradex.com/knowledge-base/linux-booting#eMMC_Fast_Boot_Mode_ApalisColibri_iMX6
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
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Currently a divider of 6 has been used, leading to following NAND
Flash Controller (NFC) clocks:
VF61: 27.7 MHz (166.7MHz bus clock)
VF50: 22 MHz (132MHz bus clock)
The NAND Flash Memory used on VF50 allows to use clock speed of
up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can
use the same divider of 4 on both modules to configure the maximal
possible clock speeds:
VF61: 41.7 MHz
VF50: 33 MHz
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Configure the Ricoh PMIC RN5T567 at startup to reset the board
without delay.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Add power driver for Ricoh PMIC used on Colibri iMX7.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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With the next release our update scripts write the kernel and
device tree in seperate UBI volumes. This allows to use a lot
less UBI/UBIFS support in U-Boot, which should lower the risk
of hitting bugs in this area. Boot times are also slightly
faster (measurements showed an improvement of ~150ms).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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