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Since we use the same UART to download U-Boot and get the U-Boot
prompt, it is quite hard to switch between the download program
and the terminal emulator within the boot delay. This patch
disables the automatic boot by setting the bootdelay to -1 when
using the recovery mode (serial downloader).
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Detect VF5xx CPU's by reading the CPU count register. Also we can
guess the second number of the CPU type (VF6x0) which indicates the
presence of a L2 cache.
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The boot ROM was not able to detect bad blocks in the U-Boot area
due to disabled "bad block marking swap" functionality. The
description of this field is a bit unclear, but tests show that
skipping bad blocks in U-Boot area only work if this field is set
to 0.
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On migration from 2011.11 to 2014.04 U-Boot the initialization
code also switched the source of the DRAM clock to system clock.
However, since Colibri VF61 runs on 500MHz system clock, we
should use PLL2 as DRAM clock.
This also broke suspend on resume: The system switches to 24MHz
FIRC as system clock when entering suspend mode while still
running from DRAM. However, DRAM seems not to work on 24MHz,
which then lead to a system freeze during entering suspend mode.
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Define the environment partition r/w in order to write the environment
from Linux. Also define ENV_RANGE to make use of the whole parittion
in case the partition contains bad blocks.
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additionally fix missing whitespace in LCD sample
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Enable the SCSC (Slow Clock Source Controller) and select the
external 32KHz oscillator. This improves accuracy of the RTC.
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while at it
- clean up environment variables and names
- make setupdate work with both SD/MMC slots
- add example for VDAC video out
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Use of malloc of do_fat_write() causes cache error on ARM v7 platforms.
Perhaps, the same problem will occur at any other CPUs.
This replaces malloc with memalign to fix cache buffer alignment.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Yoshiyuki Ito <yoshiyuki.ito.ub@renesas.com>
Tested-by: Hector Palacios <hector.palacios@digi.com>
(cherry picked from commit 8abd053cf07a1e4264d59c671e05a602fc7a31ad)
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Apalis iMX6+ 1GB V1.0A V1.0B are wired for DCE, now that the code is prepared
for DTE switch back to DCE.
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Enable VERSION_VARIABLE in order to be able to check U-Boot version
from update scripts.
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The Apalis standart uses the UART in DTE mode.
This commit uses UART1 in DTE mode for the U-Boot console and
configures all used UARTs to start in DTE mode.
Note that for this to work module version V1.0A requires TXD/RXD to be crossed
between the Apalis iMX6 and the RS232 transceiver.
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Environment offset was set to block 6 (0xC0000), which is still
inside the U-Boot partition. Since U-Boot is small enouth to fit
in the first 5 blocks, it usually is not an issue, however if
one of this 5 blocks is bad, then the environment overwrites part
of the boot loader. This fix sets the environment to erase block 12
(0x180000).
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Increase boot delay to one second again as otherwise one is not able to enter
into the interactive U-Boot console when recovering U-Boot via UART (e.g. doing
./update.sh -d /dev/ttyUSB0).
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Change to a Toradex email address.
Properly handle malloc return value.
Re-implement memory kernel argument passing in order to properly use
all available memory even on our currently used kernel.
Re-integrate U-Boot board size limit checking.
Re-add CMD_ASKENV and CMD_EXT2 but disable CMD_FLASH and CMD_LOADB/S
again.
Get rid of spurious double CMD_BOOTZ define.
Enable VERSION_VARIABLE in order to be able to check U-Boot version
from our update scripts.
Change boot delay to zero and enable ZERO_BOOTDELAY_CHECK to be more
in-line with our other BSPs.
Re-integrate vidargs environment handling.
Added setupdate command introduced on Apalis iMX6 to ease update
procedure from SD card.
While at it ran it through checkpatch.pl and cleaned it up.
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follow 10fda48779fc86e74e4482cbc7667431237cf60c
i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents
follow 164d98466103a46b7c881149e92ec2a28a6375be
Move setup_sata to common part
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follow commit 02824dc78642b3057cc8c1ab7dc32203f55a17fa
ARM: mx6: Update non-Freescale boards to include CPU errata.
follow commit b089d039b1971fc3abfe1d9bcebd0d35245fb110
i2c: update config using mxc driver to new subsystem
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follow commit a79854a90f7297ddfda2114c867fd62643fa6e3a
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2014.04-colibri_vf
Conflicts:
boards.cfg
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Move load address to the beginning of RAM to maximize available
RAM for filesystem images.
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Use UBI root partition according to MTD partition name.
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Use default environment which boots from UBI. Add commands to boot
from NFS or MMC as available on other Toradex modules.
Also configure default IP address and command prompt.
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Detect Colibri VF50 modules by read L2 cache configuration of the
running CPU. Colibri VF50 modules come without L2 cache. Configure
CPU clock accordingly.
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Add support for Toardex specific config block. This data structure
is available on NAND and written at production time. Get MAC
address as well as serial number and board revision from this
structure.
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This enables NAND for Colibri VF61/VF50. The environment is now
taken from NAND. The first block, the boot control block, is
definied as a seperate partition in order for easier erasing.
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This adds initial support for Colibri VF61 based on Freescale
Vybrid Tower System TWR-VF65GS10:
- New Machine ID
- Default UART_A on SCI0
- FEC1
- Enabled command line editing
- PLL5 based RMII clocking (e.g. no external crystal)
- UART_A and UART_C I/O muxing
- Boot from OCRAM gfxRAM
Tested on Colibri VF61 V1.1 booting using serial loader over
UART.
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Add an additional target which prepends the u-boot.imx image with
0x400 padding bytes. On Vybrid, this is required for NAND boot
devices. The configuration CONFIG_IMX_NAND enables this image
for a board.
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Add writebcb command which creates a NAND Boot Configuration Block
at the beginning of the active flash device. The offset of the
boot firmware are specified using arguments, at least one location
is mandatory.
Currently only the FCB (Firmware Configuration Block) is supported,
the DBBT (Discovered Bad Block Table) is optional and is not
used currently.
The firmware, e.g. U-Boot (along with the IVT header and a 0x400
long prefix) need to be written to NAND seperatly.
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This adds initial support for Freescale NFC (NAND Flash Controller).
The IP is used in ARM based Vybrid SoCs as well as on some PowerPC
devices. This driver is only tested on Vybrid.
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Add pin mux for NAND Flash Controller.
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Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.
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The i.MX V2 headers total size is 0x7fc. The header is placed
in front of the U-Boot binary which of course is aligned to
text base. Hence the header starting point is not page
aligned (e.g. at 0x3f400404). This is still a valid header,
which boots fine using serial loader. However, the image
fails to boot from NAND (tested on a VF61x SoC).
Most parts of the header have a length of a multiply of 16
bytes.The rest of the header is filled with 8 bytes long DCD
data. Only the boot data header is 3 word long (12 bytes).
This patch makes sure the whole image is exactly 0x800 by
adding one padding word after the boot data header. Since
the individual data structures are referenced by pointers,
this still results in a valid i.MX V2 header while
maintaining page alignment.
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Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves DDR3
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.
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Signed-off-by: Tom Rini <trini@ti.com>
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Add CONFIG_SYS_GENERIC_BOARD to use common/board_[fr].c for kzm9g.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework
Before commit 2035d77d, i2c probe command works properly on kzm9g board.
KZM-A9-GT# i2c probe
Valid chip addresses: 0C 12 1D 32 39 3D 40 60
After commit 2035d77d, i2c probe command does not work.
KZM-A9-GT# i2c probe
Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
sh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Commit d016dc42cedbf6102e100fa9ecb58462edfb14f8 changed the layout of BCH8 SW
on omap3 boards. We need to adopt the ecc layout for the nand_spl_simle
driver to avoid wrong ecc errors.
Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de>
Cc: Thomas Weber <thomas.weber@corscience.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de>
Cc: Thomas Weber <thomas.weber@corscience.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Commit 890880583d84607e36b52a785a96b167728bbf73 introduced EEPROM parsing and
board detection but faild to return a valid tricorder_eeprom struct for backup
case. When pressing S200 while reading EEPROM we ignore the value. We
returned falsely a tricorder_eeprom struct with uninitialized data which is
just garbage.
Initialize it by zeroing the whole structure.
Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de>
Cc: Thomas Weber <thomas.weber@corscience.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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During switch to device tree, commit 1ecab0f has removed this code.
INFORM4 and INFORM5 registers are used by TRATS2 first stage bootloader for
providing recovery. For normal operation, those two must be cleared out.
This error emerges when one force reset from u-boot's command line for
three times.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
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In some use cases, SPL linker script was not updated even when
it should be.
For instance,
$ make tricoder_config all
[ build complete ]
... modify include/configs/tricoder.h
$ make
spl/u-boot-spl.lds should be updated in this case, but it wasn't.
To fix this problem, linker scripts generation should be handled
by $(call if_changed_dep,...) rather than by $(call if_changed,...).
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reported-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
include/configs/trats.h
include/configs/trats2.h
include/mmc.h
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This patch add gicv3 support to uboot armv8 platform.
Changes for v2:
- rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
- move smp_kick_all_cpus() from gic.S to start.S, it would be
implementation dependent.
- Each core initialize it's own ReDistributor instead of master
initializeing all ReDistributors. This is advised by arnab.basu
<arnab.basu@freescale.com>.
Signed-off-by: David Feng <fenghua@phytium.com.cn>
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The conditional is using a variable that is not defined.
Signed-off-by: Rommel G Custodio <sessyargc+u-boot@gmail.com>
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When flush the d$ with set/way instruction, it need calculate the way's
offset = log2(Associativity); but in current uboot's code, it use below
formula to calculate the offset: log2(Associativity * 2 - 1), so finally
it cannot flush data cache properly.
Signed-off-by: Leo Yan <leoy@marvell.com>
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For ARMv8, U-boot has been running at EL3 with cache and MMU enabled.
Without proper setup for EL2, cache and MMU are both disabled (out of
reset). Before switching, we need to flush the dcache to make sure the
data is in the main memory.
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: David.Feng <fenghua@phytium.com.cn>
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