| Age | Commit message (Collapse) | Author |
|---|
|
Without this, when CONFIG_ENV_VARS_UBOOT_CONFIG is active we get
a compile time error when doing 'make env'.
In file included from tools/env/fw_env.c:117:0:
include/env_default.h:110:11: error: expected ‘}’ before ‘CONFIG_SYS_ARCH’
When building U-Boot this is included indirectly by the compiler switch
-include
/home/trdx/git.toradex.com/u-boot-2014.10-toradex/include/linux/kconfig.h
|
|
This patch fixes operation of our on-board AX88772B chip without EEPROM
but with a ethaddr coming from the regular U-Boot environment. This is
a forward port of some remaining parts initially implemented by
Antmicro.
|
|
DDR leveling parameters are board specific, hence we should be able
to set them differently per board. Extract the leveling parameters
in a seperate struct to be able to set them per board.
|
|
With the new JEDEC standardized initialization parameter, the
initialization takes longer than 200us. Use the status bit to
determine whether the memory initialization was completed.
Also use recommended JEDEC defaults for t_INIT.
|
|
On VF50, we can use PLL1 as DDR clock since the CPU is clocked
with 400MHz as well. This saves some power (measured around ~10mW).
|
|
Add Toradex config block support using the new common config block
handling. Extend common config block handling to support reading
from NAND too.
|
|
Migrate Apalis/Colibri T30 to U-Boot 2014.10 and integrate new update
concept based on Apalis/Colibri iMX6 and Colibri VF50/VF61.
|
|
Add common confg block hanlding. The config block is a Toradex
specific data structure containing manufacturing data and static
module information such as ethernet address.
|
|
Now that the FW/SW synchronisation is fixed we can reduce the hack
introduced by the following commit:
02bf24ad4a7c882e25771f656b973d5458695cf0
e1000: i210/i211 hack
Note that we leave one final hack for now required for unprogrammed
i210 operation.
|
|
I finally had a look at the datasheet and spotted an additional
register address difference between regular E1000 and i210/i211 chips.
This patch fixes this and now successfully works on programmed
i210/i211 as well as unprogrammed i211.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
|
|
Commit 951860634fdb557bbb58e0f99215391bc0c29779 may have changed
the logic unintentially from "if (!(swfw_sync & (fwmask | swmask)))"
to "if ((swfw_sync & swmask) && !(swfw_sync & fwmask))". This change
breaks some e1000 NIC with a message "ERROR: Unable to read EEPROM!".
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Marek Vasut <marex@denx.de>
CC: Tim Harvey <tharvey@gateworks.com>
|
|
Migrating our BSPs towards mainline U-Boot I noticed it suddenly booting
slower. With mainline Linux I noticed about a 1 to 2 second increase
while booting downstream L4T takes 10 to 15 seconds longer!
This reverts commit 858530a8c0a7ce7e573e513934804a00d6676813.
Conflicts:
drivers/serial/Makefile
|
|
Synchronize environment with i.MX6 U-boot. Load device tree
unconditionally, but set parameter to device tree file only when
loading succeeded. Also load the device tree when using SD or NFS
boot.
|
|
Switch to zImage for SD and NFS-Boot. Explicitly define the load
address in all commands.
|
|
Newer UBI implementation do not allow small UBI partitions since
the amount of bad blocks is now calculated by the size of the MTD
partition (instead volume size). On small partitions, this leads
to UBI partitions only consisting of reserved blocks. Therefor we
now use only one volume, which also allows better wear leveling
and bad block management.
Since it is needed to attach the whole UBI partition, mounting
the UBI filesystem would be a good option. Measurement showed that
the overhead reading from UBI filesystem compared to read from
a UBI volume is minimal (below 100ms).
Furthermore, this also adds support to load device trees for newer,
device tree based kernels. By setting the variable fdt_board, the
scripts read the FDT file and try to pass this to the kernel. The
FDT file will be concatinated:
${soc}-colibri-{fdt_board}.dtb
E.g. when fdt_board is set to "eval-v3", the scripts will load the
device tree file "vf610-colibri-eval-v3.dtb" on a Colibri VF61.
|
|
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows to use
the variable ${soc} for Linux device tree files.
|
|
Enables caches which provides a rather huge speedup of the boot
loader. Also mark the on-chip RAM as cachable since this is the
area U-Boot runs from.
|
|
Since we use the same UART to download U-Boot and get the U-Boot
prompt, it is quite hard to switch between the download program
and the terminal emulator within the boot delay. This patch
disables the automatic boot by setting the bootdelay to -1 when
using the recovery mode (serial downloader).
|
|
Detect VF5xx CPU's by reading the CPU count register. Also we can
guess the second number of the CPU type (VF6x0) which indicates the
presence of a L2 cache.
|
|
The boot ROM was not able to detect bad blocks in the U-Boot area
due to disabled "bad block marking swap" functionality. The
description of this field is a bit unclear, but tests show that
skipping bad blocks in U-Boot area only work if this field is set
to 0.
|
|
Enable the SCSC (Slow Clock Source Controller) and select the
external 32KHz oscillator. This improves accuracy of the RTC.
|
|
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC. The board support package is based on Freescale Tower
board, with following differences:
- CPU clocked at 500MHz
- Use PLL2 as DDR3 clock (400MHz)
- New Machine ID
- Console on UART1 (Colibri UART_A)
- Ethernet on FEC1
- Enabled command line editing
- PLL5 based RMII clocking (e.g. no external crystal)
- UART_A and UART_C I/O muxing
- Boot from OCRAM gfxRAM
- Boot from NAND by default
Tested on Colibri VF50/VF61 booting using serial loader over UART.
|
|
Add an additional target which prepends the u-boot.imx image with
0x400 padding bytes. On Vybrid, this is required for NAND boot
devices. The configuration CONFIG_IMX_NAND enables this image
for a board.
|
|
Add writebcb command which creates a NAND Boot Configuration Block
at the beginning of the active flash device. The offset of the
boot firmware are specified using arguments, at least one location
is mandatory.
Currently only the FCB (Firmware Configuration Block) is supported,
the DBBT (Discovered Bad Block Table) is optional and is not
used currently.
The firmware, e.g. U-Boot (along with the IVT header and a 0x400
long prefix) need to be written to NAND seperatly.
|
|
The i.MX V2 headers total size is 0x7fc. The header is placed
in front of the U-Boot binary which of course is aligned to
text base. Hence the header starting point is not page
aligned (e.g. at 0x3f400404). This is still a valid header,
which boots fine using serial loader. However, the image
fails to boot from NAND (tested on a VF61x SoC).
Most parts of the header have a length of a multiply of 16
bytes.The rest of the header is filled with 8 bytes long DCD
data. Only the boot data header is 3 word long (12 bytes).
This patch makes sure the whole image is exactly 0x800 by
adding one padding word after the boot data header. Since
the individual data structures are referenced by pointers,
this still results in a valid i.MX V2 header while
maintaining page alignment.
|
|
In order to avoid code duplication move the DDR initialization to
the common place under imx-common. Currently, only TREF, TRFC,
COL_DIFF and ROW_DIFF can be choosen from board file.
|
|
Prepare v2014.10
|
|
Signed-off-by: Tom Rini <trini@ti.com>
|
|
Currently uboot wrongly uses 25mV / step for dcdc3, this is a copy and paste
error introduced when adding the axp152_mvolt_to_target during review of the
axp152.c driver. This results in u-boot setting Vddr to 2.3V instead of 1.5V.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
|
With the introduction of CONFIG_LOCALVERSION support we cannot build
tools without having a config file (as we won't know our PLAIN_VERSION
until then).
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Tom Rini <trini@ti.com>
|
|
|
|
Now with everything in place actually enable i210/i211 aka gigabit
Ethernet over PCIe support.
|
|
Hack driver to avoid the following error for now
e1000: e1000#0: ERROR: Hardware Initialization Failed
|
|
This patch adds support for i211 as well as unprogrammed aka tools only
i210/i211 chip support.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
|
|
This network interface card in found on the NVIDIA Jetson TK1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
RX and TX descriptor rings should be aligned to 256 byte boundaries. Use
the DEFINE_ALIGN_BUFFER() macro to define the buffers so that they don't
have to be manually aligned later on. Also make sure that the buffers do
align to cache-line boundaries in case the cache-line is higher than the
256 byte alignment requirements of the NIC.
Also add a warning if the cache-line size is larger than the descriptor
size, because the driver may discard changes to descriptors made by the
hardware when requeuing RX buffers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
According to the top-level README file, this configuration setting can
be used to override the number of receive buffers that an ethernet NIC
uses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Some boards, most notably those with a PCIe ethernet NIC, require this
to avoid cache coherency problems. Since the option adds very little
code and overhead enable it across all Tegra generations. Other drivers
may also start supporting this functionality at some point, so enabling
it now will automatically reap the benefits later on.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Conflicts:
include/configs/tegra-common.h
|
|
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).
The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).
While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Conflicts:
README
|
|
'u-boot-arm/master'
|
|
|
|
When DEBUG is set, output memory region used for malloc().
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
|
size_t is the canonical type to represent variables that contain a size.
Use it instead of signed integer. Physical addresses can be larger than
32-bit, so use a more appropriate type for them as well. phys_addr_t is
a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
the system is 64-bit or uses a form of physical address extension to use
a larger address space on 32-bit systems. Using these types the same API
can be implemented on a wider range of systems.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Remove two gratuituous blank lines, uses u32 (instead of int) as the
type for values that will be written to a register, moves the beginning
of the variable declaration section to a separate line (rather than the
one with the opening brace) and keeps the function signature on a single
line where possible.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
|
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Add the device tree node for the PCIe controller found on Tegra124 SoCs.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.
In addition the board has a mini-PCIe expansion slot.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
|
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
