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Unify code with Apalis iMX6 while not changing behaviour
Add board_rev to the U-Boot environment. On V1.0A HW: 010a
Add CONFIG_ENV_VARS_UBOOT_CONFIG
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- Default to DTE UART mode, as used on HW V1.1 but automatically fall back
to use DCE UART on V1.0 HW.
- If using the default device tree filename imx6q-apalis-eval.dtb, switch to
the V1.0 devicetree on V1.0 HW. If device tree name is not the default leave
it alone.
- Add board_rev to the U-Boot environment. On V1.0A HW: 010a
- Add CONFIG_ENV_VARS_UBOOT_CONFIG
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- Add a 2GB RAM configuration with quick and dirty DDR optimization values.
- Make sure the device-tree is not relocated to high-memory.
- Configure eMMC reset to GPIO with pullup. The boot ROM already did a pulse.
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This is needed during production or Ethernet will not work.
This partly reverts commit b5e9ee3bb9ac34d6073083e1ccb4fda3ef45426a.
While at it fix coding style.
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- use PWM 4 through a buffer for BL_PWM
- use UARTs in DTE mode (Pinout change from V1.1 HW)
- enable mtest
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Be consistent with other Toradex products
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Be consistent with other Toradex products
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This gives a fast basic ram test.
While at it clean up whitespace
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remove double defines
remove unneeded environment
remove usb nic driver
move defines to were they logically belong
move the (unused) ramdisk_addr_r out of the addresses used for the kernel
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Without this X does not start on a Colibri iMX6S for lack of RAM.
galcore.contiguousSize=50331648 (48MB)
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Adds the patch_ddr_size cmd which patches the DCD data structure
settings for the DDR memory controller optimized for the module.
Currently this is only the bus width which is changed from 32bit
to 64bit on DL modules.
This allows to use a unified U-Boot for S and DL modules. Right after
flashing the U-Boot to eMMC this cmd will be run to complete the
update.
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http://lists.denx.de/pipermail/u-boot/2012-September/134347.html
allows for reading files in chunks from the shell.
When this feature is used to read past the end of a file an error
was returned instead of returning the bytes read up to the end of
file. Thus the following fails in the shell:
offset = 0
len = chunksize
do
read file, offset, len
write data
until bytes_read < len
The patch changes the behaviour to printing an informational
message and returning the actual read number of bytes.
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Prepare for additional SKU's
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UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.
This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.
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The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.
Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.
Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.
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Since we use the same UART to download U-Boot and get the U-Boot
prompt, it is quite hard to switch between the download program
and the terminal emulator within the boot delay. This patch
disables the automatic boot by setting the bootdelay to -1 when
using the recovery mode (serial downloader).
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Detect VF5xx CPU's by reading the CPU count register. Also we can
guess the second number of the CPU type (VF6x0) which indicates the
presence of a L2 cache.
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The boot ROM was not able to detect bad blocks in the U-Boot area
due to disabled "bad block marking swap" functionality. The
description of this field is a bit unclear, but tests show that
skipping bad blocks in U-Boot area only work if this field is set
to 0.
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On migration from 2011.11 to 2014.04 U-Boot the initialization
code also switched the source of the DRAM clock to system clock.
However, since Colibri VF61 runs on 500MHz system clock, we
should use PLL2 as DRAM clock.
This also broke suspend on resume: The system switches to 24MHz
FIRC as system clock when entering suspend mode while still
running from DRAM. However, DRAM seems not to work on 24MHz,
which then lead to a system freeze during entering suspend mode.
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Define the environment partition r/w in order to write the environment
from Linux. Also define ENV_RANGE to make use of the whole parittion
in case the partition contains bad blocks.
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additionally fix missing whitespace in LCD sample
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Enable the SCSC (Slow Clock Source Controller) and select the
external 32KHz oscillator. This improves accuracy of the RTC.
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while at it
- clean up environment variables and names
- make setupdate work with both SD/MMC slots
- add example for VDAC video out
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Use of malloc of do_fat_write() causes cache error on ARM v7 platforms.
Perhaps, the same problem will occur at any other CPUs.
This replaces malloc with memalign to fix cache buffer alignment.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Yoshiyuki Ito <yoshiyuki.ito.ub@renesas.com>
Tested-by: Hector Palacios <hector.palacios@digi.com>
(cherry picked from commit 8abd053cf07a1e4264d59c671e05a602fc7a31ad)
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Apalis iMX6+ 1GB V1.0A V1.0B are wired for DCE, now that the code is prepared
for DTE switch back to DCE.
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Enable VERSION_VARIABLE in order to be able to check U-Boot version
from update scripts.
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The Apalis standart uses the UART in DTE mode.
This commit uses UART1 in DTE mode for the U-Boot console and
configures all used UARTs to start in DTE mode.
Note that for this to work module version V1.0A requires TXD/RXD to be crossed
between the Apalis iMX6 and the RS232 transceiver.
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