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2014-06-27colibri vf50/61: fix environment offsetStefan Agner
Environment offset was set to block 6 (0xC0000), which is still inside the U-Boot partition. Since U-Boot is small enouth to fit in the first 5 blocks, it usually is not an issue, however if one of this 5 blocks is bad, then the environment overwrites part of the boot loader. This fix sets the environment to erase block 12 (0x180000).
2014-05-23colibri vf50/61: increase boot delay to fix uart loadingColibri_VF_LinuxImageV2.2Beta1_20140603Marcel Ziswiler
Increase boot delay to one second again as otherwise one is not able to enter into the interactive U-Boot console when recovering U-Boot via UART (e.g. doing ./update.sh -d /dev/ttyUSB0).
2014-05-23colibri vf50/61: fix various issuesMarcel Ziswiler
Change to a Toradex email address. Properly handle malloc return value. Re-implement memory kernel argument passing in order to properly use all available memory even on our currently used kernel. Re-integrate U-Boot board size limit checking. Re-add CMD_ASKENV and CMD_EXT2 but disable CMD_FLASH and CMD_LOADB/S again. Get rid of spurious double CMD_BOOTZ define. Enable VERSION_VARIABLE in order to be able to check U-Boot version from our update scripts. Change boot delay to zero and enable ZERO_BOOTDELAY_CHECK to be more in-line with our other BSPs. Re-integrate vidargs environment handling. Added setupdate command introduced on Apalis iMX6 to ease update procedure from SD card. While at it ran it through checkpatch.pl and cleaned it up.
2014-05-06apalis_imx6: changed pad names and setup_sataMax Krummenacher
follow 10fda48779fc86e74e4482cbc7667431237cf60c i.MX6DQ/DLS: replace pad names with their Linux kernel equivalents follow 164d98466103a46b7c881149e92ec2a28a6375be Move setup_sata to common part
2014-05-06ARM: mx6: CPU errata and I2C changesMax Krummenacher
follow commit 02824dc78642b3057cc8c1ab7dc32203f55a17fa ARM: mx6: Update non-Freescale boards to include CPU errata. follow commit b089d039b1971fc3abfe1d9bcebd0d35245fb110 i2c: update config using mxc driver to new subsystem
2014-05-06board: arm: convert makefiles to Kbuild styleMax Krummenacher
follow commit a79854a90f7297ddfda2114c867fd62643fa6e3a
2014-05-06Merge remote-tracking branch 'remotes/origin/toradex_imx6' into ↵Max Krummenacher
2014.04-colibri_vf Conflicts: boards.cfg
2014-04-30colibri_vf: move load addressStefan Agner
Move load address to the beginning of RAM to maximize available RAM for filesystem images.
2014-04-29colibri_vf: fix ubi root partitionStefan Agner
Use UBI root partition according to MTD partition name.
2014-04-28colibri_vf: change default environmentStefan Agner
Use default environment which boots from UBI. Add commands to boot from NFS or MMC as available on other Toradex modules. Also configure default IP address and command prompt.
2014-04-24colibri_vf: add detection for Colibri VF50Stefan Agner
Detect Colibri VF50 modules by read L2 cache configuration of the running CPU. Colibri VF50 modules come without L2 cache. Configure CPU clock accordingly.
2014-04-24colibri_vf: add Toradex config blockStefan Agner
Add support for Toardex specific config block. This data structure is available on NAND and written at production time. Get MAC address as well as serial number and board revision from this structure.
2014-04-24colibri_vf: enable NAND and use environment from NANDStefan Agner
This enables NAND for Colibri VF61/VF50. The environment is now taken from NAND. The first block, the boot control block, is definied as a seperate partition in order for easier erasing.
2014-04-24arm: vf610: initial integration for Colibri VF61Stefan Agner
This adds initial support for Colibri VF61 based on Freescale Vybrid Tower System TWR-VF65GS10: - New Machine ID - Default UART_A on SCI0 - FEC1 - Enabled command line editing - PLL5 based RMII clocking (e.g. no external crystal) - UART_A and UART_C I/O muxing - Boot from OCRAM gfxRAM Tested on Colibri VF61 V1.1 booting using serial loader over UART.
2014-04-24imx: add u-boot-nand.imx targetStefan Agner
Add an additional target which prepends the u-boot.imx image with 0x400 padding bytes. On Vybrid, this is required for NAND boot devices. The configuration CONFIG_IMX_NAND enables this image for a board.
2014-04-23imx: add writebcb commandStefan Agner
Add writebcb command which creates a NAND Boot Configuration Block at the beginning of the active flash device. The offset of the boot firmware are specified using arguments, at least one location is mandatory. Currently only the FCB (Firmware Configuration Block) is supported, the DBBT (Discovered Bad Block Table) is optional and is not used currently. The firmware, e.g. U-Boot (along with the IVT header and a 0x400 long prefix) need to be written to NAND seperatly.
2014-04-23mtd: nand: add Freescale NFC driverStefan Agner
This adds initial support for Freescale NFC (NAND Flash Controller). The IP is used in ARM based Vybrid SoCs as well as on some PowerPC devices. This driver is only tested on Vybrid.
2014-04-23arm: vf610: add NFC pin muxStefan Agner
Add pin mux for NAND Flash Controller.
2014-04-23arm: vf610: add NFC clock supportStefan Agner
Add NFC (NAND Flash Controller) clock support and enable them at board initialization time.
2014-04-23tools: make imxheader size align on page sizeStefan Agner
The i.MX V2 headers total size is 0x7fc. The header is placed in front of the U-Boot binary which of course is aligned to text base. Hence the header starting point is not page aligned (e.g. at 0x3f400404). This is still a valid header, which boots fine using serial loader. However, the image fails to boot from NAND (tested on a VF61x SoC). Most parts of the header have a length of a multiply of 16 bytes.The rest of the header is filled with 8 bytes long DCD data. Only the boot data header is 3 word long (12 bytes). This patch makes sure the whole image is exactly 0x800 by adding one padding word after the boot data header. Since the individual data structures are referenced by pointers, this still results in a valid i.MX V2 header while maintaining page alignment.
2014-04-23arm: vf610: add DDR_SEL_PAD_CONTR registerStefan Agner
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves DDR3 issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual.
2014-04-14Prepare v2014.04v2014.04Tom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2014-04-14arm: kzm9g: Add CONFIG_SYS_GENERIC_BOARDTetsuyuki Kobayashi
Add CONFIG_SYS_GENERIC_BOARD to use common/board_[fr].c for kzm9g. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-14i2c: sh_i2c: bugfix: i2c probe command does not workTetsuyuki Kobayashi
This is regression of commit 2035d77d i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework Before commit 2035d77d, i2c probe command works properly on kzm9g board. KZM-A9-GT# i2c probe Valid chip addresses: 0C 12 1D 32 39 3D 40 60 After commit 2035d77d, i2c probe command does not work. KZM-A9-GT# i2c probe Valid chip addresses: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F sh_i2c_probe() calls sh_i2c_read(), but read length is 0. So acutally it does not read device at all. This patch prepares dummy buffer and read data into it. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-04-11board:tricorder: fixup SPL OOB layoutAndreas Bießmann
Commit d016dc42cedbf6102e100fa9ecb58462edfb14f8 changed the layout of BCH8 SW on omap3 boards. We need to adopt the ecc layout for the nand_spl_simle driver to avoid wrong ecc errors. Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de> Cc: Thomas Weber <thomas.weber@corscience.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-04-11board:tricorder: enable omap_gpio clocksAndreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de> Cc: Thomas Weber <thomas.weber@corscience.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-04-11board:tricorder: always work with valid eeprom dataAndreas Bießmann
Commit 890880583d84607e36b52a785a96b167728bbf73 introduced EEPROM parsing and board detection but faild to return a valid tricorder_eeprom struct for backup case. When pressing S200 while reading EEPROM we ignore the value. We returned falsely a tricorder_eeprom struct with uninitialized data which is just garbage. Initialize it by zeroing the whole structure. Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de> Cc: Thomas Weber <thomas.weber@corscience.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-04-11arm:board:trats2:FIX: Clear INFORM4 and INFORM5 registers at correct bootŁukasz Majewski
During switch to device tree, commit 1ecab0f has removed this code. INFORM4 and INFORM5 registers are used by TRATS2 first stage bootloader for providing recovery. For normal operation, those two must be cleared out. This error emerges when one force reset from u-boot's command line for three times. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-04-11kbuild: fix a bug in regeneration of linker scriptsMasahiro Yamada
In some use cases, SPL linker script was not updated even when it should be. For instance, $ make tricoder_config all [ build complete ] ... modify include/configs/tricoder.h $ make spl/u-boot-spl.lds should be updated in this case, but it wasn't. To fix this problem, linker scripts generation should be handled by $(call if_changed_dep,...) rather than by $(call if_changed,...). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reported-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-04-08Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD
Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile include/configs/trats.h include/configs/trats2.h include/mmc.h
2014-04-08arm64 patch: gicv3 supportDavid Feng
This patch add gicv3 support to uboot armv8 platform. Changes for v2: - rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S - move smp_kick_all_cpus() from gic.S to start.S, it would be implementation dependent. - Each core initialize it's own ReDistributor instead of master initializeing all ReDistributors. This is advised by arnab.basu <arnab.basu@freescale.com>. Signed-off-by: David Feng <fenghua@phytium.com.cn>
2014-04-07bootstage: arm: fix fdt stashing codeMela Custodio
The conditional is using a variable that is not defined. Signed-off-by: Rommel G Custodio <sessyargc+u-boot@gmail.com>
2014-04-07ARMv8: fix bug for flush data cache by set/wayLeo Yan
When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com>
2014-04-07armv8: Flush dcache before switching to EL2York Sun
For ARMv8, U-boot has been running at EL3 with cache and MMU enabled. Without proper setup for EL2, cache and MMU are both disabled (out of reset). Before switching, we need to flush the dcache to make sure the data is in the main memory. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: David.Feng <fenghua@phytium.com.cn>
2014-04-07arm: vf610: fix double iomux configuration for vf610twr boardMarcel Ziswiler
Get rid of double VF610_PAD_DDR_A15__DDR_A_15 iomux configuration. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2014-04-07arm: vf610: add enet1 supportMarcel Ziswiler
This patch contains several changes required for second Ethernet (enet1/RMII1) port on vf610 - ANADIG PLL5 control definitions required for Ethernet RMII1 clock - Secondary Ethernet (enet1) MAC RMII1 base address definition - RMII1 iomux definitions - VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for internal (e.g. crystal-less) Ethernet clocking. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-04-07arm: vf610: add uart0 clock/iomux definitionsMarcel Ziswiler
Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux definitions for UART0 (aka. SCI0). Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-04-07arm: vf610: fix anadig register structMarcel Ziswiler
The anadig_reg structure started at the wrong offset (fixed by adding reserved_0x000[4]), was missing some reserved field required for alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl) and further contained a too short reserved field causing further miss- alignment (reserved_0x0C4[7]). Also, rename all the reserved fields and using a memory offset based scheme for. Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl); Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
2014-04-07build:arm: Remove setting of CROSS_COMPILE environment variableŁukasz Majewski
After Kbuild introduction, the CROSS_COMPILE environment variable has been set to some default value (prefix arm-linux-). This shall be removed since it breaks building u-boot for native arm target (like qemu ARM). Moreover not all compilers have arm-linux- prefix. Additionally the u-boot cross compiles with CROSS_COMPILE= set explicitly- e.g.: CROSS_COMPILE=/ .... /arm-v7a-linux-gnueabi- make Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-04-07Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-04-07MX6: Enable ARM errata workaround 794072 and 761320Nitin Garg
Since MX6 is Cortex-A9 r2p10, enable software workaround for errata 794072 and 761320. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-04-07ARM: Add workaround for Cortex-A9 errata 761320Nitin Garg
Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-04-07ARM: Add workaround for Cortex-A9 errata 794072Nitin Garg
A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation. Exists on r1, r2, r3, r4 revisions. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2014-04-07armv8/cache: Change cache invalidate and flush functionYork Sun
When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
2014-04-07armv8/cache: Flush D-cache, invalidate I-cache for relocationYork Sun
If D-cache is enabled, we need to flush it, and invalidate i-cache before jumping to the new location. This should be done right after relocation. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
2014-04-07armv8/cache: Consolidate setting for MAIR and TCRYork Sun
Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with sub-architecture. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
2014-04-07arm: Handle .gnu.hash section in ldscriptsAndreas Färber
Avoids "could not find output section .gnu.hash" ld.bfd errors on openSUSE. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-04-07socfpga: Adding Clock Manager driverChin Liang See
Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2014-04-04Revert "Start the deprecation process for generic board"Tom Rini
We've run into a non-trivial conversion to CONFIG_SYS_GENERIC_BOARD so we'll postpone this notice until right after v2014.04 is out. This reverts commit 36c4b1d98059244c34ec3327d9cc9f3c552fd01b. Signed-off-by: Tom Rini <trini@ti.com>
2014-04-04arm: mxs: Add support for generating signed BootStreamMarek Vasut
This patch adds the groundwork for generating signed BootStream, which can be used by the HAB library in i.MX28. We are adding a new target, u-boot-signed.sb , since the process for generating regular non-signed BootStream is much easier. Moreover, the signed bootstream depends on external _proprietary_ _binary-only_ tool from Freescale called 'cst', which is available only under NDA. To make things even uglier, the CST or HAB mandates a kind-of circular dependency. The problem is, unlike the regular IVT, which is generated by mxsimage, the IVT for signed boot must be generated by hand here due to special demands of the CST. The U-Boot binary (or SPL binary) and IVT are then signed by the CST as a one block. But here is the problem. The size of the entire image (U-Boot, IVT, CST blocks) must be appended at the end of IVT. But the size of the entire image is not known until the CST has finished signing the U-Boot and IVT. We solve this by expecting the CST block to be always 3904B (which it is in case two files, U-Boot and the hand-made IVT, are signed in the CST block). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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