diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/at91sam9260ek.h | 76 | ||||
| -rw-r--r-- | include/configs/at91sam9261ek.h | 72 | ||||
| -rw-r--r-- | include/configs/at91sam9263ek.h | 138 | ||||
| -rw-r--r-- | include/configs/at91sam9g20ek.h | 22 | ||||
| -rw-r--r-- | include/configs/at91sam9rlek.h | 25 |
5 files changed, 69 insertions, 264 deletions
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index e9a9f4eddc..a4883d68ce 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -112,76 +112,23 @@ #define NAND_MAX_FLOORS 1 #undef CFG_NAND_WP -/*#define AT91_SMART_MEDIA_ALE (1 << 21)*/ /* our ALE is AD21 */ -/*#define AT91_SMART_MEDIA_CLE (1 << 22)*/ /* our CLE is AD22 */ - -/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung) - * for MASTER_CLOCK = 48000000. They were generated according to - * K9F1216U0A timings and for MASTER_CLOCK = 48000000. - * Please refer to SMC section in AT91SAM9261 datasheet to learn how - * to generate these values. - */ - -/* -#define AT91C_SM_NWE_SETUP (0 << 0) -#define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) -#define AT91C_SM_NCS_RD_SETUP (0 << 24) - -#define AT91C_SM_NWE_PULSE (2 << 0) -#define AT91C_SM_NCS_WR_PULSE (3 << 8) -#define AT91C_SM_NRD_PULSE (2 << 16) -#define AT91C_SM_NCS_RD_PULSE (4 << 24) - -#define AT91C_SM_NWE_CYCLE (3 << 0) -#define AT91C_SM_NRD_CYCLE (5 << 16) - -#define AT91C_SM_TDF (1 << 16) -*/ - -/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung) - * for MASTER_CLOCK = 100000000. They were generated according to - * K9F1216U0A timings and for MASTER_CLOCK = 100000000. - * Please refer to SMC section in AT91SAM9261 datasheet to learn how - * to generate these values. - */ - -/* These timings are specific to K9F1216U0A (samsung) */ -/* -#define AT91C_SM_NWE_SETUP (0 << 0) -#define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) -#define AT91C_SM_NCS_RD_SETUP (0 << 24) - -#define AT91C_SM_NWE_PULSE (3 << 0) -#define AT91C_SM_NCS_WR_PULSE (3 << 8) -#define AT91C_SM_NRD_PULSE (4 << 16) -#define AT91C_SM_NCS_RD_PULSE (4 << 24) - -#define AT91C_SM_NWE_CYCLE (5 << 0) -#define AT91C_SM_NRD_CYCLE (5 << 16) -*/ - /* These timings are specific to MT29F2G16AAB 256Mb (Micron) * at MCK = 100 MHZ */ - -#define AT91C_SM_NWE_SETUP (0 << 0) +#define AT91C_SM_NWE_SETUP (1 << 0) #define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) +#define AT91C_SM_NRD_SETUP (1 << 16) #define AT91C_SM_NCS_RD_SETUP (0 << 24) -#define AT91C_SM_NWE_PULSE (4 << 0) -#define AT91C_SM_NCS_WR_PULSE (6 << 8) -#define AT91C_SM_NRD_PULSE (3 << 16) -#define AT91C_SM_NCS_RD_PULSE (5 << 24) +#define AT91C_SM_NWE_PULSE (3 << 0) +#define AT91C_SM_NCS_WR_PULSE (3 << 8) +#define AT91C_SM_NRD_PULSE (3<< 16) +#define AT91C_SM_NCS_RD_PULSE (3<< 24) -#define AT91C_SM_NWE_CYCLE (6 << 0) +#define AT91C_SM_NWE_CYCLE (5 << 0) #define AT91C_SM_NRD_CYCLE (5 << 16) -#define AT91C_SM_TDF (1 << 16) - - +#define AT91C_SM_TDF (2 << 16) #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 @@ -222,13 +169,6 @@ #define CFG_NO_FLASH 1 -#undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_DATAFLASH 1 -#undef CFG_ENV_IS_IN_NAND - -/*#define CONFIG_MTD_DEBUG 1 -#define CONFIG_MTD_DEBUG_VERBOSE MTD_DEBUG_LEVEL3 -*/ #ifdef CFG_ENV_IS_IN_NAND #define CFG_ENV_OFFSET 0x60000 /* environment starts here */ #define CFG_ENV_OFFSET_REDUND 0x80000 /* redundant environment starts here */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index ce21a97cdf..9483ec81f6 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -82,6 +82,7 @@ #define CONFIG_COMMANDS \ ((CONFIG_CMD_DFL | \ CFG_CMD_NET | \ + CFG_CMD_PING | \ CFG_CMD_ENV | \ CFG_CMD_USB | \ CFG_CMD_FLASH | \ @@ -111,71 +112,23 @@ #define NAND_MAX_FLOORS 1 #undef CFG_NAND_WP -/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung) - * for MASTER_CLOCK = 48000000. They were generated according to - * K9F1216U0A timings and for MASTER_CLOCK = 48000000. - * Please refer to SMC section in AT91SAM9261 datasheet to learn how - * to generate these values. - */ - -/* -#define AT91C_SM_NWE_SETUP (0 << 0) -#define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) -#define AT91C_SM_NCS_RD_SETUP (0 << 24) - -#define AT91C_SM_NWE_PULSE (2 << 0) -#define AT91C_SM_NCS_WR_PULSE (3 << 8) -#define AT91C_SM_NRD_PULSE (2 << 16) -#define AT91C_SM_NCS_RD_PULSE (4 << 24) - -#define AT91C_SM_NWE_CYCLE (3 << 0) -#define AT91C_SM_NRD_CYCLE (5 << 16) - -#define AT91C_SM_TDF (1 << 16) -*/ - -/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung) - * for MASTER_CLOCK = 100000000. They were generated according to - * K9F1216U0A timings and for MASTER_CLOCK = 100000000. - * Please refer to SMC section in AT91SAM9261 datasheet to learn how - * to generate these values. - */ - -/* These timing are specific to K9F1216U0A (samsung) */ -/* -#define AT91C_SM_NWE_SETUP (0 << 0) -#define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) -#define AT91C_SM_NCS_RD_SETUP (0 << 24) - -#define AT91C_SM_NWE_PULSE (3 << 0) -#define AT91C_SM_NCS_WR_PULSE (3 << 8) -#define AT91C_SM_NRD_PULSE (4 << 16) -#define AT91C_SM_NCS_RD_PULSE (4 << 24) - -#define AT91C_SM_NWE_CYCLE (5 << 0) -#define AT91C_SM_NRD_CYCLE (5 << 16) -*/ - /* These timings are specific to MT29F2G16AAB 256Mb (Micron) * at MCK = 100 MHZ */ - -#define AT91C_SM_NWE_SETUP (0 << 0) +#define AT91C_SM_NWE_SETUP (1 << 0) #define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) +#define AT91C_SM_NRD_SETUP (1 << 16) #define AT91C_SM_NCS_RD_SETUP (0 << 24) -#define AT91C_SM_NWE_PULSE (4 << 0) -#define AT91C_SM_NCS_WR_PULSE (6 << 8) +#define AT91C_SM_NWE_PULSE (3 << 0) +#define AT91C_SM_NCS_WR_PULSE (3 << 8) #define AT91C_SM_NRD_PULSE (3 << 16) -#define AT91C_SM_NCS_RD_PULSE (5 << 24) +#define AT91C_SM_NCS_RD_PULSE (3 << 24) -#define AT91C_SM_NWE_CYCLE (6 << 0) +#define AT91C_SM_NWE_CYCLE (5 << 0) #define AT91C_SM_NRD_CYCLE (5 << 16) -#define AT91C_SM_TDF (1 << 16) +#define AT91C_SM_TDF (2 << 16) @@ -271,15 +224,18 @@ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_ENV_IS_IN_DATAFLASH 1 -#undef CFG_ENV_IS_IN_FLASH - #ifdef CFG_ENV_IS_IN_DATAFLASH #define CFG_ENV_OFFSET 0x4000 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4000 /* 0x8000 */ #endif +#ifdef CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 /* environment starts here */ +#define CFG_ENV_OFFSET_REDUND 0x80000 /* redundant environment starts here */ +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128kB */ +#endif + #ifdef CFG_ENV_IS_IN_FLASH #ifdef CONFIG_BOOTBINFUNC #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index f942393739..86a528b315 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -32,27 +32,20 @@ * If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_INIT_CRITICAL /* undef for developing */ /* ARM asynchronous clock */ #define CRYSTAL_16_36766MHZ 1 #ifdef CRYSTAL_16_36766MHZ - -#define AT91C_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal (16367000 / 14 * 171) */ -#define AT91C_MASTER_CLOCK (199919000/2) /* peripheral clock (AT91C_MAIN_CLOCK / 2) */ - + #define AT91C_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal (16367000 / 14 * 171) */ + #define AT91C_MASTER_CLOCK (199919000/2) /* peripheral clock (AT91C_MAIN_CLOCK / 2) */ #endif #ifdef CRYSTAL_18_432MHZ - -#define AT91C_MAIN_CLOCK 198656000 /* from 16.367 MHz crystal (16367000 / 5 * 61) */ -#define AT91C_MASTER_CLOCK (198656000/2) /* peripheral clock (AT91C_MAIN_CLOCK / 2) */ - + #define AT91C_MAIN_CLOCK 198656000 /* from 16.367 MHz crystal (16367000 / 5 * 61) */ + #define AT91C_MASTER_CLOCK (198656000/2) /* peripheral clock (AT91C_MAIN_CLOCK / 2) */ #endif -/* #define AT91C_MASTER_CLOCK 48000000 */ - #define AT91_SLOW_CLOCK 32768 /* slow clock */ #define CFG_HZ 1000 @@ -70,7 +63,7 @@ /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_MALLOC_LEN (3*CFG_ENV_SIZE + 128*1024) #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_BAUDRATE 115200 @@ -113,9 +106,9 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define NAND_MAX_CHIPS 1 /* Max number of NAND devices */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CFG_NAND_BASE 0x40000000 +#define NAND_MAX_CHIPS 1 /* Max number of NAND devices */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CFG_NAND_BASE 0x40000000 #define CONFIG_NEW_NAND_CODE #define ADDR_COLUMN 1 @@ -124,7 +117,7 @@ #define NAND_ChipID_UNKNOWN 0 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 +#undef CFG_NAND_WP /* SMC Chip select 0 timings for NorFlash S29JL032H for MASTER_CLOCK = 100 MHZ. @@ -142,108 +135,25 @@ #define AT91C_FLASH_NWE_CYCLE (7 << 0) #define AT91C_FLASH_NRD_CYCLE (7 << 16) - -/* SMC Chip select 0 timings for NorFlash S29JL032H - for MASTER_CLOCK = 48 MHZ. -*/ -/*#define AT91C_FLASH_NWE_SETUP (1 << 0) -#define AT91C_FLASH_NCS_WR_SETUP (0 << 8) -#define AT91C_FLASH_NRD_SETUP (0 << 16) -#define AT91C_FLASH_NCS_RD_SETUP (0 << 24) - -#define AT91C_FLASH_NWE_PULSE (2 << 0) -#define AT91C_FLASH_NCS_WR_PULSE (5 << 8) -#define AT91C_FLASH_NRD_PULSE (4 << 16) -#define AT91C_FLASH_NCS_RD_PULSE (4 << 24) - -#define AT91C_FLASH_NWE_CYCLE (5 << 0) -#define AT91C_FLASH_NRD_CYCLE (4 << 16) -*/ #define AT91C_FLASH_TDF (7 << 16) - - - -/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung) - for MASTER_CLOCK = 48000000. They were generated according to - K9F1216U0A timings and for MASTER_CLOCK = 48000000. - Please refer to SMC section in AT91SAM9263 datasheet to learn how - to generate these values. -*/ -/* -#define AT91C_SM_NWE_SETUP (0 << 0) -#define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) -#define AT91C_SM_NCS_RD_SETUP (0 << 24) - -#define AT91C_SM_NWE_PULSE (2 << 0) -#define AT91C_SM_NCS_WR_PULSE (3 << 8) -#define AT91C_SM_NRD_PULSE (2 << 16) -#define AT91C_SM_NCS_RD_PULSE (4 << 24) - -#define AT91C_SM_NWE_CYCLE (3 << 0) -#define AT91C_SM_NRD_CYCLE (5 << 16) - -#define AT91C_SM_TDF (1 << 16) -*/ - -/* SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung) - for MASTER_CLOCK = 100000000. They were generated according to - K9F1216U0A timings and for MASTER_CLOCK = 100000000. - Please refer to SMC section in AT91SAM9263 datasheet to learn how - to generate these values. - - These timings are specific to K9F1216U0A (samsung) -*/ -/* -#define AT91C_SM_NWE_SETUP (0 << 0) -#define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) -#define AT91C_SM_NCS_RD_SETUP (0 << 24) - -#define AT91C_SM_NWE_PULSE (3 << 0) -#define AT91C_SM_NCS_WR_PULSE (3 << 8) -#define AT91C_SM_NRD_PULSE (4 << 16) -#define AT91C_SM_NCS_RD_PULSE (4 << 24) - -#define AT91C_SM_NWE_CYCLE (5 << 0) -#define AT91C_SM_NRD_CYCLE (5 << 16) -*/ - -/* These timings are specific to TC58DVG02AFT1 (Toshiba) - at MCK = 100 MHZ -*/ -#define AT91C_SM_NWE_SETUP (0 << 0) +/* These timings are specific to 256Mb (Micron) + * at MCK = 100 MHZ + */ +#define AT91C_SM_NWE_SETUP (1 << 0) #define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (5 << 16) +#define AT91C_SM_NRD_SETUP (1 << 16) #define AT91C_SM_NCS_RD_SETUP (0 << 24) #define AT91C_SM_NWE_PULSE (3 << 0) -#define AT91C_SM_NCS_WR_PULSE (6 << 8) -#define AT91C_SM_NRD_PULSE (4 << 16) -#define AT91C_SM_NCS_RD_PULSE (11 << 24) - -#define AT91C_SM_NWE_CYCLE (6 << 0) -#define AT91C_SM_NRD_CYCLE (11 << 16) - -/* These timings are specific to TC58DVG02AFT1 (Toshiba) - at MCK = 48 MHZ -*/ -/*#define AT91C_SM_NWE_SETUP (0 << 0) -#define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (3 << 16) -#define AT91C_SM_NCS_RD_SETUP (0 << 24) - -#define AT91C_SM_NWE_PULSE (2 << 0) -#define AT91C_SM_NCS_WR_PULSE (4 << 8) -#define AT91C_SM_NRD_PULSE (2 << 16) -#define AT91C_SM_NCS_RD_PULSE (6 << 24) +#define AT91C_SM_NCS_WR_PULSE (3 << 8) +#define AT91C_SM_NRD_PULSE (3 << 16) +#define AT91C_SM_NCS_RD_PULSE (3 << 24) -#define AT91C_SM_NWE_CYCLE (4 << 0) -#define AT91C_SM_NRD_CYCLE (6 << 16) -*/ -#define AT91C_SM_TDF (1 << 16) +#define AT91C_SM_NWE_CYCLE (5 << 0) +#define AT91C_SM_NRD_CYCLE (5 << 16) +#define AT91C_SM_TDF (2 << 16) #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 @@ -284,8 +194,11 @@ #define CFG_FLASH_ERASE_TOUT (1000*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_DATAFLASH 1 +#ifdef CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 /* environment starts here */ +#define CFG_ENV_OFFSET_REDUND 0x80000 /* redundant environment starts here */ +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128kB */ +#endif #ifdef CFG_ENV_IS_IN_DATAFLASH #define CFG_ENV_OFFSET 0x4000 @@ -293,7 +206,6 @@ #define CFG_ENV_SIZE 0x4000 /* 0x8000 */ #endif - #ifdef CFG_ENV_IS_IN_FLASH #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ #define CFG_ENV_SIZE 0x2000 /* 0x8000 */ diff --git a/include/configs/at91sam9g20ek.h b/include/configs/at91sam9g20ek.h index 306f294083..81eb84eca9 100644 --- a/include/configs/at91sam9g20ek.h +++ b/include/configs/at91sam9g20ek.h @@ -36,7 +36,6 @@ /* ARM asynchronous clock */ #define AT91C_MASTER_CLOCK 132096000 /* peripheral clock */ - #define AT91_SLOW_CLOCK 32768 /* slow clock */ #define CFG_HZ 1000 @@ -115,21 +114,20 @@ /* These timings are specific to MT29F2G16AAB 256Mb (Micron) * at MCK = 100 MHZ */ - -#define AT91C_SM_NWE_SETUP (0 << 0) +#define AT91C_SM_NWE_SETUP (2 << 0) #define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) +#define AT91C_SM_NRD_SETUP (2 << 16) #define AT91C_SM_NCS_RD_SETUP (0 << 24) #define AT91C_SM_NWE_PULSE (4 << 0) -#define AT91C_SM_NCS_WR_PULSE (6 << 8) -#define AT91C_SM_NRD_PULSE (3 << 16) -#define AT91C_SM_NCS_RD_PULSE (5 << 24) +#define AT91C_SM_NCS_WR_PULSE (4 << 8) +#define AT91C_SM_NRD_PULSE (4 << 16) +#define AT91C_SM_NCS_RD_PULSE (4 << 24) -#define AT91C_SM_NWE_CYCLE (6 << 0) -#define AT91C_SM_NRD_CYCLE (5 << 16) +#define AT91C_SM_NWE_CYCLE (7 << 0) +#define AT91C_SM_NRD_CYCLE (7 << 16) -#define AT91C_SM_TDF (1 << 16) +#define AT91C_SM_TDF (3 << 16) @@ -169,10 +167,6 @@ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_DATAFLASH 1 -#undef CFG_ENV_IS_IN_NAND - #ifdef CFG_ENV_IS_IN_NAND #define CFG_ENV_OFFSET 0x60000 /* environment starts here */ #define CFG_ENV_OFFSET_REDUND 0x80000 /* redundant environment starts here */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 1618df1dd7..0be53dd622 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -51,7 +51,7 @@ /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_MALLOC_LEN (3*CFG_ENV_SIZE + 128*1024) #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_BAUDRATE 115200 @@ -111,20 +111,20 @@ * at MCK = 100 MHZ */ -#define AT91C_SM_NWE_SETUP (0 << 0) +#define AT91C_SM_NWE_SETUP (1 << 0) #define AT91C_SM_NCS_WR_SETUP (0 << 8) -#define AT91C_SM_NRD_SETUP (0 << 16) +#define AT91C_SM_NRD_SETUP (1 << 16) #define AT91C_SM_NCS_RD_SETUP (0 << 24) -#define AT91C_SM_NWE_PULSE (4 << 0) -#define AT91C_SM_NCS_WR_PULSE (6 << 8) +#define AT91C_SM_NWE_PULSE (3 << 0) +#define AT91C_SM_NCS_WR_PULSE (3 << 8) #define AT91C_SM_NRD_PULSE (3 << 16) -#define AT91C_SM_NCS_RD_PULSE (5 << 24) +#define AT91C_SM_NCS_RD_PULSE (3 << 24) -#define AT91C_SM_NWE_CYCLE (6 << 0) +#define AT91C_SM_NWE_CYCLE (5 << 0) #define AT91C_SM_NRD_CYCLE (5 << 16) -#define AT91C_SM_TDF (1 << 16) +#define AT91C_SM_TDF (2 << 16) @@ -157,15 +157,18 @@ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_ENV_IS_IN_DATAFLASH 1 -#undef CFG_ENV_IS_IN_FLASH - #ifdef CFG_ENV_IS_IN_DATAFLASH #define CFG_ENV_OFFSET 0x4000 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) #define CFG_ENV_SIZE 0x4000 /* 0x8000 */ #endif +#ifdef CFG_ENV_IS_IN_NAND +#define CFG_ENV_OFFSET 0x60000 /* environment starts here */ +#define CFG_ENV_OFFSET_REDUND 0x80000 /* redundant environment starts here */ +#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128kB */ +#endif + #ifdef CFG_ENV_IS_IN_FLASH #ifdef CONFIG_BOOTBINFUNC #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ |