diff options
Diffstat (limited to 'board/freescale/imx93_evk/spl.c')
| -rw-r--r-- | board/freescale/imx93_evk/spl.c | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index e0a9df1e5a..9a041af30e 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -67,10 +67,23 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - /* 0.9v - */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){ + /* 0.75v for Low drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); + } else { + /* 0.9v for Over drive mode + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); + } + + /* set standby voltage to 0.65v */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); /* I2C_LT_EN*/ pmic_reg_write(dev, 0xa, 0x3); @@ -105,12 +118,11 @@ void board_init_f(ulong dummy) printf("SOC: 0x%x\n", gd->arch.soc_rev); printf("LC: 0x%x\n", gd->arch.lifecycle); } + power_init_board(); - /* Increase ARM clock to 1.7Ghz */ - ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); - configure_intpll(ARM_PLL_CLK, 1700000000); /* 1.7Ghz */ - ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); + if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + set_arm_core_max_clk(); /* Init power of mix */ soc_power_init(); |