diff options
Diffstat (limited to 'board/freescale/imx8mq_evk/spl.c')
| -rw-r--r-- | board/freescale/imx8mq_evk/spl.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index bb8211dd7c..120810a111 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -218,6 +218,21 @@ int board_fit_config_name_match(const char *name) } #endif +#define GPR_PCIE_VREG_BYPASS BIT(12) +static void enable_pcie_vreg(bool enable) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + if (!enable) { + setbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS); + setbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS); + } else { + clrbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS); + clrbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS); + } +} + void board_init_f(ulong dummy) { int ret; @@ -225,6 +240,9 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); + /* PCIE_VPH connects to 3.3v on EVK, enable VREG to generate 1.8V to PHY */ + enable_pcie_vreg(true); + arch_cpu_init(); init_uart_clk(0); |