diff options
Diffstat (limited to 'arch/arm/dts/k3-j784s4-main.dtsi')
| -rw-r--r-- | arch/arm/dts/k3-j784s4-main.dtsi | 129 |
1 files changed, 118 insertions, 11 deletions
diff --git a/arch/arm/dts/k3-j784s4-main.dtsi b/arch/arm/dts/k3-j784s4-main.dtsi index 9fc098b623..da6241a1d7 100644 --- a/arch/arm/dts/k3-j784s4-main.dtsi +++ b/arch/arm/dts/k3-j784s4-main.dtsi @@ -38,7 +38,7 @@ }; }; - scm_conf: scm-conf@104000 { + scm_conf: system-controller@104000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x00 0x00104000 0x00 0x18000>; #address-cells = <1>; @@ -49,7 +49,24 @@ compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ - <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + <0x88 0x3>, <0x8c 0x3>, /* SERDES0 lane2/3 select */ + <0x90 0x3>, <0x94 0x3>, /* SERDES1 lane0/1 select */ + <0x98 0x3>, <0x9c 0x3>, /* SERDES1 lane2/3 select */ + <0xa0 0x3>, <0xa4 0x3>, /* SERDES2 lane0/1 select */ + <0xa8 0x3>, <0xac 0x3>; /* SERDES2 lane2/3 select */ + }; + + phy_gmii_sel_cpsw0: phy@44 { + compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports = <1>, <3>; + reg = <0x44 0x20>; + #phy-cells = <1>; + }; + + phy_gmii_sel_cpsw1: phy@34 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x34 0x4>; + #phy-cells = <1>; }; usb_serdes_mux: mux-controller1 { @@ -57,15 +74,105 @@ #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + }; - phy_gmii_sel_cpsw: phy@34 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x34 0x4>; - #phy-cells = <1>; + main_cpsw0: ethernet@c000000 { + compatible = "ti,j784s4-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0xc000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0xc000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw0_port1: port@1 { + reg = <1>; + label = "port1"; + ti,mac-only; + }; + + main_cpsw0_port2: port@2 { + reg = <2>; + label = "port2"; + ti,mac-only; + }; + + main_cpsw0_port3: port@3 { + reg = <3>; + label = "port3"; + ti,mac-only; + }; + + main_cpsw0_port4: port@4 { + reg = <4>; + label = "port4"; + ti,mac-only; + }; + + main_cpsw0_port5: port@5 { + reg = <5>; + label = "port5"; + }; + + main_cpsw0_port6: port@6 { + reg = <6>; + label = "port6"; + }; + + main_cpsw0_port7: port@7 { + reg = <7>; + label = "port7"; + }; + + main_cpsw0_port8: port@8 { + reg = <8>; + label = "port8"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 64 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; }; }; - main_cpsw: ethernet@c200000 { + main_cpsw1: ethernet@c200000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; #size-cells = <2>; @@ -94,15 +201,15 @@ #address-cells = <1>; #size-cells = <0>; - main_cpsw_port1: port@1 { + main_cpsw1_port1: port@1 { reg = <1>; ti,mac-only; label = "port1"; - phys = <&phy_gmii_sel_cpsw 1>; + phys = <&phy_gmii_sel_cpsw1 1>; }; }; - main_cpsw_mdio: mdio@f00 { + main_cpsw1_mdio: mdio@f00 { compatible = "ti,cpsw-mdio","ti,davinci_mdio"; reg = <0x0 0xf00 0x0 0x100>; #address-cells = <1>; @@ -514,7 +621,7 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; }; - hwspinlock: spinlock@30e00000 { + hwspinlock: hwlock@30e00000 { compatible = "ti,am654-hwspinlock"; reg = <0x00 0x30e00000 0x00 0x1000>; #hwlock-cells = <1>; |