diff options
Diffstat (limited to 'arch/arm/dts/k3-am625-verdin-r5.dts')
| -rw-r--r-- | arch/arm/dts/k3-am625-verdin-r5.dts | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 6f2cad02cb..9d84d9940b 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -14,9 +14,16 @@ a53_0: a53@0 { compatible = "ti,am654-rproc"; reg = <0x00 0x00a90000 0x00 0x10>; - assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; - assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <1250000000>; + /* + * FIXME: Currently only the SPL running on the R5 has a clock + * driver. As a workaround therefore move the assigned-clock + * stuff required for our ETH_25MHz_CLK from the cpsw3g_mdio + * node of the regular device tree to here (last one each in + * below three lines, adding a <0> as spacing for parents). + */ + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>; + assigned-clock-rates = <200000000>, <1250000000>, <25000000>; clocks = <&k3_clks 61 0>; power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; |