diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 22 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/board.c | 12 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/clock.c | 7 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/display.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/pwfm.c | 11 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra3/warmboot_avp.c | 2 |
6 files changed, 40 insertions, 16 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index 517fba30b1..4f54dd6121 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -146,6 +146,7 @@ int ap20_get_num_cpus(void) return ap20_get_family() == TEGRA_FAMILY_T3x ? 4 : 2; } +/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ int ap20_cpu_is_cortexa9(void) { u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0); @@ -180,7 +181,7 @@ static int pllx_set_rate(struct clk_pll *pll , u32 divn, u32 divm, u32 divp, bf_update(PLL_DIVM, reg, divm); bf_update(PLL_DIVN, reg, divn); bf_update(PLL_DIVP, reg, divp); - bf_update(PLL_BYPASS, reg, 0); + bf_update(PLL_BYPASS, reg, 0); /* Disable BYPASS */ writel(reg, &pll->pll_base); /* Set cpcon to PLLX_MISC */ @@ -197,6 +198,9 @@ static int pllx_set_rate(struct clk_pll *pll , u32 divn, u32 divm, u32 divp, return 0; } +/* U-Boot treats all errors as warnings, &clkrst->crc_pll[CLOCK_ID_XCPU] uses + a subscript out of range. The pragma disables the warning */ +#pragma GCC diagnostic warning "-Warray-bounds" void ap20_init_pllx(int slow) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; @@ -332,10 +336,10 @@ static void enable_cpu_power_rail(enum tegra_family_t family) if (family == TEGRA_FAMILY_T3x) { /* - * TODO(sjg): - * Fow now we do this here. We need to find out what this is + * TODO(sjg): + * For now we do this here. We need to find out what this is * doing, tidy up the code and find a better place for it. - */ + */ tegra_i2c_ll_write_addr(0x005a, 0x0002); tegra_i2c_ll_write_data(0x2328, 0x0a02); udelay(1000); @@ -384,11 +388,11 @@ void t30_init_clocks(void) { #if defined(CONFIG_TEGRA3) /* - * Sadly our clock functions don't support the V and W clocks of T30 - * yet, as well as a few other functions, so use low-level register - * access for now. This eventual removable of low-level code from - * ap20.c is the same process we went through for T20. - */ + * Sadly our clock functions don't support the V and W clocks of T30 + * yet, as well as a few other functions, so use low-level register + * access for now. This eventual removable of low-level code from + * ap20.c is the same process we went through for T20. + */ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; diff --git a/arch/arm/cpu/armv7/tegra-common/board.c b/arch/arm/cpu/armv7/tegra-common/board.c index 5a57298db7..5f772b55b6 100644 --- a/arch/arm/cpu/armv7/tegra-common/board.c +++ b/arch/arm/cpu/armv7/tegra-common/board.c @@ -1,6 +1,8 @@ /* * (C) Copyright 2010,2011 * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2012 + * Toradex, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -37,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; unsigned int board_query_sdram_size(void) { +#ifndef CONFIG_COLIBRI_T20 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; u32 reg; @@ -60,6 +63,15 @@ unsigned int board_query_sdram_size(void) default: return 0x40000000; /* 1GB */ } +#else /* CONFIG_COLIBRI_T20 */ + /* Colibri T20 does not use OdmData */ + u32 *pa_emc_adr_cfg = (void *)NV_PA_EMC_ADR_CFG_BASE; + + u32 reg = readl(pa_emc_adr_cfg); + + /* 4 MB shifted by EMEM_DEVSIZE */ + return (4 << 20) << ((reg & EMEM_DEVSIZE_MASK) >> EMEM_DEVSIZE_SHIFT); +#endif /* CONFIG_COLIBRI_T20 */ } #if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE) diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c index 01caab6b9f..0d1f209165 100644 --- a/arch/arm/cpu/armv7/tegra-common/clock.c +++ b/arch/arm/cpu/armv7/tegra-common/clock.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2012 Toradex, Inc. * See file CREDITS for list of people who contributed to this * project. * @@ -493,6 +494,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { * SPDIF - which is both 0x08 and 0x0c * */ +//I believe above comment concerning SPDIF is bogus #define NONE(name) (-1) #define OFFSET(name, value) PERIPHC_ ## name static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { @@ -1361,11 +1363,14 @@ int clock_early_init(ulong pllp_base) osc_freq_mhz = 12; break; + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + osc_freq_mhz = 13; + break; + case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ osc_freq_mhz = 26; break; - case CLOCK_OSC_FREQ_13_0: case CLOCK_OSC_FREQ_19_2: default: /* diff --git a/arch/arm/cpu/armv7/tegra-common/display.c b/arch/arm/cpu/armv7/tegra-common/display.c index 2f12084447..55ea13e128 100644 --- a/arch/arm/cpu/armv7/tegra-common/display.c +++ b/arch/arm/cpu/armv7/tegra-common/display.c @@ -117,7 +117,7 @@ static int update_display_mode(struct dc_disp_reg *disp, /* * The pixel clock divider is in 7.1 format (where the bottom bit * represents 0.5). Here we calculate the divider needed to get from - * the display clock (typically 600MHz for tegra2 and 216MHZ + * the display clock (typically 600MHz for tegra2 and 216MHz * for tegra3) to the pixel clock. We round up or down as requried. */ #if defined(CONFIG_TEGRA2) diff --git a/arch/arm/cpu/armv7/tegra-common/pwfm.c b/arch/arm/cpu/armv7/tegra-common/pwfm.c index 5ef4363082..bdc1620724 100644 --- a/arch/arm/cpu/armv7/tegra-common/pwfm.c +++ b/arch/arm/cpu/armv7/tegra-common/pwfm.c @@ -30,8 +30,11 @@ void pwfm_setup(struct pwfm_ctlr *pwfm, int enable, int pulse_width, { u32 reg; - reg = bf_pack(PWFM_ENABLE, enable) | - bf_pack(PWFM_WIDTH, pulse_width) | - bf_pack(PWFM_DIVIDER, freq_divider); - writel(reg, &pwfm->control); + if(pwfm != NULL) + { + reg = bf_pack(PWFM_ENABLE, enable) | + bf_pack(PWFM_WIDTH, pulse_width) | + bf_pack(PWFM_DIVIDER, freq_divider); + writel(reg, &pwfm->control); + } } diff --git a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c index 02772d42c1..02d320aed7 100644 --- a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c +++ b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c @@ -81,7 +81,7 @@ void wb_start(void) reg = SCLK_SWAKE_FIQ_SRC_CLKM | SCLK_SWAKE_IRQ_SRC_CLKM | SCLK_SWAKE_RUN_SRC_CLKM | SCLK_SWAKE_IDLE_SRC_CLKM | - SCLK_SYS_STATE_RUN; + SCLK_SYS_CPU_STATE_RUN; writel(reg, &clkrst->crc_sclk_brst_pol); /* Update PLLP output dividers for 408 MHz operation */ |