diff options
Diffstat (limited to 'arch/arm/cpu/armv7/vybrid')
| -rw-r--r-- | arch/arm/cpu/armv7/vybrid/clock.c | 7 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 10 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/vybrid/clock.c b/arch/arm/cpu/armv7/vybrid/clock.c index eea6af0f57..190333943e 100644 --- a/arch/arm/cpu/armv7/vybrid/clock.c +++ b/arch/arm/cpu/armv7/vybrid/clock.c @@ -176,7 +176,12 @@ static u32 get_ipg_clk(void) return freq / div; #else - return 66000000; +#ifdef CONFIG_AUTO_DETECT_FREQUENCY + if (__raw_readl(MSCM_CP0CFG1)) + return 83000000; + else +#endif + return 66000000; #endif } diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S index 8c22e3c365..630e4a8efe 100644 --- a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S +++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S @@ -132,7 +132,17 @@ ldr r1, =CONFIG_SYS_CLKCTRL_CCR str r1, [r0, #CLKCTL_CCR] +#ifdef CONFIG_AUTO_DETECT_FREQUENCY + /* check for L2 cache */ + ldr r2, =MSCM_BASE_ADDR + ldr r1, [r2, #MSCM_CP0CFG1_OFFSET] + cmp r1, #0x0 + ldr r1, =CONFIG_SYS_CLKCTRL_CCSR_400 + /* use 500 MHz if L2 cache present (Colibri VF61) */ + ldrne r1, =CONFIG_SYS_CLKCTRL_CCSR_500 +#else /* CONFIG_AUTO_DETECT_FREQUENCY */ ldr r1, =CONFIG_SYS_CLKCTRL_CCSR +#endif /* CONFIG_AUTO_DETECT_FREQUENCY */ str r1, [r0, #CLKCTL_CCSR] ldr r1, =CONFIG_SYS_CLKCTRL_CACRR |