diff options
43 files changed, 4172 insertions, 1696 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fbe90875ae..5a0f48db6d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1642,10 +1642,6 @@ config TARGET_SL28 help Support for Kontron SMARC-sAL28 board. -config TARGET_COLIBRI_PXA270 - bool "Support colibri_pxa270" - select CPU_PXA - config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select BOARD_LATE_INIT @@ -2029,7 +2025,6 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" -source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b5e73235c0..44ee3de007 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -769,7 +769,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ - fsl-imx8qxp-apalis.dtb \ fsl-imx8qxp-mek.dtb \ imx8-deneb.dtb \ imx8-giedi.dtb @@ -1001,6 +1000,9 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am62x-lp-sk.dtb \ k3-am62x-r5-lp-sk.dtb +dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-verdin.dtb \ + k3-am625-verdin-r5.dtb + dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \ k3-am62a7-r5-sk.dtb diff --git a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi deleted file mode 100644 index e41911a04a..0000000000 --- a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -&{/imx8qx-pm} { - - u-boot,dm-pre-proper; -}; - -&mu { - u-boot,dm-pre-proper; -}; - -&clk { - u-boot,dm-pre-proper; -}; - -&iomuxc { - u-boot,dm-pre-proper; -}; - -&pd_lsio { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio0 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio1 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio2 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio3 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio4 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio5 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio6 { - u-boot,dm-pre-proper; -}; - -&pd_lsio_gpio7 { - u-boot,dm-pre-proper; -}; - -&pd_dma { - u-boot,dm-pre-proper; -}; - -&pd_dma_lpuart0 { - u-boot,dm-pre-proper; -}; - -&pd_dma_lpuart3 { - u-boot,dm-pre-proper; -}; - -&pd_conn { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch0 { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch1 { - u-boot,dm-pre-proper; -}; - -&pd_conn_sdch2 { - u-boot,dm-pre-proper; -}; - -&pd_conn_enet0 { - u-boot,dm-pre-proper; -}; - -&gpio0 { - u-boot,dm-pre-proper; -}; - -&gpio1 { - u-boot,dm-pre-proper; -}; - -&gpio2 { - u-boot,dm-pre-proper; -}; - -&gpio3 { - u-boot,dm-pre-proper; -}; - -&gpio4 { - u-boot,dm-pre-proper; -}; - -&gpio5 { - u-boot,dm-pre-proper; -}; - -&gpio6 { - u-boot,dm-pre-proper; -}; - -&gpio7 { - u-boot,dm-pre-proper; -}; - -&lpuart3 { - u-boot,dm-pre-proper; -}; - -&lpuart0 { - u-boot,dm-pre-proper; -}; - -&usdhc1 { - u-boot,dm-pre-proper; - /delete-property/ assigned-clock-parents; -}; - -&usdhc2 { - u-boot,dm-pre-proper; - /delete-property/ assigned-clock-parents; -}; diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts deleted file mode 100644 index 6bd231b283..0000000000 --- a/arch/arm/dts/fsl-imx8qxp-apalis.dts +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -/dts-v1/; - -#include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-apalis-u-boot.dtsi" - -/ { - model = "Toradex Apalis iMX8X"; - compatible = "toradex,apalis-imx8x", "fsl,imx8qxp"; - - chosen { - bootargs = "console=ttyLP1,115200"; - stdout-path = &lpuart1; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>; - - apalis-imx8x { - /* Apalis UART1 */ - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* SODIMM 118 */ - SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* SODIMM 112 */ - >; - }; - - /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 - /* On-module ETH_RESET# */ - SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x06000020 - /* On-module ETH_INT# */ - SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21 - >; - }; - - /* Apalis BKL_ON */ - pinctrl_gpio_bkl_on: gpio-bkl-on { - fsl,pins = < - SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 286 */ - >; - }; - - pinctrl_hog0: hog0grp { - fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 - >; - }; - - pinctrl_hog1: hog1grp { - fsl,pins = < - /* Apalis USBO1_EN */ - SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x41 /* SODIMM 274 */ - >; - }; - - /* Apalis RESET_MOCI# */ - pinctrl_reset_moci: gpioresetmocigrp { - fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21 - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* Apalis MMC1_CD# */ - pinctrl_usdhc2_gpio: mmc1gpiogrp { - fsl,pins = < - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* SODIMM 164 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { - fsl,pins = < - SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* SODIMM 164 */ - >; - }; - - /* Apalis USBH_EN */ - pinctrl_usbh_en: usbhen { - fsl,pins = < - SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x40 /* SODIMM 84 */ - >; - }; - - /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */ - SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 154 */ - SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 150 */ - SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 160 */ - SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 162 */ - SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 144 */ - SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 146 */ - SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - }; -}; - -/* Apalis Gigabit LAN */ -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - fsl,magic-packet; - phy-handle = <ðphy0>; - phy-mode = "rgmii"; - phy-reset-duration = <10>; - phy-reset-post-delay = <150>; - phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - }; - }; -}; - -/* Apalis UART1 */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Apalis MMC1 */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - disable-wp; - status = "okay"; -}; diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi new file mode 100644 index 0000000000..6b770b63fb --- /dev/null +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -0,0 +1,2191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08 + * Tue Apr 04 2023 14:52:53 GMT+0200 (Central European Summer Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 800MHz + * Density (per channel): 16Gb + * Write DBI: Enable + * Number of Ranks: 1 +*/ + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 + + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x00027100 +#define DDRSS_CTL_12_DATA 0x00186A00 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000640 +#define DDRSS_CTL_15_DATA 0x00027100 +#define DDRSS_CTL_16_DATA 0x00186A00 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000640 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00002020 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x0000040C +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000081C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x0000081C +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x05000804 +#define DDRSS_CTL_45_DATA 0x00000700 +#define DDRSS_CTL_46_DATA 0x09090004 +#define DDRSS_CTL_47_DATA 0x00000203 +#define DDRSS_CTL_48_DATA 0x00320007 +#define DDRSS_CTL_49_DATA 0x09090023 +#define DDRSS_CTL_50_DATA 0x0000190F +#define DDRSS_CTL_51_DATA 0x00320007 +#define DDRSS_CTL_52_DATA 0x09090023 +#define DDRSS_CTL_53_DATA 0x0900190F +#define DDRSS_CTL_54_DATA 0x000A0A09 +#define DDRSS_CTL_55_DATA 0x040006DB +#define DDRSS_CTL_56_DATA 0x09092004 +#define DDRSS_CTL_57_DATA 0x00000C0A +#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_59_DATA 0x09092006 +#define DDRSS_CTL_60_DATA 0x00000C0A +#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_62_DATA 0x03042006 +#define DDRSS_CTL_63_DATA 0x04050002 +#define DDRSS_CTL_64_DATA 0x100F100F +#define DDRSS_CTL_65_DATA 0x01010008 +#define DDRSS_CTL_66_DATA 0x041F1F07 +#define DDRSS_CTL_67_DATA 0x03111103 +#define DDRSS_CTL_68_DATA 0x00001111 +#define DDRSS_CTL_69_DATA 0x00000101 +#define DDRSS_CTL_70_DATA 0x00000000 +#define DDRSS_CTL_71_DATA 0x01000000 +#define DDRSS_CTL_72_DATA 0x00130803 +#define DDRSS_CTL_73_DATA 0x000000BB +#define DDRSS_CTL_74_DATA 0x00000130 +#define DDRSS_CTL_75_DATA 0x00000C28 +#define DDRSS_CTL_76_DATA 0x00000130 +#define DDRSS_CTL_77_DATA 0x00000C28 +#define DDRSS_CTL_78_DATA 0x00000005 +#define DDRSS_CTL_79_DATA 0x0000000A +#define DDRSS_CTL_80_DATA 0x00000010 +#define DDRSS_CTL_81_DATA 0x00000098 +#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_83_DATA 0x00000098 +#define DDRSS_CTL_84_DATA 0x0000017E +#define DDRSS_CTL_85_DATA 0x03004000 +#define DDRSS_CTL_86_DATA 0x00001201 +#define DDRSS_CTL_87_DATA 0x00060005 +#define DDRSS_CTL_88_DATA 0x00000006 +#define DDRSS_CTL_89_DATA 0x00000000 +#define DDRSS_CTL_90_DATA 0x05121208 +#define DDRSS_CTL_91_DATA 0x05030A05 +#define DDRSS_CTL_92_DATA 0x05030C06 +#define DDRSS_CTL_93_DATA 0x01030C06 +#define DDRSS_CTL_94_DATA 0x02010201 +#define DDRSS_CTL_95_DATA 0x00001401 +#define DDRSS_CTL_96_DATA 0x01360014 +#define DDRSS_CTL_97_DATA 0x01360136 +#define DDRSS_CTL_98_DATA 0x00000136 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x05010303 +#define DDRSS_CTL_101_DATA 0x0C040505 +#define DDRSS_CTL_102_DATA 0x06050203 +#define DDRSS_CTL_103_DATA 0x030C0605 +#define DDRSS_CTL_104_DATA 0x05060502 +#define DDRSS_CTL_105_DATA 0x03030306 +#define DDRSS_CTL_106_DATA 0x03010000 +#define DDRSS_CTL_107_DATA 0x00010000 +#define DDRSS_CTL_108_DATA 0x00000000 +#define DDRSS_CTL_109_DATA 0x01000000 +#define DDRSS_CTL_110_DATA 0x80104002 +#define DDRSS_CTL_111_DATA 0x00040003 +#define DDRSS_CTL_112_DATA 0x00040005 +#define DDRSS_CTL_113_DATA 0x00030000 +#define DDRSS_CTL_114_DATA 0x00050004 +#define DDRSS_CTL_115_DATA 0x00000004 +#define DDRSS_CTL_116_DATA 0x00040003 +#define DDRSS_CTL_117_DATA 0x00040005 +#define DDRSS_CTL_118_DATA 0x00000000 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00030A00 +#define DDRSS_CTL_127_DATA 0x00030A00 +#define DDRSS_CTL_128_DATA 0x00030A00 +#define DDRSS_CTL_129_DATA 0x00030A00 +#define DDRSS_CTL_130_DATA 0x00030A00 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x00005518 +#define DDRSS_CTL_133_DATA 0x00030A00 +#define DDRSS_CTL_134_DATA 0x00030A00 +#define DDRSS_CTL_135_DATA 0x00030A00 +#define DDRSS_CTL_136_DATA 0x00030A00 +#define DDRSS_CTL_137_DATA 0x00030A00 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x00005518 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x03050000 +#define DDRSS_CTL_157_DATA 0x03050305 +#define DDRSS_CTL_158_DATA 0x00000000 +#define DDRSS_CTL_159_DATA 0x08010000 +#define DDRSS_CTL_160_DATA 0x000E0808 +#define DDRSS_CTL_161_DATA 0x01000000 +#define DDRSS_CTL_162_DATA 0x0E080808 +#define DDRSS_CTL_163_DATA 0x00000000 +#define DDRSS_CTL_164_DATA 0x08080801 +#define DDRSS_CTL_165_DATA 0x0000080E +#define DDRSS_CTL_166_DATA 0x00040003 +#define DDRSS_CTL_167_DATA 0x00000007 +#define DDRSS_CTL_168_DATA 0x00000000 +#define DDRSS_CTL_169_DATA 0x00000000 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x01000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x00001500 +#define DDRSS_CTL_177_DATA 0x0000100E +#define DDRSS_CTL_178_DATA 0x00000002 +#define DDRSS_CTL_179_DATA 0x00000000 +#define DDRSS_CTL_180_DATA 0x00000001 +#define DDRSS_CTL_181_DATA 0x00000002 +#define DDRSS_CTL_182_DATA 0x00000C00 +#define DDRSS_CTL_183_DATA 0x00001000 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00001000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00001000 +#define DDRSS_CTL_188_DATA 0x00000000 +#define DDRSS_CTL_189_DATA 0x00000000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x0005000A +#define DDRSS_CTL_193_DATA 0x0404000D +#define DDRSS_CTL_194_DATA 0x0000000D +#define DDRSS_CTL_195_DATA 0x005000A0 +#define DDRSS_CTL_196_DATA 0x060600C8 +#define DDRSS_CTL_197_DATA 0x000000C8 +#define DDRSS_CTL_198_DATA 0x005000A0 +#define DDRSS_CTL_199_DATA 0x060600C8 +#define DDRSS_CTL_200_DATA 0x000000C8 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000004 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000024 +#define DDRSS_CTL_209_DATA 0x00000012 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000024 +#define DDRSS_CTL_212_DATA 0x00000012 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000004 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000024 +#define DDRSS_CTL_218_DATA 0x00000012 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000024 +#define DDRSS_CTL_221_DATA 0x00000012 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000000 +#define DDRSS_CTL_224_DATA 0x00000031 +#define DDRSS_CTL_225_DATA 0x000000B1 +#define DDRSS_CTL_226_DATA 0x000000B1 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x46004646 +#define DDRSS_CTL_255_DATA 0x00002746 +#define DDRSS_CTL_256_DATA 0x00000027 +#define DDRSS_CTL_257_DATA 0x00000027 +#define DDRSS_CTL_258_DATA 0x00000027 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000000 +#define DDRSS_CTL_262_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x0000000F +#define DDRSS_CTL_264_DATA 0x0000000F +#define DDRSS_CTL_265_DATA 0x0000000F +#define DDRSS_CTL_266_DATA 0x0000000F +#define DDRSS_CTL_267_DATA 0x0000000F +#define DDRSS_CTL_268_DATA 0x0000000F +#define DDRSS_CTL_269_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00001000 +#define DDRSS_CTL_271_DATA 0x00000015 +#define DDRSS_CTL_272_DATA 0x00000015 +#define DDRSS_CTL_273_DATA 0x00000010 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000020 +#define DDRSS_CTL_277_DATA 0x00010000 +#define DDRSS_CTL_278_DATA 0x00000100 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000101 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x0C181511 +#define DDRSS_CTL_291_DATA 0x00000304 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00020000 +#define DDRSS_CTL_306_DATA 0x00400100 +#define DDRSS_CTL_307_DATA 0x00080032 +#define DDRSS_CTL_308_DATA 0x01000200 +#define DDRSS_CTL_309_DATA 0x03200040 +#define DDRSS_CTL_310_DATA 0x00020018 +#define DDRSS_CTL_311_DATA 0x00400100 +#define DDRSS_CTL_312_DATA 0x00180320 +#define DDRSS_CTL_313_DATA 0x00030000 +#define DDRSS_CTL_314_DATA 0x00280028 +#define DDRSS_CTL_315_DATA 0x00000100 +#define DDRSS_CTL_316_DATA 0x01010000 +#define DDRSS_CTL_317_DATA 0x00000000 +#define DDRSS_CTL_318_DATA 0x3FFF0000 +#define DDRSS_CTL_319_DATA 0x000FFF00 +#define DDRSS_CTL_320_DATA 0xFFFFFFFF +#define DDRSS_CTL_321_DATA 0x00FFFF00 +#define DDRSS_CTL_322_DATA 0x0B000000 +#define DDRSS_CTL_323_DATA 0x0001FFFF +#define DDRSS_CTL_324_DATA 0x01010101 +#define DDRSS_CTL_325_DATA 0x01010101 +#define DDRSS_CTL_326_DATA 0x00000118 +#define DDRSS_CTL_327_DATA 0x00000C01 +#define DDRSS_CTL_328_DATA 0x01000100 +#define DDRSS_CTL_329_DATA 0x00000000 +#define DDRSS_CTL_330_DATA 0x00000000 +#define DDRSS_CTL_331_DATA 0x01030303 +#define DDRSS_CTL_332_DATA 0x00000001 +#define DDRSS_CTL_333_DATA 0x00000000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x01000101 +#define DDRSS_CTL_372_DATA 0x01010001 +#define DDRSS_CTL_373_DATA 0x00010101 +#define DDRSS_CTL_374_DATA 0x01050503 +#define DDRSS_CTL_375_DATA 0x05020201 +#define DDRSS_CTL_376_DATA 0x08080C0C +#define DDRSS_CTL_377_DATA 0x00080308 +#define DDRSS_CTL_378_DATA 0x000B030E +#define DDRSS_CTL_379_DATA 0x000B0310 +#define DDRSS_CTL_380_DATA 0x0B0B0810 +#define DDRSS_CTL_381_DATA 0x01000000 +#define DDRSS_CTL_382_DATA 0x03020301 +#define DDRSS_CTL_383_DATA 0x04000102 +#define DDRSS_CTL_384_DATA 0x1B000004 +#define DDRSS_CTL_385_DATA 0x00000176 +#define DDRSS_CTL_386_DATA 0x00000200 +#define DDRSS_CTL_387_DATA 0x00000200 +#define DDRSS_CTL_388_DATA 0x00000200 +#define DDRSS_CTL_389_DATA 0x00000200 +#define DDRSS_CTL_390_DATA 0x00000693 +#define DDRSS_CTL_391_DATA 0x00000E9C +#define DDRSS_CTL_392_DATA 0x03050202 +#define DDRSS_CTL_393_DATA 0x00250201 +#define DDRSS_CTL_394_DATA 0x00001850 +#define DDRSS_CTL_395_DATA 0x00000200 +#define DDRSS_CTL_396_DATA 0x00000200 +#define DDRSS_CTL_397_DATA 0x00000200 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00006D68 +#define DDRSS_CTL_400_DATA 0x0000F320 +#define DDRSS_CTL_401_DATA 0x070D0402 +#define DDRSS_CTL_402_DATA 0x00250405 +#define DDRSS_CTL_403_DATA 0x00001850 +#define DDRSS_CTL_404_DATA 0x00000200 +#define DDRSS_CTL_405_DATA 0x00000200 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00006D68 +#define DDRSS_CTL_409_DATA 0x0000F320 +#define DDRSS_CTL_410_DATA 0x070D0402 +#define DDRSS_CTL_411_DATA 0x00000405 +#define DDRSS_CTL_412_DATA 0x00000000 +#define DDRSS_CTL_413_DATA 0x0302000A +#define DDRSS_CTL_414_DATA 0x01000500 +#define DDRSS_CTL_415_DATA 0x01010001 +#define DDRSS_CTL_416_DATA 0x00010001 +#define DDRSS_CTL_417_DATA 0x01010001 +#define DDRSS_CTL_418_DATA 0x02010000 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x02000201 +#define DDRSS_CTL_421_DATA 0x10100600 +#define DDRSS_CTL_422_DATA 0x00202020 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00010001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00010000 +#define DDRSS_PI_24_DATA 0x280A0001 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010000 +#define DDRSS_PI_27_DATA 0x00003200 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x00000000 +#define DDRSS_PI_30_DATA 0x01010102 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x00000000 +#define DDRSS_PI_34_DATA 0x00000001 +#define DDRSS_PI_35_DATA 0x000000AA +#define DDRSS_PI_36_DATA 0x00000055 +#define DDRSS_PI_37_DATA 0x000000B5 +#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_39_DATA 0x00000056 +#define DDRSS_PI_40_DATA 0x000000A9 +#define DDRSS_PI_41_DATA 0x000000A9 +#define DDRSS_PI_42_DATA 0x000000B5 +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x00010100 +#define DDRSS_PI_46_DATA 0x00000015 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x01000000 +#define DDRSS_PI_54_DATA 0x03000000 +#define DDRSS_PI_55_DATA 0x00000000 +#define DDRSS_PI_56_DATA 0x00001701 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x0A0A140A +#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_62_DATA 0x01000210 +#define DDRSS_PI_63_DATA 0x05000404 +#define DDRSS_PI_64_DATA 0x00010001 +#define DDRSS_PI_65_DATA 0x0001000E +#define DDRSS_PI_66_DATA 0x01010100 +#define DDRSS_PI_67_DATA 0x00010000 +#define DDRSS_PI_68_DATA 0x00000034 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x0000FFFF +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x00000000 +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x08000100 +#define DDRSS_PI_78_DATA 0x00020000 +#define DDRSS_PI_79_DATA 0x00010002 +#define DDRSS_PI_80_DATA 0x00000001 +#define DDRSS_PI_81_DATA 0x00020001 +#define DDRSS_PI_82_DATA 0x00020002 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000400 +#define DDRSS_PI_92_DATA 0x0A090B0C +#define DDRSS_PI_93_DATA 0x04060708 +#define DDRSS_PI_94_DATA 0x01000005 +#define DDRSS_PI_95_DATA 0x00000800 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00010008 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x0000AA00 +#define DDRSS_PI_100_DATA 0x00000000 +#define DDRSS_PI_101_DATA 0x00010000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000008 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00010000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x0000000A +#define DDRSS_PI_137_DATA 0x000186A0 +#define DDRSS_PI_138_DATA 0x00000100 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010001 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00010000 +#define DDRSS_PI_160_DATA 0x00000004 +#define DDRSS_PI_161_DATA 0x00000000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000800 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00101001 +#define DDRSS_PI_167_DATA 0x00000034 +#define DDRSS_PI_168_DATA 0x00000042 +#define DDRSS_PI_169_DATA 0x00020042 +#define DDRSS_PI_170_DATA 0x02000200 +#define DDRSS_PI_171_DATA 0x00000004 +#define DDRSS_PI_172_DATA 0x0000080C +#define DDRSS_PI_173_DATA 0x00081C00 +#define DDRSS_PI_174_DATA 0x001C0000 +#define DDRSS_PI_175_DATA 0x00000013 +#define DDRSS_PI_176_DATA 0x000000BB +#define DDRSS_PI_177_DATA 0x00000130 +#define DDRSS_PI_178_DATA 0x00000C28 +#define DDRSS_PI_179_DATA 0x00000130 +#define DDRSS_PI_180_DATA 0x04000C28 +#define DDRSS_PI_181_DATA 0x01010404 +#define DDRSS_PI_182_DATA 0x00001501 +#define DDRSS_PI_183_DATA 0x001D001D +#define DDRSS_PI_184_DATA 0x01000100 +#define DDRSS_PI_185_DATA 0x00000100 +#define DDRSS_PI_186_DATA 0x00000000 +#define DDRSS_PI_187_DATA 0x05050503 +#define DDRSS_PI_188_DATA 0x01010C0C +#define DDRSS_PI_189_DATA 0x01010101 +#define DDRSS_PI_190_DATA 0x000C0C0A +#define DDRSS_PI_191_DATA 0x00000000 +#define DDRSS_PI_192_DATA 0x00000000 +#define DDRSS_PI_193_DATA 0x04000000 +#define DDRSS_PI_194_DATA 0x04020808 +#define DDRSS_PI_195_DATA 0x04040204 +#define DDRSS_PI_196_DATA 0x00090031 +#define DDRSS_PI_197_DATA 0x00110039 +#define DDRSS_PI_198_DATA 0x00110039 +#define DDRSS_PI_199_DATA 0x01010101 +#define DDRSS_PI_200_DATA 0x0002000D +#define DDRSS_PI_201_DATA 0x000200C8 +#define DDRSS_PI_202_DATA 0x010000C8 +#define DDRSS_PI_203_DATA 0x000E000E +#define DDRSS_PI_204_DATA 0x00C90100 +#define DDRSS_PI_205_DATA 0x010000C9 +#define DDRSS_PI_206_DATA 0x00C900C9 +#define DDRSS_PI_207_DATA 0x32103200 +#define DDRSS_PI_208_DATA 0x01013210 +#define DDRSS_PI_209_DATA 0x0A070601 +#define DDRSS_PI_210_DATA 0x0D09070D +#define DDRSS_PI_211_DATA 0x0D09070D +#define DDRSS_PI_212_DATA 0x000C000D +#define DDRSS_PI_213_DATA 0x00001000 +#define DDRSS_PI_214_DATA 0x00000C00 +#define DDRSS_PI_215_DATA 0x00001000 +#define DDRSS_PI_216_DATA 0x00000C00 +#define DDRSS_PI_217_DATA 0x02001000 +#define DDRSS_PI_218_DATA 0x0016000D +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x000000C8 +#define DDRSS_PI_221_DATA 0x00001900 +#define DDRSS_PI_222_DATA 0x32000056 +#define DDRSS_PI_223_DATA 0x06000101 +#define DDRSS_PI_224_DATA 0x001D0204 +#define DDRSS_PI_225_DATA 0x32120058 +#define DDRSS_PI_226_DATA 0x05000101 +#define DDRSS_PI_227_DATA 0x001D0408 +#define DDRSS_PI_228_DATA 0x32120058 +#define DDRSS_PI_229_DATA 0x05000101 +#define DDRSS_PI_230_DATA 0x00000408 +#define DDRSS_PI_231_DATA 0x05030900 +#define DDRSS_PI_232_DATA 0x00040900 +#define DDRSS_PI_233_DATA 0x0000062B +#define DDRSS_PI_234_DATA 0x20010004 +#define DDRSS_PI_235_DATA 0x0A0A0A03 +#define DDRSS_PI_236_DATA 0x11090000 +#define DDRSS_PI_237_DATA 0x1009000F +#define DDRSS_PI_238_DATA 0x000062B8 +#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_240_DATA 0x0C0A0C0C +#define DDRSS_PI_241_DATA 0x11090000 +#define DDRSS_PI_242_DATA 0x1009000F +#define DDRSS_PI_243_DATA 0x000062B8 +#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_245_DATA 0x0C0A0C0C +#define DDRSS_PI_246_DATA 0x00000000 +#define DDRSS_PI_247_DATA 0x00000176 +#define DDRSS_PI_248_DATA 0x00000E9C +#define DDRSS_PI_249_DATA 0x00001850 +#define DDRSS_PI_250_DATA 0x0000F320 +#define DDRSS_PI_251_DATA 0x00001850 +#define DDRSS_PI_252_DATA 0x0000F320 +#define DDRSS_PI_253_DATA 0x01360014 +#define DDRSS_PI_254_DATA 0x03030136 +#define DDRSS_PI_255_DATA 0x00000003 +#define DDRSS_PI_256_DATA 0x00000000 +#define DDRSS_PI_257_DATA 0x05030503 +#define DDRSS_PI_258_DATA 0x00000503 +#define DDRSS_PI_259_DATA 0x00002710 +#define DDRSS_PI_260_DATA 0x000186A0 +#define DDRSS_PI_261_DATA 0x00000005 +#define DDRSS_PI_262_DATA 0x00000064 +#define DDRSS_PI_263_DATA 0x00000014 +#define DDRSS_PI_264_DATA 0x00027100 +#define DDRSS_PI_265_DATA 0x000186A0 +#define DDRSS_PI_266_DATA 0x00000005 +#define DDRSS_PI_267_DATA 0x00000640 +#define DDRSS_PI_268_DATA 0x00000136 +#define DDRSS_PI_269_DATA 0x00027100 +#define DDRSS_PI_270_DATA 0x000186A0 +#define DDRSS_PI_271_DATA 0x00000005 +#define DDRSS_PI_272_DATA 0x00000640 +#define DDRSS_PI_273_DATA 0x01000136 +#define DDRSS_PI_274_DATA 0x00320040 +#define DDRSS_PI_275_DATA 0x00010008 +#define DDRSS_PI_276_DATA 0x03200040 +#define DDRSS_PI_277_DATA 0x00010018 +#define DDRSS_PI_278_DATA 0x03200040 +#define DDRSS_PI_279_DATA 0x00000318 +#define DDRSS_PI_280_DATA 0x00280028 +#define DDRSS_PI_281_DATA 0x03040404 +#define DDRSS_PI_282_DATA 0x00000303 +#define DDRSS_PI_283_DATA 0x02020101 +#define DDRSS_PI_284_DATA 0x67676767 +#define DDRSS_PI_285_DATA 0x00000000 +#define DDRSS_PI_286_DATA 0x55000000 +#define DDRSS_PI_287_DATA 0x00000000 +#define DDRSS_PI_288_DATA 0x3C00005A +#define DDRSS_PI_289_DATA 0x00005500 +#define DDRSS_PI_290_DATA 0x00005A00 +#define DDRSS_PI_291_DATA 0x0D100F3C +#define DDRSS_PI_292_DATA 0x0003020E +#define DDRSS_PI_293_DATA 0x00000001 +#define DDRSS_PI_294_DATA 0x01000000 +#define DDRSS_PI_295_DATA 0x00020201 +#define DDRSS_PI_296_DATA 0x00000000 +#define DDRSS_PI_297_DATA 0x00000000 +#define DDRSS_PI_298_DATA 0x00000004 +#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_300_DATA 0x00000031 +#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00100F27 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x00000024 +#define DDRSS_PI_307_DATA 0x00000012 +#define DDRSS_PI_308_DATA 0x000000B1 +#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_310_DATA 0x00000000 +#define DDRSS_PI_311_DATA 0x46000000 +#define DDRSS_PI_312_DATA 0x00150F27 +#define DDRSS_PI_313_DATA 0x00000000 +#define DDRSS_PI_314_DATA 0x00000024 +#define DDRSS_PI_315_DATA 0x00000012 +#define DDRSS_PI_316_DATA 0x000000B1 +#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_318_DATA 0x00000000 +#define DDRSS_PI_319_DATA 0x46000000 +#define DDRSS_PI_320_DATA 0x00150F27 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000004 +#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_324_DATA 0x00000031 +#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00100F27 +#define DDRSS_PI_329_DATA 0x00000000 +#define DDRSS_PI_330_DATA 0x00000024 +#define DDRSS_PI_331_DATA 0x00000012 +#define DDRSS_PI_332_DATA 0x000000B1 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x46000000 +#define DDRSS_PI_336_DATA 0x00150F27 +#define DDRSS_PI_337_DATA 0x00000000 +#define DDRSS_PI_338_DATA 0x00000024 +#define DDRSS_PI_339_DATA 0x00000012 +#define DDRSS_PI_340_DATA 0x000000B1 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x00000000 +#define DDRSS_PI_343_DATA 0x46000000 +#define DDRSS_PI_344_DATA 0x00150F27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01000000 +#define DDRSS_PHY_6_DATA 0x03000400 +#define DDRSS_PHY_7_DATA 0x00000001 +#define DDRSS_PHY_8_DATA 0x00000001 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x01010000 +#define DDRSS_PHY_12_DATA 0x00010000 +#define DDRSS_PHY_13_DATA 0x00C00001 +#define DDRSS_PHY_14_DATA 0x00CC0008 +#define DDRSS_PHY_15_DATA 0x00660601 +#define DDRSS_PHY_16_DATA 0x00000003 +#define DDRSS_PHY_17_DATA 0x00000000 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x0000AAAA +#define DDRSS_PHY_20_DATA 0x00005555 +#define DDRSS_PHY_21_DATA 0x0000B5B5 +#define DDRSS_PHY_22_DATA 0x00004A4A +#define DDRSS_PHY_23_DATA 0x00005656 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B7B7 +#define DDRSS_PHY_26_DATA 0x00004848 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x08000000 +#define DDRSS_PHY_30_DATA 0x0F000008 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x00E4E400 +#define DDRSS_PHY_33_DATA 0x00071020 +#define DDRSS_PHY_34_DATA 0x000C0020 +#define DDRSS_PHY_35_DATA 0x00062000 +#define DDRSS_PHY_36_DATA 0x00000000 +#define DDRSS_PHY_37_DATA 0x55555555 +#define DDRSS_PHY_38_DATA 0xAAAAAAAA +#define DDRSS_PHY_39_DATA 0x55555555 +#define DDRSS_PHY_40_DATA 0xAAAAAAAA +#define DDRSS_PHY_41_DATA 0x00005555 +#define DDRSS_PHY_42_DATA 0x01000100 +#define DDRSS_PHY_43_DATA 0x00800180 +#define DDRSS_PHY_44_DATA 0x00000001 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000000 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x041F07FF +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x01CC0B01 +#define DDRSS_PHY_75_DATA 0x1003CC0B +#define DDRSS_PHY_76_DATA 0x20000140 +#define DDRSS_PHY_77_DATA 0x07FF0200 +#define DDRSS_PHY_78_DATA 0x0000DD01 +#define DDRSS_PHY_79_DATA 0x00100303 +#define DDRSS_PHY_80_DATA 0x00000000 +#define DDRSS_PHY_81_DATA 0x00000000 +#define DDRSS_PHY_82_DATA 0x00021000 +#define DDRSS_PHY_83_DATA 0x00100010 +#define DDRSS_PHY_84_DATA 0x00100010 +#define DDRSS_PHY_85_DATA 0x00100010 +#define DDRSS_PHY_86_DATA 0x00100010 +#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_88_DATA 0x51516041 +#define DDRSS_PHY_89_DATA 0x31C06000 +#define DDRSS_PHY_90_DATA 0x07AB0340 +#define DDRSS_PHY_91_DATA 0x0000C0C0 +#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_93_DATA 0x00000504 +#define DDRSS_PHY_94_DATA 0x42100010 +#define DDRSS_PHY_95_DATA 0x010C053E +#define DDRSS_PHY_96_DATA 0x000F0C1D +#define DDRSS_PHY_97_DATA 0x01000140 +#define DDRSS_PHY_98_DATA 0x007A0120 +#define DDRSS_PHY_99_DATA 0x00000C00 +#define DDRSS_PHY_100_DATA 0x000001CC +#define DDRSS_PHY_101_DATA 0x20100200 +#define DDRSS_PHY_102_DATA 0x00000005 +#define DDRSS_PHY_103_DATA 0x56704132 +#define DDRSS_PHY_104_DATA 0x00000008 +#define DDRSS_PHY_105_DATA 0x034C034C +#define DDRSS_PHY_106_DATA 0x034C034C +#define DDRSS_PHY_107_DATA 0x034C034C +#define DDRSS_PHY_108_DATA 0x034C034C +#define DDRSS_PHY_109_DATA 0x0000034C +#define DDRSS_PHY_110_DATA 0x00008000 +#define DDRSS_PHY_111_DATA 0x00800080 +#define DDRSS_PHY_112_DATA 0x00800080 +#define DDRSS_PHY_113_DATA 0x00800080 +#define DDRSS_PHY_114_DATA 0x00800080 +#define DDRSS_PHY_115_DATA 0x00800080 +#define DDRSS_PHY_116_DATA 0x00800080 +#define DDRSS_PHY_117_DATA 0x00800080 +#define DDRSS_PHY_118_DATA 0x00800080 +#define DDRSS_PHY_119_DATA 0x01800080 +#define DDRSS_PHY_120_DATA 0x01000000 +#define DDRSS_PHY_121_DATA 0x00000000 +#define DDRSS_PHY_122_DATA 0x00000000 +#define DDRSS_PHY_123_DATA 0x00080200 +#define DDRSS_PHY_124_DATA 0x00000000 +#define DDRSS_PHY_125_DATA 0x0000F0F0 +#define DDRSS_PHY_126_DATA 0x00000000 +#define DDRSS_PHY_127_DATA 0x00000000 +#define DDRSS_PHY_128_DATA 0x00000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00000000 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00000000 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01000000 +#define DDRSS_PHY_262_DATA 0x03000400 +#define DDRSS_PHY_263_DATA 0x00000001 +#define DDRSS_PHY_264_DATA 0x00000001 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x01010000 +#define DDRSS_PHY_268_DATA 0x00010000 +#define DDRSS_PHY_269_DATA 0x00C00001 +#define DDRSS_PHY_270_DATA 0x00CC0008 +#define DDRSS_PHY_271_DATA 0x00660601 +#define DDRSS_PHY_272_DATA 0x00000003 +#define DDRSS_PHY_273_DATA 0x00000000 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x0000AAAA +#define DDRSS_PHY_276_DATA 0x00005555 +#define DDRSS_PHY_277_DATA 0x0000B5B5 +#define DDRSS_PHY_278_DATA 0x00004A4A +#define DDRSS_PHY_279_DATA 0x00005656 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B7B7 +#define DDRSS_PHY_282_DATA 0x00004848 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x08000000 +#define DDRSS_PHY_286_DATA 0x0F000008 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x00E4E400 +#define DDRSS_PHY_289_DATA 0x00071020 +#define DDRSS_PHY_290_DATA 0x000C0020 +#define DDRSS_PHY_291_DATA 0x00062000 +#define DDRSS_PHY_292_DATA 0x00000000 +#define DDRSS_PHY_293_DATA 0x55555555 +#define DDRSS_PHY_294_DATA 0xAAAAAAAA +#define DDRSS_PHY_295_DATA 0x55555555 +#define DDRSS_PHY_296_DATA 0xAAAAAAAA +#define DDRSS_PHY_297_DATA 0x00005555 +#define DDRSS_PHY_298_DATA 0x01000100 +#define DDRSS_PHY_299_DATA 0x00800180 +#define DDRSS_PHY_300_DATA 0x00000000 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000000 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x041F07FF +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x01CC0B01 +#define DDRSS_PHY_331_DATA 0x1003CC0B +#define DDRSS_PHY_332_DATA 0x20000140 +#define DDRSS_PHY_333_DATA 0x07FF0200 +#define DDRSS_PHY_334_DATA 0x0000DD01 +#define DDRSS_PHY_335_DATA 0x00100303 +#define DDRSS_PHY_336_DATA 0x00000000 +#define DDRSS_PHY_337_DATA 0x00000000 +#define DDRSS_PHY_338_DATA 0x00021000 +#define DDRSS_PHY_339_DATA 0x00100010 +#define DDRSS_PHY_340_DATA 0x00100010 +#define DDRSS_PHY_341_DATA 0x00100010 +#define DDRSS_PHY_342_DATA 0x00100010 +#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_344_DATA 0x51516041 +#define DDRSS_PHY_345_DATA 0x31C06000 +#define DDRSS_PHY_346_DATA 0x07AB0340 +#define DDRSS_PHY_347_DATA 0x0000C0C0 +#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_349_DATA 0x00000504 +#define DDRSS_PHY_350_DATA 0x42100010 +#define DDRSS_PHY_351_DATA 0x010C053E +#define DDRSS_PHY_352_DATA 0x000F0C1D +#define DDRSS_PHY_353_DATA 0x01000140 +#define DDRSS_PHY_354_DATA 0x007A0120 +#define DDRSS_PHY_355_DATA 0x00000C00 +#define DDRSS_PHY_356_DATA 0x000001CC +#define DDRSS_PHY_357_DATA 0x20100200 +#define DDRSS_PHY_358_DATA 0x00000005 +#define DDRSS_PHY_359_DATA 0x03415762 +#define DDRSS_PHY_360_DATA 0x00000008 +#define DDRSS_PHY_361_DATA 0x034C034C +#define DDRSS_PHY_362_DATA 0x034C034C +#define DDRSS_PHY_363_DATA 0x034C034C +#define DDRSS_PHY_364_DATA 0x034C034C +#define DDRSS_PHY_365_DATA 0x0000034C +#define DDRSS_PHY_366_DATA 0x00008000 +#define DDRSS_PHY_367_DATA 0x00800080 +#define DDRSS_PHY_368_DATA 0x00800080 +#define DDRSS_PHY_369_DATA 0x00800080 +#define DDRSS_PHY_370_DATA 0x00800080 +#define DDRSS_PHY_371_DATA 0x00800080 +#define DDRSS_PHY_372_DATA 0x00800080 +#define DDRSS_PHY_373_DATA 0x00800080 +#define DDRSS_PHY_374_DATA 0x00800080 +#define DDRSS_PHY_375_DATA 0x01800080 +#define DDRSS_PHY_376_DATA 0x01000000 +#define DDRSS_PHY_377_DATA 0x00000000 +#define DDRSS_PHY_378_DATA 0x00000000 +#define DDRSS_PHY_379_DATA 0x00080200 +#define DDRSS_PHY_380_DATA 0x00000000 +#define DDRSS_PHY_381_DATA 0x0000F0F0 +#define DDRSS_PHY_382_DATA 0x00000000 +#define DDRSS_PHY_383_DATA 0x00000000 +#define DDRSS_PHY_384_DATA 0x00000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00000000 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00000000 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x00000000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00000000 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x00000100 +#define DDRSS_PHY_518_DATA 0x00000200 +#define DDRSS_PHY_519_DATA 0x00000000 +#define DDRSS_PHY_520_DATA 0x00000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00400000 +#define DDRSS_PHY_524_DATA 0x00000080 +#define DDRSS_PHY_525_DATA 0x00DCBA98 +#define DDRSS_PHY_526_DATA 0x03000000 +#define DDRSS_PHY_527_DATA 0x00200000 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000000 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000000 +#define DDRSS_PHY_532_DATA 0x0000002A +#define DDRSS_PHY_533_DATA 0x00000015 +#define DDRSS_PHY_534_DATA 0x00000015 +#define DDRSS_PHY_535_DATA 0x0000002A +#define DDRSS_PHY_536_DATA 0x00000033 +#define DDRSS_PHY_537_DATA 0x0000000C +#define DDRSS_PHY_538_DATA 0x0000000C +#define DDRSS_PHY_539_DATA 0x00000033 +#define DDRSS_PHY_540_DATA 0x0A418820 +#define DDRSS_PHY_541_DATA 0x003F0000 +#define DDRSS_PHY_542_DATA 0x000F013F +#define DDRSS_PHY_543_DATA 0x0000000F +#define DDRSS_PHY_544_DATA 0x020002CC +#define DDRSS_PHY_545_DATA 0x00030000 +#define DDRSS_PHY_546_DATA 0x00000300 +#define DDRSS_PHY_547_DATA 0x00000300 +#define DDRSS_PHY_548_DATA 0x00000300 +#define DDRSS_PHY_549_DATA 0x00000300 +#define DDRSS_PHY_550_DATA 0x00000300 +#define DDRSS_PHY_551_DATA 0x42080010 +#define DDRSS_PHY_552_DATA 0x0000803E +#define DDRSS_PHY_553_DATA 0x00000003 +#define DDRSS_PHY_554_DATA 0x00000002 +#define DDRSS_PHY_555_DATA 0x00000000 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000000 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000000 +#define DDRSS_PHY_588_DATA 0x00000000 +#define DDRSS_PHY_589_DATA 0x00000000 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x00000000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000000 +#define DDRSS_PHY_596_DATA 0x00000000 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00000000 +#define DDRSS_PHY_600_DATA 0x00000000 +#define DDRSS_PHY_601_DATA 0x00000000 +#define DDRSS_PHY_602_DATA 0x00000000 +#define DDRSS_PHY_603_DATA 0x00000000 +#define DDRSS_PHY_604_DATA 0x00000000 +#define DDRSS_PHY_605_DATA 0x00000000 +#define DDRSS_PHY_606_DATA 0x00000000 +#define DDRSS_PHY_607_DATA 0x00000000 +#define DDRSS_PHY_608_DATA 0x00000000 +#define DDRSS_PHY_609_DATA 0x00000000 +#define DDRSS_PHY_610_DATA 0x00000000 +#define DDRSS_PHY_611_DATA 0x00000000 +#define DDRSS_PHY_612_DATA 0x00000000 +#define DDRSS_PHY_613_DATA 0x00000000 +#define DDRSS_PHY_614_DATA 0x00000000 +#define DDRSS_PHY_615_DATA 0x00000000 +#define DDRSS_PHY_616_DATA 0x00000000 +#define DDRSS_PHY_617_DATA 0x00000000 +#define DDRSS_PHY_618_DATA 0x00000000 +#define DDRSS_PHY_619_DATA 0x00000000 +#define DDRSS_PHY_620_DATA 0x00000000 +#define DDRSS_PHY_621_DATA 0x00000000 +#define DDRSS_PHY_622_DATA 0x00000000 +#define DDRSS_PHY_623_DATA 0x00000000 +#define DDRSS_PHY_624_DATA 0x00000000 +#define DDRSS_PHY_625_DATA 0x00000000 +#define DDRSS_PHY_626_DATA 0x00000000 +#define DDRSS_PHY_627_DATA 0x00000000 +#define DDRSS_PHY_628_DATA 0x00000000 +#define DDRSS_PHY_629_DATA 0x00000000 +#define DDRSS_PHY_630_DATA 0x00000000 +#define DDRSS_PHY_631_DATA 0x00000000 +#define DDRSS_PHY_632_DATA 0x00000000 +#define DDRSS_PHY_633_DATA 0x00000000 +#define DDRSS_PHY_634_DATA 0x00000000 +#define DDRSS_PHY_635_DATA 0x00000000 +#define DDRSS_PHY_636_DATA 0x00000000 +#define DDRSS_PHY_637_DATA 0x00000000 +#define DDRSS_PHY_638_DATA 0x00000000 +#define DDRSS_PHY_639_DATA 0x00000000 +#define DDRSS_PHY_640_DATA 0x00000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00000000 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00000000 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x00000000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00000000 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x00000100 +#define DDRSS_PHY_774_DATA 0x00000200 +#define DDRSS_PHY_775_DATA 0x00000000 +#define DDRSS_PHY_776_DATA 0x00000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00400000 +#define DDRSS_PHY_780_DATA 0x00000080 +#define DDRSS_PHY_781_DATA 0x00DCBA98 +#define DDRSS_PHY_782_DATA 0x03000000 +#define DDRSS_PHY_783_DATA 0x00200000 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000000 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000000 +#define DDRSS_PHY_788_DATA 0x0000002A +#define DDRSS_PHY_789_DATA 0x00000015 +#define DDRSS_PHY_790_DATA 0x00000015 +#define DDRSS_PHY_791_DATA 0x0000002A +#define DDRSS_PHY_792_DATA 0x00000033 +#define DDRSS_PHY_793_DATA 0x0000000C +#define DDRSS_PHY_794_DATA 0x0000000C +#define DDRSS_PHY_795_DATA 0x00000033 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x000F0000 +#define DDRSS_PHY_799_DATA 0x0000000F +#define DDRSS_PHY_800_DATA 0x020002CC +#define DDRSS_PHY_801_DATA 0x00030000 +#define DDRSS_PHY_802_DATA 0x00000300 +#define DDRSS_PHY_803_DATA 0x00000300 +#define DDRSS_PHY_804_DATA 0x00000300 +#define DDRSS_PHY_805_DATA 0x00000300 +#define DDRSS_PHY_806_DATA 0x00000300 +#define DDRSS_PHY_807_DATA 0x42080010 +#define DDRSS_PHY_808_DATA 0x0000803E +#define DDRSS_PHY_809_DATA 0x00000003 +#define DDRSS_PHY_810_DATA 0x00000002 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000000 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000000 +#define DDRSS_PHY_844_DATA 0x00000000 +#define DDRSS_PHY_845_DATA 0x00000000 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x00000000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000000 +#define DDRSS_PHY_852_DATA 0x00000000 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00000000 +#define DDRSS_PHY_856_DATA 0x00000000 +#define DDRSS_PHY_857_DATA 0x00000000 +#define DDRSS_PHY_858_DATA 0x00000000 +#define DDRSS_PHY_859_DATA 0x00000000 +#define DDRSS_PHY_860_DATA 0x00000000 +#define DDRSS_PHY_861_DATA 0x00000000 +#define DDRSS_PHY_862_DATA 0x00000000 +#define DDRSS_PHY_863_DATA 0x00000000 +#define DDRSS_PHY_864_DATA 0x00000000 +#define DDRSS_PHY_865_DATA 0x00000000 +#define DDRSS_PHY_866_DATA 0x00000000 +#define DDRSS_PHY_867_DATA 0x00000000 +#define DDRSS_PHY_868_DATA 0x00000000 +#define DDRSS_PHY_869_DATA 0x00000000 +#define DDRSS_PHY_870_DATA 0x00000000 +#define DDRSS_PHY_871_DATA 0x00000000 +#define DDRSS_PHY_872_DATA 0x00000000 +#define DDRSS_PHY_873_DATA 0x00000000 +#define DDRSS_PHY_874_DATA 0x00000000 +#define DDRSS_PHY_875_DATA 0x00000000 +#define DDRSS_PHY_876_DATA 0x00000000 +#define DDRSS_PHY_877_DATA 0x00000000 +#define DDRSS_PHY_878_DATA 0x00000000 +#define DDRSS_PHY_879_DATA 0x00000000 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x00000000 +#define DDRSS_PHY_882_DATA 0x00000000 +#define DDRSS_PHY_883_DATA 0x00000000 +#define DDRSS_PHY_884_DATA 0x00000000 +#define DDRSS_PHY_885_DATA 0x00000000 +#define DDRSS_PHY_886_DATA 0x00000000 +#define DDRSS_PHY_887_DATA 0x00000000 +#define DDRSS_PHY_888_DATA 0x00000000 +#define DDRSS_PHY_889_DATA 0x00000000 +#define DDRSS_PHY_890_DATA 0x00000000 +#define DDRSS_PHY_891_DATA 0x00000000 +#define DDRSS_PHY_892_DATA 0x00000000 +#define DDRSS_PHY_893_DATA 0x00000000 +#define DDRSS_PHY_894_DATA 0x00000000 +#define DDRSS_PHY_895_DATA 0x00000000 +#define DDRSS_PHY_896_DATA 0x00000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00000000 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00000000 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x0000002A +#define DDRSS_PHY_1045_DATA 0x00000015 +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x0000002A +#define DDRSS_PHY_1048_DATA 0x00000033 +#define DDRSS_PHY_1049_DATA 0x0000000C +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x00000033 +#define DDRSS_PHY_1052_DATA 0x2307B9AC +#define DDRSS_PHY_1053_DATA 0x10000000 +#define DDRSS_PHY_1054_DATA 0x000F0000 +#define DDRSS_PHY_1055_DATA 0x0000000F +#define DDRSS_PHY_1056_DATA 0x020002CC +#define DDRSS_PHY_1057_DATA 0x00030000 +#define DDRSS_PHY_1058_DATA 0x00000300 +#define DDRSS_PHY_1059_DATA 0x00000300 +#define DDRSS_PHY_1060_DATA 0x00000300 +#define DDRSS_PHY_1061_DATA 0x00000300 +#define DDRSS_PHY_1062_DATA 0x00000300 +#define DDRSS_PHY_1063_DATA 0x42080010 +#define DDRSS_PHY_1064_DATA 0x0000803E +#define DDRSS_PHY_1065_DATA 0x00000003 +#define DDRSS_PHY_1066_DATA 0x00000002 +#define DDRSS_PHY_1067_DATA 0x00000000 +#define DDRSS_PHY_1068_DATA 0x00000000 +#define DDRSS_PHY_1069_DATA 0x00000000 +#define DDRSS_PHY_1070_DATA 0x00000000 +#define DDRSS_PHY_1071_DATA 0x00000000 +#define DDRSS_PHY_1072_DATA 0x00000000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00010100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000000 +#define DDRSS_PHY_1286_DATA 0x00050000 +#define DDRSS_PHY_1287_DATA 0x04000000 +#define DDRSS_PHY_1288_DATA 0x00000055 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00000000 +#define DDRSS_PHY_1292_DATA 0x00000000 +#define DDRSS_PHY_1293_DATA 0x00002001 +#define DDRSS_PHY_1294_DATA 0x00004001 +#define DDRSS_PHY_1295_DATA 0x00020028 +#define DDRSS_PHY_1296_DATA 0x01010100 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x0F0F0E06 +#define DDRSS_PHY_1300_DATA 0x00010101 +#define DDRSS_PHY_1301_DATA 0x010F0004 +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x00000000 +#define DDRSS_PHY_1304_DATA 0x00000064 +#define DDRSS_PHY_1305_DATA 0x00000000 +#define DDRSS_PHY_1306_DATA 0x00000000 +#define DDRSS_PHY_1307_DATA 0x01020103 +#define DDRSS_PHY_1308_DATA 0x0F020102 +#define DDRSS_PHY_1309_DATA 0x03030303 +#define DDRSS_PHY_1310_DATA 0x03030303 +#define DDRSS_PHY_1311_DATA 0x00041B42 +#define DDRSS_PHY_1312_DATA 0x00005201 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x00000000 +#define DDRSS_PHY_1318_DATA 0x00000000 +#define DDRSS_PHY_1319_DATA 0x07030101 +#define DDRSS_PHY_1320_DATA 0x00005400 +#define DDRSS_PHY_1321_DATA 0x000040A2 +#define DDRSS_PHY_1322_DATA 0x00024410 +#define DDRSS_PHY_1323_DATA 0x00004410 +#define DDRSS_PHY_1324_DATA 0x00004410 +#define DDRSS_PHY_1325_DATA 0x00004410 +#define DDRSS_PHY_1326_DATA 0x00004410 +#define DDRSS_PHY_1327_DATA 0x00004410 +#define DDRSS_PHY_1328_DATA 0x00004410 +#define DDRSS_PHY_1329_DATA 0x00004410 +#define DDRSS_PHY_1330_DATA 0x00004410 +#define DDRSS_PHY_1331_DATA 0x00004410 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000076 +#define DDRSS_PHY_1334_DATA 0x00000400 +#define DDRSS_PHY_1335_DATA 0x00000008 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x03000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x04102006 +#define DDRSS_PHY_1346_DATA 0x00041020 +#define DDRSS_PHY_1347_DATA 0x01C98C98 +#define DDRSS_PHY_1348_DATA 0x3F400000 +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F +#define DDRSS_PHY_1350_DATA 0x0000001F +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000001 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x76543210 +#define DDRSS_PHY_1360_DATA 0x00040198 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00040700 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000002 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 +#define DDRSS_PHY_1372_DATA 0x00020002 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00001142 +#define DDRSS_PHY_1375_DATA 0x03020000 +#define DDRSS_PHY_1376_DATA 0x00000080 +#define DDRSS_PHY_1377_DATA 0x03900390 +#define DDRSS_PHY_1378_DATA 0x03900390 +#define DDRSS_PHY_1379_DATA 0x03900390 +#define DDRSS_PHY_1380_DATA 0x03900390 +#define DDRSS_PHY_1381_DATA 0x03000300 +#define DDRSS_PHY_1382_DATA 0x03000300 +#define DDRSS_PHY_1383_DATA 0x00000300 +#define DDRSS_PHY_1384_DATA 0x00000300 +#define DDRSS_PHY_1385_DATA 0x00000300 +#define DDRSS_PHY_1386_DATA 0x00000300 +#define DDRSS_PHY_1387_DATA 0x3183BF77 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x0C000DFF +#define DDRSS_PHY_1390_DATA 0x30000DFF +#define DDRSS_PHY_1391_DATA 0x3F0DFF11 +#define DDRSS_PHY_1392_DATA 0x01990000 +#define DDRSS_PHY_1393_DATA 0x780DFFCC +#define DDRSS_PHY_1394_DATA 0x00000C11 +#define DDRSS_PHY_1395_DATA 0x00018011 +#define DDRSS_PHY_1396_DATA 0x0089FF00 +#define DDRSS_PHY_1397_DATA 0x000C3F11 +#define DDRSS_PHY_1398_DATA 0x01990000 +#define DDRSS_PHY_1399_DATA 0x000C3F11 +#define DDRSS_PHY_1400_DATA 0x01990000 +#define DDRSS_PHY_1401_DATA 0x3F0DFF11 +#define DDRSS_PHY_1402_DATA 0x01990000 +#define DDRSS_PHY_1403_DATA 0x00018011 +#define DDRSS_PHY_1404_DATA 0x0089FF00 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts new file mode 100644 index 0000000000..b0080bef29 --- /dev/null +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Toradex Verdin AM62 dts file for R5 SPL + * Copyright 2023 Toradex - https://www.toradex.com/ + */ + +#include "k3-am625-verdin.dts" +#include "k3-am625-verdin-lpddr4-1600MTs.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am625-verdin-u-boot.dtsi" + +/ { + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1250000000>; + clocks = <&k3_clks 61 0>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + ti,sci = <&dmsc>; + ti,sci-host-id = <10>; + ti,sci-proc-id = <32>; + u-boot,dm-spl; + }; + + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + ti,host-id = <36>; + ti,secure-host; + u-boot,dm-spl; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ + u-boot,dm-spl; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "rt", "scfg", "target_data"; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x0 0x44860000 0x0 0x20000>, + <0x0 0x43600000 0x0 0x10000>; + u-boot,dm-spl; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + u-boot,dm-spl; + }; + + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x420000 0x0 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + u-boot,dm-spl; + }; +}; + +&cbass_mcu { + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x4100000 0x0 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + u-boot,dm-spl; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&main_bcdma { + ti,sci = <&dm_tifs>; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; + +&main_pmx0 { + u-boot,dm-spl; + + /* Verdin UART_1 */ + pinctrl_uart1: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ + AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ + AM62X_IOPAD(0x01ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ + AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ + >; + u-boot,dm-spl; + }; +}; + +/* Verdin UART_1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + u-boot,dm-spl; +}; + +&mcu_pmx0 { + u-boot,dm-spl; + + /* Verdin UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ + AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ + AM62X_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */ + AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ + >; + u-boot,dm-spl; + }; +}; + +/* Verdin UART_2 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + status = "okay"; + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am625-verdin-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-u-boot.dtsi new file mode 100644 index 0000000000..13f108a311 --- /dev/null +++ b/arch/arm/dts/k3-am625-verdin-u-boot.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + */ + +/ { + aliases { + eeprom0 = &eeprom_module; + eeprom1 = &eeprom_carrier_board; + eeprom2 = &eeprom_display_adapter; + usb0 = &usb0; + }; + + chosen { + tick-timer = &timer1; + }; + + memory@80000000 { + u-boot,dm-spl; + }; +}; + +&cbass_main { + u-boot,dm-spl; + + timer1: timer@2400000 { + compatible = "ti,omap5430-timer"; + reg = <0x00 0x2400000 0x00 0x80>; + clock-frequency = <25000000>; + ti,timer-alwon; + u-boot,dm-spl; + }; +}; + +&cbass_mcu { + u-boot,dm-spl; +}; + +&cbass_wakeup { + u-boot,dm-spl; +}; + +&chipid { + u-boot,dm-spl; +}; + +&cpsw3g { + reg = <0x0 0x8000000 0x0 0x200000>, + <0x0 0x43000200 0x0 0x8>; + reg-names = "cpsw_nuss", "mac_efuse"; + /delete-property/ ranges; + u-boot,dm-spl; + + cpsw-phy-sel@04044 { + compatible = "ti,am64-phy-gmii-sel"; + reg = <0x0 0x00104044 0x0 0x8>; + u-boot,dm-spl; + }; +}; + +&cpsw3g_phy0 { + u-boot,dm-spl; +}; + +&cpsw_port1 { + u-boot,dm-spl; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&dmsc { + u-boot,dm-spl; + + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + u-boot,dm-spl; + }; +}; + +&dmss { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&main_bcdma { + u-boot,dm-spl; +}; + +&main_gpio0 { + u-boot,dm-spl; +}; + +&main_pktdma { + u-boot,dm-spl; +}; + +&main_pmx0 { + u-boot,dm-spl; +}; + +&main_uart0 { + u-boot,dm-spl; +}; + +&pinctrl_mdio { + u-boot,dm-spl; +}; + +&pinctrl_rgmii1 { + u-boot,dm-spl; +}; + +&pinctrl_sdhci1 { + u-boot,dm-spl; +}; + +&pinctrl_uart0 { + u-boot,dm-spl; +}; + +®_sdhc1_vmmc { + u-boot,dm-spl; +}; + +®_sdhc1_vqmmc { + u-boot,dm-spl; +}; + +&sdhci0 { + u-boot,dm-spl; +}; + +&sdhci1 { + u-boot,dm-spl; +}; + +&secure_proxy_main { + u-boot,dm-spl; +}; + +&usbss0 { + u-boot,dm-spl; +}; + +&usb0 { + /* Since role switching is not supported in U-Boot */ + /delete-property/ extcon; + dr_mode = "peripheral"; + u-boot,dm-spl; +}; + +&wkup_conf { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am625-verdin.dts b/arch/arm/dts/k3-am625-verdin.dts new file mode 100644 index 0000000000..736c513f5f --- /dev/null +++ b/arch/arm/dts/k3-am625-verdin.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> + +#include "k3-am625.dtsi" + +/ { + compatible = "toradex,verdin-am62", "ti,am625"; + model = "Toradex Verdin AM62"; + + aliases { + ethernet0 = &cpsw_port1; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + serial2 = &main_uart0; + }; + + chosen { + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ + }; + + /* Verdin SD_1 Power Supply */ + reg_sdhc1_vmmc: regulator-sdhci1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vsel_sd>; + /* PMIC_VSEL_SD */ + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-name = "LDO1-VSEL-SD (PMIC)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + states = <1800000 0x0>, + <3300000 0x1>; +// vin-supply = <®_sd_3v3_1v8>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rtos_ipc_memory_region: ipc-memories@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00300000>; + no-map; + }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0x00c00000>; + no-map; + }; + + lpm_ctx_ddr: lpm-memory@9e700000 { + reg = <0x00 0x9e700000 0x00 0x80000>; + alignment = <0x1000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio // TBD: move pinctrl to &cpsw3g_mdio ? + &pinctrl_rgmii1>; // TODO: move pinctrl to &cpsw_port1 ? +}; + +/* MDIO, shared between Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + assigned-clocks = <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 22>; + assigned-clock-rates = <25000000>; + interrupt-parent = <&main_gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_clock &pinctrl_eth_int &pinctrl_eth_reset>; + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <1000>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + phy-handle = <&cpsw3g_phy0>; + phy-mode = "rgmii-rxid"; +}; + +/* On-module I2C - PMIC_I2C */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + eeprom_module: eeprom@50 { + compatible = "st,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; + reg = <0x50>; + pagesize = <16>; + }; + + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02", "atmel,24c02", "i2c-eeprom"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +&main_pmx0 { + /* PMIC_ETH_RESET# */ + pinctrl_eth_reset: main-gpio0-17-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ + > ; + }; + + /* PMIC_VSEL_SD */ + pinctrl_vsel_sd: main-gpio0-21-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + /* PMIC_ETH_INT# */ + pinctrl_eth_int: main-gpio0-25-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ + >; + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-29-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ + >; + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: main-gpio0-31-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ + >; + }; + + /* On-module I2C - PMIC_I2C */ + pinctrl_i2c0: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c1: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ + >; + }; + + /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ + pinctrl_mdio: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ + >; + }; + + /* On-module eMMC */ + pinctrl_sdhci0: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + /* Verdin SD_1 */ + pinctrl_sdhci1: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ + >; + }; + + /* Verdin ETH_1 RGMII (On-module PHY) */ + pinctrl_rgmii1: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + /* ETH_25MHz_CLK */ + pinctrl_eth_clock: main-system-clkout0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ + >; + }; + + /* Verdin UART_3, used as the Linux console */ + pinctrl_uart0: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ + >; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; +}; + +/* On-module eMMC */ +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; + disable-wp; + ti,driver-strength-ohm = <50>; + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + ti,vbus-divider; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 04b9729109..9d1f73dfc7 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -65,11 +65,6 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP -config TARGET_APALIS_IMX8X - bool "Support Apalis iMX8X module" - select BOARD_LATE_INIT - select IMX8QXP - config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT @@ -103,7 +98,6 @@ source "board/freescale/imx8qxp_mek/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" -source "board/toradex/apalis-imx8x/Kconfig" source "board/siemens/capricorn/Kconfig" config IMX_SNVS_SEC_SC diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 9c0572597f..0ba4ae007f 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -208,4 +208,5 @@ source "board/ti/am62ax/Kconfig" source "board/ti/j721e/Kconfig" source "board/ti/j721s2/Kconfig" source "board/ti/j784s4/Kconfig" +source "board/toradex/verdin-am62/Kconfig" endif diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 15bd9d029a..c61e74edfd 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -63,6 +63,7 @@ #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4) #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) #define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig deleted file mode 100644 index ee61e09736..0000000000 --- a/board/toradex/apalis-imx8x/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -if TARGET_APALIS_IMX8X - -config SYS_BOARD - default "apalis-imx8x" - -config SYS_VENDOR - default "toradex" - -config SYS_CONFIG_NAME - default "apalis-imx8x" - -config TDX_CFG_BLOCK - default y - -config TDX_HAVE_MMC - default y - -config TDX_CFG_BLOCK_DEV - default "0" - -config TDX_CFG_BLOCK_PART - default "1" - -# Toradex config block in eMMC, at the end of 1st "boot sector" -config TDX_CFG_BLOCK_OFFSET - default "-512" - -source "board/toradex/common/Kconfig" - -endif diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS deleted file mode 100644 index 5272154447..0000000000 --- a/board/toradex/apalis-imx8x/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -Apalis iMX8X -M: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> -W: http://developer.toradex.com/software/linux/linux-software -S: Maintained -F: arch/arm/dts/fsl-imx8x-apalis.dts -F: arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi -F: board/toradex/apalis-imx8x/ -F: configs/apalis-imx8x_defconfig -F: doc/board/toradex/apalis-imx8x.rst -F: include/configs/apalis-imx8x.h diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile deleted file mode 100644 index 9d6e85b742..0000000000 --- a/board/toradex/apalis-imx8x/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2020 Toradex -# - -obj-y += apalis-imx8x.o diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg deleted file mode 100644 index 58c62d0a65..0000000000 --- a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2020 Toradex - * - * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure - * and create imx8image boot image - */ - -#define __ASSEMBLY__ - -/* Boot from SD, sector size 0x400 */ -BOOT_FROM EMMC_FASTBOOT 0x400 -/* SoC type IMX8QX */ -SOC_TYPE IMX8QX -/* Append seco container image */ -APPEND mx8qx-ahab-container.img -/* Create the 2nd container */ -CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU mx8qx-apalis-scfw-tcm.bin -/* Add ATF image with exec attribute */ -IMAGE A35 bl31.bin 0x80000000 -/* Add U-Boot image with load attribute */ -DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c deleted file mode 100644 index 739d2e5155..0000000000 --- a/board/toradex/apalis-imx8x/apalis-imx8x.c +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 Toradex - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> - -#include <asm/arch/clock.h> -#include <asm/arch/imx8-pins.h> -#include <asm/arch/iomux.h> -#include <asm/arch/sci/sci.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <env.h> -#include <errno.h> -#include <linux/libfdt.h> - -#include "../common/tdx-cfg-block.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ - (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ - (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ - (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) - -static iomux_cfg_t uart1_pads[] = { - SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -void board_mem_get_layout(u64 *phys_sdram_1_start, - u64 *phys_sdram_1_size, - u64 *phys_sdram_2_start, - u64 *phys_sdram_2_size) -{ - u32 is_dualx = 0, val = 0; - sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val); - - if (scierr == SC_ERR_NONE) { - /* DX has two A35 cores disabled */ - is_dualx = (val & 0xf) != 0x0; - } - - *phys_sdram_1_start = PHYS_SDRAM_1; - if (is_dualx) - /* Our DX based SKUs only have 1 GB RAM */ - *phys_sdram_1_size = SZ_1G; - else - *phys_sdram_1_size = PHYS_SDRAM_1_SIZE; - *phys_sdram_2_start = PHYS_SDRAM_2; - *phys_sdram_2_size = PHYS_SDRAM_2_SIZE; -} - -int board_early_init_f(void) -{ - sc_pm_clock_rate_t rate; - sc_err_t err = 0; - - /* - * This works around that having only UART3 up the baudrate is 1.2M - * instead of 115.2k. Set UART0 clock root to 80 MHz - */ - rate = 80000000; - err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); - if (err != SC_ERR_NONE) - return 0; - - /* Set UART3 clock root to 80 MHz and enable it */ - rate = SC_80MHZ; - err = sc_pm_setup_uart(SC_R_UART_1, rate); - if (err != SC_ERR_NONE) - return 0; - - setup_iomux_uart(); - - return 0; -} - -#if IS_ENABLED(CONFIG_DM_GPIO) -static void board_gpio_init(void) -{ - /* TODO */ -} -#else -static inline void board_gpio_init(void) {} -#endif - -#if IS_ENABLED(CONFIG_FEC_MXC) -#include <miiphy.h> - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - -int checkboard(void) -{ - puts("Model: Toradex Apalis iMX8X\n"); - - build_info(); - print_bootinfo(); - - return 0; -} - -int board_init(void) -{ - board_gpio_init(); - - return 0; -} - -/* - * Board specific reset that is system reset. - */ -void reset_cpu(ulong addr) -{ - /* TODO */ -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return ft_common_board_setup(blob, bd); -} -#endif - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -/* TODO move to common */ - env_set("board_name", "Apalis iMX8X"); -#endif - - return 0; -} diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig deleted file mode 100644 index f646baa3f0..0000000000 --- a/board/toradex/colibri_pxa270/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if TARGET_COLIBRI_PXA270 - -config SYS_BOARD - default "colibri_pxa270" - -config SYS_VENDOR - default "toradex" - -config SYS_CONFIG_NAME - default "colibri_pxa270" - -config TDX_CFG_BLOCK - default y - -config TDX_HAVE_NOR - default y - -config TDX_CFG_BLOCK_OFFSET - default "262144" - -source "board/toradex/common/Kconfig" - -endif diff --git a/board/toradex/colibri_pxa270/MAINTAINERS b/board/toradex/colibri_pxa270/MAINTAINERS deleted file mode 100644 index b378d7be5a..0000000000 --- a/board/toradex/colibri_pxa270/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -COLIBRI_PXA270 BOARD -M: Marek Vasut <marek.vasut@gmail.com> -S: Maintained -F: board/toradex/colibri_pxa270/ -F: include/configs/colibri_pxa270.h -F: configs/colibri_pxa270_defconfig diff --git a/board/toradex/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile deleted file mode 100644 index ea610cfea9..0000000000 --- a/board/toradex/colibri_pxa270/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Toradex Colibri PXA270 Support -# -# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - -obj-y := colibri_pxa270.o diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c deleted file mode 100644 index 273a17f608..0000000000 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Toradex Colibri PXA270 Support - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * Copyright (C) 2016-2019 Marcel Ziswiler <marcel.ziswiler@toradex.com> - */ - -#include <common.h> -#include <cpu_func.h> -#include <dm.h> -#include <init.h> -#include <net.h> -#include <asm/arch/hardware.h> -#include <asm/arch/pxa.h> -#include <asm/arch/regs-mmc.h> -#include <asm/arch/regs-uart.h> -#include <asm/io.h> -#include <dm/platdata.h> -#include <dm/platform_data/pxa_mmc_gen.h> -#include <dm/platform_data/serial_pxa.h> -#include <netdev.h> -#include <serial.h> -#include <usb.h> -#include <asm/mach-types.h> -#include <linux/delay.h> -#include "../common/tdx-common.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Toradex Colibri PXA270 */ - gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; - - /* address of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int checkboard(void) -{ - puts("Model: Toradex Colibri PXA270\n"); - - return 0; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return ft_common_board_setup(blob, bd); -} -#endif - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -#ifdef CONFIG_CMD_USB -int board_usb_init(int index, enum usb_init_type init) -{ - writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); - - writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - - while (UHCHR & UHCHR_FSBIR) - ; - - writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); - writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); - - /* Clear any OTG Pin Hold */ - if (readl(PSSR) & PSSR_OTGPH) - writel(readl(PSSR) | PSSR_OTGPH, PSSR); - - writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); - writel(readl(UHCRHDA) | 0x100, UHCRHDA); - - /* Set port power control mask bits, only 3 ports. */ - writel(readl(UHCRHDB) | (0x7 << 17), UHCRHDB); - - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) -{ - writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - udelay(11); - writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - - writel(readl(UHCCOMS) | 1, UHCCOMS); - udelay(10); - - writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); -} -#endif - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif - -#ifdef CONFIG_CMD_MMC -#if !CONFIG_IS_ENABLED(DM_MMC) -int board_mmc_init(struct bd_info *bis) -{ - pxa_mmc_register(0); - return 0; -} -#else /* !CONFIG_IS_ENABLED(DM_MMC) */ -static const struct pxa_mmc_plat mmc_platdata = { - .base = (struct pxa_mmc_regs *)MMC0_BASE, -}; - -U_BOOT_DEVICE(pxa_mmcs) = { - .name = "pxa_mmc", - .platdata = &mmc_platdata, -}; -#endif /* !CONFIG_IS_ENABLED(DM_MMC) */ -#endif - -static const struct pxa_serial_platdata serial_platdata = { - .base = (struct pxa_uart_regs *)FFUART_BASE, - .port = FFUART_INDEX, - .baudrate = CONFIG_BAUDRATE, -}; - -U_BOOT_DEVICE(pxa_serials) = { - .name = "serial_pxa", - .platdata = &serial_platdata, -}; diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index adab0a0802..07f6f83c37 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -10,23 +10,6 @@ #include <command.h> #include <asm/cache.h> -#if defined(CONFIG_TARGET_APALIS_IMX6) || \ - defined(CONFIG_TARGET_APALIS_IMX8) || \ - defined(CONFIG_TARGET_APALIS_IMX8X) || \ - defined(CONFIG_TARGET_COLIBRI_IMX6) || \ - defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ - defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ - defined(CONFIG_TARGET_VERDIN_IMX8MN) || \ - defined(CONFIG_TARGET_VERDIN_IMX8MP) -#include <asm/arch/sys_proto.h> -#else -#define is_cpu_type(cpu) (0) -#endif -#if defined(CONFIG_CPU_PXA27X) -#include <asm/arch-pxa/pxa.h> -#else -#define cpu_is_pxa27x(cpu) (0) -#endif #include <cli.h> #include <console.h> #include <env.h> @@ -81,69 +64,79 @@ bool valid_cfgblock_carrier; struct toradex_hw tdx_car_hw_tag; #endif -const char * const toradex_modules[] = { - [0] = "UNKNOWN MODULE", - [1] = "Colibri PXA270 312MHz", - [2] = "Colibri PXA270 520MHz", - [3] = "Colibri PXA320 806MHz", - [4] = "Colibri PXA300 208MHz", - [5] = "Colibri PXA310 624MHz", - [6] = "Colibri PXA320 806MHz IT", - [7] = "Colibri PXA300 208MHz XT", - [8] = "Colibri PXA270 312MHz", - [9] = "Colibri PXA270 520MHz", - [10] = "Colibri VF50 128MB", /* not currently on sale */ - [11] = "Colibri VF61 256MB", - [12] = "Colibri VF61 256MB IT", - [13] = "Colibri VF50 128MB IT", - [14] = "Colibri iMX6 Solo 256MB", - [15] = "Colibri iMX6 DualLite 512MB", - [16] = "Colibri iMX6 Solo 256MB IT", - [17] = "Colibri iMX6 DualLite 512MB IT", - [18] = "UNKNOWN MODULE", - [19] = "UNKNOWN MODULE", - [20] = "Colibri T20 256MB", - [21] = "Colibri T20 512MB", - [22] = "Colibri T20 512MB IT", - [23] = "Colibri T30 1GB", - [24] = "Colibri T20 256MB IT", - [25] = "Apalis T30 2GB", - [26] = "Apalis T30 1GB", - [27] = "Apalis iMX6 Quad 1GB", - [28] = "Apalis iMX6 Quad 2GB IT", - [29] = "Apalis iMX6 Dual 512MB", - [30] = "Colibri T30 1GB IT", - [31] = "Apalis T30 1GB IT", - [32] = "Colibri iMX7 Solo 256MB", - [33] = "Colibri iMX7 Dual 512MB", - [34] = "Apalis TK1 2GB", - [35] = "Apalis iMX6 Dual 1GB IT", - [36] = "Colibri iMX6ULL 256MB", - [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT", - [38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT", - [39] = "Colibri iMX7 Dual 1GB (eMMC)", - [40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT", - [41] = "Colibri iMX7 Dual 512MB EPDC", - [42] = "Apalis TK1 4GB", - [43] = "Colibri T20 512MB IT SETEK", - [44] = "Colibri iMX6ULL 512MB IT", - [45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth", - [46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT", - [47] = "Apalis iMX8 QuadMax 4GB IT", - [48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT", - [49] = "Apalis iMX8 QuadPlus 2GB", - [50] = "Colibri iMX8 QuadXPlus 2GB IT", - [51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth", - [52] = "Colibri iMX8 DualX 1GB", - [53] = "Apalis iMX8 QuadXPlus 2GB ECC IT", - [54] = "Apalis iMX8 DualXPlus 1GB", - [55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT", - [56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on sale */ - [57] = "Verdin iMX8M Mini DualLite 1GB", - [58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT", - [59] = "Verdin iMX8M Mini Quad 2GB IT", - [60] = "Verdin iMX8M Mini DualLite 1GB WB IT", - [61] = "Verdin iMX8M Plus Quad 2GB", +#define TARGET_IS_ENABLED(x) IS_ENABLED(CONFIG_TARGET_ ## x) + +const struct toradex_som toradex_modules[] = { + [0] = { "UNKNOWN MODULE", 0 }, + [1] = { "Colibri PXA270 312MHz", 0 }, + [2] = { "Colibri PXA270 520MHz", 0 }, + [3] = { "Colibri PXA320 806MHz", 0 }, + [4] = { "Colibri PXA300 208MHz", 0 }, + [5] = { "Colibri PXA310 624MHz", 0 }, + [6] = { "Colibri PXA320IT 806MHz", 0 }, + [7] = { "Colibri PXA300 208MHz XT", 0 }, + [8] = { "Colibri PXA270 312MHz", 0 }, + [9] = { "Colibri PXA270 520MHz", 0 }, + [10] = { "Colibri VF50 128MB", TARGET_IS_ENABLED(COLIBRI_VF) }, + [11] = { "Colibri VF61 256MB", TARGET_IS_ENABLED(COLIBRI_VF) }, + [12] = { "Colibri VF61 256MB IT", TARGET_IS_ENABLED(COLIBRI_VF) }, + [13] = { "Colibri VF50 128MB IT", TARGET_IS_ENABLED(COLIBRI_VF) }, + [14] = { "Colibri iMX6S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [15] = { "Colibri iMX6DL 512MB", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [16] = { "Colibri iMX6S 256MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [17] = { "Colibri iMX6DL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6) }, + [18] = { "UNKNOWN MODULE", 0 }, + [19] = { "UNKNOWN MODULE", 0 }, + [20] = { "Colibri T20 256MB", TARGET_IS_ENABLED(COLIBRI_T20) }, + [21] = { "Colibri T20 512MB", TARGET_IS_ENABLED(COLIBRI_T20) }, + [22] = { "Colibri T20 512MB IT", TARGET_IS_ENABLED(COLIBRI_T20) }, + [23] = { "Colibri T30 1GB", TARGET_IS_ENABLED(COLIBRI_T30) }, + [24] = { "Colibri T20 256MB IT", TARGET_IS_ENABLED(COLIBRI_T20) }, + [25] = { "Apalis T30 2GB", TARGET_IS_ENABLED(APALIS_T30) }, + [26] = { "Apalis T30 1GB", TARGET_IS_ENABLED(APALIS_T30) }, + [27] = { "Apalis iMX6Q 1GB", TARGET_IS_ENABLED(APALIS_IMX6) }, + [28] = { "Apalis iMX6Q 2GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + [29] = { "Apalis iMX6D 512MB", TARGET_IS_ENABLED(APALIS_IMX6) }, + [30] = { "Colibri T30 1GB IT", TARGET_IS_ENABLED(COLIBRI_T30) }, + [31] = { "Apalis T30 1GB IT", TARGET_IS_ENABLED(APALIS_T30) }, + [32] = { "Colibri iMX7S 256MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + [33] = { "Colibri iMX7D 512MB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + [34] = { "Apalis TK1 2GB", TARGET_IS_ENABLED(APALIS_TK1) }, + [35] = { "Apalis iMX6D 1GB IT", TARGET_IS_ENABLED(APALIS_IMX6) }, + [36] = { "Colibri iMX6ULL 256MB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + [37] = { "Apalis iMX8QM 4GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + [38] = { "Colibri iMX8QXP 2GB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + [39] = { "Colibri iMX7D 1GB", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + [40] = { "Colibri iMX6ULL 512MB WB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + [41] = { "Colibri iMX7D 512MB EPDC", TARGET_IS_ENABLED(COLIBRI_IMX7) }, + [42] = { "Apalis TK1 4GB", TARGET_IS_ENABLED(APALIS_TK1) }, + [43] = { "Colibri T20 512MB IT SETEK", TARGET_IS_ENABLED(COLIBRI_T20) }, + [44] = { "Colibri iMX6ULL 512MB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + [45] = { "Colibri iMX6ULL 512MB WB", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + [46] = { "Apalis iMX8QXP 2GB WB IT", 0 }, + [47] = { "Apalis iMX8QM 4GB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + [48] = { "Apalis iMX8QP 2GB WB", TARGET_IS_ENABLED(APALIS_IMX8) }, + [49] = { "Apalis iMX8QP 2GB", TARGET_IS_ENABLED(APALIS_IMX8) }, + [50] = { "Colibri iMX8QXP 2GB IT", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + [51] = { "Colibri iMX8DX 1GB WB", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + [52] = { "Colibri iMX8DX 1GB", TARGET_IS_ENABLED(COLIBRI_IMX8X) }, + [53] = { "Apalis iMX8QXP 2GB ECC IT", 0 }, + [54] = { "Apalis iMX8DXP 1GB", TARGET_IS_ENABLED(APALIS_IMX8) }, + [55] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [56] = { "Verdin iMX8M Nano Quad 1GB WB", 0 }, + [57] = { "Verdin iMX8M Mini DualLite 1GB", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [58] = { "Verdin iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + [59] = { "Verdin iMX8M Mini Quad 2GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [60] = { "Verdin iMX8M Mini DualLite 1GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [61] = { "Verdin iMX8M Plus Quad 2GB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + [62] = { "Colibri iMX6ULL 1GB IT", TARGET_IS_ENABLED(COLIBRI_IMX6ULL) }, + [63] = { "Verdin iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + [64] = { "Verdin iMX8M Plus Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + [65] = { "Verdin iMX8M Plus QuadLite 1GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + [66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + [67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + [68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + [69] = { "Verdin AM62 Quad 1GB WB IT", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, }; const char * const toradex_carrier_boards[] = { @@ -158,6 +151,42 @@ const char * const toradex_display_adapters[] = { [159] = "Verdin DSI to LVDS Adapter", }; +const u32 toradex_ouis[] = { + [0] = 0x00142dUL, + [1] = 0x8c06cbUL, +}; + +static u32 get_serial_from_mac(struct toradex_eth_addr *eth_addr) +{ + int i; + u32 oui = ntohl(eth_addr->oui) >> 8; + u32 nic = ntohl(eth_addr->nic) >> 8; + + for (i = 0; i < ARRAY_SIZE(toradex_ouis); i++) { + if (toradex_ouis[i] == oui) + break; + } + + return (u32)((i << 24) + nic); +} + +void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr) +{ + u8 oui_index = tdx_serial >> 24; + u32 nic = tdx_serial & GENMASK(23, 0); + u32 oui; + + if (oui_index >= ARRAY_SIZE(toradex_ouis)) { + puts("Can't find OUI for this serial#\n"); + oui_index = 0; + } + + oui = toradex_ouis[oui_index]; + + eth_addr->oui = htonl(oui << 8); + eth_addr->nic = htonl(nic << 8); +} + #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC static int tdx_cfg_block_mmc_storage(u8 *config_block, int write) { @@ -330,8 +359,7 @@ int read_tdx_cfg_block(void) memcpy(&tdx_eth_addr, config_block + offset, 6); - /* NIC part of MAC address is serial number */ - tdx_serial = ntohl(tdx_eth_addr.nic) >> 8; + tdx_serial = get_serial_from_mac(&tdx_eth_addr); break; case TAG_HW: memcpy(&tdx_hw_tag, config_block + offset, 8); @@ -344,8 +372,7 @@ int read_tdx_cfg_block(void) } /* Cap product id to avoid issues with a yet unknown one */ - if (tdx_hw_tag.prodid >= (sizeof(toradex_modules) / - sizeof(toradex_modules[0]))) + if (tdx_hw_tag.prodid >= ARRAY_SIZE(toradex_modules)) tdx_hw_tag.prodid = 0; out: @@ -353,194 +380,56 @@ out: return ret; } +static int parse_assembly_string(char *string_to_parse, u16 *assembly) +{ + if (string_to_parse[3] >= 'A' && string_to_parse[3] <= 'Z') + *assembly = string_to_parse[3] - 'A'; + else if (string_to_parse[3] == '#') + *assembly = simple_strtoul(&string_to_parse[4], NULL, 10); + else + return -EINVAL; + + return 0; +} + static int get_cfgblock_interactive(void) { char message[CONFIG_SYS_CBSIZE]; - char *soc; - char it = 'n'; - char wb = 'n'; int len = 0; + int ret = 0; + unsigned int prodid; + int i; - /* Unknown module by default */ - tdx_hw_tag.prodid = 0; + printf("Enabled modules:\n"); + for (i = 0; i < ARRAY_SIZE(toradex_modules); i++) { + if (toradex_modules[i].is_enabled) + printf(" %04d %s\n", i, toradex_modules[i].name); + } - if (cpu_is_pxa27x()) - sprintf(message, "Is the module the 312 MHz version? [y/N] "); - else - it = 'y'; - -#if defined(CONFIG_TARGET_APALIS_IMX8) || \ - defined(CONFIG_TARGET_APALIS_IMX8X) || \ - defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \ - defined(CONFIG_TARGET_COLIBRI_IMX8X) || \ - defined(CONFIG_TARGET_VERDIN_IMX8MM) || \ - defined(CONFIG_TARGET_VERDIN_IMX8MP) - sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] "); + sprintf(message, "Enter the module ID: "); len = cli_readline(message); - wb = console_buffer[0]; -#endif - soc = env_get("soc"); - if (!strcmp("mx6", soc)) { -#ifdef CONFIG_TARGET_APALIS_IMX6 - if (it == 'y' || it == 'Y') { - if (is_cpu_type(MXC_CPU_MX6Q)) - tdx_hw_tag.prodid = APALIS_IMX6Q_IT; - else - tdx_hw_tag.prodid = APALIS_IMX6D_IT; - } else { - if (is_cpu_type(MXC_CPU_MX6Q)) - tdx_hw_tag.prodid = APALIS_IMX6Q; - else - tdx_hw_tag.prodid = APALIS_IMX6D; - } -#elif CONFIG_TARGET_COLIBRI_IMX6 - if (it == 'y' || it == 'Y') { - if (is_cpu_type(MXC_CPU_MX6DL)) - tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT; - else if (is_cpu_type(MXC_CPU_MX6SOLO)) - tdx_hw_tag.prodid = COLIBRI_IMX6S_IT; - } else { - if (is_cpu_type(MXC_CPU_MX6DL)) - tdx_hw_tag.prodid = COLIBRI_IMX6DL; - else if (is_cpu_type(MXC_CPU_MX6SOLO)) - tdx_hw_tag.prodid = COLIBRI_IMX6S; - } -#elif CONFIG_TARGET_COLIBRI_IMX6ULL - if (it == 'y' || it == 'Y') { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT; - else - tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT; - } else { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT; - else - tdx_hw_tag.prodid = COLIBRI_IMX6ULL; - } -#endif - } else if (!strcmp("imx7d", soc)) - tdx_hw_tag.prodid = COLIBRI_IMX7D; - else if (!strcmp("imx7s", soc)) - tdx_hw_tag.prodid = COLIBRI_IMX7S; - else if (is_cpu_type(MXC_CPU_IMX8QM)) { - if (it == 'y' || it == 'Y') { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT; - else - tdx_hw_tag.prodid = APALIS_IMX8QM_IT; - } else { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = APALIS_IMX8QP_WIFI_BT; - else - tdx_hw_tag.prodid = APALIS_IMX8QP; - } - } else if (is_cpu_type(MXC_CPU_IMX8QXP)) { -#ifdef CONFIG_TARGET_APALIS_IMX8X - if (it == 'y' || it == 'Y' || wb == 'y' || wb == 'Y') { - tdx_hw_tag.prodid = APALIS_IMX8QXP_WIFI_BT_IT; - } else { - if (gd->ram_size == 0x40000000) - tdx_hw_tag.prodid = APALIS_IMX8DXP; - else - tdx_hw_tag.prodid = APALIS_IMX8QXP; - } -#elif CONFIG_TARGET_COLIBRI_IMX8X - if (it == 'y' || it == 'Y') { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT; - else - tdx_hw_tag.prodid = COLIBRI_IMX8QXP_IT; - } else { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = COLIBRI_IMX8DX_WIFI_BT; - else - tdx_hw_tag.prodid = COLIBRI_IMX8DX; - } -#endif - } else if (is_cpu_type(MXC_CPU_IMX8MMDL)) { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT; - else - tdx_hw_tag.prodid = VERDIN_IMX8MMDL; - } else if (is_cpu_type(MXC_CPU_IMX8MM)) { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT; - else - tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT; - } else if (is_cpu_type(MXC_CPU_IMX8MN)) { - tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT; - } else if (is_cpu_type(MXC_CPU_IMX8MP)) { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT; - else - tdx_hw_tag.prodid = VERDIN_IMX8MPQ; - } else if (!strcmp("tegra20", soc)) { - if (it == 'y' || it == 'Y') - if (gd->ram_size == 0x10000000) - tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT; - else - tdx_hw_tag.prodid = COLIBRI_T20_512MB_IT; - else - if (gd->ram_size == 0x10000000) - tdx_hw_tag.prodid = COLIBRI_T20_256MB; - else - tdx_hw_tag.prodid = COLIBRI_T20_512MB; - } else if (cpu_is_pxa27x()) { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ; - else - tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ; - } -#ifdef CONFIG_MACH_TYPE - else if (!strcmp("tegra30", soc)) { - if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = APALIS_T30_IT; - else - if (gd->ram_size == 0x40000000) - tdx_hw_tag.prodid = APALIS_T30_1GB; - else - tdx_hw_tag.prodid = APALIS_T30_2GB; - } else { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = COLIBRI_T30_IT; - else - tdx_hw_tag.prodid = COLIBRI_T30; - } - } -#endif /* CONFIG_MACH_TYPE */ - else if (!strcmp("tegra124", soc)) { - tdx_hw_tag.prodid = APALIS_TK1_2GB; - } else if (!strcmp("vf500", soc)) { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = COLIBRI_VF50_IT; - else - tdx_hw_tag.prodid = COLIBRI_VF50; - } else if (!strcmp("vf610", soc)) { - if (it == 'y' || it == 'Y') - tdx_hw_tag.prodid = COLIBRI_VF61_IT; - else - tdx_hw_tag.prodid = COLIBRI_VF61; - } - - if (!tdx_hw_tag.prodid) { - printf("Module type not detectable due to unknown SoC\n"); + prodid = simple_strtoul(console_buffer, NULL, 10); + if (prodid >= ARRAY_SIZE(toradex_modules) || !toradex_modules[prodid].is_enabled) { + printf("Parsing module id failed\n"); return -1; } + tdx_hw_tag.prodid = prodid; + len = 0; while (len < 4) { - sprintf(message, "Enter the module version (e.g. V1.1B): V"); + sprintf(message, "Enter the module version (e.g. V1.1B or V1.1#26): V"); len = cli_readline(message); } tdx_hw_tag.ver_major = console_buffer[0] - '0'; tdx_hw_tag.ver_minor = console_buffer[2] - '0'; - tdx_hw_tag.ver_assembly = console_buffer[3] - 'A'; - if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1) - tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ - - COLIBRI_PXA270_V1_312MHZ); + ret = parse_assembly_string(console_buffer, &tdx_hw_tag.ver_assembly); + if (ret) { + printf("Parsing module version failed\n"); + return ret; + } while (len < 8) { sprintf(message, "Enter module serial number: "); @@ -555,6 +444,8 @@ static int get_cfgblock_interactive(void) static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag, u32 *serial) { + char revision[3] = {barcode[6], barcode[7], '\0'}; + if (strlen(barcode) < 16) { printf("Argument too short, barcode is 16 chars long\n"); return -1; @@ -563,7 +454,7 @@ static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag, /* Get hardware information from the first 8 digits */ tag->ver_major = barcode[4] - '0'; tag->ver_minor = barcode[5] - '0'; - tag->ver_assembly = barcode[7] - '0'; + tag->ver_assembly = simple_strtoul(revision, NULL, 10); barcode[4] = '\0'; tag->prodid = simple_strtoul(barcode, NULL, 10); @@ -741,11 +632,11 @@ static int get_cfgblock_carrier_interactive(void) { char message[CONFIG_SYS_CBSIZE]; int len; + int ret = 0; printf("Supported carrier boards:\n"); printf("CARRIER BOARD NAME\t\t [ID]\n"); - for (int i = 0; i < sizeof(toradex_carrier_boards) / - sizeof(toradex_carrier_boards[0]); i++) + for (int i = 0; i < ARRAY_SIZE(toradex_carrier_boards); i++) if (toradex_carrier_boards[i]) printf("%s \t\t [%d]\n", toradex_carrier_boards[i], i); @@ -754,13 +645,18 @@ static int get_cfgblock_carrier_interactive(void) tdx_car_hw_tag.prodid = simple_strtoul(console_buffer, NULL, 10); do { - sprintf(message, "Enter carrier board version (e.g. V1.1B): V"); + sprintf(message, "Enter carrier board version (e.g. V1.1B or V1.1#26): V"); len = cli_readline(message); } while (len < 4); tdx_car_hw_tag.ver_major = console_buffer[0] - '0'; tdx_car_hw_tag.ver_minor = console_buffer[2] - '0'; - tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A'; + + ret = parse_assembly_string(console_buffer, &tdx_car_hw_tag.ver_assembly); + if (ret) { + printf("Parsing module version failed\n"); + return ret; + } while (len < 8) { sprintf(message, "Enter carrier board serial number: "); @@ -937,8 +833,7 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc, } /* Convert serial number to MAC address (the storage format) */ - tdx_eth_addr.oui = htonl(0x00142dUL << 8); - tdx_eth_addr.nic = htonl(tdx_serial << 8); + get_mac_from_serial(tdx_serial, &tdx_eth_addr); /* Valid Tag */ write_tag(config_block, &offset, TAG_VALID, NULL, 0); diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 9debd5f046..405a25acda 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -20,6 +20,11 @@ struct toradex_eth_addr { u32 nic:24; } __attribute__((__packed__)); +struct toradex_som { + const char *name; + int is_enabled; +}; + enum { COLIBRI_PXA270_V1_312MHZ = 1, COLIBRI_PXA270_V1_520MHZ, @@ -31,7 +36,7 @@ enum { COLIBRI_PXA270_312MHZ, COLIBRI_PXA270_520MHZ, COLIBRI_VF50, /* 10 */ - COLIBRI_VF61, /* not currently on sale */ + COLIBRI_VF61, COLIBRI_VF61_IT, COLIBRI_VF50_IT, COLIBRI_IMX6S, @@ -62,7 +67,7 @@ enum { COLIBRI_IMX7D_EMMC, COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */ COLIBRI_IMX7D_EPDC, - APALIS_TK1_4GB, /* not currently on sale */ + APALIS_TK1_4GB, COLIBRI_T20_512MB_IT_SETEK, COLIBRI_IMX6ULL_IT, COLIBRI_IMX6ULL_WIFI_BT, /* 45 */ @@ -82,6 +87,14 @@ enum { VERDIN_IMX8MMQ_IT, VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */ VERDIN_IMX8MPQ, + COLIBRI_IMX6ULL_IT_EMMC, + VERDIN_IMX8MPQ_IT, + VERDIN_IMX8MPQ_2GB_WIFI_BT_IT, + VERDIN_IMX8MPQL_IT, /* 65 */ + VERDIN_IMX8MPQ_8GB_WIFI_BT, + APALIS_IMX8QM_8GB_WIFI_BT_IT, + VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN, + VERDIN_AM62Q_WIFI_BT_IT, }; enum { @@ -94,7 +107,7 @@ enum { VERDIN_DSI_TO_LVDS_ADAPTER = 159, }; -extern const char * const toradex_modules[]; +extern const struct toradex_som toradex_modules[]; extern const char * const toradex_carrier_boards[]; extern bool valid_cfgblock; extern struct toradex_hw tdx_hw_tag; @@ -108,4 +121,6 @@ int read_tdx_cfg_block_carrier(void); int try_migrate_tdx_cfg_block_carrier(void); +void get_mac_from_serial(u32 tdx_serial, struct toradex_eth_addr *eth_addr); + #endif /* _TDX_CFG_BLOCK_H */ diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index a3d287ed5e..716174d86d 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -20,15 +20,17 @@ #include <asm/setup.h> #include "tdx-common.h" -#define TORADEX_OUI 0x00142dUL +#define SERIAL_STR_LEN 8 +#define MODULE_VER_STR_LEN 4 // V1.1 +#define MODULE_REV_STR_LEN 3 // [A-Z] or #[26-99] #ifdef CONFIG_TDX_CFG_BLOCK -static char tdx_serial_str[9]; -static char tdx_board_rev_str[6]; +static char tdx_serial_str[SERIAL_STR_LEN + 1]; +static char tdx_board_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA -static char tdx_car_serial_str[9]; -static char tdx_car_rev_str[6]; +static char tdx_car_serial_str[SERIAL_STR_LEN + 1]; +static char tdx_car_rev_str[MODULE_VER_STR_LEN + MODULE_REV_STR_LEN + 1]; static char *tdx_carrier_board_name; #endif @@ -79,28 +81,45 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif /* CONFIG_SERIAL_TAG */ +static const char *get_board_assembly(u16 ver_assembly) +{ + static char ver_name[MODULE_REV_STR_LEN + 1]; + + if (ver_assembly < 26) { + ver_name[0] = (char)ver_assembly + 'A'; + ver_name[1] = '\0'; + } else { + snprintf(ver_name, sizeof(ver_name), + "#%u", ver_assembly); + } + + return ver_name; +} + int show_board_info(void) { unsigned char ethaddr[6]; if (read_tdx_cfg_block()) { printf("MISSING TORADEX CONFIG BLOCK\n"); - tdx_eth_addr.oui = htonl(TORADEX_OUI << 8); - tdx_eth_addr.nic = htonl(tdx_serial << 8); + get_mac_from_serial(tdx_serial, &tdx_eth_addr); checkboard(); } else { - sprintf(tdx_serial_str, "%08u", tdx_serial); - sprintf(tdx_board_rev_str, "V%1d.%1d%c", - tdx_hw_tag.ver_major, - tdx_hw_tag.ver_minor, - (char)tdx_hw_tag.ver_assembly + 'A'); + snprintf(tdx_serial_str, sizeof(tdx_serial_str), + "%08u", tdx_serial); + snprintf(tdx_board_rev_str, sizeof(tdx_board_rev_str), + "V%1d.%1d%s", + tdx_hw_tag.ver_major, + tdx_hw_tag.ver_minor, + get_board_assembly(tdx_hw_tag.ver_assembly)); env_set("serial#", tdx_serial_str); - printf("Model: Toradex %s %s, Serial# %s\n", - toradex_modules[tdx_hw_tag.prodid], - tdx_board_rev_str, - tdx_serial_str); + printf("Model: Toradex %04d %s %s\n", + tdx_hw_tag.prodid, + toradex_modules[tdx_hw_tag.prodid].name, + tdx_board_rev_str); + printf("Serial#: %s\n", tdx_serial_str); #ifdef CONFIG_TDX_CFG_BLOCK_EXTRA if (read_tdx_cfg_block_carrier()) { printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n"); @@ -109,12 +128,13 @@ int show_board_info(void) tdx_carrier_board_name = (char *) toradex_carrier_boards[tdx_car_hw_tag.prodid]; - sprintf(tdx_car_serial_str, "%08u", tdx_car_serial); - sprintf(tdx_car_rev_str, "V%1d.%1d%c", - tdx_car_hw_tag.ver_major, - tdx_car_hw_tag.ver_minor, - (char)tdx_car_hw_tag.ver_assembly + - 'A'); + snprintf(tdx_car_serial_str, sizeof(tdx_car_serial_str), + "%08u", tdx_car_serial); + snprintf(tdx_car_rev_str, sizeof(tdx_car_rev_str), + "V%1d.%1d%s", + tdx_car_hw_tag.ver_major, + tdx_car_hw_tag.ver_minor, + get_board_assembly(tdx_car_hw_tag.ver_assembly)); env_set("carrier_serial#", tdx_car_serial_str); printf("Carrier: Toradex %s %s, Serial# %s\n", @@ -132,8 +152,8 @@ int show_board_info(void) if (!eth_env_get_enetaddr("ethaddr", ethaddr)) eth_env_set_enetaddr("ethaddr", (u8 *)&tdx_eth_addr); -#ifdef CONFIG_TDX_CFG_BLOCK_2ND_ETHADDR - if (!eth_env_get_enetaddr("eth1addr", ethaddr)) { + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK_2ND_ETHADDR) && + !eth_env_get_enetaddr("eth1addr", ethaddr)) { /* * Secondary MAC address is allocated from block * 0x100000 higher then the first MAC address @@ -142,7 +162,6 @@ int show_board_info(void) ethaddr[3] += 0x10; eth_env_set_enetaddr("eth1addr", ethaddr); } -#endif return 0; } @@ -170,7 +189,7 @@ int ft_common_board_setup(void *blob, struct bd_info *bd) if (tdx_hw_tag.ver_major) { char prod_id[5]; - sprintf(prod_id, "%04u", tdx_hw_tag.prodid); + snprintf(prod_id, sizeof(prod_id), "%04u", tdx_hw_tag.prodid); fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5); fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str, diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h index 8020df5b44..81375de598 100644 --- a/board/toradex/common/tdx-common.h +++ b/board/toradex/common/tdx-common.h @@ -11,8 +11,4 @@ int ft_common_board_setup(void *blob, struct bd_info *bd); -#if defined(CONFIG_DM_VIDEO) -int show_boot_logo(void); -#endif - #endif /* _TDX_COMMON_H */ diff --git a/board/toradex/verdin-am62/Kconfig b/board/toradex/verdin-am62/Kconfig new file mode 100644 index 0000000000..bd22b6fe4c --- /dev/null +++ b/board/toradex/verdin-am62/Kconfig @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2023 Toradex +# + +choice + prompt "Toradex Verdin AM62 based boards" + optional + +config TARGET_VERDIN_AM62_A53 + bool "Toradex Verdin AM62 running on A53" + select ARM64 + select SOC_K3_AM625 + imply BOARD + imply SPL_BOARD + +config TARGET_VERDIN_AM62_R5 + bool "Toradex Verdin AM62 running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select SOC_K3_AM625 + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_VERDIN_AM62_A53 + +config SYS_BOARD + default "verdin-am62" + +config SYS_CONFIG_NAME + default "verdin-am62" + +config SYS_VENDOR + default "toradex" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_EXTRA + default y + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif + +if TARGET_VERDIN_AM62_R5 + +config SYS_BOARD + default "verdin-am62" + +config SYS_CONFIG_NAME + default "verdin-am62" + +config SYS_VENDOR + default "toradex" + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +endif diff --git a/board/toradex/verdin-am62/MAINTAINERS b/board/toradex/verdin-am62/MAINTAINERS new file mode 100644 index 0000000000..1e2639d9a3 --- /dev/null +++ b/board/toradex/verdin-am62/MAINTAINERS @@ -0,0 +1,14 @@ +Verdin AM62 +F: arch/arm/dts/k3-am625-verdin-r5.dts +F: arch/arm/dts/k3-am625-verdin.dts +F: arch/arm/dts/k3-am625-verdin-u-boot.dtsi +F: arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +F: board/toradex/verdin-am62/ +F: configs/verdin-am62_a53_defconfig +F: configs/verdin-am62_r5_defconfig +F: configs/verdin-am62_r5_usbdfu_defconfig +F: doc/board/toradex/verdin-am62.rst +F: include/configs/verdin-am62.h +M: Marcel Ziswiler <marcel.ziswiler@toradex.com> +S: Maintained +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am-62 diff --git a/board/toradex/verdin-am62/Makefile b/board/toradex/verdin-am62/Makefile new file mode 100644 index 0000000000..af1a5508ed --- /dev/null +++ b/board/toradex/verdin-am62/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2023 Toradex +# + +obj-y += verdin-am62.o diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c new file mode 100644 index 0000000000..e718eb0030 --- /dev/null +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Board specific initialization for Verdin AM62 SoM + * + * Copyright 2023 Toradex - https://www.toradex.com/ + * + */ + +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <common.h> +#include <dm/uclass.h> +#include <env.h> +#include <fdt_support.h> +#include <i2c.h> +#include <k3-ddrss.h> +#include <power/tps65219.h> +#include <spl.h> + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* from 5.8 Boot Memory Maps */ +#define BOOT_PARAMETER_TABLE 0x43c3f298 +/* from 5.6.1 Common Header */ +#define BOOT_PARAMETER_PRIMARY_PERIPHERAL (*(u16 *)(BOOT_PARAMETER_TABLE + 0x04)) +#define BOOT_PARAMETER_SECONDARY_PERIPHERAL (*(u16 *)(BOOT_PARAMETER_TABLE + 0x204)) +#define BOOT_PARAMETER_EMMC 101 +#define BOOT_PARAMETER_SD 100 +#define BOOT_PARAMETER_USB_DFU 70 + +#define PMIC_I2C_BUS 0x0 +#define PMIC_I2C_ADDRESS 0x30 +#define PMIC_BUCK1_VSET_850 0xa + +int board_init(void) +{ + struct udevice *dev; + u8 addr, data[1]; + int err; + + /* Set PMIC Buck1 aka +VDD_CORE to 850 mV */ + err = i2c_get_chip_for_busnum(PMIC_I2C_BUS, PMIC_I2C_ADDRESS, 1, &dev); + if (err) { + printf("%s: Cannot find PMIC I2C chip (err=%d)\n", __func__, err); + } else { + addr = TPS65219_BUCK1_VOUT_REG; + err = dm_i2c_read(dev, addr, data, 1); + if (err) + debug("failed to get TPS65219_BUCK1_VOUT_REG (err=%d)\n", err); + data[0] &= ~TPS65219_VOLT_MASK; + data[0] |= PMIC_BUCK1_VSET_850; + err = dm_i2c_write(dev, addr, data, 1); + if (err) + debug("failed to set TPS65219_BUCK1_VOUT_REG (err=%d)\n", err); + } + + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#if defined(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_K3_AM64_DDRSS) +static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); +} +#else +static void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS); + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} +#endif + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ +#if IS_ENABLED(CONFIG_K3_AM64_DDRSS) + fixup_ddr_driver_for_ecc(spl_image); +#else + fixup_memory_node(spl_image); +#endif +} +#endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +#if !defined(CONFIG_SPL_BUILD) +/* Should check if we were booted over dfu, and if so go to DFU / UMS for download */ +void decide_on_dfu(void) +{ + /* + * SD boot with sdcard, 7000f290: 00000000 + * SD boot without sdcard, dfu, 7000f290: 00000001 + * eMMC Boot, eMMC flashed 7000f290: 00000000 + * eMMC Boot, eMMC zeroed 7000f290: 00000001 + * DFU Boot 7000f290: 00000000 + * + * If this Memory location will stay untouched in future versions is + * unknown, so the code might break. + * Compare with arch/arm/mach-k3/am625_init.c which however is SPL only + */ + u32 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + u32 bootmode = bootindex & 1 ? BOOT_PARAMETER_SECONDARY_PERIPHERAL : + BOOT_PARAMETER_PRIMARY_PERIPHERAL; + + if (bootmode == BOOT_PARAMETER_USB_DFU) { + printf("DFU boot mode detected, going to DFU again for further downloads\n"); + env_set("bootcmd", "setenv dfu_alt_info $dfu_alt_info_emmc;" + "dfu 0 mmc 0; ums 0 mmc 0"); + } + + debug("Booting from %s boot device\n", bootindex & 1 ? "Secondary" : + "Primary"); + debug("Primary boot device as read from boot parameters %hd\n", + BOOT_PARAMETER_PRIMARY_PERIPHERAL); + debug("Secondary boot device as read from boot parameters %hd\n", + BOOT_PARAMETER_SECONDARY_PERIPHERAL); +} +#else +void decide_on_dfu(void) {} +#endif /* CONFIG_SPL_BUILD */ + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + int is_wifi = 0; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a module with + * Wi-Fi/Bluetooth make sure we use the -wifi device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62Q_WIFI_BT_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + /* set bootcmd to start DFU and then UMS mode if booted from DFU */ + decide_on_dfu(); + + return 0; +} + +#define CTRLMMR_USB0_PHY_CTRL 0x43004008 +#define CTRLMMR_USB1_PHY_CTRL 0x43004018 +#define CORE_VOLTAGE 0x80000000 + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + u32 val; + + /* Set USB0 PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB0_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Set USB1 PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB1_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB1_PHY_CTRL); + + /* We use the 32k FOUT from the Epson RX8130CE RTC chip */ + /* In WKUP_LFOSC0 clear the power down bit and set the bypass bit + * The bypass bit is required as we provide a CMOS clock signal and + * the power down seems to be required also in the bypass case + * despite of the datasheet stating otherwise + */ + /* Compare with the AM62 datasheet, + * Table 7-21. LFXOSC Modes of Operation + */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL; + val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL; + writel(val, MCU_CTRL_LFXOSC_CTRL); + /* Make sure to mux up to take the SoC 32k from the LFOSC input */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); +} +#endif diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 7cfae8767c..9292ff36ea 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -145,7 +145,8 @@ static void select_dt_from_module_version(void) * device tree. */ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || - (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT); + (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN); } switch (get_pcb_revision()) { diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig deleted file mode 100644 index 777d3a9354..0000000000 --- a/configs/apalis-imx8x_defconfig +++ /dev/null @@ -1,77 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_SYS_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x89000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_DM_GPIO=y -CONFIG_TARGET_APALIS_IMX8X=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" -CONFIG_BOOTDELAY=1 -CONFIG_LOG=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SYS_PROMPT="Apalis iMX8X # " -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_UUID=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=4096 -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_ENV=y -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig deleted file mode 100644 index 2865730b8f..0000000000 --- a/configs/colibri_pxa270_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_TARGET_COLIBRI_PXA270=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200" -CONFIG_SYS_DEVICE_NULLDEV=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_DISPLAY_BOARDINFO_LATE=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_SYS_LONGHELP is not set -CONFIG_SYS_PROMPT="$ " -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_EXPORTENV is not set -# CONFIG_CMD_IMPORTENV is not set -CONFIG_CMD_DM=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x80000 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_DM=y -CONFIG_DM_MMC=y -CONFIG_PXA_MMC_GENERIC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_DM_SERIAL=y -CONFIG_PXA_SERIAL=y -CONFIG_USB=y -# CONFIG_REGEX is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig new file mode 100644 index 0000000000..32405a21b6 --- /dev/null +++ b/configs/verdin-am62_a53_defconfig @@ -0,0 +1,202 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 +CONFIG_TARGET_VERDIN_AM62_A53=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am625-verdin-${variant}-${fdt_board}.dtb" +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_ANDROID_AB=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot A53 SPL" +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_PROMPT="Verdin AM62 # " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ABOOTIMG=y +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BCB=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y +CONFIG_CMD_DDRSS=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_GPIO_HOG=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65219=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS65219=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_HOST_ETHER=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LIBAVB=y +CONFIG_HEXDUMP=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig new file mode 100644 index 0000000000..70c44dfd2f --- /dev/null +++ b/configs/verdin-am62_r5_defconfig @@ -0,0 +1,111 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x7000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_VERDIN_AM62_R5=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x3A7F0 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-r5" +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y +CONFIG_ESM_K3=y +CONFIG_DM_MMC=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_DM_THERMAL=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/verdin-am62_r5_usbdfu_defconfig b/configs/verdin-am62_r5_usbdfu_defconfig new file mode 100644 index 0000000000..677073b808 --- /dev/null +++ b/configs/verdin-am62_r5_usbdfu_defconfig @@ -0,0 +1,129 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x7000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_VERDIN_AM62_R5=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x3A7F0 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-verdin-r5" +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_ESM_K3=y +CONFIG_DM_MMC=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/doc/board/toradex/apalix-imx8x.rst b/doc/board/toradex/apalix-imx8x.rst deleted file mode 100644 index ce7dde8d00..0000000000 --- a/doc/board/toradex/apalix-imx8x.rst +++ /dev/null @@ -1,74 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -Apalis iMX8X V1.1A Module -========================== - -Quick Start ------------ - -- Build the ARM trusted firmware binary -- Get scfw_tcm.bin and ahab-container.img -- Build U-Boot -- Load U-Boot binary using uuu -- Flash U-Boot binary into the eMMC -- Boot - -Get and Build the ARM Trusted Firmware --------------------------------------- - -.. code-block:: bash - - $ git clone -b toradex_imx_5.4.24_2.1.0 http://git.toradex.com/cgit/imx-atf.git - $ cd imx-atf/ - $ make PLAT=imx8qx bl31 - -Get scfw_tcm.bin and ahab-container.img ---------------------------------------- - -.. code-block:: bash - - $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/blob/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.6.3.bin - $ chmod +x imx-seco-3.6.3.bin - $ ./imx-seco-3.6.3.bin - -Copy the following binaries to the U-Boot folder: - -.. code-block:: bash - - $ cp imx-atf/build/imx8qx/release/bl31.bin . - $ cp imx-seco-3.6.3/firmware/seco/mx8qxb0-ahab-container.img mx8qx-ahab-container.imx8_defconfig - -Build U-Boot ------------- -.. code-block:: bash - - $ make apalis-imx8x_defconfig - $ make u-boot-dtb.imx - -Load the U-Boot Binary Using UUU --------------------------------- - -Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``: - -https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases - -Put the module into USB recovery aka serial downloader mode, connect USB device -to your host and execute uuu: - -.. code-block:: bash - - sudo ./uuu u-boot/u-boot-dtb.imx - -Flash the U-Boot Binary into the eMMC -------------------------------------- - -Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area -partition and boot: - -.. code-block:: bash - - load mmc 1:1 $loadaddr u-boot-dtb.imx - setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 - mmc dev 0 1 - mmc write ${loadaddr} 0x0 ${blkcnt} diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index abba648f86..89fbdcbb9e 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -6,8 +6,9 @@ Toradex .. toctree:: :maxdepth: 2 - apalix-imx8 - apalix-imx8x + apalis-imx8 colibri_imx7 colibri-imx8x + verdin-am62 verdin-imx8mm + verdin-imx8mp diff --git a/doc/board/toradex/verdin-am62.rst b/doc/board/toradex/verdin-am62.rst new file mode 100644 index 0000000000..e4feb19587 --- /dev/null +++ b/doc/board/toradex/verdin-am62.rst @@ -0,0 +1,185 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later +.. sectionauthor:: Marcel Ziswiler <marcel.ziswiler@toradex.com> + +Verdin AM62 Module +================== + +Quick Start +----------- + +- Get the binary-only SYSFW +- Get binary-only TI Linux firmware +- Build the ARM trusted firmware binary +- Build the OPTEE binary +- Build U-Boot for the R5 +- Build U-Boot for the A53 +- Flash to eMMC +- Boot + +For an overview of the TI AM62 SoC boot flow please head over to: +.. file:: ../ti/am62x_sk.rst + +Get the SYSFW +------------- + +.. code-block:: bash + + $ echo "Downloading SYSFW..." + $ git clone git://git.ti.com/k3-image-gen/k3-image-gen.git + +Get the TI Linux Firmware +------------- + +.. code-block:: bash + + $ echo "Downloading TI Linux Firmware..." + $ git clone -b ti-linux-firmware git://git.ti.com/processor-firmware/ti-linux-firmware.git + +Get and Build the ARM Trusted Firmware (Trusted Firmware A) +----------------------------------------------------------- + +.. code-block:: bash + + $ echo "Downloading and building TF-A..." + $ git clone https://github.com/ARM-software/arm-trusted-firmware.git + $ cd arm-trusted-firmware + +Then build ATF (TF-A): + +.. code-block:: bash + + $ export ARCH=aarch64 + $ export CROSS_COMPILE=aarch64-none-linux-gnu- + $ make PLAT=k3 TARGET_BOARD=lite SPD=opteed + +Note: Currently, not buildable with gcc-12.2 please revert to using gcc-11.3. +Note: Currently, latest master is broken please revert to using 2fcd408bb3a6756767a43c073c597cef06e7f2d5. + +Get and Build OPTEE +------------------- + +.. code-block:: bash + + $ echo "Downloading and building OPTEE..." + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + +Then build OPTEE: + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-linux-gnueabihf- + $ export CROSS_COMPILE64=aarch64-none-linux-gnu- + $ make PLATFORM=k3 CFG_ARM64_core=y + +Build U-Boot for R5 +------------------- + +.. code-block:: bash + + $ export ARCH=arm + $ export CROSS_COMPILE=arm-none-linux-gnueabihf- + $ make verdin-am62_r5_defconfig O=/tmp/r5 + $ make O=/tmp/r5 + $ cd ../k3-image-gen + $ make SOC=am62x SBL=/tmp/r5/spl/u-boot-spl.bin SYSFW_PATH=../ti-linux-firmware/ti-sysfw/ti-fs-firmware-am62x-gp.bin + $ cp tiboot3-am62x-gp-evm.bin ../tiboot3.bin + +Build U-Boot for A53 +-------------------- + +.. code-block:: bash + + $ export ARCH=arm64 + $ export CROSS_COMPILE=aarch64-none-linux-gnu- + $ make verdin-am62_a53_defconfig O=/tmp/a53 + $ make ATF=$PWD/../arm-trusted-firmware/build/k3/lite/release/bl31.bin TEE=$PWD/../optee_os/out/arm-plat-k3/core/tee-pager_v2.bin DM=$PWD/../ti-linux-firmware/ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f O=/tmp/a53 + $ cp /tmp/a53/tispl.bin ../ + $ cp /tmp/a53/u-boot.img ../ + +Note: Relative paths to the artefacts are known to not work. + +Flash to eMMC +------------- + +.. code-block:: bash + + => mmc dev 0 1 + => fatload mmc 1 ${loadaddr} tiboot3.bin + => mmc write ${loadaddr} 0x0 0x400 + => fatload mmc 1 ${loadaddr} tispl.bin + => mmc write ${loadaddr} 0x400 0x1000 + => fatload mmc 1 ${loadaddr} u-boot.img + => mmc write ${loadaddr} 0x1400 0x2000 + +As a convenience, instead of those commands one may also use the update U-Boot +wrapper: + +.. code-block:: bash + + > run update_uboot + +Boot +---- + +Output: + +.. code-block:: bash + +U-Boot SPL 2021.01-12793-gfbc143af80e-dirty (Feb 16 2023 - 09:09:06 +0100) +SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.0--v08.06.00 (Chill Capybar') +SPL initial stack usage: 13424 bytes +Trying to boot from MMC2 +Warning: Detected image signing certificate on GP device. Skipping certificate t +o prevent boot failure. This will fail if the image was also encrypted +Warning: Detected image signing certificate on GP device. Skipping certificate t +o prevent boot failure. This will fail if the image was also encrypted +Starting ATF on ARM64 core... + +NOTICE: BL31: v2.7(release):v2.7.0-359-g1309c6c80 +NOTICE: BL31: Built : 09:28:14, Jan 17 2023 +I/TC: +I/TC: OP-TEE version: 3.19.0-15-gd6c5d003 (gcc version 10.3.1 20210621 (GNU Tool +chain for the A-profile Architecture 10.3-2021.07 (arm-10.29))) #2 Tue Jan 17 07 +:55:55 UTC 2023 aarch64 +I/TC: WARNING: This OP-TEE configuration might be insecure! +I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html +I/TC: Primary CPU initializing +I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.0--v08.06.00 (Chill Capybar') +I/TC: HUK Initialized +I/TC: Activated SA2UL device +I/TC: Fixing SA2UL firewall owner for GP device +I/TC: Enabled firewalls for SA2UL TRNG device +I/TC: SA2UL TRNG initialized +I/TC: SA2UL Drivers initialized +I/TC: Primary CPU switching to normal world boot + +U-Boot SPL 2021.01-12793-gfbc143af80e-dirty (Feb 16 2023 - 11:43:02 +0100) +SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.0--v08.06.00 (Chill Capybar') +Trying to boot from MMC2 + + +U-Boot 2021.01-12793-gfbc143af80e-dirty (Feb 16 2023 - 11:43:02 +0100) + +SoC: AM62X SR1.0 GP +DRAM: 1 GiB +MMC: mmc@fa10000: 0, mmc@fa00000: 1, mmc@fa20000: 2 +Loading Environment from MMC... *** Warning - bad CRC, using default environment + +In: serial@2800000 +Out: serial@2800000 +Err: serial@2800000 +Model: Toradex 0069 Verdin AM62 Quad 1GB WB IT V1.0A +Serial#: 00000001 +get_tdx_eeprom: cannot find EEPROM by node +MISSING TORADEX CARRIER CONFIG BLOCKS +get_tdx_eeprom: cannot find EEPROM by node +am65_cpsw_nuss ethernet@8000000: K3 CPSW: nuss_ver: 0x6BA01103 cpsw_ver: 0x6BA81103 ale_ver: 0x00290105 Ports:2 mdio_freq:1000000 +Setting variant to wifi +Net: +Warning: ethernet@8000000port@1 MAC addresses don't match: +Address in ROM is 34:08:e1:7e:90:ad +Address in environment is 00:14:2d:00:00:01 +eth0: ethernet@8000000port@1 +Hit any key to stop autoboot: 0 +Verdin AM62 # diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h deleted file mode 100644 index db31c210f5..0000000000 --- a/include/configs/apalis-imx8x.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2020 Toradex - */ - -#ifndef __APALIS_IMX8X_H -#define __APALIS_IMX8X_H - -#include <asm/arch/imx-regs.h> -#include <linux/sizes.h> -#include <linux/stringify.h> - -#define CONFIG_REMAKE_ELF - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_TFTP_TSIZE - -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - -#define FEC_ENET_ENABLE_TXC_DELAY -#define FEC_ENET_ENABLE_RXC_DELAY - -#define MEM_LAYOUT_ENV_SETTINGS \ - "kernel_addr_r=0x80280000\0" \ - "fdt_addr_r=0x83100000\0" \ - "ramdisk_addr_r=0x8a000000\0" \ - "scriptaddr=0x83200000\0" - -#ifdef CONFIG_AHAB_BOOT -#define AHAB_ENV "sec_boot=yes\0" -#else -#define AHAB_ENV "sec_boot=no\0" -#endif - -/* Boot M4 */ -#define M4_BOOT_ENV \ - "m4_0_image=m4_0.bin\0" \ - "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${m4_0_image}\0" \ - "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ - -#define MFG_NAND_PARTITION "" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) -#include <config_distro_bootcmd.h> -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" - -#define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs ${consoleargs} " \ - "rdinit=/linuxrc g_mass_storage.stall=0 " \ - "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ - "g_mass_storage.idProduct=0x37FF " \ - "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ - "${vidargs} clk_ignore_unused\0" \ - "initrd_addr=0x83800000\0" \ - "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ - "${fdt_addr};\0" \ - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - AHAB_ENV \ - BOOTENV \ - CONFIG_MFG_ENV_SETTINGS \ - M4_BOOT_ENV \ - MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ - "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ - "fdt_file=imx8qxp-apalis-eval.dtb\0" \ - "fdtfile=imx8qxp-apalis-eval.dtb\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "image=Image\0" \ - "initrd_addr=0x83800000\0" \ - "mmcargs=setenv bootargs ${consoleargs} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "netargs=setenv bootargs ${consoleargs} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ - "${vidargs}\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ - "apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \ - "${fdt_addr}\0" \ - "panel=NULL\0" \ - "script=boot.scr\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ - "if test \"$confirm\" = \"y\"; then " \ - "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ - "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ - "${blkcnt}; fi\0" \ - "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" - -/* Link Definitions */ -#define CONFIG_LOADADDR 0x89000000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_2 0x880000000 -#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 8000000 /* 8MHz */ - -/* Networking */ -#define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE 0x5b040000 -#define CONFIG_FEC_MXC_PHYADDR 0x4 -#define CONFIG_ETHPRIME "eth0" -#define CONFIG_FEC_XCV_TYPE RGMII -#define FEC_QUIRK_ENET_MAC -#define PHY_ANEG_TIMEOUT 20000 - -#endif /* __APALIS_IMX8X_H */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h deleted file mode 100644 index 3dedcdaad2..0000000000 --- a/include/configs/colibri_pxa270.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Toradex Colibri PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -/* Avoid overwriting factory configuration block */ -#define CONFIG_BOARD_SIZE_LIMIT 0x40000 - -/* - * Environment settings - */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) -#define CONFIG_BOOTCOMMAND \ - "if fatload mmc 0 0xa0000000 uImage; then " \ - "bootm 0xa0000000; " \ - "fi; " \ - "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ - "bootm 0xa0000000; " \ - "fi; " \ - "bootm 0xc0000;" -#define CONFIG_TIMESTAMP -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * Serial Console Configuration - */ - -/* - * Bootloader Components Configuration - */ - -/* I2C support */ -#ifdef CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PXA -#define CONFIG_PXA_STD_I2C -#define CONFIG_PXA_PWR_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -/* LCD support */ -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_PXA_VGA -#define CONFIG_LCD_LOGO -#endif - -/* - * Networking Configuration - */ -#ifdef CONFIG_CMD_NET - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000000 -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_NET_RETRY_COUNT 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#endif - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ - -/* - * DRAM Map - */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ - -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) -#endif - -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -/* Skip factory configuration block */ - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00000000 -#define CONFIG_SYS_GPSR1_VAL 0x00020000 -#define CONFIG_SYS_GPSR2_VAL 0x0002c000 -#define CONFIG_SYS_GPSR3_VAL 0x00000000 - -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 - -#define CONFIG_SYS_GPDR0_VAL 0xc8008000 -#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 -#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff -#define CONFIG_SYS_GPDR3_VAL 0x0061e804 - -#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 -#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 -#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00500240 -#define CONFIG_SYS_CCCR 0x02000290 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 -#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 -#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 -#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 -#define CONFIG_SYS_MDREFR_VAL 0x2003a031 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00028307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x00038787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0002830f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -#include "pxa-common.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h deleted file mode 100644 index 52d77e06ac..0000000000 --- a/include/configs/pxa-common.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Toradex Colibri PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __CONFIG_PXA_COMMON_H__ -#define __CONFIG_PXA_COMMON_H__ - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* - * OHCI USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#ifdef CONFIG_CPU_PXA27X -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#else -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci" -#endif - -#endif /* __CONFIG_PXA_COMMON_H__ */ diff --git a/include/configs/verdin-am62.h b/include/configs/verdin-am62.h new file mode 100644 index 0000000000..027266d29f --- /dev/null +++ b/include/configs/verdin-am62.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Configuration header file for Verdin AM62 SoM + * + * Copyright 2023 Toradex - https://www.toradex.com/ + */ + +#ifndef __CONFIG_VERDIN_AM62_H +#define __CONFIG_VERDIN_AM62_H + +#include <environment/ti/k3_dfu.h> +#include <linux/sizes.h> + +#define CONFIG_LOADADDR 0x88200000 + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#if defined(CONFIG_TARGET_VERDIN_AM62_A53) +#define CONFIG_SPL_MAX_SIZE SZ_1M +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) +#else /* CONFIG_TARGET_VERDIN_AM62_A53 */ +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x3000 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location allocated for Device Manager data and some memory filled in by + * the boot ROM that we want to read out without any interference from the + * C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (0x43c3e000 -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR 0x43c3a7f0 +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#endif /* CONFIG_TARGET_VERDIN_AM62_A53 */ + +#define MEM_LAYOUT_ENV_SETTINGS \ + "fdt_addr_r=0x90200000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_comp_addr_r=0x80200000\0" \ + "kernel_comp_size=0x08000000\0" \ + "ramdisk_addr_r=0x90300000\0" \ + "scriptaddr=0x90280000\0" + +/* Enable Distro Boot */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include <config_distro_bootcmd.h> + +#define EXTRA_ENV_DFUARGS \ + DFU_ALT_INFO_EMMC \ + DFU_ALT_INFO_RAM + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + EXTRA_ENV_DFUARGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "boot_scripts=boot.scr\0" \ + "boot_script_dhcp=boot.scr\0" \ + "console=ttyS2\0" \ + "fdt_board=dev\0" \ + "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ + "consoleblank=0 earlycon=ns16550a,mmio32,0x02800000\0" \ + "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" + +/* Now for the remaining common defines */ +#include <configs/ti_armv7_common.h> + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#endif +#define CONFIG_SYS_MALLOC_LEN SZ_128M + +#endif /* __CONFIG_VERDIN_AM62_H */ diff --git a/include/misc.h b/include/misc.h index 79263ed480..d523b43c33 100644 --- a/include/misc.h +++ b/include/misc.h @@ -6,6 +6,8 @@ #ifndef _MISC_H_ #define _MISC_H_ +#include <dm/ofnode.h> + /** * misc_read() - Read the device to buffer, optional. * @dev: the device diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index c93946842a..6f6d759329 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -1691,7 +1691,7 @@ class Builder: term = threading.Thread(target=self.queue.join) term.setDaemon(True) term.start() - while term.isAlive(): + while term.is_alive(): term.join(100) # Wait until we have processed all output |