diff options
| -rw-r--r-- | arch/arm/dts/imx8mm-verdin.dts | 11 | ||||
| -rw-r--r-- | board/toradex/verdin-imx8mm/spl.c | 5 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index d8ccb2b9e5..033ef998c6 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -465,12 +465,6 @@ <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_se050_ena>; imx8mm-verdin { - pinctrl_ctrl_force_off_moci: forceoffgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */ - >; - }; - pinctrl_can1_int: can1intgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 @@ -723,6 +717,7 @@ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 >; }; @@ -739,6 +734,7 @@ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 >; }; @@ -755,6 +751,7 @@ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 >; }; @@ -849,7 +846,7 @@ pinctrl_wifi_ctrl: wifictrlgrp { fsl,pins = < MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* WIFI_WKUP_WLAN */ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ >; }; diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 463378b610..c2539f9738 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -68,6 +68,8 @@ struct i2c_pads_info i2c_pad_info1 = { #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | \ PAD_CTL_FSEL2) #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) +#define USDHC_RESET_PAD_CTRL (PAD_CTL_DSE1 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2 | PAD_CTL_PE) static iomux_v3_cfg_t const usdhc1_pads[] = { IMX8MM_PAD_SD1_CLK_USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -80,7 +82,8 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B | MUX_PAD_CTRL(USDHC_RESET_PAD_CTRL), + IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static iomux_v3_cfg_t const usdhc2_pads[] = { |