Add support for a bios-base device tree/flashmap setting

This setting specifies where the bios image described by the "flash" section
starts in the ROM. When the device tree is consumed by u-boot, this value is
added to the given offset of accesses to the flash so that it ends up in the
right place in the ROM. The binary fmap will reflect that address directly so
that tools like flashrom can use it without modification. By not modifying the
locations of the sections in the "flash" node of the device tree directly, we
can continue to share definitions between boards that have the same layout for
the BIOS image itself but who may be offset differently in the ROM. If not
present, a default value of 0 is used. Unmodified device trees will continue
to behave like they always have.

The name bios-base isn't perfect since on ARM there is no bios. Another
alternative firmware-base is also flawed because there are multiple firmwares
in the ROM on x86. Yet another option, flashmap-base, doesn't quite work either
because flashmap already has a very similarly named field which describes where
the image described by the flashmap appears in the physical address space.
Because bios-base fits the best on x86 and x86 is currently the only place it's
used, that's the name I went with.

BUG=chrome-os-partner:5844
TEST=Used this and other changes to compensate for the image offset and vboot
on stumpy. Vbooted on x86-alex. Built with vboot_test and vbexport_test built
in to verify that they still compile.

Change-Id: Ie727fc2db27f7d0db8ebf7ed2b98bc97052b4923
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://gerrit.chromium.org/gerrit/7239
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>

2 files changed, 27 insertions, 9 deletions

diff --git a/lib/chromeos/fdt_decode.c b/lib/chromeos/fdt_decode.c
index ace7fa3a87..bf63621a21 100644
--- a/lib/chromeos/fdt_decode.c
+++ b/lib/chromeos/fdt_decode.c
@@ -71,25 +71,31 @@ static int decode_fmap_entry(const void *blob, int offset, const char *base,
 	return 0;
 }
 
-static int decode_block_lba(const void *blob, int offset, const char *path,
+static int decode_int_property(const void *blob, int offset, const char *name,
 		uint64_t *out)
 {
 	int length;
 	uint32_t *property;
 
-	offset = relpath_offset(blob, offset, path);
-	if (offset < 0)
-		return offset;
-
-	property = (uint32_t *)fdt_getprop(blob, offset, "block-lba", &length);
-	if (!property) {
-		VBDEBUG(PREFIX "failed to load LBA '%s/block-lba'\n", path);
+	property = (uint32_t *)fdt_getprop(blob, offset, name, &length);
+	if (!property || length < 1) {
+		VBDEBUG(PREFIX "failed to load int %s\n", name);
 		return -FDT_ERR_MISSING;
 	}
 	*out = fdt32_to_cpu(*property);
 	return 0;
 }
 
+static int decode_block_lba(const void *blob, int offset, const char *path,
+		uint64_t *out)
+{
+	offset = relpath_offset(blob, offset, path);
+	if (offset < 0)
+		return offset;
+
+	return decode_int_property(blob, offset, "block-lba", out);
+}
+
 int decode_firmware_entry(const char *blob, int fmap_offset, const char *name,
 		struct fmap_firmware_entry *entry)
 {
@@ -115,6 +121,10 @@ int fdt_decode_twostop_fmap(const void *blob, struct twostop_fmap *config)
 		VBDEBUG(PREFIX "chromeos,flashmap node is missing\n");
 		return fmap_offset;
 	}
+	if (decode_int_property(blob, fmap_offset, "bios-base",
+			&config->firmware_base)) {
+		config->firmware_base = 0;
+	}
 	err = decode_firmware_entry(blob, fmap_offset, "rw-a",
 			&config->readwrite_a);
 	err |= decode_firmware_entry(blob, fmap_offset, "rw-b",
diff --git a/lib/chromeos/firmware_storage_spi.c b/lib/chromeos/firmware_storage_spi.c
index 26e01046db..e1a34c0cbc 100644
--- a/lib/chromeos/firmware_storage_spi.c
+++ b/lib/chromeos/firmware_storage_spi.c
@@ -11,6 +11,7 @@
 /* Implementation of firmware storage access interface for SPI */
 
 #include <common.h>
+#include <libfdt.h>
 #include <malloc.h>
 #include <spi_flash.h>
 #include <chromeos/common.h>
@@ -25,6 +26,8 @@
 # define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Check the right-exclusive range [offset:offset+*count_ptr), and adjust
  * value pointed by <count_ptr> to form a valid range when needed.
@@ -52,6 +55,8 @@ static int read_spi(firmware_storage_t *file, uint32_t offset, uint32_t count,
 {
 	struct spi_flash *flash = file->context;
 
+	offset += file->firmware_base;
+
 	if (border_check(flash, offset, count))
 		return -1;
 
@@ -108,6 +113,8 @@ static int write_spi(firmware_storage_t *file, uint32_t offset, uint32_t count,
 	uint32_t k, n;
 	int status, ret = -1;
 
+	offset += file->firmware_base;
+
 	/* We will erase <n> bytes starting from <k> */
 	k = offset;
 	n = count;
@@ -159,7 +166,7 @@ static int close_spi(firmware_storage_t *file)
 	return 0;
 }
 
-int firmware_storage_open_spi(firmware_storage_t *file)
+int firmware_storage_open_spi(firmware_storage_t *file, uint64_t firmware_base)
 {
 	const unsigned int bus = 0;
 	const unsigned int cs = 0;
@@ -172,6 +179,7 @@ int firmware_storage_open_spi(firmware_storage_t *file)
 		return -1;
 	}
 
+	file->firmware_base = firmware_base;
 	file->read = read_spi;
 	file->write = write_spi;
 	file->close = close_spi;