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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-08-22 16:16:26 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-08-22 16:16:26 +0200
commit2a1325206da5381292c2b268e248702c523cc927 (patch)
tree45d684a865eab51b0711d07782b1d8e8ae9d9932 /include/configs/tegra2-common.h
parent2f2f858faddd3cce54f7c64bc8fc8b596c1ddfaf (diff)
Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808
Diffstat (limited to 'include/configs/tegra2-common.h')
-rw-r--r--include/configs/tegra2-common.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 8396dc4d3b..d8f1eda7b3 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -107,7 +107,8 @@
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_TEGRA2_WARMBOOT
-#define TEGRA_LP0_ADDR 0x1C406000
+//ToDo: determine LP0 address dynamically
+#define TEGRA_LP0_ADDR 0x0C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
"lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " "
@@ -154,9 +155,9 @@
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 TEGRA_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
+/* Size queried at runtime by board_query_sdram_size() */
-#define CONFIG_SYS_TEXT_BASE 0x00E08000
+#define CONFIG_SYS_TEXT_BASE 0x00108000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define BCT_SDRAM_PARAMS_OFFSET (BCT_OFFSET + 0x88)