diff options
| author | Sudhakar Rajashekhara <sudhakar.raj@ti.com> | 2010-11-03 13:15:23 +0530 |
|---|---|---|
| committer | Sudhakar Rajashekhara <sudhakar.raj@ti.com> | 2010-11-03 13:15:23 +0530 |
| commit | eab9d7e640fd85ebdafb31e57255c8a21149c7a8 (patch) | |
| tree | 7ad22931f1eb5aea6061f9e867b60fbee38ea8bc /include/asm-arm/arch-davinci/hardware.h | |
| parent | 978955ff4a9771e888b3e99039513fc5f671c419 (diff) | |
da8xx/omap-l1: modifications for Logic PD Rev.3 AM18xx EVM2009.11-omapl138-201011030745
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will. When
GP0[11] is high, SD0 will work but NOR flash will not.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Diffstat (limited to 'include/asm-arm/arch-davinci/hardware.h')
| -rw-r--r-- | include/asm-arm/arch-davinci/hardware.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index a14845faf1..b4593cd61e 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -157,6 +157,10 @@ typedef volatile unsigned int * dv_reg_p; #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define CFGCHIP3 (DAVINCI_BOOTCFG_BASE + 0x188) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) |