diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-11-16 11:57:54 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2018-11-20 18:28:22 +0800 |
| commit | 71398b89a06fada6c53a31e17101c3cc3a47d049 (patch) | |
| tree | 331534b8ec660c7bff7877209774e8ecf72e3140 /drivers | |
| parent | 42d8eedc167cfba7f7363c56c176b7f7057e4a0e (diff) | |
MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip
Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit 566b798213ab9690966f163de2765acdbfe647a7)
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/imx8m/lpddr4_init.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/ddr/imx8m/lpddr4_init.c b/drivers/ddr/imx8m/lpddr4_init.c index ee6a8dc686..d6422b9b0a 100644 --- a/drivers/ddr/imx8m/lpddr4_init.c +++ b/drivers/ddr/imx8m/lpddr4_init.c @@ -50,7 +50,10 @@ void ddr_init(struct dram_timing_info *dram_timing) reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ debug("DDRINFO: cfg clk\n"); - dram_pll_init(DRAM_PLL_OUT_750M); + if (is_imx8mq()) + dram_pll_init(DRAM_PLL_OUT_800M); + else + dram_pll_init(DRAM_PLL_OUT_750M); /* * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, |