diff options
| author | Breno Lima <breno.lima@nxp.com> | 2018-09-20 19:03:28 -0300 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-10-10 02:00:31 -0700 |
| commit | 16495f0464b3a4420ca8e7da3e7e3eb3c66ec447 (patch) | |
| tree | 250f632a5812d7117913d02138be2e85b19efe16 /doc/imx/common/README.imx5 | |
| parent | 876ec321565507b84b765813f0bac23912589440 (diff) | |
MLK-19722-5 doc: imx: Reorganize i.MX SoC common documentation
The following documents describe device details according to the
i.MX family:
- README.imx25
- README.imx27
- README.imx5
- README.imx6
- README.mxs
Move all device common related document to doc/imx/common for a better
directory structure.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
(cherry picked from commit 2098487e28507e64f54ff0ce8d3826ff6e2936c0)
Diffstat (limited to 'doc/imx/common/README.imx5')
| -rw-r--r-- | doc/imx/common/README.imx5 | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/doc/imx/common/README.imx5 b/doc/imx/common/README.imx5 new file mode 100644 index 0000000000..ea0e144ced --- /dev/null +++ b/doc/imx/common/README.imx5 @@ -0,0 +1,40 @@ +U-Boot for Freescale i.MX5x + +This file contains information for the port of U-Boot to the Freescale +i.MX5x SoCs. + +1. CONFIGURATION OPTIONS/SETTINGS +--------------------------------- + +1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. + This option should be enabled by all boards using the i.MX51 silicon + version up until (including) 3.0 running at 800MHz. + The PLL's in the i.MX51 processor can go out of lock due to a metastable + condition in an analog flip-flop when used at high frequencies. + This workaround implements an undocumented feature in the PLL (dither + mode), which causes the effect of this failure to be much lower (in terms + of frequency deviation), avoiding system failure, or at least decreasing + the likelihood of system failure. + +1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. + This option should be enabled for boards having a SYS_ON_OFF_CTL signal + connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the + reference designs. + +2. CONVENTIONS FOR FUSE ASSIGNMENTS +----------------------------------- + +2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the + natural MAC byte order (i.e. MSB first). + + This is an example how to program an example MAC address 01:23:45:67:89:ab + into the eFuses. Assure that the programming voltage is available and then + execute: + + => fuse prog -y 1 9 01 23 45 67 89 ab + + After programming a MAC address, consider locking the MAC fuses. This is + done by programming the MAC_ADDR_LOCK fuse, which is bit 4 of word 0 in + bank 1: + + => fuse prog -y 1 0 10 |