diff options
| author | Zhang Jiejing <jiejing.zhang@freescale.com> | 2012-12-11 15:23:46 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-12-12 19:51:59 +0800 |
| commit | 956ae96db2cdcc6e17f0b28aa97484717957b4c8 (patch) | |
| tree | c9253a5325e8db63b4e7abdb5635d8415078f4df /cpu/arm_cortexa8/mx6/generic.c | |
| parent | 658971fe22d1beb640ede108419d75b2919a2d80 (diff) | |
ENGR00235817 mx6: use SNVS LPGPR register to store boot mode value.
After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Diffstat (limited to 'cpu/arm_cortexa8/mx6/generic.c')
| -rw-r--r-- | cpu/arm_cortexa8/mx6/generic.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index c3ce97effd..2ee8e1b928 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -1146,14 +1146,14 @@ int check_and_clean_recovery_flag(void) { int flag_set = 0; u32 reg; - reg = readl(SRC_BASE_ADDR + SRC_GPR10); + reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); flag_set = !!(reg & ANDROID_RECOVERY_BOOT); /* clean it in case looping infinite here.... */ if (flag_set) { reg &= ~ANDROID_RECOVERY_BOOT; - writel(reg, SRC_BASE_ADDR + SRC_GPR10); + writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); } return flag_set; @@ -1168,14 +1168,15 @@ int fastboot_check_and_clean_flag(void) { int flag_set = 0; u32 reg; - reg = readl(SRC_BASE_ADDR + SRC_GPR10); + + reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR); flag_set = !!(reg & ANDROID_FASTBOOT_BOOT); /* clean it in case looping infinite here.... */ if (flag_set) { reg &= ~ANDROID_FASTBOOT_BOOT; - writel(reg, SRC_BASE_ADDR + SRC_GPR10); + writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR); } return flag_set; |