summaryrefslogtreecommitdiff
path: root/common
diff options
context:
space:
mode:
authorSimon Glass <sjg@chromium.org>2011-11-29 16:35:54 -0800
committerGerrit <chrome-bot@google.com>2011-12-12 10:23:42 -0800
commit6f22f8c501202a48d386465d2808afd1bdc6825e (patch)
tree36401c29a0f529d11d03d8aef58de10524c7c097 /common
parentceb5dac413f6d1c0b624ee9466244b5a5bd6091a (diff)
tegra: Remove CONFIG_SYS_PLLP_BASE_IS_408MHZ
This setting is now in the fdt, so remove the CONFIG item. BUG=chromium-os:23496 TEST=build and boot on Seaboard, T33, Kaen Change-Id: I336a6cc2140c725fdda85330efe617f82f205a90 Reviewed-on: https://gerrit.chromium.org/gerrit/12250 Commit-Ready: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'common')
-rw-r--r--common/fdt_decode.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/common/fdt_decode.c b/common/fdt_decode.c
index b983710bcd..4f1eb59b2c 100644
--- a/common/fdt_decode.c
+++ b/common/fdt_decode.c
@@ -306,9 +306,7 @@ int fdt_decode_uart_console(const void *blob, struct fdt_uart *uart,
uart->silent = fdt_decode_get_config_int(blob, "silent_console", 0);
uart->io_mapped = get_int(blob, node, "io-mapped", 0);
uart->compat = fdt_decode_lookup(blob, node);
-#if defined(CONFIG_TEGRA3) && !defined(CONFIG_SYS_PLLP_BASE_IS_408MHZ)
- uart->clock_freq = 216000000;
-#endif
+
/* Calculate divisor if required */
if ((uart->divisor == -1) && (uart->clock_freq != -1))
fdt_decode_uart_calc_divisor(uart);