diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-03-20 11:16:09 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-03-20 11:16:09 +0100 |
| commit | b9a3c3a53a146883cda13c5f5869b0a8a07f9cb4 (patch) | |
| tree | 0981e25138a456c954401df5599db89d0140f1c6 /arch | |
| parent | 4a803df96dbdcbee38d2cdccf3da0654f5587327 (diff) | |
colibri-imx8qxp: fix ethernet functionality
Fix Ethernet functionality. The FEC clock on i.MX 8X really has an
additional by 2 divider plus our design requires the ENET0_RCLK50M_OUT
on the ENET0_RGMII_TXC pin to be turned on for the Micrel PHY.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-imx8qxp-colibri.dts | 6 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8/clock.c | 8 |
2 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index 0d331f7f1d..6195122a26 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -70,11 +70,11 @@ pinctrl_fec1: fec1grp { fsl,pins = < - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 - SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index dff2d405fe..53236c980e 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -124,7 +124,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk) u32 imx_get_fecclk(void) { +#ifdef CONFIG_TARGET_COLIBRI_IMX8QXP + return mxc_get_clock(MXC_FEC_CLK)/2; +#else return mxc_get_clock(MXC_FEC_CLK); +#endif } static struct imx_i2c_map *get_i2c_desc(unsigned i2c_num) @@ -432,7 +436,11 @@ void init_clk_fec(int index) /* Configure GPR regisers */ sc_misc_set_control(ipc, enet[index], SC_C_TXCLK, 0); sc_misc_set_control(ipc, enet[index], SC_C_CLKDIV, 1); /* Enable divclk */ +#ifdef CONFIG_TARGET_COLIBRI_IMX8QXP + sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 0); +#else sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_50, 1); +#endif sc_misc_set_control(ipc, enet[index], SC_C_DISABLE_125, 1); sc_misc_set_control(ipc, enet[index], SC_C_SEL_125, 0); sc_misc_set_control(ipc, enet[index], SC_C_IPG_STOP, 0); |