diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-06-25 19:19:09 +0800 |
|---|---|---|
| committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-06-26 11:30:24 +0800 |
| commit | 8a204312abad7913f9b2209a71bef81853647b21 (patch) | |
| tree | 47d1e2f159f3fe83d568f7e11eca25129cd24756 /arch | |
| parent | eae62ae8de1893f7cf08e276ab841d3f99245603 (diff) | |
arm: socfpga: misc_s10: Fix EMAC register address calculation
Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.
This fixes write to invalid address.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/misc_s10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index ccff78a230..670bfa1a31 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -68,7 +68,7 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) return -EINVAL; clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 + - gmac_index, + (gmac_index * sizeof(u32)), SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); return 0; |