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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-08-22 16:16:26 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-08-22 16:16:26 +0200 |
| commit | 2a1325206da5381292c2b268e248702c523cc927 (patch) | |
| tree | 45d684a865eab51b0711d07782b1d8e8ae9d9932 /arch/arm/cpu/armv7/tegra-common/display.c | |
| parent | 2f2f858faddd3cce54f7c64bc8fc8b596c1ddfaf (diff) | |
Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808
Diffstat (limited to 'arch/arm/cpu/armv7/tegra-common/display.c')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/display.c b/arch/arm/cpu/armv7/tegra-common/display.c index 2f12084447..55ea13e128 100644 --- a/arch/arm/cpu/armv7/tegra-common/display.c +++ b/arch/arm/cpu/armv7/tegra-common/display.c @@ -117,7 +117,7 @@ static int update_display_mode(struct dc_disp_reg *disp, /* * The pixel clock divider is in 7.1 format (where the bottom bit * represents 0.5). Here we calculate the divider needed to get from - * the display clock (typically 600MHz for tegra2 and 216MHZ + * the display clock (typically 600MHz for tegra2 and 216MHz * for tegra3) to the pixel clock. We round up or down as requried. */ #if defined(CONFIG_TEGRA2) |