diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-11-03 15:35:02 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-11-13 15:54:37 -0500 |
| commit | 4d0fec0e69189bd81c09909fc4eb742c63d5d7ee (patch) | |
| tree | aa0689931712615a5c9d2292f7383e1d404816ea | |
| parent | 8b01ebd8128821febd84ee0f413c16d6339678d6 (diff) | |
ARM: k2g: Update PLL Multiplier and divider values
Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18
[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | board/ti/ks2_evm/board_k2g.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 8f16845d8e..40edbaa33f 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -66,7 +66,7 @@ static struct pll_init_data tetris_pll_config[NUM_SPDS] = { static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; -static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; +static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16}; struct pll_init_data *get_pll_init_data(int pll) { |