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authorMarek Vasut <marex@denx.de>2014-09-21 13:57:40 +0200
committerMarek Vasut <marex@denx.de>2014-10-06 17:46:51 +0200
commit4ab333b765db5cd00b297b4c0e3cd3af5fe320fc (patch)
tree937b9b1834de9603527c73523af8e76c9d24c2a3
parent97ce274d97e9c1796d58ae34aadcbc10293cccd7 (diff)
arm: socfpga: Move cache_enable to CPU code
Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
-rw-r--r--arch/arm/cpu/armv7/socfpga/misc.c10
-rw-r--r--board/altera/socfpga/socfpga_cyclone5.c3
2 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 76186c511b..7f9d7f0133 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -33,6 +33,16 @@ int dram_init(void)
return 0;
}
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
/*
* DesignWare Ethernet initialization
*/
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 6b982778be..0f81d899a6 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -34,9 +34,6 @@ int board_early_init_f(void)
*/
int board_init(void)
{
- icache_enable();
- dcache_enable();
-
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;