arm: dts: k3-am62a-lp4: update to latest output from the emif tool

After a little debugging on the am62px some of these values will need to
be changed. Update to these new values to improve stability at higher IO
voltages.

Signed-off-by: Bryan Brattlof <bb@ti.com>

1 files changed, 22 insertions, 20 deletions

diff --git a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
index 9f50d7eae6..d6d8736dde 100644
--- a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
+++ b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01
- * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time)
+ * AM62Ax SysConfig DDR Subsystem Register Configuration Tool v0.10.02
+ * Thu Jan 25 2024 10:38:48 GMT-0600 (Central Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1866MHz
  * Density (per channel): 8Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_1 933000000
 #define DDRSS_PLL_FREQUENCY_2 933000000
+#define DDRSS_SDRAM_IDX 16
+#define DDRSS_REGION_IDX 17
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -402,10 +404,10 @@
 #define DDRSS_CTL_386_DATA 0x01090903
 #define DDRSS_CTL_387_DATA 0x05020201
 #define DDRSS_CTL_388_DATA 0x0E081B1B
-#define DDRSS_CTL_389_DATA 0x0008030E
-#define DDRSS_CTL_390_DATA 0x0B12030E
-#define DDRSS_CTL_391_DATA 0x0B120314
-#define DDRSS_CTL_392_DATA 0x12120814
+#define DDRSS_CTL_389_DATA 0x0008040E
+#define DDRSS_CTL_390_DATA 0x0B120406
+#define DDRSS_CTL_391_DATA 0x0B120406
+#define DDRSS_CTL_392_DATA 0x12120806
 #define DDRSS_CTL_393_DATA 0x01000000
 #define DDRSS_CTL_394_DATA 0x07030701
 #define DDRSS_CTL_395_DATA 0x04000103
@@ -417,8 +419,8 @@
 #define DDRSS_CTL_401_DATA 0x00000200
 #define DDRSS_CTL_402_DATA 0x00000693
 #define DDRSS_CTL_403_DATA 0x00000E9C
-#define DDRSS_CTL_404_DATA 0x03050202
-#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x37200404
 #define DDRSS_CTL_406_DATA 0x000038C8
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
@@ -426,8 +428,8 @@
 #define DDRSS_CTL_410_DATA 0x00000200
 #define DDRSS_CTL_411_DATA 0x0000FF84
 #define DDRSS_CTL_412_DATA 0x000237D0
-#define DDRSS_CTL_413_DATA 0x111F0402
-#define DDRSS_CTL_414_DATA 0x37200C0D
+#define DDRSS_CTL_413_DATA 0x111A0402
+#define DDRSS_CTL_414_DATA 0x37200C09
 #define DDRSS_CTL_415_DATA 0x000038C8
 #define DDRSS_CTL_416_DATA 0x00000200
 #define DDRSS_CTL_417_DATA 0x00000200
@@ -435,8 +437,8 @@
 #define DDRSS_CTL_419_DATA 0x00000200
 #define DDRSS_CTL_420_DATA 0x0000FF84
 #define DDRSS_CTL_421_DATA 0x000237D0
-#define DDRSS_CTL_422_DATA 0x111F0402
-#define DDRSS_CTL_423_DATA 0x00200C0D
+#define DDRSS_CTL_422_DATA 0x111A0402
+#define DDRSS_CTL_423_DATA 0x00200C09
 #define DDRSS_CTL_424_DATA 0x00000000
 #define DDRSS_CTL_425_DATA 0x02000A00
 #define DDRSS_CTL_426_DATA 0x00050003
@@ -964,7 +966,7 @@
 #define DDRSS_PHY_89_DATA 0x00100010
 #define DDRSS_PHY_90_DATA 0x00100010
 #define DDRSS_PHY_91_DATA 0x00100010
-#define DDRSS_PHY_92_DATA 0x02040010
+#define DDRSS_PHY_92_DATA 0x02000010
 #define DDRSS_PHY_93_DATA 0x00000005
 #define DDRSS_PHY_94_DATA 0x51516042
 #define DDRSS_PHY_95_DATA 0x31C06000
@@ -1220,7 +1222,7 @@
 #define DDRSS_PHY_345_DATA 0x00100010
 #define DDRSS_PHY_346_DATA 0x00100010
 #define DDRSS_PHY_347_DATA 0x00100010
-#define DDRSS_PHY_348_DATA 0x02040010
+#define DDRSS_PHY_348_DATA 0x02000010
 #define DDRSS_PHY_349_DATA 0x00000005
 #define DDRSS_PHY_350_DATA 0x51516042
 #define DDRSS_PHY_351_DATA 0x31C06000
@@ -1476,7 +1478,7 @@
 #define DDRSS_PHY_601_DATA 0x00100010
 #define DDRSS_PHY_602_DATA 0x00100010
 #define DDRSS_PHY_603_DATA 0x00100010
-#define DDRSS_PHY_604_DATA 0x02040010
+#define DDRSS_PHY_604_DATA 0x02000010
 #define DDRSS_PHY_605_DATA 0x00000005
 #define DDRSS_PHY_606_DATA 0x51516042
 #define DDRSS_PHY_607_DATA 0x31C06000
@@ -1732,7 +1734,7 @@
 #define DDRSS_PHY_857_DATA 0x00100010
 #define DDRSS_PHY_858_DATA 0x00100010
 #define DDRSS_PHY_859_DATA 0x00100010
-#define DDRSS_PHY_860_DATA 0x02040010
+#define DDRSS_PHY_860_DATA 0x02000010
 #define DDRSS_PHY_861_DATA 0x00000005
 #define DDRSS_PHY_862_DATA 0x51516042
 #define DDRSS_PHY_863_DATA 0x31C06000
@@ -2699,7 +2701,7 @@
 #define DDRSS_PHY_1824_DATA 0x0F0F0804
 #define DDRSS_PHY_1825_DATA 0x00800120
 #define DDRSS_PHY_1826_DATA 0x00041B42
-#define DDRSS_PHY_1827_DATA 0x00005201
+#define DDRSS_PHY_1827_DATA 0x00004201
 #define DDRSS_PHY_1828_DATA 0x00000000
 #define DDRSS_PHY_1829_DATA 0x00000000
 #define DDRSS_PHY_1830_DATA 0x00000000
@@ -2760,7 +2762,7 @@
 #define DDRSS_PHY_1885_DATA 0x00000002
 #define DDRSS_PHY_1886_DATA 0x00000000
 #define DDRSS_PHY_1887_DATA 0x00000000
-#define DDRSS_PHY_1888_DATA 0x00000AC4
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
 #define DDRSS_PHY_1889_DATA 0x04000004
 #define DDRSS_PHY_1890_DATA 0x00000000
 #define DDRSS_PHY_1891_DATA 0x00001142
@@ -2789,10 +2791,10 @@
 #define DDRSS_PHY_1914_DATA 0x0089FF00
 #define DDRSS_PHY_1915_DATA 0x000C3F11
 #define DDRSS_PHY_1916_DATA 0x01990000
-#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1917_DATA 0x000C3F91
 #define DDRSS_PHY_1918_DATA 0x01990000
 #define DDRSS_PHY_1919_DATA 0x3F0DFF11
 #define DDRSS_PHY_1920_DATA 0x00EF0000
 #define DDRSS_PHY_1921_DATA 0x00018011
 #define DDRSS_PHY_1922_DATA 0x0089FF00
-#define DDRSS_PHY_1923_DATA 0x20040004
+#define DDRSS_PHY_1923_DATA 0x20040006