diff options
| author | Ravi Gunasekaran <r-gunasekaran@ti.com> | 2024-02-14 16:22:00 +0530 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2024-03-21 14:26:33 +0000 |
| commit | 607d1f04685773b04885cb7989f9df2a6a71d54d (patch) | |
| tree | ce6a2cc5b32669ed517499ed1fbfa221d0a28813 | |
| parent | ef0e791936ad7b5306fd2dca3fba69fe459b1afd (diff) | |
arm: dts: k3-j722s: Add support for SERDES0
Add SERDES0 and its wrapper description to support USB3
and SGMII interfaces.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-j722s.dtsi | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j722s.dtsi b/arch/arm/dts/k3-j722s.dtsi index a635d547e7..d689845418 100644 --- a/arch/arm/dts/k3-j722s.dtsi +++ b/arch/arm/dts/k3-j722s.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> +#include <dt-bindings/phy/phy-ti.h> #include "k3-am62p5.dtsi" @@ -73,6 +74,50 @@ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; }; + + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + + assigned-clocks = <&k3_clks 279 1>; + assigned-clock-parents = <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; }; /* Main domain overrides */ @@ -85,6 +130,15 @@ ti,interrupt-ranges = <0 237 8>; }; +&main_conf { + serdes0_ln_ctrl: mux-controller@4080 { + compatible = "mmio-mux"; + reg = <0x4080 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ + }; +}; + &oc_sram { reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>; |