arm: dts: k3-am62p-lp4: update to latest DDR configs

After a little bit of debugging and characterization at different IO
voltages, some of these values will need to change. Update to these
latest settings to improve stability at higher IO voltages.

Signed-off-by: Bryan Brattlof <bb@ti.com>

1 files changed, 65 insertions, 63 deletions

diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
index b5fdba46a0..f664352015 100644
--- a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
+++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.09.10
- * Wed Aug 23 2023 17:48:42 GMT-0500 (Central Daylight Time)
+ * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02
+ * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1600MHz
  * Density (per channel): 16Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_1 800000000
 #define DDRSS_PLL_FREQUENCY_2 800000000
+#define DDRSS_SDRAM_IDX 17
+#define DDRSS_REGION_IDX 17
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -55,9 +57,9 @@
 #define DDRSS_CTL_39_DATA 0x00000000
 #define DDRSS_CTL_40_DATA 0x0000040C
 #define DDRSS_CTL_41_DATA 0x00000000
-#define DDRSS_CTL_42_DATA 0x00001040
+#define DDRSS_CTL_42_DATA 0x00000E38
 #define DDRSS_CTL_43_DATA 0x00000000
-#define DDRSS_CTL_44_DATA 0x00001040
+#define DDRSS_CTL_44_DATA 0x00000E38
 #define DDRSS_CTL_45_DATA 0x00000000
 #define DDRSS_CTL_46_DATA 0x05000804
 #define DDRSS_CTL_47_DATA 0x00000700
@@ -224,20 +226,20 @@
 #define DDRSS_CTL_208_DATA 0x00000004
 #define DDRSS_CTL_209_DATA 0x00000000
 #define DDRSS_CTL_210_DATA 0x00000000
-#define DDRSS_CTL_211_DATA 0x00000064
-#define DDRSS_CTL_212_DATA 0x00000036
+#define DDRSS_CTL_211_DATA 0x00000054
+#define DDRSS_CTL_212_DATA 0x0000002D
 #define DDRSS_CTL_213_DATA 0x00000000
-#define DDRSS_CTL_214_DATA 0x00000064
-#define DDRSS_CTL_215_DATA 0x00000036
+#define DDRSS_CTL_214_DATA 0x00000054
+#define DDRSS_CTL_215_DATA 0x0000002D
 #define DDRSS_CTL_216_DATA 0x00000000
 #define DDRSS_CTL_217_DATA 0x00000004
 #define DDRSS_CTL_218_DATA 0x00000000
 #define DDRSS_CTL_219_DATA 0x00000000
-#define DDRSS_CTL_220_DATA 0x00000064
-#define DDRSS_CTL_221_DATA 0x00000036
+#define DDRSS_CTL_220_DATA 0x00000054
+#define DDRSS_CTL_221_DATA 0x0000002D
 #define DDRSS_CTL_222_DATA 0x00000000
-#define DDRSS_CTL_223_DATA 0x00000064
-#define DDRSS_CTL_224_DATA 0x00000036
+#define DDRSS_CTL_223_DATA 0x00000054
+#define DDRSS_CTL_224_DATA 0x0000002D
 #define DDRSS_CTL_225_DATA 0x00000000
 #define DDRSS_CTL_226_DATA 0x00000000
 #define DDRSS_CTL_227_DATA 0x00000029
@@ -399,13 +401,13 @@
 #define DDRSS_CTL_383_DATA 0x01000101
 #define DDRSS_CTL_384_DATA 0x01010001
 #define DDRSS_CTL_385_DATA 0x00010101
-#define DDRSS_CTL_386_DATA 0x010A0A03
+#define DDRSS_CTL_386_DATA 0x01080803
 #define DDRSS_CTL_387_DATA 0x05020201
-#define DDRSS_CTL_388_DATA 0x0C081C1C
-#define DDRSS_CTL_389_DATA 0x0008030C
-#define DDRSS_CTL_390_DATA 0x0B12030E
-#define DDRSS_CTL_391_DATA 0x0B120315
-#define DDRSS_CTL_392_DATA 0x12120815
+#define DDRSS_CTL_388_DATA 0x0C081818
+#define DDRSS_CTL_389_DATA 0x0008040C
+#define DDRSS_CTL_390_DATA 0x0B100406
+#define DDRSS_CTL_391_DATA 0x0B100406
+#define DDRSS_CTL_392_DATA 0x10100806
 #define DDRSS_CTL_393_DATA 0x01000000
 #define DDRSS_CTL_394_DATA 0x06030601
 #define DDRSS_CTL_395_DATA 0x04000103
@@ -417,8 +419,8 @@
 #define DDRSS_CTL_401_DATA 0x00000200
 #define DDRSS_CTL_402_DATA 0x00000693
 #define DDRSS_CTL_403_DATA 0x00000E9C
-#define DDRSS_CTL_404_DATA 0x03050202
-#define DDRSS_CTL_405_DATA 0x32200201
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x32200404
 #define DDRSS_CTL_406_DATA 0x000030B0
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
@@ -426,8 +428,8 @@
 #define DDRSS_CTL_410_DATA 0x00000200
 #define DDRSS_CTL_411_DATA 0x0000DB18
 #define DDRSS_CTL_412_DATA 0x0001E6E0
-#define DDRSS_CTL_413_DATA 0x131F0402
-#define DDRSS_CTL_414_DATA 0x32200C0D
+#define DDRSS_CTL_413_DATA 0x0F160402
+#define DDRSS_CTL_414_DATA 0x32200A07
 #define DDRSS_CTL_415_DATA 0x000030B0
 #define DDRSS_CTL_416_DATA 0x00000200
 #define DDRSS_CTL_417_DATA 0x00000200
@@ -435,8 +437,8 @@
 #define DDRSS_CTL_419_DATA 0x00000200
 #define DDRSS_CTL_420_DATA 0x0000DB18
 #define DDRSS_CTL_421_DATA 0x0001E6E0
-#define DDRSS_CTL_422_DATA 0x131F0402
-#define DDRSS_CTL_423_DATA 0x00200C0D
+#define DDRSS_CTL_422_DATA 0x0F160402
+#define DDRSS_CTL_423_DATA 0x00200A07
 #define DDRSS_CTL_424_DATA 0x00000000
 #define DDRSS_CTL_425_DATA 0x02000A00
 #define DDRSS_CTL_426_DATA 0x00050003
@@ -447,7 +449,7 @@
 #define DDRSS_CTL_431_DATA 0x02000201
 #define DDRSS_CTL_432_DATA 0x02010000
 #define DDRSS_CTL_433_DATA 0x06000200
-#define DDRSS_CTL_434_DATA 0x00002222
+#define DDRSS_CTL_434_DATA 0x00001E1E
 #define DDRSS_PI_0_DATA 0x00000B00
 #define DDRSS_PI_1_DATA 0x00000000
 #define DDRSS_PI_2_DATA 0x00000000
@@ -628,13 +630,13 @@
 #define DDRSS_PI_177_DATA 0x00F000F0
 #define DDRSS_PI_178_DATA 0x00202001
 #define DDRSS_PI_179_DATA 0x00000034
-#define DDRSS_PI_180_DATA 0x0000005B
-#define DDRSS_PI_181_DATA 0x0002005B
+#define DDRSS_PI_180_DATA 0x00000057
+#define DDRSS_PI_181_DATA 0x00020057
 #define DDRSS_PI_182_DATA 0x02000200
 #define DDRSS_PI_183_DATA 0x00000004
-#define DDRSS_PI_184_DATA 0x0000100C
-#define DDRSS_PI_185_DATA 0x00104000
-#define DDRSS_PI_186_DATA 0x00400000
+#define DDRSS_PI_184_DATA 0x00000E0C
+#define DDRSS_PI_185_DATA 0x000E3800
+#define DDRSS_PI_186_DATA 0x00380000
 #define DDRSS_PI_187_DATA 0x00000013
 #define DDRSS_PI_188_DATA 0x000000BB
 #define DDRSS_PI_189_DATA 0x00000260
@@ -647,15 +649,15 @@
 #define DDRSS_PI_196_DATA 0x01000100
 #define DDRSS_PI_197_DATA 0x00000100
 #define DDRSS_PI_198_DATA 0x00000000
-#define DDRSS_PI_199_DATA 0x050A0A03
-#define DDRSS_PI_200_DATA 0x01011C1C
+#define DDRSS_PI_199_DATA 0x05080803
+#define DDRSS_PI_200_DATA 0x01011818
 #define DDRSS_PI_201_DATA 0x01010101
 #define DDRSS_PI_202_DATA 0x000C0C0A
 #define DDRSS_PI_203_DATA 0x00000000
 #define DDRSS_PI_204_DATA 0x00000000
 #define DDRSS_PI_205_DATA 0x04000000
-#define DDRSS_PI_206_DATA 0x0C021414
-#define DDRSS_PI_207_DATA 0x0404020C
+#define DDRSS_PI_206_DATA 0x0A021010
+#define DDRSS_PI_207_DATA 0x0404020A
 #define DDRSS_PI_208_DATA 0x00090031
 #define DDRSS_PI_209_DATA 0x00190041
 #define DDRSS_PI_210_DATA 0x00190041
@@ -683,14 +685,14 @@
 #define DDRSS_PI_232_DATA 0x00000190
 #define DDRSS_PI_233_DATA 0x00001900
 #define DDRSS_PI_234_DATA 0x32000056
-#define DDRSS_PI_235_DATA 0x06000301
-#define DDRSS_PI_236_DATA 0x00250204
-#define DDRSS_PI_237_DATA 0x3212005C
-#define DDRSS_PI_238_DATA 0x17000301
-#define DDRSS_PI_239_DATA 0x00250C14
-#define DDRSS_PI_240_DATA 0x3212005C
-#define DDRSS_PI_241_DATA 0x17000301
-#define DDRSS_PI_242_DATA 0x00000C14
+#define DDRSS_PI_235_DATA 0x06000101
+#define DDRSS_PI_236_DATA 0x00230204
+#define DDRSS_PI_237_DATA 0x3212005A
+#define DDRSS_PI_238_DATA 0x13000101
+#define DDRSS_PI_239_DATA 0x00230A10
+#define DDRSS_PI_240_DATA 0x3212005A
+#define DDRSS_PI_241_DATA 0x13000101
+#define DDRSS_PI_242_DATA 0x00000A10
 #define DDRSS_PI_243_DATA 0x05030900
 #define DDRSS_PI_244_DATA 0x00040900
 #define DDRSS_PI_245_DATA 0x0000062B
@@ -785,16 +787,16 @@
 #define DDRSS_PI_334_DATA 0x00000000
 #define DDRSS_PI_335_DATA 0x20002B27
 #define DDRSS_PI_336_DATA 0x00000000
-#define DDRSS_PI_337_DATA 0x00000064
-#define DDRSS_PI_338_DATA 0x00000036
+#define DDRSS_PI_337_DATA 0x00000054
+#define DDRSS_PI_338_DATA 0x0000002D
 #define DDRSS_PI_339_DATA 0x000000A9
 #define DDRSS_PI_340_DATA 0x00000000
 #define DDRSS_PI_341_DATA 0x00000000
 #define DDRSS_PI_342_DATA 0x35000000
 #define DDRSS_PI_343_DATA 0x20152B27
 #define DDRSS_PI_344_DATA 0x00000000
-#define DDRSS_PI_345_DATA 0x00000064
-#define DDRSS_PI_346_DATA 0x00000036
+#define DDRSS_PI_345_DATA 0x00000054
+#define DDRSS_PI_346_DATA 0x0000002D
 #define DDRSS_PI_347_DATA 0x000000A9
 #define DDRSS_PI_348_DATA 0x00000000
 #define DDRSS_PI_349_DATA 0x00000000
@@ -809,16 +811,16 @@
 #define DDRSS_PI_358_DATA 0x00000000
 #define DDRSS_PI_359_DATA 0x20002B27
 #define DDRSS_PI_360_DATA 0x00000000
-#define DDRSS_PI_361_DATA 0x00000064
-#define DDRSS_PI_362_DATA 0x00000036
+#define DDRSS_PI_361_DATA 0x00000054
+#define DDRSS_PI_362_DATA 0x0000002D
 #define DDRSS_PI_363_DATA 0x000000A9
 #define DDRSS_PI_364_DATA 0x00000000
 #define DDRSS_PI_365_DATA 0x00000000
 #define DDRSS_PI_366_DATA 0x35000000
 #define DDRSS_PI_367_DATA 0x20152B27
 #define DDRSS_PI_368_DATA 0x00000000
-#define DDRSS_PI_369_DATA 0x00000064
-#define DDRSS_PI_370_DATA 0x00000036
+#define DDRSS_PI_369_DATA 0x00000054
+#define DDRSS_PI_370_DATA 0x0000002D
 #define DDRSS_PI_371_DATA 0x000000A9
 #define DDRSS_PI_372_DATA 0x00000000
 #define DDRSS_PI_373_DATA 0x00000000
@@ -833,16 +835,16 @@
 #define DDRSS_PI_382_DATA 0x00000000
 #define DDRSS_PI_383_DATA 0x20002B27
 #define DDRSS_PI_384_DATA 0x00000000
-#define DDRSS_PI_385_DATA 0x00000064
-#define DDRSS_PI_386_DATA 0x00000036
+#define DDRSS_PI_385_DATA 0x00000054
+#define DDRSS_PI_386_DATA 0x0000002D
 #define DDRSS_PI_387_DATA 0x000000A9
 #define DDRSS_PI_388_DATA 0x00000000
 #define DDRSS_PI_389_DATA 0x00000000
 #define DDRSS_PI_390_DATA 0x35000000
 #define DDRSS_PI_391_DATA 0x20152B27
 #define DDRSS_PI_392_DATA 0x00000000
-#define DDRSS_PI_393_DATA 0x00000064
-#define DDRSS_PI_394_DATA 0x00000036
+#define DDRSS_PI_393_DATA 0x00000054
+#define DDRSS_PI_394_DATA 0x0000002D
 #define DDRSS_PI_395_DATA 0x000000A9
 #define DDRSS_PI_396_DATA 0x00000000
 #define DDRSS_PI_397_DATA 0x00000000
@@ -857,16 +859,16 @@
 #define DDRSS_PI_406_DATA 0x00000000
 #define DDRSS_PI_407_DATA 0x20002B27
 #define DDRSS_PI_408_DATA 0x00000000
-#define DDRSS_PI_409_DATA 0x00000064
-#define DDRSS_PI_410_DATA 0x00000036
+#define DDRSS_PI_409_DATA 0x00000054
+#define DDRSS_PI_410_DATA 0x0000002D
 #define DDRSS_PI_411_DATA 0x000000A9
 #define DDRSS_PI_412_DATA 0x00000000
 #define DDRSS_PI_413_DATA 0x00000000
 #define DDRSS_PI_414_DATA 0x35000000
 #define DDRSS_PI_415_DATA 0x20152B27
 #define DDRSS_PI_416_DATA 0x00000000
-#define DDRSS_PI_417_DATA 0x00000064
-#define DDRSS_PI_418_DATA 0x00000036
+#define DDRSS_PI_417_DATA 0x00000054
+#define DDRSS_PI_418_DATA 0x0000002D
 #define DDRSS_PI_419_DATA 0x000000A9
 #define DDRSS_PI_420_DATA 0x00000000
 #define DDRSS_PI_421_DATA 0x00000000
@@ -952,7 +954,7 @@
 #define DDRSS_PHY_77_DATA 0x00000401
 #define DDRSS_PHY_78_DATA 0x00000000
 #define DDRSS_PHY_79_DATA 0x01CC0B01
-#define DDRSS_PHY_80_DATA 0x1003CC0C
+#define DDRSS_PHY_80_DATA 0x1003CC0B
 #define DDRSS_PHY_81_DATA 0x20000140
 #define DDRSS_PHY_82_DATA 0x07FF0200
 #define DDRSS_PHY_83_DATA 0x0000DD01
@@ -1208,7 +1210,7 @@
 #define DDRSS_PHY_333_DATA 0x00000401
 #define DDRSS_PHY_334_DATA 0x00000000
 #define DDRSS_PHY_335_DATA 0x01CC0B01
-#define DDRSS_PHY_336_DATA 0x1003CC0C
+#define DDRSS_PHY_336_DATA 0x1003CC0B
 #define DDRSS_PHY_337_DATA 0x20000140
 #define DDRSS_PHY_338_DATA 0x07FF0200
 #define DDRSS_PHY_339_DATA 0x0000DD01
@@ -1464,7 +1466,7 @@
 #define DDRSS_PHY_589_DATA 0x00000401
 #define DDRSS_PHY_590_DATA 0x00000000
 #define DDRSS_PHY_591_DATA 0x01CC0B01
-#define DDRSS_PHY_592_DATA 0x1003CC0C
+#define DDRSS_PHY_592_DATA 0x1003CC0B
 #define DDRSS_PHY_593_DATA 0x20000140
 #define DDRSS_PHY_594_DATA 0x07FF0200
 #define DDRSS_PHY_595_DATA 0x0000DD01
@@ -1720,7 +1722,7 @@
 #define DDRSS_PHY_845_DATA 0x00000401
 #define DDRSS_PHY_846_DATA 0x00000000
 #define DDRSS_PHY_847_DATA 0x01CC0B01
-#define DDRSS_PHY_848_DATA 0x1003CC0C
+#define DDRSS_PHY_848_DATA 0x1003CC0B
 #define DDRSS_PHY_849_DATA 0x20000140
 #define DDRSS_PHY_850_DATA 0x07FF0200
 #define DDRSS_PHY_851_DATA 0x0000DD01
@@ -2789,7 +2791,7 @@
 #define DDRSS_PHY_1914_DATA 0x0089FF00
 #define DDRSS_PHY_1915_DATA 0x000C3F11
 #define DDRSS_PHY_1916_DATA 0x01990000
-#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1917_DATA 0x000C3F91
 #define DDRSS_PHY_1918_DATA 0x01990000
 #define DDRSS_PHY_1919_DATA 0x3F0DFF11
 #define DDRSS_PHY_1920_DATA 0x00EF0000