diff options
| author | Nitin Yadav <n-yadav@ti.com> | 2023-02-08 17:30:14 +0530 |
|---|---|---|
| committer | Praneeth Bajjuri <praneeth@ti.com> | 2023-02-08 10:46:54 -0600 |
| commit | bc34c09a2bfc858eeba9d899ecba298771b5c588 (patch) | |
| tree | 35c12bab44b0d6772f7051e88e80e3504d8f3954 | |
| parent | 9203ec505bb3d04b06af923c26a609d15104d66b (diff) | |
arm: dts: ti: k3-am62: Add GPMC nodes
This adds GPMC and ELM nodes in preparation to
add GPMC NAND addon card support.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
| -rw-r--r-- | arch/arm/dts/k3-am62-main.dtsi | 30 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am62.dtsi | 2 |
2 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index cd2cea2dba..4d31dba4b2 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -540,6 +540,36 @@ }; }; + gpmc0: memory-controller@3b000000 { + compatible = "ti,am64-gpmc"; + status = "disabled"; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 80 0>; + clock-names = "fck"; + reg = <0x00 0x03b000000 0x00 0x400>, + <0x00 0x050000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + elm0: ecc@25010000 { + compatible = "ti,am64-elm"; + status = "disabled"; + reg = <0x00 0x25010000 0x00 0x2000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 54 0>; + clock-names = "fck"; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi index bc2997b185..4e056afa47 100644 --- a/arch/arm/dts/k3-am62.dtsi +++ b/arch/arm/dts/k3-am62.dtsi @@ -74,6 +74,8 @@ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ /* MCU Domain Range */ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, |