diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2023-04-05 08:21:17 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2023-04-05 08:21:17 +0200 |
| commit | 5ecbc52530b00a6e2f39658be54d959c27a4f93d (patch) | |
| tree | 6de0c4375e2a7da8914436a192d0ed19c4eaa1ef | |
| parent | 1599df538a93a3848f82b21b4ac6f1f96abd676e (diff) | |
arm: dts: k3-am625-verdin-lpddr4-1600MTs: update to sysconfig v0.09.08
Update LPDDR4 RAM timings to what the online AM62x SysConfig DDR
Subsystem Register Configuration Tool v0.09.08 generates which supports
bit swizzle configuration. From its README:
v9.08
-added automatic change of RL, WL and nWR when frequency is changed
-added DQ swizzle and byte swap configuration flexibilty for AM62x/AM62A LPDDR4
-PHY_CAL_CLK updated divider values for higher frequencies
-CS ODT fix bug introduced in previous release
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi index fbe9670856..6b770b63fb 100644 --- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.05 - * Fri Jan 27 2023 15:03:47 GMT+0100 (Central European Standard Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08 + * Tue Apr 04 2023 14:52:53 GMT+0200 (Central European Summer Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 800MHz * Density (per channel): 16Gb @@ -886,7 +886,7 @@ #define DDRSS_PHY_100_DATA 0x000001CC #define DDRSS_PHY_101_DATA 0x20100200 #define DDRSS_PHY_102_DATA 0x00000005 -#define DDRSS_PHY_103_DATA 0x56704132 // [Byte 0 SWIZZLE] PHY_DQ_DM_SWIZZLE0_0 +#define DDRSS_PHY_103_DATA 0x56704132 #define DDRSS_PHY_104_DATA 0x00000008 #define DDRSS_PHY_105_DATA 0x034C034C #define DDRSS_PHY_106_DATA 0x034C034C @@ -1142,7 +1142,7 @@ #define DDRSS_PHY_356_DATA 0x000001CC #define DDRSS_PHY_357_DATA 0x20100200 #define DDRSS_PHY_358_DATA 0x00000005 -#define DDRSS_PHY_359_DATA 0x03415762 // [Byte 1 SWIZZLE] PHY_DQ_DM_SWIZZLE0_1 +#define DDRSS_PHY_359_DATA 0x03415762 #define DDRSS_PHY_360_DATA 0x00000008 #define DDRSS_PHY_361_DATA 0x034C034C #define DDRSS_PHY_362_DATA 0x034C034C @@ -2154,7 +2154,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x00000AC3 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 |