Merge tag '08.06.00.007' into toradex_ti-u-boot-2021.01_bringup-ELB-5176

Merge TI U-Boot RC Release 08.06.00.007

70 files changed, 3935 insertions, 414 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5a66844a3a..44ee3de007 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -985,8 +985,10 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
 			       k3-am68-sk-r5-base-board.dtb\
 			       k3-j721s2-common-proc-board.dtb\
 			       k3-j721s2-r5-common-proc-board.dtb
-dtb-$(CONFIG_SOC_K3_J784S4) += k3-j784s4-evm.dtb\
-			       k3-j784s4-r5-evm.dtb
+dtb-$(CONFIG_SOC_K3_J784S4) +=	k3-am69-sk.dtb \
+				k3-am69-r5-sk.dtb \
+				k3-j784s4-evm.dtb \
+				k3-j784s4-r5-evm.dtb
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 			      k3-am642-r5-evm.dtb \
 			      k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
index cd2cea2dba..4d31dba4b2 100644
--- a/arch/arm/dts/k3-am62-main.dtsi
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -540,6 +540,36 @@
 		};
 	};
 
+	gpmc0: memory-controller@3b000000 {
+		compatible = "ti,am64-gpmc";
+		status = "disabled";
+		power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 80 0>;
+		clock-names = "fck";
+		reg = <0x00 0x03b000000 0x00 0x400>,
+			<0x00 0x050000000 0x00 0x8000000>;
+		reg-names = "cfg", "data";
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		gpmc,num-cs = <3>;
+		gpmc,num-waitpins = <2>;
+		#address-cells = <2>;
+		#size-cells = <1>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	elm0: ecc@25010000 {
+		compatible = "ti,am64-elm";
+		status = "disabled";
+		reg = <0x00 0x25010000 0x00 0x2000>;
+		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 54 0>;
+		clock-names = "fck";
+	};
+
 	hwspinlock: spinlock@2a000000 {
 		compatible = "ti,am64-hwspinlock";
 		reg = <0x00 0x2a000000 0x00 0x1000>;
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
index 9d210d55fc..ffb5c296c2 100644
--- a/arch/arm/dts/k3-am62-mcu.dtsi
+++ b/arch/arm/dts/k3-am62-mcu.dtsi
@@ -33,4 +33,16 @@
 		clocks = <&k3_clks 106 2>;
 		clock-names = "fck";
 	};
+
+mcu_m4fss: m4fss@5000000 {
+		compatible = "ti,am64-m4fss";
+		reg = <0x00 0x5000000 0x00 0x30000>,
+			<0x00 0x5040000 0x00 0x10000>;
+		reg-names = "iram", "dram";
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <9>;
+		ti,sci-proc-ids = <0x18 0xff>;
+		resets = <&k3_reset 9 1>;
+		firmware-name = "am62-mcu-m4f0_0-fw";
+	};
 };
diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
index bc2997b185..4e056afa47 100644
--- a/arch/arm/dts/k3-am62.dtsi
+++ b/arch/arm/dts/k3-am62.dtsi
@@ -74,6 +74,8 @@
 			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
 			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
 			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+			 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
+			 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
 
 			 /* MCU Domain Range */
 			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi
index fb7f9cd126..174fd809cb 100644
--- a/arch/arm/dts/k3-am62a-main.dtsi
+++ b/arch/arm/dts/k3-am62a-main.dtsi
@@ -549,4 +549,30 @@
 		resets = <&k3_reset 208 1>;
 		firmware-name = "am62a-c71_0-fw";
 	};
+
+	fss: bus@fc00000 {
+		compatible = "simple-bus";
+		reg = <0x00 0x0fc00000 0x00 0x70000>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		ospi0: spi@fc40000 {
+			compatible = "ti,am654-ospi", "cdns,qspi-nor";
+			reg = <0x00 0x0fc40000 0x00 0x100>,
+			      <0x05 0x00000000 0x01 0x00000000>;
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x0>;
+			clocks = <&k3_clks 75 7>;
+			assigned-clocks = <&k3_clks 75 7>;
+			assigned-clock-parents = <&k3_clks 75 8>;
+			assigned-clock-rates = <166666666>;
+			power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
 };
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index ea2e202237..1baba79795 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -25,7 +25,9 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */
+		/* 4G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
 		u-boot,dm-spl;
 	};
 
@@ -149,3 +151,8 @@
 &main_bcdma {
 	ti,sci = <&dm_tifs>;
 };
+
+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x08000000>;
+};
diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
index 69bfc378e1..6f0c583603 100644
--- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
@@ -192,3 +192,23 @@
 &usb0 {
 	u-boot,dm-spl;
 };
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&ospi0_pins_default {
+	u-boot,dm-spl;
+};
+
+&ospi0 {
+	u-boot,dm-spl;
+
+	flash@0 {
+		u-boot,dm-spl;
+
+		partitions {
+			u-boot,dm-spl;
+		};
+	};
+};
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index be14f74078..859a04ff0b 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -22,6 +22,7 @@
 		mmc1 = &sdhci1;
 		remoteproc0 = &mcu_r5fss0_core0;
 		remoteproc1 = &c7x_0;
+		spi0 = &ospi0;
 	};
 
 	chosen {
@@ -30,8 +31,9 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+		/* 4G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
 	};
 
 	reserved-memory {
@@ -250,6 +252,22 @@
 			AM62AX_IOPAD(0x164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */
 		>;
 	};
+
+	ospi0_pins_default: ospi0-pins-default {
+		pinctrl-single,pins = <
+			AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
+			AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
+			AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
+			AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
+			AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
+			AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
+			AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
+			AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
+			AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
+			AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
+			AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
+		>;
+	};
 };
 
 &cpsw3g {
@@ -388,3 +406,67 @@
 &usb0 {
 	dr_mode = "peripheral";
 };
+
+&fss {
+	status = "okay";
+};
+
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ospi0_pins_default>;
+
+	flash@0{
+		compatible = "spi-nand";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <2>;
+		cdns,phy-mode;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "ospi.tiboot3";
+				reg = <0x0 0x80000>;
+			};
+
+			partition@80000 {
+				label = "ospi.tispl";
+				reg = <0x80000 0x200000>;
+			};
+
+			partition@280000 {
+				label = "ospi.u-boot";
+				reg = <0x280000 0x400000>;
+			};
+
+			partition@680000 {
+				label = "ospi.env";
+				reg = <0x680000 0x40000>;
+			};
+
+			partition@6c0000 {
+				label = "ospi.env.backup";
+				reg = <0x6c0000 0x40000>;
+			};
+
+			partition@2000000 {
+				label = "ospi.rootfs";
+				reg = <0x2000000 0x5fc0000>;
+			};
+
+			partition@7fc0000 {
+				label = "ospi.phypattern";
+				reg = <0x7fc0000 0x40000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/k3-am62x-lp-sk-nand.dtsi b/arch/arm/dts/k3-am62x-lp-sk-nand.dtsi
new file mode 100644
index 0000000000..6af804571d
--- /dev/null
+++ b/arch/arm/dts/k3-am62x-lp-sk-nand.dtsi
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT overlay for HSE NAND expansion card on AM62X LP-SK
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifdef CONFIG_NAND_OMAP_GPMC
+&elm0 {
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&main_pmx0 {
+	gpmc0_pins_default: gpmc0-pins-default {
+	       pinctrl-single,pins = <
+		       AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (M25) GPMC0_AD0 */
+		       AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (N23) GPMC0_AD1 */
+		       AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (N24) GPMC0_AD2 */
+		       AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (N25) GPMC0_AD3 */
+		       AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (P24) GPMC0_AD4 */
+		       AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (P22) GPMC0_AD5 */
+		       AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (P21) GPMC0_AD6 */
+		       AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (R23) GPMC0_AD7 */
+		       AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (L23) GPMC0_ADVn_ALE */
+		       AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (L24) GPMC0_OEn_REn */
+		       AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L25) GPMC0_WEn */
+		       AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (M24) GPMC0_BE0n_CLE */
+		       AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (M21) GPMC0_CSn0 */
+		       AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (U23) GPMC0_WAIT0 */
+		>;
+		u-boot,dm-spl;
+	};
+};
+
+&gpmc0 {
+	pinctrl-names = "default";
+	status = "okay";
+	pinctrl-0 = <&gpmc0_pins_default>;
+	ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
+	#address-cells = <2>;
+	#size-cells = <1>;
+	u-boot,dm-spl;
+
+	nand0_0: nand@0,0 {
+		compatible = "ti,am64-nand";
+		reg = <0 0 64>;         /* device IO registers */
+		interrupt-parent = <&gpmc0>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>; /* termcount */
+		rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+		ti,nand-xfer-type = "prefetch-polled";
+		ti,nand-ecc-opt = "bch8";       /* BCH8: Bootrom limitation */
+		ti,elm-id = <&elm0>;
+		nand-bus-width = <8>;
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <40>;
+		gpmc,cs-wr-off-ns = <40>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <25>;
+		gpmc,adv-wr-off-ns = <25>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <20>;
+		gpmc,oe-on-ns = <3>;
+		gpmc,oe-off-ns = <30>;
+		gpmc,access-ns = <30>;
+		gpmc,rd-cycle-ns = <40>;
+		gpmc,wr-cycle-ns = <40>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		u-boot,dm-spl;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "NAND.tiboot3";
+				reg = <0x00000000 0x00200000>;  /* 2M */
+			};
+			partition@200000 {
+				label = "NAND.tispl";
+				reg = <0x00200000 0x00200000>;  /* 2M */
+			};
+			partition@400000 {
+				label = "NAND.tiboot3.backup";  /* 2M */
+				reg = <0x00400000 0x00200000>;  /* BootROM looks at 4M */
+			};
+			partition@600000 {
+				label = "NAND.u-boot";
+				reg = <0x00600000 0x00400000>;  /* 4M */
+			};
+			partition@a00000 {
+				label = "NAND.u-boot-env";
+				reg = <0x00a00000 0x00040000>;  /* 256K */
+			};
+			partition@a40000 {
+				label = "NAND.u-boot-env.backup";
+				reg = <0x00a40000 0x00040000>;  /* 256K */
+			};
+			partition@a80000 {
+				label = "NAND.file-system";
+				reg = <0x00a80000 0x3f580000>;
+			};
+		};
+	};
+};
+
+
+#endif
diff --git a/arch/arm/dts/k3-am62x-lp-sk-u-boot.dtsi b/arch/arm/dts/k3-am62x-lp-sk-u-boot.dtsi
index 12bff527a4..1c8b7d0b9a 100644
--- a/arch/arm/dts/k3-am62x-lp-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62x-lp-sk-u-boot.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include "k3-am62x-sk-common-u-boot.dtsi"
+#include "k3-am62x-lp-sk-nand.dtsi"
 
 &ospi0 {
 	u-boot,dm-spl;
diff --git a/arch/arm/dts/k3-am62x-lp-sk.dts b/arch/arm/dts/k3-am62x-lp-sk.dts
index c94079eb8e..d1a7bf26cc 100644
--- a/arch/arm/dts/k3-am62x-lp-sk.dts
+++ b/arch/arm/dts/k3-am62x-lp-sk.dts
@@ -75,9 +75,9 @@
 				reg = <0x6c0000 0x40000>;
 			};
 
-			partition@800000 {
+			partition@2000000 {
 				label = "ospi.rootfs";
-				reg = <0x800000 0x77c0000>;
+				reg = <0x2000000 0x5fc0000>;
 			};
 
 			partition@7fc0000 {
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
index e67ddebccf..72ebb1400f 100644
--- a/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-common.dtsi
@@ -21,6 +21,7 @@
 		usb0 = &usb0;
 		usb1 = &usb1;
 		spi0 = &ospi0;
+		remoteproc0 = &mcu_m4fss;
 	};
 
 	chosen {
@@ -40,6 +41,18 @@
 		#size-cells = <2>;
 		ranges;
 
+		mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9cb00000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_m4fss_memory_region: m4f-memory@9cc00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9cc00000 0x00 0xe00000>;
+			no-map;
+		};
+
 		secure_tfa_ddr: tfa@9e780000 {
 			reg = <0x00 0x9e780000 0x00 0x80000>;
 			alignment = <0x1000>;
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
new file mode 100644
index 0000000000..f69ebe991d
--- /dev/null
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j784s4.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
+#include "k3-j784s4-ddr.dtsi"
+
+/ {
+	chosen {
+		firmware-loader = &fs_loader0;
+		stdout-path = &main_uart8;
+		tick-timer = &timer1;
+	};
+
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a72_0;
+	};
+
+	fs_loader0: fs_loader@0 {
+		compatible = "u-boot,fs-loader";
+		u-boot,dm-pre-reloc;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 32G RAM */
+		reg = <0x00 0x80000000 0x00 0x80000000>,
+		       <0x08 0x80000000 0x07 0x80000000>;
+	};
+
+	a72_0: a72@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x0 0x00a90000 0x0 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 202 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+		assigned-clock-parents = <&k3_clks 61 1>;
+		assigned-clock-rates = <200000000>, <2000000000>;
+		ti,sci = <&sms>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		u-boot,dm-spl;
+	};
+
+	clk_200mhz: dummy_clock_200mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		u-boot,dm-spl;
+	};
+
+	clk_19_2mhz: dummy_clock_19_2mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <19200000>;
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_mcu_wakeup {
+	sa3_secproxy: secproxy@44880000 {
+		u-boot,dm-spl;
+		compatible = "ti,am654-secure-proxy";
+		reg = <0x0 0x44880000 0x0 0x20000>,
+		      <0x0 0x44860000 0x0 0x20000>,
+		      <0x0 0x43600000 0x0 0x10000>;
+		reg-names = "rt", "scfg", "target_data";
+		#mbox-cells = <1>;
+	};
+
+	mcu_secproxy: secproxy@2a380000 {
+		compatible = "ti,am654-secure-proxy";
+		reg = <0x0 0x2a380000 0x0 0x80000>,
+		      <0x0 0x2a400000 0x0 0x80000>,
+		      <0x0 0x2a480000 0x0 0x80000>;
+		reg-names = "rt", "scfg", "target_data";
+		#mbox-cells = <1>;
+		u-boot,dm-spl;
+	};
+
+	sysctrler: sysctrler {
+		compatible = "ti,am654-system-controller";
+		mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
+		mbox-names = "tx", "rx", "boot_notify";
+		u-boot,dm-spl;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <3>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&mcu_secproxy 21>,
+			<&mcu_secproxy 23>;
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+
+	main_uart8_pins_default: main-uart8-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
+			J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
+		>;
+	};
+
+	 main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
+			J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
+			J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+			J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
+			J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
+			J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
+			J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
+			J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
+		>;
+	};
+
+	main_usbss0_pins_default: main-usbss0-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+		>;
+	};
+};
+
+&wkup_pmx0 {
+
+	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
+			J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
+			J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
+			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
+			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
+			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
+			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
+			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
+			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
+			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
+			J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
+			J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */
+			J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */
+		>;
+	};
+
+	mcu_uart0_pins_default: mcu-uart0-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
+			J784S4_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
+		>;
+	};
+
+	wkup_uart0_pins_default: wkup-uart0-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+			J784S4_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+			J784S4_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
+			J784S4_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */
+		>;
+	};
+};
+
+&sms {
+	mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+	mbox-names = "tx", "rx", "notify";
+	ti,host-id = <4>;
+	ti,secure-host;
+	u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+	u-boot,dm-spl;
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+	u-boot,dm-spl;
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_uart0_pins_default>;
+};
+
+&main_uart8 {
+	u-boot,dm-spl;
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart8_pins_default>;
+};
+
+&main_sdhci0 {
+	/delete-property/ power-domains;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-names = "clk_xin";
+	clocks = <&clk_200mhz>;
+	ti,driver-strength-ohm = <50>;
+	non-removable;
+	bus-width = <8>;
+};
+
+&main_sdhci1 {
+	/delete-property/ power-domains;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/* pinctrl-0 = <&main_mmc1_pins_default>; */
+	pinctrl-names = "default";
+	clock-names = "clk_xin";
+	clocks = <&clk_200mhz>;
+	ti,driver-strength-ohm = <50>;
+};
+
+&usbss0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	ti,vbus-divider;
+	ti,usb2-only;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+};
+
+&mcu_ringacc {
+	ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+	ti,sci = <&dm_tifs>;
+};
+
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+	reg = <0x0 0x47040000 0x0 0x100>,
+	      <0x0 0x50000000 0x0 0x8000000>;
+
+	flash@0{
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+		cdns,phy-mode;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+#include "k3-am69-sk-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
new file mode 100644
index 0000000000..7d4eb8cee8
--- /dev/null
+++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+
+	aliases {
+		serial0 = &wkup_uart0;
+		serial1 = &mcu_uart0;
+		serial2 = &main_uart8;
+		mmc0 = &main_sdhci0;
+		mmc1 = &main_sdhci1;
+		i2c0 = &wkup_i2c0;
+		i2c1 = &mcu_i2c0;
+		i2c2 = &mcu_i2c1;
+		i2c3 = &main_i2c0;
+		ethernet0 = &mcu_cpsw_port1;
+		spi0 = &ospi0;
+	};
+};
+
+&wkup_i2c0 {
+	u-boot,dm-spl;
+};
+
+&cbass_main {
+	u-boot,dm-spl;
+};
+
+&main_navss {
+	u-boot,dm-spl;
+};
+
+&main_r5fss0 {
+	ti,cluster-mode = <0>;
+};
+
+&main_r5fss1 {
+	ti,cluster-mode = <0>;
+};
+
+&cbass_mcu_wakeup {
+	u-boot,dm-spl;
+
+	timer1: timer@40400000 {
+		compatible = "ti,omap5430-timer";
+		reg = <0x0 0x40400000 0x0 0x80>;
+		ti,timer-alwon;
+		clock-frequency = <250000000>; /* HACK: Temporary fix for wrongly configured MCU_TIMER_CLKSEL */
+		u-boot,dm-spl;
+	};
+
+	chipid@43000014 {
+		u-boot,dm-spl;
+	};
+};
+
+&mcu_navss {
+	u-boot,dm-spl;
+};
+
+&mcu_ringacc {
+	reg =   <0x0 0x2b800000 0x0 0x400000>,
+		<0x0 0x2b000000 0x0 0x400000>,
+		<0x0 0x28590000 0x0 0x100>,
+		<0x0 0x2a500000 0x0 0x40000>,
+		<0x0 0x28440000 0x0 0x40000>;
+	reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+	u-boot,dm-spl;
+};
+
+&mcu_udmap {
+	reg =   <0x0 0x285c0000 0x0 0x100>,
+		<0x0 0x284c0000 0x0 0x4000>,
+		<0x0 0x2a800000 0x0 0x40000>,
+		<0x0 0x284a0000 0x0 0x4000>,
+		<0x0 0x2aa00000 0x0 0x40000>,
+		<0x0 0x28400000 0x0 0x2000>;
+	reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+		    "tchanrt", "rflow";
+	u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+	u-boot,dm-spl;
+};
+
+&sms {
+	u-boot,dm-spl;
+	k3_sysreset: sysreset-controller {
+		compatible = "ti,sci-sysreset";
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+};
+
+&main_uart8_pins_default {
+	u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+	u-boot,dm-spl;
+};
+
+&main_usbss0_pins_default {
+	u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+	u-boot,dm-spl;
+};
+
+&k3_pds {
+	u-boot,dm-spl;
+};
+
+&k3_clks {
+	u-boot,dm-spl;
+};
+
+&k3_reset {
+	u-boot,dm-spl;
+};
+
+&main_uart8 {
+	u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+	u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+	u-boot,dm-spl;
+};
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&usbss0 {
+	u-boot,dm-spl;
+};
+
+&usb0 {
+	dr_mode = "peripheral";
+	u-boot,dm-spl;
+};
+
+&mcu_cpsw {
+	reg = <0x0 0x46000000 0x0 0x200000>,
+	      <0x0 0x40f00200 0x0 0x8>;
+	reg-names = "cpsw_nuss", "mac_efuse";
+	/delete-property/ ranges;
+
+	cpsw-phy-sel@40f04040 {
+		compatible = "ti,am654-cpsw-phy-sel";
+		reg= <0x0 0x40f04040 0x0 0x4>;
+		reg-names = "gmii-sel";
+	};
+};
+
+&mcu_fss0_ospi0_pins_default {
+	u-boot,dm-spl;
+};
+
+&serdes_ln_ctrl {
+	u-boot,mux-autoprobe;
+};
+
+&usb_serdes_mux {
+	u-boot,mux-autoprobe;
+};
+
+&ospi0 {
+	u-boot,dm-spl;
+
+	flash@0 {
+		cdns,phy-mode;
+		u-boot,dm-spl;
+
+		partition@3fc0000 {
+			label = "ospi.phypattern";
+			reg = <0x3fc0000 0x40000>;
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&main_sdhci0 {
+	u-boot,dm-spl;
+};
+
+&main_sdhci1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am69-sk.dts b/arch/arm/dts/k3-am69-sk.dts
new file mode 100644
index 0000000000..4cd4963801
--- /dev/null
+++ b/arch/arm/dts/k3-am69-sk.dts
@@ -0,0 +1,908 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Design Files: https://www.ti.com/lit/zip/SPRR466
+ * TRM: https://www.ti.com/lit/zip/spruj52
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include "k3-j784s4.dtsi"
+
+/ {
+	compatible = "ti,am69-sk", "ti,j784s4";
+	model = "Texas Instruments AM69 SK";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	aliases {
+		serial2 = &main_uart8;
+		mmc0 = &main_sdhci0;
+		mmc1 = &main_sdhci1;
+		can0 = &mcu_mcan0;
+		can1 = &mcu_mcan1;
+		remoteproc0 = &mcu_r5fss0_core0;
+		remoteproc1 = &mcu_r5fss0_core1;
+		remoteproc2 = &main_r5fss0_core0;
+		remoteproc3 = &main_r5fss0_core1;
+		remoteproc4 = &main_r5fss1_core0;
+		remoteproc5 = &main_r5fss1_core1;
+		remoteproc6 = &main_r5fss2_core0;
+		remoteproc7 = &main_r5fss2_core1;
+		remoteproc8 = &c71_0;
+		remoteproc9 = &c71_1;
+		remoteproc10 = &c71_2;
+		remoteproc11 = &c71_3;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 32G RAM */
+		reg = <0x00 0x80000000 0x00 0x80000000>,
+		       <0x08 0x80000000 0x07 0x80000000>;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa5100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa6100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa7100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_0_memory_region: c71-memory@a8100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa8100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_1_dma_memory_region: c71-dma-memory@a9000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa9000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_1_memory_region: c71-memory@a9100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa9100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_2_dma_memory_region: c71-dma-memory@aa000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xaa000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_2_memory_region: c71-memory@aa100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xaa100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c71_3_dma_memory_region: c71-dma-memory@ab000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xab000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c71_3_memory_region: c71-memory@ab100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xab100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@ac000000 {
+			reg = <0x00 0xac000000 0x00 0x03000000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		eth_multicast_memory_region: eth-multicast-memories@adc00000 {
+			reg = <0x00 0xaf000000 0x00 0x2000000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	vusb_main: regulator-vusb-main5v0 {
+		/* USB MAIN INPUT 5V DC */
+		compatible = "regulator-fixed";
+		regulator-name = "vusb-main5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_5v0: regulator-vsys5v0 {
+		/* Output of LM61460 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vusb_main>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_3v3: regulator-vsys3v3 {
+		/* Output of LM5143 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vusb_main>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_mmc1: regulator-sd {
+		/* Output of TPS22918 */
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vsys_3v3>;
+		gpio = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	};
+
+	vdd_sd_dv: regulator-tlv71033 {
+		/* Output of TLV71033 */
+		compatible = "regulator-gpio";
+		regulator-name = "tlv71033";
+		pinctrl-names = "default";
+		pinctrl-0 = <&vdd_sd_dv_pins_default>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		vin-supply = <&vsys_5v0>;
+		gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x0>,
+			 <3300000 0x1>;
+	};
+
+	transceiver1: can-phy0 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		standby-gpios = <&exp1 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	transceiver2: can-phy1 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+	};
+};
+
+&wkup_pmx0 {
+	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
+			J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
+			J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
+			J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
+			J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
+			J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
+			J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
+			J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
+			J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
+			J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
+			J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
+		>;
+	};
+
+	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
+			J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
+			J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
+			J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
+			J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
+			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
+			J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
+			J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
+			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
+			J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
+			J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
+			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu-mdio-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
+			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
+		>;
+	};
+
+	mcu_mcan0_pins_default: mcu-mcan0-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */
+			J784S4_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */
+		>;
+	};
+
+	mcu_mcan1_pins_default: mcu-mcan1-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */
+			J784S4_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */
+		>;
+	};
+};
+
+&main_pmx0 {
+	main_uart8_pins_default: main-uart8-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
+			J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
+		>;
+	};
+
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
+			J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
+			J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
+			J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+			J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
+			J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
+			J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
+			J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
+			J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
+		>;
+	};
+
+	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
+		>;
+	};
+
+	main_usbss0_pins_default: main-usbss0-pins-default {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+		>;
+	};
+};
+
+&main_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+
+	exp1: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
+				  "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#", "IO_EXP_PCIe1_M.2_RTSz",
+				  "IO_EXP_PCIe3_M.2_RTSz", "PM_INA_BUS_EN", "ENET1_EXP_PWRDN",
+				  "EXP1_ENET_RSTz", "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#",
+				  "PCIe1_M.2_CLKREQ#", "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2";
+	};
+};
+
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+		spi-max-frequency = <25000000>;
+		cdns,tshsl-ns = <60>;
+		cdns,tsd2d-ns = <60>;
+		cdns,tchsh-ns = <60>;
+		cdns,tslch-ns = <60>;
+		cdns,read-delay = <4>;
+		cdns,phy-mode;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+&main_sdhci0 {
+	/* eMMC */
+	non-removable;
+	ti,driver-strength-ohm = <50>;
+	/* Disabling all the UHS modes, to re-enable UHS modes, remove the
+	 * sdhci-caps-mask and no-1-8-v property.
+	 */
+	sdhci-caps-mask = <0x00000007 0x00000000>;
+	no-1-8-v;
+	disable-wp;
+};
+
+&main_sdhci1 {
+	/* SD card */
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	pinctrl-names = "default";
+	disable-wp;
+	vmmc-supply = <&vdd_mmc1>;
+	vqmmc-supply = <&vdd_sd_dv>;
+	/* Disabling all the UHS modes, to re-enable UHS modes, remove the
+	 * sdhci-caps-mask and no-1-8-v property.
+	 */
+	sdhci-caps-mask = <0x00000007 0x00000000>;
+	no-1-8-v;
+};
+
+&mailbox0_cluster0 {
+	interrupts = <436>;
+
+	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	interrupts = <432>;
+
+	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	interrupts = <428>;
+
+	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	interrupts = <424>;
+
+	mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster4 {
+	interrupts = <420>;
+
+	mbox_c71_0: mbox-c71-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c71_1: mbox-c71-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster5 {
+	interrupts = <416>;
+
+	mbox_c71_2: mbox-c71-2 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c71_3: mbox-c71-3 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+&mailbox0_cluster6 {
+	status = "disabled";
+};
+
+&mailbox0_cluster7 {
+	status = "disabled";
+};
+
+&mailbox0_cluster8 {
+	status = "disabled";
+};
+
+&mailbox0_cluster9 {
+	status = "disabled";
+};
+
+&mailbox0_cluster10 {
+	status = "disabled";
+};
+
+&mailbox0_cluster11 {
+	status = "disabled";
+};
+
+&mailbox1_cluster0 {
+	status = "disabled";
+};
+
+&mailbox1_cluster1 {
+	status = "disabled";
+};
+
+&mailbox1_cluster2 {
+	status = "disabled";
+};
+
+&mailbox1_cluster3 {
+	status = "disabled";
+};
+
+&mailbox1_cluster4 {
+	status = "disabled";
+};
+
+&mailbox1_cluster5 {
+	status = "disabled";
+};
+
+&mailbox1_cluster6 {
+	status = "disabled";
+};
+
+&mailbox1_cluster7 {
+	status = "disabled";
+};
+
+&mailbox1_cluster8 {
+	status = "disabled";
+};
+
+&mailbox1_cluster9 {
+	status = "disabled";
+};
+
+&mailbox1_cluster10 {
+	status = "disabled";
+};
+
+&mailbox1_cluster11 {
+	status = "disabled";
+};
+
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+			<&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
+};
+
+&main_r5fss2_core0 {
+	mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
+	memory-region = <&main_r5fss2_core0_dma_memory_region>,
+			<&main_r5fss2_core0_memory_region>;
+};
+
+&main_r5fss2_core1 {
+	mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
+	memory-region = <&main_r5fss2_core1_dma_memory_region>,
+			<&main_r5fss2_core1_memory_region>;
+};
+
+&c71_0 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+	memory-region = <&c71_0_dma_memory_region>,
+			<&c71_0_memory_region>;
+};
+
+&c71_1 {
+	mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
+	memory-region = <&c71_1_dma_memory_region>,
+			<&c71_1_memory_region>;
+};
+
+&c71_2 {
+	mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
+	memory-region = <&c71_2_dma_memory_region>,
+			<&c71_2_memory_region>;
+};
+
+&c71_3 {
+	mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
+	memory-region = <&c71_3_dma_memory_region>,
+			<&c71_3_memory_region>;
+};
+
+&main_gpio2 {
+	status = "disabled";
+};
+
+&main_gpio4 {
+	status = "disabled";
+};
+
+&main_gpio6 {
+	status = "disabled";
+};
+
+&wkup_gpio1 {
+	status = "disabled";
+};
+
+&wkup_uart0 {
+	status = "reserved";
+};
+
+&main_uart0 {
+	status = "disabled";
+};
+
+&main_uart1 {
+	status = "disabled";
+};
+
+&main_uart2 {
+	status = "disabled";
+};
+
+&main_uart3 {
+	status = "disabled";
+};
+
+&main_uart4 {
+	status = "disabled";
+};
+
+&main_uart5 {
+	status = "disabled";
+};
+
+&main_uart6 {
+	status = "disabled";
+};
+
+&main_uart7 {
+	status = "disabled";
+};
+
+&main_uart8 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart8_pins_default>;
+	/* Shared with TFA on this platform */
+	power-domains = <&k3_pds 395 TI_SCI_PD_SHARED>;
+};
+
+&main_uart9 {
+	status = "disabled";
+};
+
+&main_i2c1 {
+	status = "disabled";
+};
+
+&main_i2c2 {
+	status = "disabled";
+};
+
+&main_i2c3 {
+	status = "disabled";
+};
+
+&main_i2c4 {
+	status = "disabled";
+};
+
+&main_i2c5 {
+	status = "disabled";
+};
+
+&main_i2c6 {
+	status = "disabled";
+};
+
+&mcu_cpsw {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+	mcu_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&mcu_cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&mcu_phy0>;
+};
+
+&serdes_ln_ctrl {
+	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+		      <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>;
+};
+
+&serdes_refclk {
+	clock-frequency = <100000000>;
+};
+
+&serdes0 {
+	serdes0_usb_link: phy@3 {
+		reg = <3>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+		resets = <&serdes_wiz0 4>;
+	};
+};
+
+&usb_serdes_mux {
+	idle-states = <0>; /* USB0 to SERDES0 */
+};
+
+&usbss0 {
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	pinctrl-names = "default";
+	ti,vbus-divider;
+};
+
+&usb0 {
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	phys = <&serdes0_usb_link>;
+	phy-names = "cdns3,usb3-phy";
+};
+
+&mcu_mcan0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan0_pins_default>;
+	phys = <&transceiver1>;
+};
+
+&mcu_mcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan1_pins_default>;
+	phys = <&transceiver2>;
+};
+
+&main_mcan0 {
+	status = "disabled";
+};
+
+&main_mcan1 {
+	status = "disabled";
+};
+
+&main_mcan2 {
+	status = "disabled";
+};
+
+&main_mcan3 {
+	status = "disabled";
+};
+
+&main_mcan4 {
+	status = "disabled";
+};
+
+&main_mcan5 {
+	status = "disabled";
+};
+
+&main_mcan6 {
+	status = "disabled";
+};
+
+&main_mcan7 {
+	status = "disabled";
+};
+
+&main_mcan8 {
+	status = "disabled";
+};
+
+&main_mcan9 {
+	status = "disabled";
+};
+
+&main_mcan10 {
+	status = "disabled";
+};
+
+&main_mcan11 {
+	status = "disabled";
+};
+
+&main_mcan12 {
+	status = "disabled";
+};
+
+&main_mcan13 {
+	status = "disabled";
+};
+
+&main_mcan14 {
+	status = "disabled";
+};
+
+&main_mcan15 {
+	status = "disabled";
+};
+
+&main_mcan16 {
+	status = "disabled";
+};
+
+&main_mcan17 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index eeeb1e0f32..95e8797f76 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -275,7 +275,8 @@
 
 		hbmc: hyperbus@47034000 {
 			compatible = "ti,am654-hbmc";
-			reg = <0x00 0x47034000 0x00 0x100>,
+			reg = <0x00 0x47030000 0x00 0xc>,
+				<0x00 0x47034000 0x00 0x100>,
 				<0x05 0x00000000 0x01 0x0000000>;
 			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 			clocks = <&k3_clks 102 0>;
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index a34957c6d6..a5159ce9d3 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -187,7 +187,8 @@
 
 		hbmc: hyperbus@47034000 {
 			compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
-			reg = <0x0 0x47034000 0x0 0x100>,
+			reg = <0x0 0x47030000 0x0 0xc>,
+				<0x0 0x47034000 0x0 0x100>,
 				<0x5 0x00000000 0x1 0x0000000>;
 			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 			#address-cells = <2>;
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 0ce69a1a45..9d6f7dbbd5 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -17,7 +17,7 @@
 		i2c1 = &mcu_i2c0;
 		i2c2 = &mcu_i2c1;
 		i2c3 = &main_i2c0;
-		ethernet0 = &cpsw_port1;
+		ethernet0 = &mcu_cpsw_port1;
 		spi0 = &ospi0;
 		spi1 = &ospi1;
 	};
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
index 8e023ec291..5e213b2c11 100644
--- a/arch/arm/dts/k3-j784s4-evm.dts
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -845,7 +845,7 @@
 	};
 };
 
-&main_cpsw_mdio {
+&main_cpsw1_mdio {
 	main_phy0: ethernet-phy@0 {
 		reg = <0>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -854,12 +854,12 @@
 	};
 };
 
-&cpsw_port1 {
+&mcu_cpsw_port1 {
 	phy-mode = "rgmii-rxid";
 	phy-handle = <&mcu_phy0>;
 };
 
-&main_cpsw_port1 {
+&main_cpsw1_port1 {
 	phy-mode = "rgmii-rxid";
 	phy-handle = <&main_phy0>;
 };
diff --git a/arch/arm/dts/k3-j784s4-main.dtsi b/arch/arm/dts/k3-j784s4-main.dtsi
index 9fc098b623..da6241a1d7 100644
--- a/arch/arm/dts/k3-j784s4-main.dtsi
+++ b/arch/arm/dts/k3-j784s4-main.dtsi
@@ -38,7 +38,7 @@
 		};
 	};
 
-	scm_conf: scm-conf@104000 {
+	scm_conf: system-controller@104000 {
 		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
 		reg = <0x00 0x00104000 0x00 0x18000>;
 		#address-cells = <1>;
@@ -49,7 +49,24 @@
 			compatible = "mmio-mux";
 			#mux-control-cells = <1>;
 			mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
-					<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+					<0x88 0x3>, <0x8c 0x3>, /* SERDES0 lane2/3 select */
+					<0x90 0x3>, <0x94 0x3>, /* SERDES1 lane0/1 select */
+					<0x98 0x3>, <0x9c 0x3>, /* SERDES1 lane2/3 select */
+					<0xa0 0x3>, <0xa4 0x3>, /* SERDES2 lane0/1 select */
+					<0xa8 0x3>, <0xac 0x3>; /* SERDES2 lane2/3 select */
+		};
+
+		phy_gmii_sel_cpsw0: phy@44 {
+			compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
+			ti,qsgmii-main-ports = <1>, <3>;
+			reg = <0x44 0x20>;
+			#phy-cells = <1>;
+		};
+
+		phy_gmii_sel_cpsw1: phy@34 {
+			compatible = "ti,am654-phy-gmii-sel";
+			reg = <0x34 0x4>;
+			#phy-cells = <1>;
 		};
 
 		usb_serdes_mux: mux-controller1 {
@@ -57,15 +74,105 @@
 			#mux-control-cells = <1>;
 			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
 		};
+	};
 
-		phy_gmii_sel_cpsw: phy@34 {
-			compatible = "ti,am654-phy-gmii-sel";
-			reg = <0x34 0x4>;
-			#phy-cells = <1>;
+	main_cpsw0: ethernet@c000000 {
+		compatible = "ti,j784s4-cpswxg-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0xc000000 0x0 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x0 0x0 0x0 0xc000000 0x0 0x200000>;
+		dma-coherent;
+		clocks = <&k3_clks 64 0>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&main_udmap 0xca00>,
+		       <&main_udmap 0xca01>,
+		       <&main_udmap 0xca02>,
+		       <&main_udmap 0xca03>,
+		       <&main_udmap 0xca04>,
+		       <&main_udmap 0xca05>,
+		       <&main_udmap 0xca06>,
+		       <&main_udmap 0xca07>,
+		       <&main_udmap 0x4a00>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			main_cpsw0_port1: port@1 {
+				reg = <1>;
+				label = "port1";
+				ti,mac-only;
+			};
+
+			main_cpsw0_port2: port@2 {
+				reg = <2>;
+				label = "port2";
+				ti,mac-only;
+			};
+
+			main_cpsw0_port3: port@3 {
+				reg = <3>;
+				label = "port3";
+				ti,mac-only;
+			};
+
+			main_cpsw0_port4: port@4 {
+				reg = <4>;
+				label = "port4";
+				ti,mac-only;
+			};
+
+			main_cpsw0_port5: port@5 {
+				reg = <5>;
+				label = "port5";
+			};
+
+			main_cpsw0_port6: port@6 {
+				reg = <6>;
+				label = "port6";
+			};
+
+			main_cpsw0_port7: port@7 {
+				reg = <7>;
+				label = "port7";
+			};
+
+			main_cpsw0_port8: port@8 {
+				reg = <8>;
+				label = "port8";
+			};
+		};
+
+		main_cpsw0_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+			reg = <0x0 0xf00 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 64 0>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts@3d000 {
+			compatible = "ti,am65-cpts";
+			reg = <0x0 0x3d000 0x0 0x400>;
+			clocks = <&k3_clks 64 3>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
 		};
 	};
 
-	main_cpsw: ethernet@c200000 {
+	main_cpsw1: ethernet@c200000 {
 		compatible = "ti,j721e-cpsw-nuss";
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -94,15 +201,15 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			main_cpsw_port1: port@1 {
+			main_cpsw1_port1: port@1 {
 				reg = <1>;
 				ti,mac-only;
 				label = "port1";
-				phys = <&phy_gmii_sel_cpsw 1>;
+				phys = <&phy_gmii_sel_cpsw1 1>;
 			};
 		};
 
-		main_cpsw_mdio: mdio@f00 {
+		main_cpsw1_mdio: mdio@f00 {
 			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 			reg = <0x0 0xf00 0x0 0x100>;
 			#address-cells = <1>;
@@ -514,7 +621,7 @@
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		hwspinlock: spinlock@30e00000 {
+		hwspinlock: hwlock@30e00000 {
 			compatible = "ti,am654-hwspinlock";
 			reg = <0x00 0x30e00000 0x00 0x1000>;
 			#hwlock-cells = <1>;
diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
index b855f928c4..56d8bef409 100644
--- a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
@@ -269,7 +269,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			cpsw_port1: port@1 {
+			mcu_cpsw_port1: port@1 {
 				reg = <1>;
 				ti,mac-only;
 				label = "port1";
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index b43492ff9a..d103c73770 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -324,6 +324,9 @@ static u32 __get_primary_bootmedia(u32 devstat)
 	case BOOT_DEVICE_SERIAL_NAND:
 		return BOOT_DEVICE_SPINAND;
 
+	case BOOT_DEVICE_NAND:
+		return BOOT_DEVICE_NAND;
+
 	case BOOT_DEVICE_MMC:
 		if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
 				MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c
index aeb2e4087f..926585725a 100644
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62a7_init.c
@@ -17,6 +17,9 @@
 
 
 #if defined(CONFIG_SPL_BUILD)
+struct fwl_data cbass_main_fwls[] = {
+       { "FSS_DAT_REG3", 7, 8 },
+};
 
 /*
  * This uninitialized global variable would normal end up in the .bss section,
@@ -174,6 +177,9 @@ void board_init_f(ulong dummy)
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 
+       /* Disable ROM configured firewalls right after loading sysfw */
+       remove_fwl_configs(cbass_main_fwls, ARRAY_SIZE(cbass_main_fwls));
+
 #if defined(CONFIG_K3_AM62A_DDRSS)
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 	if (ret)
diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c
index c0881778fe..47ea973197 100644
--- a/arch/arm/mach-k3/am62x/clk-data.c
+++ b/arch/arm/mach-k3/am62x/clk-data.c
@@ -3,9 +3,9 @@
  * AM62X specific clock platform data
  *
  * This file is auto generated. Please do not hand edit and report any issues
- * to Dave Gerlach <d-gerlach@ti.com>.
+ * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
@@ -20,16 +20,6 @@ static const char * const gluelogic_hfosc0_clkout_parents[] = {
 	NULL,
 };
 
-static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
-	"board_0_mmc0_clklb_out",
-	"board_0_mmc0_clk_out",
-};
-
-static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
-	"board_0_mmc1_clklb_out",
-	"board_0_mmc1_clk_out",
-};
-
 static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
 	"board_0_ospi0_dqs_out",
 	"board_0_ospi0_lbclko_out",
@@ -88,6 +78,11 @@ static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
 	"hsdiv4_16fft_main_2_hsdivout2_clk",
 };
 
+static const char * const main_gpmc_fclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_0_hsdivout3_clk",
+	"postdiv4_16ff_main_2_hsdivout7_clk",
+};
+
 static const char * const main_gtcclk_sel_out0_parents[] = {
 	"postdiv4_16ff_main_2_hsdivout5_clk",
 	"postdiv4_16ff_main_0_hsdivout6_clk",
@@ -137,10 +132,6 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
 	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
-	CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
-	CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
-	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
-	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
 	CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
@@ -158,45 +149,44 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
 	CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
 	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
-	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
-	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
-	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
-	CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
-	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
-	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
-	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
-	CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
-	CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
-	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
-	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
-	CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
-	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
-	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
-	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
-	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
-	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
-	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
-	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
-	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
-	CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
-	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
+	CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
+	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+	CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+	CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000),
+	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+	CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+	CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
+	CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
+	CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
+	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+	CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+	CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
+	CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
+	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
+	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
+	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
+	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
+	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
+	CLK_DIV("postdiv4_16ff_main_2_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x68209c, 0, 7, 0, 0),
+	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
+	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
 	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
 	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
 	CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
-	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
-	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
-	CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
-	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
-	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
-	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
+	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
+	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
+	CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
+	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
+	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
@@ -206,13 +196,14 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
 	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
 	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
+	CLK_MUX("main_gpmc_fclk_sel_out0", main_gpmc_fclk_sel_out0_parents, 2, 0x108180, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
 	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
 	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
 	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
 	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
 	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
-	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
+	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
 	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
@@ -255,16 +246,11 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
 	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-	DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
-	DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
-	DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
+	DEV_CLK(54, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
 	DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
 	DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
-	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
-	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
-	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
 	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
 	DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
@@ -290,6 +276,10 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
 	DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
 	DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(80, 0, "main_gpmc_fclk_sel_out0"),
+	DEV_CLK(80, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+	DEV_CLK(80, 2, "postdiv4_16ff_main_2_hsdivout7_clk"),
+	DEV_CLK(80, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
 	DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(95, 2, "wkup_clksel_out0"),
@@ -360,7 +350,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 
 const struct ti_k3_clk_platdata am62x_clk_platdata = {
 	.clk_list = clk_list,
-	.clk_list_cnt = 90,
+	.clk_list_cnt = 86,
 	.soc_dev_clk_data = soc_dev_clk_data,
-	.soc_dev_clk_data_cnt = 137,
+	.soc_dev_clk_data_cnt = 136,
 };
diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c
index 616d0650b9..f413313533 100644
--- a/arch/arm/mach-k3/am62x/dev-data.c
+++ b/arch/arm/mach-k3/am62x/dev-data.c
@@ -3,9 +3,9 @@
  * AM62X specific device platform data
  *
  * This file is auto generated. Please do not hand edit and report any issues
- * to Dave Gerlach <d-gerlach@ti.com>.
+ * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -25,21 +25,22 @@ static struct ti_pd soc_pd_list[] = {
 
 static struct ti_lpsc soc_lpsc_list[] = {
 	[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
-	[1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
+	[1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
 	[2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]),
 	[3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]),
-	[4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
-	[5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]),
-	[6] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
-	[7] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
-	[8] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
-	[9] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
-	[10] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
-	[11] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]),
-	[12] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[11]),
-	[13] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[11]),
-	[14] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[13]),
-	[15] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
+	[4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]),
+	[5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[10]),
+	[6] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
+	[7] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
+	[8] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
+	[9] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
+	[10] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
+	[11] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
+	[12] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[12]),
+	[13] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[12]),
+	[14] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[12]),
+	[15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[14]),
+	[16] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[14]),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -53,17 +54,19 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(55, &soc_lpsc_list[3]),
 	PSC_DEV(178, &soc_lpsc_list[4]),
 	PSC_DEV(179, &soc_lpsc_list[5]),
-	PSC_DEV(57, &soc_lpsc_list[6]),
-	PSC_DEV(58, &soc_lpsc_list[7]),
-	PSC_DEV(161, &soc_lpsc_list[8]),
-	PSC_DEV(162, &soc_lpsc_list[9]),
-	PSC_DEV(75, &soc_lpsc_list[10]),
-	PSC_DEV(102, &soc_lpsc_list[11]),
-	PSC_DEV(146, &soc_lpsc_list[11]),
-	PSC_DEV(13, &soc_lpsc_list[12]),
-	PSC_DEV(166, &soc_lpsc_list[13]),
-	PSC_DEV(135, &soc_lpsc_list[14]),
-	PSC_DEV(136, &soc_lpsc_list[15]),
+	PSC_DEV(54, &soc_lpsc_list[6]),
+	PSC_DEV(80, &soc_lpsc_list[6]),
+	PSC_DEV(57, &soc_lpsc_list[7]),
+	PSC_DEV(58, &soc_lpsc_list[8]),
+	PSC_DEV(161, &soc_lpsc_list[9]),
+	PSC_DEV(162, &soc_lpsc_list[10]),
+	PSC_DEV(75, &soc_lpsc_list[11]),
+	PSC_DEV(102, &soc_lpsc_list[12]),
+	PSC_DEV(146, &soc_lpsc_list[12]),
+	PSC_DEV(13, &soc_lpsc_list[13]),
+	PSC_DEV(166, &soc_lpsc_list[14]),
+	PSC_DEV(135, &soc_lpsc_list[15]),
+	PSC_DEV(136, &soc_lpsc_list[16]),
 };
 
 const struct ti_k3_pd_platdata am62x_pd_platdata = {
@@ -73,6 +76,6 @@ const struct ti_k3_pd_platdata am62x_pd_platdata = {
 	.devs = soc_dev_list,
 	.num_psc = 2,
 	.num_pd = 5,
-	.num_lpsc = 16,
-	.num_devs = 21,
+	.num_lpsc = 17,
+	.num_devs = 23,
 };
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 77e1ed9419..bd4086bb04 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -627,9 +627,11 @@ int misc_init_r(void)
 			printf("Failed to probe am65_cpsw_nuss driver\n");
 	}
 
-	/* Default FIT boot on non-GP devices */
-	if (get_device_type() != K3_DEVICE_TYPE_GP)
-		env_set("boot_fit", "1");
+	/* Default FIT boot on HS-SE devices */
+	if (get_device_type() == K3_DEVICE_TYPE_HS_SE) {
+		if (!env_get("boot_fit"))
+			env_set("boot_fit", "1");
+	}
 
 	return 0;
 }
diff --git a/arch/arm/mach-k3/include/mach/am62_spl.h b/arch/arm/mach-k3/include/mach/am62_spl.h
index 4a052bce22..08e63c0b26 100644
--- a/arch/arm/mach-k3/include/mach/am62_spl.h
+++ b/arch/arm/mach-k3/include/mach/am62_spl.h
@@ -22,7 +22,7 @@
 
 #define BOOT_DEVICE_USB			0x2A
 #define BOOT_DEVICE_DFU			0x0A
-#define BOOT_DEVICE_GPMC_NAND		0x0B
+#define BOOT_DEVICE_NAND		0x0B
 #define BOOT_DEVICE_GPMC_NOR		0x0C
 #define BOOT_DEVICE_XSPI		0x0E
 #define BOOT_DEVICE_NOBOOT		0x0F
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index ad55a556bb..f1ce45d69b 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -28,6 +28,7 @@
 #ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_K3_LOAD_SYSFW
 struct fwl_data cbass_hc_cfg0_fwls[] = {
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
 	{ "PCIE0_CFG", 2560, 8 },
 	{ "PCIE1_CFG", 2561, 8 },
 	{ "USB3SS0_CORE", 2568, 4 },
@@ -36,11 +37,16 @@ struct fwl_data cbass_hc_cfg0_fwls[] = {
 	{ "UFS_HCI0_CFG", 2580, 4 },
 	{ "SERDES0", 2584, 1 },
 	{ "SERDES1", 2585, 1 },
+#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+	{ "PCIE1_CFG", 2561, 7 },
+#endif
 }, cbass_hc0_fwls[] = {
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
 	{ "PCIE0_HP", 2528, 24 },
 	{ "PCIE0_LP", 2529, 24 },
 	{ "PCIE1_HP", 2530, 24 },
 	{ "PCIE1_LP", 2531, 24 },
+#endif
 }, cbass_rc_cfg0_fwls[] = {
 	{ "EMMCSD4SS0_CFG", 2380, 4 },
 }, cbass_rc0_fwls[] = {
diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4_init.c
index b5949f4b8c..e112b7a8e4 100644
--- a/arch/arm/mach-k3/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4_init.c
@@ -185,6 +185,11 @@ void board_init_f(ulong dummy)
 		k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
 				k3_mmc_stop_clock, k3_mmc_restart_clock);
 
+#ifdef CONFIG_SPL_OF_LIST
+		if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+			do_board_detect();
+#endif
+
 		if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
 			/*
 			 * Force probe of clk_k3 driver here to ensure basic default clock
diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c
index f5c2f46884..a7c3d43e43 100644
--- a/board/ti/am62ax/evm.c
+++ b/board/ti/am62ax/evm.c
@@ -55,6 +55,94 @@ int board_fit_config_name_match(const char *name)
 #define CTRLMMR_USB1_PHY_CTRL	0x43004018
 #define CORE_VOLTAGE		0x80000000
 
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+	int ret;
+
+	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+					 CONFIG_EEPROM_CHIP_ADDRESS);
+	if (ret) {
+		printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+		       CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+						 CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		if (ret)
+			pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+			       CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+	}
+
+	return ret;
+}
+
+int checkboard(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (!do_board_detect())
+		printf("Board: %s rev %s\n", ep->name, ep->version);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static void setup_board_eeprom_env(void)
+{
+	char *name = "am62ax_skevm";
+
+	if (do_board_detect())
+		goto invalid_eeprom;
+
+	if (board_is_am62ax_skevm())
+		name = "am62ax_skevm";
+	else
+		printf("Unidentified board claims %s in eeprom header\n",
+		       board_ti_get_name());
+
+invalid_eeprom:
+	set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+	unsigned long board_serial;
+	char *endp;
+	char serial_string[17] = { 0 };
+
+	if (env_get("serial#"))
+		return;
+
+	board_serial = simple_strtoul(ep->serial, &endp, 16);
+	if (*endp != '\0') {
+		pr_err("Error: Can't set serial# to %s\n", ep->serial);
+		return;
+	}
+
+	snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+	env_set("serial#", serial_string);
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+		struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+		setup_board_eeprom_env();
+		setup_serial();
+		/*
+		 * The first MAC address for ethernet a.k.a. ethernet0 comes from
+		 * efuse populated via the am654 gigabit eth switch subsystem driver.
+		 * All the other ones are populated via EEPROM, hence continue with
+		 * an index of 1.
+		 */
+		board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
+	}
+	return 0;
+}
+#endif
+
 #if defined(CONFIG_SPL_BOARD_INIT)
 void spl_board_init(void)
 {
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index acc0a08f96..ae9b8871d2 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -9,19 +9,36 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <env.h>
+#include <net.h>
 #include <spl.h>
 #include <dm/uclass.h>
 #include <k3-ddrss.h>
 #include <fdt_support.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
-#include <env.h>
+#include <asm/gpio.h>
 
 #include "../common/board_detect.h"
 
 #define board_is_am62x_skevm()		board_ti_k3_is("AM62-SKEVM")
 #define board_is_am62x_lp_skevm()	board_ti_k3_is("AM62-LP-SKEVM")
 
+#define AM62X_MAX_DAUGHTER_CARDS	8
+
+/* Daughter card presence detection signals */
+enum {
+	AM62X_LPSK_HSE_BRD_DET,
+	AM62X_LPSK_BRD_DET_COUNT,
+};
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARM64)
+static struct gpio_desc board_det_gpios[AM62X_LPSK_BRD_DET_COUNT];
+#endif
+
+/* Max number of MAC addresses that are parsed/processed per daughter card */
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR	8
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
@@ -182,6 +199,153 @@ static void setup_serial(void)
 #endif
 #endif
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARM64)
+static const char *k3_dtbo_list[AM62X_MAX_DAUGHTER_CARDS] = {NULL};
+
+static int init_daughtercard_det_gpio(char *gpio_name, struct gpio_desc *desc)
+{
+	int ret;
+
+	memset(desc, 0, sizeof(*desc));
+	ret = dm_gpio_lookup_name(gpio_name, desc);
+	if (ret < 0) {
+		pr_err("Failed to lookup gpio %s: %d\n", gpio_name, ret);
+		return ret;
+	}
+
+	/* Request GPIO, simply re-using the name as label */
+	ret = dm_gpio_request(desc, gpio_name);
+	if (ret < 0) {
+		pr_err("Failed to request gpio %s: %d\n", gpio_name, ret);
+		return ret;
+	}
+
+	return dm_gpio_set_dir_flags(desc, GPIOD_IS_IN);
+}
+
+static int probe_daughtercards(void)
+{
+	struct ti_am6_eeprom ep;
+	char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+	u8 mac_addr_cnt;
+	char name_overlays[1024] = { 0 };
+	int i, nb_dtbos = 0;
+	int ret;
+
+	/*
+	 * Daughter card presence detection signal name to GPIO (via I2C I/O
+	 * expander @ address 0x53) name and EEPROM I2C address mapping.
+	 */
+	const struct {
+		char *gpio_name;
+		u8 i2c_addr;
+	} slot_map[AM62X_LPSK_BRD_DET_COUNT] = {
+		{ "gpio@22_2", 0x53, },	/* AM62X_LPSK_HSE_BRD_DET */
+	};
+
+	/* Declaration of daughtercards to probe */
+	const struct {
+		u8 slot_index;		/* Slot the card is installed */
+		char *card_name;	/* EEPROM-programmed card name */
+		char *dtbo_name;	/* Device tree overlay to apply */
+		u8 eth_offset;		/* ethXaddr MAC address index offset */
+	} cards[] = {
+		{
+			AM62X_LPSK_HSE_BRD_DET,
+			"SK-NAND-DC01",
+			"k3-am62x-lp-sk-nand.dtbo",
+			0,
+		},
+	};
+
+	/*
+	 * Initialize GPIO used for daughtercard slot presence detection and
+	 * keep the resulting handles in local array for easier access.
+	 */
+	for (i = 0; i < AM62X_LPSK_BRD_DET_COUNT; i++) {
+		ret = init_daughtercard_det_gpio(slot_map[i].gpio_name,
+						 &board_det_gpios[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	memset(k3_dtbo_list, 0, sizeof(k3_dtbo_list));
+	for (i = 0; i < ARRAY_SIZE(cards); i++) {
+		/* Obtain card-specific slot index and associated I2C address */
+		u8 slot_index = cards[i].slot_index;
+		u8 i2c_addr = slot_map[slot_index].i2c_addr;
+		const char *dtboname;
+
+		/*
+		 * The presence detection signal is active-low, hence skip
+		 * over this card slot if anything other than 0 is returned.
+		 */
+		ret = dm_gpio_get_value(&board_det_gpios[slot_index]);
+		if (ret < 0)
+			return ret;
+		else if (ret)
+			continue;
+
+		/* Get and parse the daughter card EEPROM record */
+		ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS, i2c_addr,
+					    &ep,
+					    (char **)mac_addr,
+					    DAUGHTER_CARD_NO_OF_MAC_ADDR,
+					    &mac_addr_cnt);
+
+		if (ret) {
+			pr_err("Reading daughtercard EEPROM at 0x%02x failed %d\n",
+			       i2c_addr, ret);
+			/*
+			 * Even this is pretty serious let's just skip over
+			 * this particular daughtercard, rather than ending
+			 * the probing process altogether.
+			 */
+			continue;
+		}
+
+		/* Only process the parsed data if we found a match */
+		if (strncmp(ep.name, cards[i].card_name, sizeof(ep.name)))
+			continue;
+		printf("Detected: %s rev %s\n", ep.name, ep.version);
+
+		int j;
+
+		for (j = 0; j < mac_addr_cnt; j++) {
+			if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+				continue;
+
+			eth_env_set_enetaddr_by_index("eth",
+						      cards[i].eth_offset + j,
+						      (uchar *)mac_addr[j]);
+		}
+		/* Skip if no overlays are to be added */
+		if (!strlen(cards[i].dtbo_name))
+			continue;
+
+		dtboname = cards[i].dtbo_name;
+		k3_dtbo_list[nb_dtbos++] = dtboname;
+
+		/*
+		 * Make sure we are not running out of buffer space by checking
+		 * if we can fit the new overlay, a trailing space to be used
+		 * as a separator, plus the terminating zero.
+		 */
+		if (strlen(name_overlays) + strlen(dtboname) + 2 >
+		    sizeof(name_overlays))
+			return -ENOMEM;
+
+		/* Append to our list of overlays */
+		strcat(name_overlays, dtboname);
+		strcat(name_overlays, " ");
+	}
+	/* Apply device tree overlay(s) to the U-Boot environment, if any */
+	if (strlen(name_overlays))
+		return env_set("name_overlays", name_overlays);
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -197,11 +361,13 @@ int board_late_init(void)
 		 * an index of 1.
 		 */
 		board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
-	}
 
-	/* Default FIT boot on non-GP devices */
-	if (get_device_type() != K3_DEVICE_TYPE_GP)
-		env_set("boot_fit", "1");
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARM64)
+		/* Check for and probe any plugged-in daughtercards */
+		if (board_is_am62x_lp_skevm())
+			probe_daughtercards();
+#endif
+	}
 
 	return 0;
 }
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index f691ea4ebb..07e7d9cc8b 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -28,6 +28,8 @@
 
 #define board_is_j784s4_evm()	board_ti_k3_is("J784S4-EVM")
 
+#define board_is_am69_sk()	board_ti_k3_is("AM69-SK")
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
@@ -77,8 +79,15 @@ int dram_init_banksize(void)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	if (!strcmp(name, "J784S4X-EVM"))
-		return 0;
+	bool eeprom_read = board_ti_was_eeprom_read();
+
+	if (!eeprom_read || board_is_j784s4_evm()) {
+		if ((!strcmp(name, "k3-j784s4-evm")) || (!strcmp(name, "k3-j784s4-r5-evm")))
+				return 0;
+	} else if (!eeprom_read || board_is_am69_sk()) {
+		if ((!strcmp(name, "k3-am69-sk")) || (!strcmp(name, "k3-am69-r5-sk")))
+				return 0;
+	}
 
 	return -1;
 }
@@ -105,11 +114,20 @@ int do_board_detect(void)
 {
 	int ret;
 
+	if (board_ti_was_eeprom_read())
+		return 0;
+
 	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
 					 CONFIG_EEPROM_CHIP_ADDRESS);
-	if (ret)
-		pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
-		       CONFIG_EEPROM_CHIP_ADDRESS, ret);
+	if (ret) {
+		printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+			CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+						CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		if (ret)
+			pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+				CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+	}
 
 	return ret;
 }
@@ -136,6 +154,8 @@ static void setup_board_eeprom_env(void)
 
 	if (board_is_j784s4_evm())
 		name = "j784s4";
+	else if (board_is_am69_sk())
+		name = "am69-sk";
 	else
 		printf("Unidentified board claims %s in eeprom header\n",
 		       board_ti_get_name());
diff --git a/common/Kconfig b/common/Kconfig
index 2bce8c9ba1..ed05dd5ce8 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -577,6 +577,15 @@ config AVB_BUF_SIZE
 	  AVB requires a buffer for memory transactions. This variable defines the
 	  buffer size.
 
+config AVB_PUBKEY_FILE
+	string "Path to the root public key file"
+	default "default.avbpubkey"
+	help
+	  This specifies the path to file having the public key that u-boot
+	  will use to verify the payload against. The file can usually be
+	  created via `avbtool extract_public_key --key <path_to_private_key>
+	  --out <path_to_public_key>`.
+
 endif # AVB_VERIFY
 
 config SPL_HASH
diff --git a/common/Makefile b/common/Makefile
index 10e7f8bace..72ffa9eb9a 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -139,3 +139,35 @@ obj-$(CONFIG_CMD_LOADB) += xyzModem.o
 obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o
 
 obj-$(CONFIG_AVB_VERIFY) += avb_verify.o
+###################################################
+# Build avb_pubkey.o from CONFIG_AVB_PUBKEY_FILE
+obj-$(CONFIG_AVB_VERIFY) += avb_pubkey.o
+
+
+# Workaround: ARM linker (bfd) has a bug that segfault occurs when trying to
+# parse a binary file as an input. That issue is fixed in GCC 6.2 [1] but we
+# are using GCC 4.9 and it doesn't look like we are going to upgrade to the
+# recent version. Fortunately, the gold linker doesn't have the problem. So,
+# forcibely use the gold linker when building the avb_pubkey.o.  U-boot has
+# been using bfd linker [2] for features (like OVERLAY), but that matters only
+# for the final linking. Gold linker is okay for converting the binary key file
+# into an ELF object file.
+# [1] https://sourceware.org/legacy-ml/binutils-cvs/2016-10/msg00110.html
+# [2] https://u-boot.denx.narkive.com/5JODsok5/patch-config-always-use-gnu-ld
+ld_for_avbpubkey := $(LD)
+ifneq ($(findstring arm-,$(LD)),)
+    ifeq ($(shell $(LD) -v | grep "GNU gold" 2> /dev/null),)
+        ld_for_avbpubkey := arm-linux-androideabi-ld.gold
+    endif
+endif
+
+# The content of the file which CONFIG_AVB_PUBKEY_FILE refers to is imported
+# as binary. Copying to a temporary file `avb_pubkey` is necessary to keep the
+# name of the auto-generated symbols which are defined around the imported
+# region the same. The symbol names follow the path of the input file.
+$(obj)/avb_pubkey.o: PRIVATE_LD := $(ld_for_avbpubkey)
+ld_for_avbpubkey :=
+$(obj)/avb_pubkey.o: $(srctree)/$(subst $(quote),,$(CONFIG_AVB_PUBKEY_FILE))
+	cp $< $(obj)/avb_pubkey
+	$(PRIVATE_LD) $(KBUILD_LDFLAGS) -r -b binary $(obj)/avb_pubkey -o $@
+	rm $(obj)/avb_pubkey
diff --git a/common/avb_verify.c b/common/avb_verify.c
index db10d0f21f..6b9f72d1ba 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -13,112 +13,11 @@
 #include <tee.h>
 #include <tee/optee_ta_avb.h>
 
-static const unsigned char avb_root_pub[1032] = {
-	0x0, 0x0, 0x10, 0x0, 0x55, 0xd9, 0x4, 0xad, 0xd8, 0x4,
-	0xaf, 0xe3, 0xd3, 0x84, 0x6c, 0x7e, 0xd, 0x89, 0x3d, 0xc2,
-	0x8c, 0xd3, 0x12, 0x55, 0xe9, 0x62, 0xc9, 0xf1, 0xf, 0x5e,
-	0xcc, 0x16, 0x72, 0xab, 0x44, 0x7c, 0x2c, 0x65, 0x4a, 0x94,
-	0xb5, 0x16, 0x2b, 0x0, 0xbb, 0x6, 0xef, 0x13, 0x7, 0x53,
-	0x4c, 0xf9, 0x64, 0xb9, 0x28, 0x7a, 0x1b, 0x84, 0x98, 0x88,
-	0xd8, 0x67, 0xa4, 0x23, 0xf9, 0xa7, 0x4b, 0xdc, 0x4a, 0xf,
-	0xf7, 0x3a, 0x18, 0xae, 0x54, 0xa8, 0x15, 0xfe, 0xb0, 0xad,
-	0xac, 0x35, 0xda, 0x3b, 0xad, 0x27, 0xbc, 0xaf, 0xe8, 0xd3,
-	0x2f, 0x37, 0x34, 0xd6, 0x51, 0x2b, 0x6c, 0x5a, 0x27, 0xd7,
-	0x96, 0x6, 0xaf, 0x6b, 0xb8, 0x80, 0xca, 0xfa, 0x30, 0xb4,
-	0xb1, 0x85, 0xb3, 0x4d, 0xaa, 0xaa, 0xc3, 0x16, 0x34, 0x1a,
-	0xb8, 0xe7, 0xc7, 0xfa, 0xf9, 0x9, 0x77, 0xab, 0x97, 0x93,
-	0xeb, 0x44, 0xae, 0xcf, 0x20, 0xbc, 0xf0, 0x80, 0x11, 0xdb,
-	0x23, 0xc, 0x47, 0x71, 0xb9, 0x6d, 0xd6, 0x7b, 0x60, 0x47,
-	0x87, 0x16, 0x56, 0x93, 0xb7, 0xc2, 0x2a, 0x9a, 0xb0, 0x4c,
-	0x1, 0xc, 0x30, 0xd8, 0x93, 0x87, 0xf0, 0xed, 0x6e, 0x8b,
-	0xbe, 0x30, 0x5b, 0xf6, 0xa6, 0xaf, 0xdd, 0x80, 0x7c, 0x45,
-	0x5e, 0x8f, 0x91, 0x93, 0x5e, 0x44, 0xfe, 0xb8, 0x82, 0x7,
-	0xee, 0x79, 0xca, 0xbf, 0x31, 0x73, 0x62, 0x58, 0xe3, 0xcd,
-	0xc4, 0xbc, 0xc2, 0x11, 0x1d, 0xa1, 0x4a, 0xbf, 0xfe, 0x27,
-	0x7d, 0xa1, 0xf6, 0x35, 0xa3, 0x5e, 0xca, 0xdc, 0x57, 0x2f,
-	0x3e, 0xf0, 0xc9, 0x5d, 0x86, 0x6a, 0xf8, 0xaf, 0x66, 0xa7,
-	0xed, 0xcd, 0xb8, 0xed, 0xa1, 0x5f, 0xba, 0x9b, 0x85, 0x1a,
-	0xd5, 0x9, 0xae, 0x94, 0x4e, 0x3b, 0xcf, 0xcb, 0x5c, 0xc9,
-	0x79, 0x80, 0xf7, 0xcc, 0xa6, 0x4a, 0xa8, 0x6a, 0xd8, 0xd3,
-	0x31, 0x11, 0xf9, 0xf6, 0x2, 0x63, 0x2a, 0x1a, 0x2d, 0xd1,
-	0x1a, 0x66, 0x1b, 0x16, 0x41, 0xbd, 0xbd, 0xf7, 0x4d, 0xc0,
-	0x4a, 0xe5, 0x27, 0x49, 0x5f, 0x7f, 0x58, 0xe3, 0x27, 0x2d,
-	0xe5, 0xc9, 0x66, 0xe, 0x52, 0x38, 0x16, 0x38, 0xfb, 0x16,
-	0xeb, 0x53, 0x3f, 0xe6, 0xfd, 0xe9, 0xa2, 0x5e, 0x25, 0x59,
-	0xd8, 0x79, 0x45, 0xff, 0x3, 0x4c, 0x26, 0xa2, 0x0, 0x5a,
-	0x8e, 0xc2, 0x51, 0xa1, 0x15, 0xf9, 0x7b, 0xf4, 0x5c, 0x81,
-	0x9b, 0x18, 0x47, 0x35, 0xd8, 0x2d, 0x5, 0xe9, 0xad, 0xf,
-	0x35, 0x74, 0x15, 0xa3, 0x8e, 0x8b, 0xcc, 0x27, 0xda, 0x7c,
-	0x5d, 0xe4, 0xfa, 0x4, 0xd3, 0x5, 0xb, 0xba, 0x3a, 0xb2,
-	0x49, 0x45, 0x2f, 0x47, 0xc7, 0xd, 0x41, 0x3f, 0x97, 0x80,
-	0x4d, 0x3f, 0xc1, 0xb5, 0xbb, 0x70, 0x5f, 0xa7, 0x37, 0xaf,
-	0x48, 0x22, 0x12, 0x45, 0x2e, 0xf5, 0xf, 0x87, 0x92, 0xe2,
-	0x84, 0x1, 0xf9, 0x12, 0xf, 0x14, 0x15, 0x24, 0xce, 0x89,
-	0x99, 0xee, 0xb9, 0xc4, 0x17, 0x70, 0x70, 0x15, 0xea, 0xbe,
-	0xc6, 0x6c, 0x1f, 0x62, 0xb3, 0xf4, 0x2d, 0x16, 0x87, 0xfb,
-	0x56, 0x1e, 0x45, 0xab, 0xae, 0x32, 0xe4, 0x5e, 0x91, 0xed,
-	0x53, 0x66, 0x5e, 0xbd, 0xed, 0xad, 0xe6, 0x12, 0x39, 0xd,
-	0x83, 0xc9, 0xe8, 0x6b, 0x6c, 0x2d, 0xa5, 0xee, 0xc4, 0x5a,
-	0x66, 0xae, 0x8c, 0x97, 0xd7, 0xd, 0x6c, 0x49, 0xc7, 0xf5,
-	0xc4, 0x92, 0x31, 0x8b, 0x9, 0xee, 0x33, 0xda, 0xa9, 0x37,
-	0xb6, 0x49, 0x18, 0xf8, 0xe, 0x60, 0x45, 0xc8, 0x33, 0x91,
-	0xef, 0x20, 0x57, 0x10, 0xbe, 0x78, 0x2d, 0x83, 0x26, 0xd6,
-	0xca, 0x61, 0xf9, 0x2f, 0xe0, 0xbf, 0x5, 0x30, 0x52, 0x5a,
-	0x12, 0x1c, 0x0, 0xa7, 0x5d, 0xcc, 0x7c, 0x2e, 0xc5, 0x95,
-	0x8b, 0xa3, 0x3b, 0xf0, 0x43, 0x2e, 0x5e, 0xdd, 0x0, 0xdb,
-	0xd, 0xb3, 0x37, 0x99, 0xa9, 0xcd, 0x9c, 0xb7, 0x43, 0xf7,
-	0x35, 0x44, 0x21, 0xc2, 0x82, 0x71, 0xab, 0x8d, 0xaa, 0xb4,
-	0x41, 0x11, 0xec, 0x1e, 0x8d, 0xfc, 0x14, 0x82, 0x92, 0x4e,
-	0x83, 0x6a, 0xa, 0x6b, 0x35, 0x5e, 0x5d, 0xe9, 0x5c, 0xcc,
-	0x8c, 0xde, 0x39, 0xd1, 0x4a, 0x5b, 0x5f, 0x63, 0xa9, 0x64,
-	0xe0, 0xa, 0xcb, 0xb, 0xb8, 0x5a, 0x7c, 0xc3, 0xb, 0xe6,
-	0xbe, 0xfe, 0x8b, 0xf, 0x7d, 0x34, 0x8e, 0x2, 0x66, 0x74,
-	0x1, 0x6c, 0xca, 0x76, 0xac, 0x7c, 0x67, 0x8, 0x2f, 0x3f,
-	0x1a, 0xa6, 0x2c, 0x60, 0xb3, 0xff, 0xda, 0x8d, 0xb8, 0x12,
-	0xc, 0x0, 0x7f, 0xcc, 0x50, 0xa1, 0x5c, 0x64, 0xa1, 0xe2,
-	0x5f, 0x32, 0x65, 0xc9, 0x9c, 0xbe, 0xd6, 0xa, 0x13, 0x87,
-	0x3c, 0x2a, 0x45, 0x47, 0xc, 0xca, 0x42, 0x82, 0xfa, 0x89,
-	0x65, 0xe7, 0x89, 0xb4, 0x8f, 0xf7, 0x1e, 0xe6, 0x23, 0xa5,
-	0xd0, 0x59, 0x37, 0x79, 0x92, 0xd7, 0xce, 0x3d, 0xfd, 0xe3,
-	0xa1, 0xb, 0xcf, 0x6c, 0x85, 0xa0, 0x65, 0xf3, 0x5c, 0xc6,
-	0x4a, 0x63, 0x5f, 0x6e, 0x3a, 0x3a, 0x2a, 0x8b, 0x6a, 0xb6,
-	0x2f, 0xbb, 0xf8, 0xb2, 0x4b, 0x62, 0xbc, 0x1a, 0x91, 0x25,
-	0x66, 0xe3, 0x69, 0xca, 0x60, 0x49, 0xb, 0xf6, 0x8a, 0xbe,
-	0x3e, 0x76, 0x53, 0xc2, 0x7a, 0xa8, 0x4, 0x17, 0x75, 0xf1,
-	0xf3, 0x3, 0x62, 0x1b, 0x85, 0xb2, 0xb0, 0xef, 0x80, 0x15,
-	0xb6, 0xd4, 0x4e, 0xdf, 0x71, 0xac, 0xdb, 0x2a, 0x4, 0xd4,
-	0xb4, 0x21, 0xba, 0x65, 0x56, 0x57, 0xe8, 0xfa, 0x84, 0xa2,
-	0x7d, 0x13, 0xe, 0xaf, 0xd7, 0x9a, 0x58, 0x2a, 0xa3, 0x81,
-	0x84, 0x8d, 0x9, 0xa0, 0x6a, 0xc1, 0xbb, 0xd9, 0xf5, 0x86,
-	0xac, 0xbd, 0x75, 0x61, 0x9, 0xe6, 0x8c, 0x3d, 0x77, 0xb2,
-	0xed, 0x30, 0x20, 0xe4, 0x0, 0x1d, 0x97, 0xe8, 0xbf, 0xc7,
-	0x0, 0x1b, 0x21, 0xb1, 0x16, 0xe7, 0x41, 0x67, 0x2e, 0xec,
-	0x38, 0xbc, 0xe5, 0x1b, 0xb4, 0x6, 0x23, 0x31, 0x71, 0x1c,
-	0x49, 0xcd, 0x76, 0x4a, 0x76, 0x36, 0x8d, 0xa3, 0x89, 0x8b,
-	0x4a, 0x7a, 0xf4, 0x87, 0xc8, 0x15, 0xf, 0x37, 0x39, 0xf6,
-	0x6d, 0x80, 0x19, 0xef, 0x5c, 0xa8, 0x66, 0xce, 0x1b, 0x16,
-	0x79, 0x21, 0xdf, 0xd7, 0x31, 0x30, 0xc4, 0x21, 0xdd, 0x34,
-	0x5b, 0xd2, 0x1a, 0x2b, 0x3e, 0x5d, 0xf7, 0xea, 0xca, 0x5,
-	0x8e, 0xb7, 0xcb, 0x49, 0x2e, 0xa0, 0xe3, 0xf4, 0xa7, 0x48,
-	0x19, 0x10, 0x9c, 0x4, 0xa7, 0xf4, 0x28, 0x74, 0xc8, 0x6f,
-	0x63, 0x20, 0x2b, 0x46, 0x24, 0x26, 0x19, 0x1d, 0xd1, 0x2c,
-	0x31, 0x6d, 0x5a, 0x29, 0xa2, 0x6, 0xa6, 0xb2, 0x41, 0xcc,
-	0xa, 0x27, 0x96, 0x9, 0x96, 0xac, 0x47, 0x65, 0x78, 0x68,
-	0x51, 0x98, 0xd6, 0xd8, 0xa6, 0x2d, 0xa0, 0xcf, 0xec, 0xe2,
-	0x74, 0xf2, 0x82, 0xe3, 0x97, 0xd9, 0x7e, 0xd4, 0xf8, 0xb,
-	0x70, 0x43, 0x3d, 0xb1, 0x7b, 0x97, 0x80, 0xd6, 0xcb, 0xd7,
-	0x19, 0xbc, 0x63, 0xb, 0xfd, 0x4d, 0x88, 0xfe, 0x67, 0xac,
-	0xb8, 0xcc, 0x50, 0xb7, 0x68, 0xb3, 0x5b, 0xd6, 0x1e, 0x25,
-	0xfc, 0x5f, 0x3c, 0x8d, 0xb1, 0x33, 0x7c, 0xb3, 0x49, 0x1,
-	0x3f, 0x71, 0x55, 0xe, 0x51, 0xba, 0x61, 0x26, 0xfa, 0xea,
-	0xe5, 0xb5, 0xe8, 0xaa, 0xcf, 0xcd, 0x96, 0x9f, 0xd6, 0xc1,
-	0x5f, 0x53, 0x91, 0xad, 0x5, 0xde, 0x20, 0xe7, 0x51, 0xda,
-	0x5b, 0x95, 0x67, 0xed, 0xf4, 0xee, 0x42, 0x65, 0x70, 0x13,
-	0xb, 0x70, 0x14, 0x1c, 0xc9, 0xe0, 0x19, 0xca, 0x5f, 0xf5,
-	0x1d, 0x70, 0x4b, 0x6c, 0x6, 0x74, 0xec, 0xb5, 0x2e, 0x77,
-	0xe1, 0x74, 0xa1, 0xa3, 0x99, 0xa0, 0x85, 0x9e, 0xf1, 0xac,
-	0xd8, 0x7e,
-};
+/** Location of the root public key. These symbols are declared at the start
+ * and end of region where the content of the file CONFIG_AVB_PUBKEY_FILE is
+ * imported into. */
+extern const unsigned char _binary_common_avb_pubkey_start;
+extern const unsigned char _binary_common_avb_pubkey_end;
 
 /**
  * ============================================================================
@@ -589,14 +488,16 @@ static AvbIOResult validate_vbmeta_public_key(AvbOps *ops,
 					      public_key_metadata_length,
 					      bool *out_key_is_trusted)
 {
+	size_t root_pubkey_size = (size_t)&_binary_common_avb_pubkey_end -
+			(size_t)&_binary_common_avb_pubkey_start;
 	if (!public_key_length || !public_key_data || !out_key_is_trusted)
 		return AVB_IO_RESULT_ERROR_IO;
 
 	*out_key_is_trusted = false;
-	if (public_key_length != sizeof(avb_root_pub))
+	if (public_key_length != root_pubkey_size)
 		return AVB_IO_RESULT_ERROR_IO;
 
-	if (memcmp(avb_root_pub, public_key_data, public_key_length) == 0)
+	if (memcmp(&_binary_common_avb_pubkey_start, public_key_data, public_key_length) == 0)
 		*out_key_is_trusted = true;
 
 	return AVB_IO_RESULT_OK;
diff --git a/common/spl/spl_mtd.c b/common/spl/spl_mtd.c
index 0e89b0b54c..395e17a421 100644
--- a/common/spl/spl_mtd.c
+++ b/common/spl/spl_mtd.c
@@ -46,13 +46,17 @@ static int spl_mtd_load_image(struct spl_image_info *spl_image,
 	switch (bootdev->boot_device) {
 	case BOOT_DEVICE_SPINAND:
 		mtd = get_mtd_device_nm("spi-nand0");
-		if (IS_ERR_OR_NULL(mtd))
+		if (IS_ERR_OR_NULL(mtd)) {
 			printf("MTD device %s not found, ret %ld\n", "spi-nand",
 			       PTR_ERR(mtd));
+			err = PTR_ERR(mtd);
+			goto remove_mtd_device;
+		}
 		break;
 	default:
 		puts(SPL_TPL_PROMPT "Unsupported MTD Boot Device!\n");
-		return -EINVAL;
+		err = -EINVAL;
+		goto remove_mtd_device;
 	}
 
 	header = spl_get_load_buffer(0, sizeof(*header));
@@ -60,7 +64,7 @@ static int spl_mtd_load_image(struct spl_image_info *spl_image,
 	err = mtd_read(mtd, spl_mtd_get_uboot_offs(), sizeof(*header),
 		       &ret_len, (void *)header);
 	if (err)
-		return err;
+		goto remove_mtd_device;
 
 	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
@@ -70,25 +74,27 @@ static int spl_mtd_load_image(struct spl_image_info *spl_image,
 		load.filename = NULL;
 		load.bl_len = 1;
 		load.read = spl_mtd_fit_read;
-		return spl_load_simple_fit(spl_image, &load,
-					   spl_mtd_get_uboot_offs(), header);
+		err = spl_load_simple_fit(spl_image, &load,
+					  spl_mtd_get_uboot_offs(), header);
 	} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
 		load.dev = mtd;
 		load.priv = NULL;
 		load.filename = NULL;
 		load.bl_len = 1;
 		load.read = spl_mtd_fit_read;
-		return spl_load_imx_container(spl_image, &load,
-					      spl_mtd_get_uboot_offs());
+		err = spl_load_imx_container(spl_image, &load,
+					     spl_mtd_get_uboot_offs());
 	} else {
 		err = spl_parse_image_header(spl_image, header);
 		if (err)
-			return err;
-		return mtd_read(mtd, spl_mtd_get_uboot_offs(), spl_image->size,
-				&ret_len, (void *)(ulong)spl_image->load_addr);
+			goto remove_mtd_device;
+		err = mtd_read(mtd, spl_mtd_get_uboot_offs(), spl_image->size,
+			       &ret_len, (void *)(ulong)spl_image->load_addr);
 	}
 
-	return -EINVAL;
+remove_mtd_device:
+	mtd_remove(mtd);
+	return err;
 }
 
 SPL_LOAD_IMAGE_METHOD("SPINAND", 0, BOOT_DEVICE_SPINAND, spl_mtd_load_image);
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index fbc7315c40..fed70ab835 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -29,8 +29,6 @@ CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboo
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_MISC_INIT_R is not set
-CONFIG_AVB_VERIFY=y
-CONFIG_ANDROID_AB=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA=y
@@ -40,15 +38,12 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
-CONFIG_CMD_ABOOTIMG=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_BCB=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_AB_SELECT=y
 CONFIG_BOOTP_DNS2=y
 # CONFIG_CMD_PMIC is not set
-CONFIG_CMD_AVB=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
@@ -117,4 +112,3 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_LIBAVB=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 25c1b74e3d..70af855991 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -34,8 +34,6 @@ CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboo
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_MISC_INIT_R is not set
-CONFIG_AVB_VERIFY=y
-CONFIG_ANDROID_AB=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA=y
@@ -43,14 +41,11 @@ CONFIG_SPL_DMA=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_CMD_ADTIMG=y
-CONFIG_CMD_ABOOTIMG=y
 CONFIG_CMD_BCB=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_AB_SELECT=y
 CONFIG_BOOTP_DNS2=y
 # CONFIG_CMD_PMIC is not set
-CONFIG_CMD_AVB=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
@@ -113,4 +108,3 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_LIBAVB=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 8b4939e13a..ae3ac2f566 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -36,8 +36,6 @@ CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboo
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_MISC_INIT_R is not set
-CONFIG_AVB_VERIFY=y
-CONFIG_ANDROID_AB=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA=y
@@ -49,14 +47,11 @@ CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
-CONFIG_CMD_ABOOTIMG=y
 CONFIG_CMD_BCB=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_AB_SELECT=y
 CONFIG_BOOTP_DNS2=y
 # CONFIG_CMD_PMIC is not set
-CONFIG_CMD_AVB=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
@@ -121,4 +116,3 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
-CONFIG_LIBAVB=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index fbad302822..bc02634a43 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_GPIO_SUPPORT=y
@@ -13,6 +14,7 @@ CONFIG_TARGET_AM62A7_A53_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
 CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
 CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
@@ -20,6 +22,8 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-sk"
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -38,25 +42,31 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD_LOAD=y
+CONFIG_SYS_MTD_U_BOOT_OFFS=0x280000
+CONFIG_SPL_NAND_SPI_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
 CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_CMD_BOOTZ is not set
 # CONFIG_CMD_ASKENV is not set
 # CONFIG_CMD_EEPROM is not set
-# CONFIG_CMD_GPIO is not set
-# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_I2C is not set
-# CONFIG_CMD_TIME is not set
-# CONFIG_CMD_EXT4_WRITE is not set
-CONFIG_CMD_DFU=y
-CONFIG_MISC=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_EXT4_WRITE is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=spi-nand0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),98048k@32m(ospi.rootfs),256k@130816k(ospi.phypattern)"
+CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPL_MULTI_DTB_FIT=y
@@ -66,6 +76,7 @@ CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
@@ -75,6 +86,10 @@ CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DFU_MTD=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
 CONFIG_DMA_CHANNELS=y
@@ -99,6 +114,10 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
@@ -116,17 +135,22 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
 CONFIG_SOC_DEVICE_TI_K3=y
 CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_CADENCE_QSPI_PHY=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
@@ -138,5 +162,4 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index f906ec9918..476d91e30e 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -4,7 +4,7 @@ CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SYS_MALLOC_F_LEN=0x7000
 CONFIG_SOC_K3_AM62A7=y
 CONFIG_TARGET_AM62A7_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
@@ -15,15 +15,20 @@ CONFIG_SPL_TEXT_BASE=0x43c00000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk"
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_MISC_INIT_R=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SEPARATE_BSS=y
@@ -34,6 +39,9 @@ CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD_LOAD=y
+CONFIG_SPL_NAND_SPI_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
@@ -58,6 +66,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
@@ -81,6 +90,11 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 CONFIG_SPL_PINCTRL=y
@@ -97,6 +111,9 @@ CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
 CONFIG_SOC_DEVICE_TI_K3=y
 CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index c32826f1db..d9bf9a5b7d 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -74,6 +74,7 @@ CONFIG_CMD_DDRSS=y
 # CONFIG_CMD_REGULATOR is not set
 # CONFIG_CMD_EXT4_WRITE is not set
 CONFIG_CMD_AVB=y
+CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
@@ -97,6 +98,7 @@ CONFIG_CLK_TI_SCI=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_DFU_MTD=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
 CONFIG_DMA_CHANNELS=y
@@ -153,6 +155,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_REMOTEPROC_TI_K3_M4F=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/am62x_lpsk_a53_defconfig b/configs/am62x_lpsk_a53_defconfig
index 57fe09ad8c..2b8158f06b 100644
--- a/configs/am62x_lpsk_a53_defconfig
+++ b/configs/am62x_lpsk_a53_defconfig
@@ -47,6 +47,11 @@ CONFIG_SPL_ETH_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_DRIVERS=y
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_IDENT=y
 CONFIG_SPL_MTD_LOAD=y
 CONFIG_SYS_MTD_U_BOOT_OFFS=0x280000
 CONFIG_SPL_NAND_SPI_SUPPORT=y
@@ -69,8 +74,10 @@ CONFIG_CMD_ABOOTIMG=y
 # CONFIG_CMD_EEPROM is not set
 CONFIG_CMD_BCB=y
 CONFIG_CMD_DM=y
-# CONFIG_CMD_GPIO is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_NAND=y
 # CONFIG_CMD_SPI is not set
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_AB_SELECT=y
@@ -87,6 +94,7 @@ CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
@@ -99,6 +107,7 @@ CONFIG_CLK_TI_SCI=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_DFU_MTD=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
 CONFIG_DMA_CHANNELS=y
@@ -114,6 +123,7 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
+CONFIG_TI_GPMC=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_HS200_SUPPORT=y
@@ -124,7 +134,14 @@ CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_NAND_OMAP_ELM=y
+# CONFIG_SPL_NAND_AM33XX_BCH is not set
 CONFIG_MTD_SPI_NAND=y
+CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0,nand0=omap2-nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),98048k@32m(ospi.rootfs),256k@130816k(ospi.phypattern);omap2-nand.0:2m(NAND.tiboot3),2m(NAND.tispl),2m(NAND.tiboot3.backup),4m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup),-(NAND.file-system)"
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_SOFT_RESET=y
@@ -171,3 +188,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
 CONFIG_LIBAVB=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_SPL_DM_PCA953X=y
diff --git a/configs/am62x_lpsk_r5_defconfig b/configs/am62x_lpsk_r5_defconfig
index eaca19e2ed..ef7ede0519 100644
--- a/configs/am62x_lpsk_r5_defconfig
+++ b/configs/am62x_lpsk_r5_defconfig
@@ -68,6 +68,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
diff --git a/configs/am62x_lpsk_r5_gpmc_defconfig b/configs/am62x_lpsk_r5_gpmc_defconfig
new file mode 100644
index 0000000000..e9e7007120
--- /dev/null
+++ b/configs/am62x_lpsk_r5_gpmc_defconfig
@@ -0,0 +1,119 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x7000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62x-r5-lp-sk"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_DRIVERS=y
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_IDENT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MISC=y
+CONFIG_TI_GPMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
+CONFIG_MTDPARTS_DEFAULT="omap2-nand.0:2m(NAND.tiboot3),2m(NAND.tispl),2m(NAND.tiboot3.backup),4m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup),-(NAND.file-system)"
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_NAND_OMAP_ELM=y
+# CONFIG_SPL_NAND_AM33XX_BCH is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_DM_THERMAL=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 5c424a6d75..03bcd8b28f 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -19,6 +20,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_ENV_OFFSET_REDUND=0x6A0000
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -31,7 +34,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index b268baff42..ebc75fc5b2 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PANIC_HANG=y
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index b5622334ff..a686672e46 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -84,6 +84,7 @@ CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_OF_LIST="k3-j784s4-evm k3-am69-sk"
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
@@ -209,3 +210,4 @@ CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TI_I2C_BOARD_DETECT=y
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 9991676cb1..473c210454 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -68,6 +68,9 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j784s4-r5-evm k3-am69-r5-sk"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
@@ -170,3 +173,4 @@ CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
 CONFIG_SPL_SIZE_LIMIT=0x80000
 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TI_I2C_BOARD_DETECT=y
diff --git a/default.avbpubkey b/default.avbpubkey
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/default.avbpubkey
diff --git a/doc/device-tree-bindings/mtd/ti,elm.yaml b/doc/device-tree-bindings/mtd/ti,elm.yaml
new file mode 100644
index 0000000000..87128c0045
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/ti,elm.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,elm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments Error Location Module (ELM).
+
+maintainers:
+  - Roger Quadros <rogerq@kernel.org>
+
+description:
+  ELM module is used together with GPMC and NAND Flash to detect
+  errors and the location of the error based on BCH algorithms
+  so they can be corrected if possible.
+
+properties:
+  compatible:
+    enum:
+      - ti,am3352-elm
+      - ti,am64-elm
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: Functional clock.
+
+  clock-names:
+    items:
+      - const: fck
+
+  power-domains:
+    maxItems: 1
+
+  ti,hwmods:
+    description:
+      Name of the HWMOD associated with ELM. This is for legacy
+      platforms only.
+    $ref: /schemas/types.yaml#/definitions/string
+    deprecated: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: ti,am64-elm
+    then:
+      required:
+        - clocks
+        - clock-names
+        - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    elm: ecc@0 {
+        compatible = "ti,am3352-elm";
+        reg = <0x0 0x2000>;
+        interrupts = <4>;
+    };
diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c
index 846b0e832b..ec375fd54e 100644
--- a/drivers/mtd/hbmc-am654.c
+++ b/drivers/mtd/hbmc-am654.c
@@ -12,27 +12,32 @@
 
 #define FSS_SYSC_REG	0x4
 
-#define HYPERBUS_CALIB_COUNT 25
+#define HYPERBUS_CALIB_COUNT 64
+#define HYPERBUS_CALIB_MIN_TRIES 48
+#define HYPERBUS_CALIB_SUCCESS_COUNT 4
+#define HYPERBUS_CALIB_SIZE 64
+
+#define HYPERBUS_CFG_DLL_STAT_REG 4
+#define HYPERBUS_CFG_MDLL_LOCK BIT(0)
+#define HYPERBUS_CFG_SDLL_LOCK BIT(1)
+#define HYPERBUS_CFG_RAM_STAT_REG 8
+#define HYPERBUS_CFG_RAM_FIFO_INIT_DONE BIT(0)
 
 struct am654_hbmc_priv {
 	void __iomem *mmiobase;
+	void __iomem *cfgregbase;
 	bool calibrated;
 };
 
-/* Calibrate by looking for "QRY" string within the CFI space */
-static int am654_hyperbus_calibrate(struct udevice *dev)
+/* confirm calibration by looking for "QRY" string within the CFI space */
+static int am654_hyperbus_calibrate_check(struct udevice *dev)
 {
 	struct am654_hbmc_priv *priv = dev_get_priv(dev);
 	int count = HYPERBUS_CALIB_COUNT;
 	int pass_count = 0;
+	int ret = -EIO;
 	u16 qry[3];
 
-	if (priv->calibrated)
-		return 0;
-
-	writew(0xF0, priv->mmiobase);
-	writew(0x98, priv->mmiobase + 0xaa);
-
 	while (count--) {
 		qry[0] = readw(priv->mmiobase + 0x20);
 		qry[1] = readw(priv->mmiobase + 0x22);
@@ -42,13 +47,67 @@ static int am654_hyperbus_calibrate(struct udevice *dev)
 			pass_count++;
 		else
 			pass_count = 0;
-		if (pass_count == 5)
+
+		if (pass_count > HYPERBUS_CALIB_SUCCESS_COUNT)
+			return 0;
+	}
+
+	return ret;
+}
+
+static int am654_hyperbus_calibrate(struct udevice *dev)
+{
+	struct am654_hbmc_priv *priv = dev_get_priv(dev);
+	char verifybuf[HYPERBUS_CALIB_SIZE];
+	char rdbuf[HYPERBUS_CALIB_SIZE];
+	int tries = HYPERBUS_CALIB_COUNT;
+	int pass_count = 0;
+	unsigned int reg;
+	int ret = -EIO;
+
+	if (priv->calibrated)
+		return 0;
+
+	if (!priv->cfgregbase || !priv->mmiobase)
+		return ret;
+
+	reg = readl(priv->cfgregbase + HYPERBUS_CFG_RAM_STAT_REG);
+	if (!(reg & HYPERBUS_CFG_RAM_FIFO_INIT_DONE)) {
+		dev_err(dev, "Hyperbus RAM FIFO init failed\n");
+		return ret;
+	}
+
+	writew(0xF0, priv->mmiobase);
+	writew(0x98, priv->mmiobase + 0xaa);
+
+	/*
+	 * Perform calibration by reading 64 bytes from CFI region and
+	 * compare with previously read data, and ensure Delay Locked Loop(DLL)
+	 * is stabilized.
+	 */
+	while (tries--) {
+		memcpy(rdbuf, priv->mmiobase, HYPERBUS_CALIB_SIZE);
+		if (!memcmp(rdbuf, verifybuf, HYPERBUS_CALIB_SIZE)) {
+			reg = readl(priv->cfgregbase + HYPERBUS_CFG_DLL_STAT_REG);
+			if ((reg & HYPERBUS_CFG_MDLL_LOCK) &&
+			    (reg & HYPERBUS_CFG_SDLL_LOCK))
+				pass_count++;
+			else
+				pass_count = 0;
+		}
+		memcpy(verifybuf, rdbuf, HYPERBUS_CALIB_SIZE);
+		if (pass_count > HYPERBUS_CALIB_SUCCESS_COUNT &&
+		    tries < HYPERBUS_CALIB_MIN_TRIES)
 			break;
 	}
+
+	if (tries > 0)
+		ret = am654_hyperbus_calibrate_check(dev);
+
 	writew(0xF0, priv->mmiobase);
 	writew(0xFF, priv->mmiobase);
 
-	return pass_count == 5;
+	return ret;
 }
 
 static int am654_select_hbmc(struct udevice *dev)
@@ -68,7 +127,9 @@ static int am654_hbmc_probe(struct udevice *dev)
 	struct am654_hbmc_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	priv->mmiobase = devfdt_remap_addr_index(dev, 1);
+	priv->cfgregbase = devfdt_remap_addr_index(dev, 0);
+	priv->mmiobase = devfdt_remap_addr_index(dev, 2);
+
 	if (dev_read_bool(dev, "mux-controls")) {
 		ret = am654_select_hbmc(dev);
 		if (ret) {
@@ -79,9 +140,9 @@ static int am654_hbmc_probe(struct udevice *dev)
 
 	if (!priv->calibrated) {
 		ret = am654_hyperbus_calibrate(dev);
-		if (!ret) {
+		if (IS_ERR_VALUE(ret)) {
 			dev_err(dev, "Calibration Failed\n");
-			return -EIO;
+			return ret;
 		}
 	}
 	priv->calibrated = true;
diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c
index 5418217431..cf749b4a16 100644
--- a/drivers/mtd/mtd-uclass.c
+++ b/drivers/mtd/mtd-uclass.c
@@ -24,6 +24,18 @@ int mtd_probe(struct udevice *dev)
 	return device_probe(dev);
 }
 
+/**
+ * mtd_remove - Remove the device @dev
+ *
+ * @dev: U-Boot device to probe
+ *
+ * @return 0 on success, an error otherwise.
+ */
+int mtd_remove(struct mtd_info *mtd)
+{
+	return device_remove(mtd->dev, DM_REMOVE_NORMAL);
+}
+
 /*
  * Implement a MTD uclass which should include most flash drivers.
  * The uclass private is pointed to mtd_info.
diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c
index 35c6dd1f1b..35a066df41 100644
--- a/drivers/mtd/nand/raw/omap_elm.c
+++ b/drivers/mtd/nand/raw/omap_elm.c
@@ -15,9 +15,14 @@
 #include <common.h>
 #include <asm/io.h>
 #include <linux/errno.h>
-#include <linux/mtd/omap_elm.h>
 #include <asm/arch/hardware.h>
 
+#include <dm.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#include "omap_elm.h"
+
 #define DRIVER_NAME		"omap-elm"
 #define ELM_DEFAULT_POLY (0)
 
@@ -180,6 +185,7 @@ void elm_reset(void)
 		;
 }
 
+#ifdef ELM_BASE
 /**
  * elm_init - Initialize ELM module
  *
@@ -191,3 +197,32 @@ void elm_init(void)
 	elm_cfg = (struct elm *)ELM_BASE;
 	elm_reset();
 }
+#endif
+
+#ifdef CONFIG_SYS_NAND_SELF_INIT
+static int elm_probe(struct udevice *dev)
+{
+#ifndef ELM_BASE
+	struct resource res;
+
+	dev_read_resource(dev, 0, &res);
+	elm_cfg = devm_ioremap(dev, res.start, resource_size(&res));
+	elm_reset();
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id elm_ids[] = {
+	{ .compatible = "ti,am3352-elm" },
+	{ .compatible = "ti,am64-elm" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpmc_elm) = {
+	.name           = DRIVER_NAME,
+	.id             = UCLASS_MTD,
+	.of_match       = elm_ids,
+	.probe          = elm_probe,
+};
+#endif /* CONFIG_SYS_NAND_SELF_INIT */
diff --git a/include/linux/mtd/omap_elm.h b/drivers/mtd/nand/raw/omap_elm.h
index f3db00d55d..a7f7bacb15 100644
--- a/include/linux/mtd/omap_elm.h
+++ b/drivers/mtd/nand/raw/omap_elm.h
@@ -74,6 +74,12 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
 		u32 *error_locations);
 int elm_config(enum bch_level level);
 void elm_reset(void);
+#ifdef ELM_BASE
 void elm_init(void);
+#else
+static inline void elm_init(void)
+{
+}
+#endif
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_ELM_H */
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index f499d8611f..8c0f3a4233 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -13,10 +13,11 @@
 #include <linux/bch.h>
 #include <linux/compiler.h>
 #include <nand.h>
-#include <linux/mtd/omap_elm.h>
 #include <soc.h>
 #include <dm/uclass.h>
 
+#include "omap_elm.h"
+
 #define BADBLOCK_MARKER_LENGTH	2
 #define SECTOR_BYTES		512
 #define ECCSIZE0_SHIFT		12
@@ -1267,6 +1268,15 @@ void board_nand_init(void)
 	struct udevice *dev;
 	int ret;
 
+#ifdef CONFIG_NAND_OMAP_ELM
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_GET_DRIVER(gpmc_elm), &dev);
+	if (ret && ret != -ENODEV) {
+		pr_err("%s: Failed to get ELM device: %d\n", __func__, ret);
+		return;
+	}
+#endif
+
 	ret = uclass_get_device_by_driver(UCLASS_MTD,
 					  DM_GET_DRIVER(gpmc_nand), &dev);
 	if (ret && ret != -ENODEV)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 9ca012d481..0c88310e28 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -51,9 +51,11 @@ static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
 
 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
 {
-	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
-						      spinand->scratchbuf);
 	int ret;
+	struct spi_mem_op op = spinand->ctrl_ops->ops.get_feature;
+
+	op.data.buf.out = spinand->scratchbuf;
+	memset(&op.addr.val, reg, op.addr.nbytes);
 
 	ret = spi_mem_exec_op(spinand->slave, &op);
 	if (ret)
@@ -65,10 +67,11 @@ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
 
 static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
 {
-	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
-						      spinand->scratchbuf);
+	struct spi_mem_op op = spinand->ctrl_ops->ops.set_feature;
 
-	*spinand->scratchbuf = val;
+	op.data.buf.out = spinand->scratchbuf;
+	memset(&op.addr.val, reg, op.addr.nbytes);
+	memset(spinand->scratchbuf, val, op.data.nbytes);
 	return spi_mem_exec_op(spinand->slave, &op);
 }
 
@@ -206,9 +209,9 @@ static int spinand_init_quad_enable(struct spinand_device *spinand)
 	if (!(spinand->flags & SPINAND_HAS_QE_BIT))
 		return 0;
 
-	if (spinand->op_templates.read_cache->data.buswidth == 4 ||
-	    spinand->op_templates.write_cache->data.buswidth == 4 ||
-	    spinand->op_templates.update_cache->data.buswidth == 4)
+	if (spinand->data_ops.read_cache->data.buswidth == 4 ||
+	    spinand->data_ops.write_cache->data.buswidth == 4 ||
+	    spinand->data_ops.update_cache->data.buswidth == 4)
 		enable = true;
 
 	return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
@@ -222,9 +225,9 @@ static int spinand_ecc_enable(struct spinand_device *spinand,
 			       enable ? CFG_ECC_ENABLE : 0);
 }
 
-static int spinand_write_enable_op(struct spinand_device *spinand)
+int spinand_write_enable_op(struct spinand_device *spinand)
 {
-	struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
+	struct spi_mem_op op = spinand->ctrl_ops->ops.write_enable;
 
 	return spi_mem_exec_op(spinand->slave, &op);
 }
@@ -234,15 +237,16 @@ static int spinand_load_page_op(struct spinand_device *spinand,
 {
 	struct nand_device *nand = spinand_to_nand(spinand);
 	unsigned int row = nanddev_pos_to_row(nand, &req->pos);
-	struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
+	struct spi_mem_op op = spinand->ctrl_ops->ops.page_read;
 
+	op.addr.val = row;
 	return spi_mem_exec_op(spinand->slave, &op);
 }
 
 static int spinand_read_from_cache_op(struct spinand_device *spinand,
 				      const struct nand_page_io_req *req)
 {
-	struct spi_mem_op op = *spinand->op_templates.read_cache;
+	struct spi_mem_op op = *spinand->data_ops.read_cache;
 	struct nand_device *nand = spinand_to_nand(spinand);
 	struct mtd_info *mtd = nanddev_to_mtd(nand);
 	struct nand_page_io_req adjreq = *req;
@@ -315,28 +319,34 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
 static int spinand_write_to_cache_op(struct spinand_device *spinand,
 				     const struct nand_page_io_req *req)
 {
-	struct spi_mem_op op = *spinand->op_templates.write_cache;
+	struct spi_mem_op op = *spinand->data_ops.write_cache;
 	struct nand_device *nand = spinand_to_nand(spinand);
 	struct mtd_info *mtd = nanddev_to_mtd(nand);
 	struct nand_page_io_req adjreq = *req;
-	unsigned int nbytes = 0;
-	void *buf = NULL;
+	void *buf = spinand->databuf;
+	unsigned int nbytes;
 	u16 column = 0;
 	int ret;
 
-	memset(spinand->databuf, 0xff,
-	       nanddev_page_size(nand) +
-	       nanddev_per_page_oobsize(nand));
+	/*
+	 * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
+	 * the cache content to 0xFF (depends on vendor implementation), so we
+	 * must fill the page cache entirely even if we only want to program
+	 * the data portion of the page, otherwise we might corrupt the BBM or
+	 * user data previously programmed in OOB area.
+	 */
+	nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
+	memset(spinand->databuf, 0xff, nbytes);
+	adjreq.dataoffs = 0;
+	adjreq.datalen = nanddev_page_size(nand);
+	adjreq.databuf.out = spinand->databuf;
+	adjreq.ooblen = nanddev_per_page_oobsize(nand);
+	adjreq.ooboffs = 0;
+	adjreq.oobbuf.out = spinand->oobbuf;
 
-	if (req->datalen) {
+	if (req->datalen)
 		memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
 		       req->datalen);
-		adjreq.dataoffs = 0;
-		adjreq.datalen = nanddev_page_size(nand);
-		adjreq.databuf.out = spinand->databuf;
-		nbytes = adjreq.datalen;
-		buf = spinand->databuf;
-	}
 
 	if (req->ooblen) {
 		if (req->mode == MTD_OPS_AUTO_OOB)
@@ -347,19 +357,11 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
 		else
 			memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
 			       req->ooblen);
-
-		adjreq.ooblen = nanddev_per_page_oobsize(nand);
-		adjreq.ooboffs = 0;
-		nbytes += nanddev_per_page_oobsize(nand);
-		if (!buf) {
-			buf = spinand->oobbuf;
-			column = nanddev_page_size(nand);
-		}
 	}
 
 	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
 
-	op = *spinand->op_templates.update_cache;
+	op = *spinand->data_ops.update_cache;
 	op.addr.val = column;
 
 	/*
@@ -385,12 +387,12 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
 
 		/*
 		 * We need to use the RANDOM LOAD CACHE operation if there's
-		 * more than one iteration, because the LOAD operation resets
-		 * the cache to 0xff.
+		 * more than one iteration, because the LOAD operation might
+		 * reset the cache to 0xff.
 		 */
 		if (nbytes) {
 			column = op.addr.val;
-			op = *spinand->op_templates.update_cache;
+			op = *spinand->data_ops.update_cache;
 			op.addr.val = column;
 		}
 	}
@@ -403,8 +405,9 @@ static int spinand_program_op(struct spinand_device *spinand,
 {
 	struct nand_device *nand = spinand_to_nand(spinand);
 	unsigned int row = nanddev_pos_to_row(nand, &req->pos);
-	struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row);
+	struct spi_mem_op op = spinand->ctrl_ops->ops.program_execute;
 
+	op.addr.val = row;
 	return spi_mem_exec_op(spinand->slave, &op);
 }
 
@@ -413,8 +416,9 @@ static int spinand_erase_op(struct spinand_device *spinand,
 {
 	struct nand_device *nand = &spinand->base;
 	unsigned int row = nanddev_pos_to_row(nand, pos);
-	struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row);
+	struct spi_mem_op op = spinand->ctrl_ops->ops.block_erase;
 
+	op.addr.val = row;
 	return spi_mem_exec_op(spinand->slave, &op);
 }
 
@@ -465,7 +469,7 @@ static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
 
 static int spinand_reset_op(struct spinand_device *spinand)
 {
-	struct spi_mem_op op = SPINAND_RESET_OP;
+	struct spi_mem_op op = spinand->ctrl_ops->ops.reset;
 	int ret;
 
 	ret = spi_mem_exec_op(spinand->slave, &op);
@@ -833,6 +837,16 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
 	&winbond_spinand_manufacturer,
 };
 
+static const struct spinand_ctrl_ops spinand_default_ctrl_ops =
+			SPINAND_CTRL_OPS(SPINAND_1S,
+					 SPINAND_RESET_OP,
+					 SPINAND_GET_FEATURE_OP(0, NULL),
+					 SPINAND_SET_FEATURE_OP(0, NULL),
+					 SPINAND_WR_EN_DIS_OP(true),
+					 SPINAND_BLK_ERASE_OP(0),
+					 SPINAND_PAGE_READ_OP(0),
+					 SPINAND_PROG_EXEC_OP(0));
+
 static int spinand_manufacturer_detect(struct spinand_device *spinand)
 {
 	unsigned int i;
@@ -867,8 +881,8 @@ static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
 }
 
 static const struct spi_mem_op *
-spinand_select_op_variant(struct spinand_device *spinand,
-			  const struct spinand_op_variants *variants)
+spinand_select_data_op_variant(struct spinand_device *spinand,
+				const struct spinand_op_variants *variants)
 {
 	struct nand_device *nand = spinand_to_nand(spinand);
 	unsigned int i;
@@ -900,6 +914,93 @@ spinand_select_op_variant(struct spinand_device *spinand,
 	return NULL;
 }
 
+static const struct spinand_ctrl_ops *
+spinand_select_ctrl_ops_variant(struct spinand_device *spinand,
+				const struct spinand_ctrl_ops_variants *variants,
+				const enum spinand_protocol protocol)
+{
+	unsigned int i;
+
+	for (i = 0; i < variants->nvariants; i++) {
+		const struct spinand_ctrl_ops *ctrl_ops =
+			&variants->ctrl_ops_list[i];
+
+		if (ctrl_ops->protocol != protocol)
+			continue;
+
+		if (!spi_mem_supports_op(spinand->slave,
+					 &ctrl_ops->ops.reset) ||
+		    !spi_mem_supports_op(spinand->slave,
+					 &ctrl_ops->ops.get_feature) ||
+		    !spi_mem_supports_op(spinand->slave,
+					 &ctrl_ops->ops.set_feature) ||
+		    !spi_mem_supports_op(spinand->slave,
+					 &ctrl_ops->ops.write_enable) ||
+		    !spi_mem_supports_op(spinand->slave,
+					 &ctrl_ops->ops.block_erase) ||
+		    !spi_mem_supports_op(spinand->slave,
+					 &ctrl_ops->ops.page_read) ||
+		    !spi_mem_supports_op(spinand->slave,
+					 &ctrl_ops->ops.program_execute))
+			continue;
+
+		return ctrl_ops;
+	}
+
+	return NULL;
+}
+
+static bool spinand_op_is_octal_dtr(const struct spi_mem_op *op)
+{
+	return  op->cmd.buswidth == 8 && op->cmd.dtr &&
+		op->addr.buswidth == 8 && op->addr.dtr &&
+		op->data.buswidth == 8 && op->data.dtr;
+}
+
+static int spinand_init_octal_dtr_enable(struct spinand_device *spinand)
+{
+	struct udevice *dev = spinand->slave->dev;
+	const struct spinand_ctrl_ops *octal_dtr_ctrl_ops;
+	int ret;
+
+	if (!(spinand->flags & SPINAND_HAS_OCTAL_DTR_BIT))
+		return 0;
+
+	if (!(spinand_op_is_octal_dtr(spinand->data_ops.read_cache) &&
+	      spinand_op_is_octal_dtr(spinand->data_ops.write_cache) &&
+	      spinand_op_is_octal_dtr(spinand->data_ops.update_cache)))
+		return 0;
+
+	octal_dtr_ctrl_ops = spinand_select_ctrl_ops_variant(spinand,
+					spinand->desc_entry->ctrl_ops_variants,
+					SPINAND_8D);
+
+	if (!octal_dtr_ctrl_ops)
+		return 0;
+
+	if (!spinand->manufacturer->ops->change_protocol) {
+		dev_info(dev,
+			 "Missing ->change_mode(), unable to switch mode\n");
+		return -EOPNOTSUPP;
+	}
+
+	ret = spinand->manufacturer->ops->change_protocol(spinand, SPINAND_8D);
+	if (ret) {
+		dev_err(dev,
+			"Failed to enable Octal DTR SPI mode (err = %d)\n",
+			ret);
+		return ret;
+	}
+
+	spinand->protocol = SPINAND_8D;
+	spinand->ctrl_ops = octal_dtr_ctrl_ops;
+
+	dev_dbg(dev,
+		"%s SPI NAND switched to Octal DTR SPI (8D-8D-8D) mode\n",
+		spinand->manufacturer->name);
+	return 0;
+}
+
 /**
  * spinand_match_and_init() - Try to find a match between a device ID and an
  *			      entry in a spinand_info table
@@ -934,24 +1035,25 @@ int spinand_match_and_init(struct spinand_device *spinand,
 		spinand->eccinfo = table[i].eccinfo;
 		spinand->flags = table[i].flags;
 		spinand->select_target = table[i].select_target;
+		spinand->desc_entry = &table[i];
 
-		op = spinand_select_op_variant(spinand,
-					       info->op_variants.read_cache);
+		op = spinand_select_data_op_variant(spinand,
+					info->data_ops_variants.read_cache);
 		if (!op)
 			return -ENOTSUPP;
 
-		spinand->op_templates.read_cache = op;
+		spinand->data_ops.read_cache = op;
 
-		op = spinand_select_op_variant(spinand,
-					       info->op_variants.write_cache);
+		op = spinand_select_data_op_variant(spinand,
+					info->data_ops_variants.write_cache);
 		if (!op)
 			return -ENOTSUPP;
 
-		spinand->op_templates.write_cache = op;
+		spinand->data_ops.write_cache = op;
 
-		op = spinand_select_op_variant(spinand,
-					       info->op_variants.update_cache);
-		spinand->op_templates.update_cache = op;
+		op = spinand_select_data_op_variant(spinand,
+					info->data_ops_variants.update_cache);
+		spinand->data_ops.update_cache = op;
 
 		return 0;
 	}
@@ -1035,6 +1137,9 @@ static int spinand_init(struct spinand_device *spinand)
 	if (!spinand->scratchbuf)
 		return -ENOMEM;
 
+	spinand->protocol = SPINAND_1S;
+	spinand->ctrl_ops = &spinand_default_ctrl_ops;
+
 	ret = spinand_detect(spinand);
 	if (ret)
 		goto err_free_bufs;
@@ -1085,6 +1190,10 @@ static int spinand_init(struct spinand_device *spinand)
 			goto err_free_bufs;
 	}
 
+	ret = spinand_init_octal_dtr_enable(spinand);
+	if (ret)
+		goto err_manuf_cleanup;
+
 	ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
 	if (ret)
 		goto err_manuf_cleanup;
@@ -1188,26 +1297,25 @@ err_spinand_cleanup:
 	return ret;
 }
 
-#ifndef __UBOOT__
 static int spinand_remove(struct udevice *slave)
 {
-	struct spinand_device *spinand;
+	struct spinand_device *spinand = dev_get_priv(slave);
 	struct mtd_info *mtd;
-	int ret;
 
-	spinand = spi_mem_get_drvdata(slave);
 	mtd = spinand_to_mtd(spinand);
 	free(mtd->name);
 
+#ifndef __UBOOT__
 	ret = mtd_device_unregister(mtd);
 	if (ret)
 		return ret;
-
+#endif
 	spinand_cleanup(spinand);
 
 	return 0;
 }
 
+#ifndef __UBOOT__
 static const struct spi_device_id spinand_ids[] = {
 	{ .name = "spi-nand" },
 	{ /* sentinel */ },
@@ -1249,4 +1357,6 @@ U_BOOT_DRIVER(spinand) = {
 	.of_match = spinand_ids,
 	.priv_auto_alloc_size = sizeof(struct spinand_device),
 	.probe = spinand_probe,
+	.remove = spinand_remove,
+	.flags = DM_FLAG_OS_PREPARE,
 };
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index 4f8b8de3a9..d8eb12c382 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -13,12 +13,26 @@
 #include <linux/kernel.h>
 #endif
 #include <linux/bitops.h>
+#include <linux/delay.h>
 #include <linux/mtd/spinand.h>
 
 #define SPINAND_MFR_WINBOND		0xEF
+#define WINBOND_ID_LEN			3
 
 #define WINBOND_CFG_BUF_READ		BIT(3)
 
+/* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/
+#define WINBOND_VCR_IO_MODE_OCTAL_DTR	0xE7
+#define WINBOND_VCR_IO_MODE_SINGLE_STR	0xFF
+#define WINBOND_VCR_IO_MODE_ADDR	0x00
+
+/* Use 12 dummy clk cycles for using Octal DTR SPI at max 120MHZ */
+#define WINBOND_VCR_DUMMY_CLK_COUNT	12
+#define WINBOND_VCR_DUMMY_CLK_DEFAULT	0xFF
+#define WINBOND_VCR_DUMMY_CLK_ADDR	0x01
+
+#define WINBOND_POR_DELAY_US		1000
+
 static SPINAND_OP_VARIANTS(read_cache_variants_w25m02gv,
 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -36,15 +50,36 @@ static SPINAND_OP_VARIANTS(update_cache_variants_w25m02gv,
 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
 
 static SPINAND_OP_VARIANTS(read_cache_variants_w35n01jw,
+		SPINAND_PAGE_READ_FROM_CACHE_OCTALIO_DTR_OP(0, 24, NULL, 0),
 		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
 		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
 
 static SPINAND_OP_VARIANTS(write_cache_variants_w35n01jw,
+		SPINAND_PROG_LOAD_OCTALIO_DTR(true, 0, NULL, 0),
 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
 
 static SPINAND_OP_VARIANTS(update_cache_variants_w35n01jw,
+		SPINAND_PROG_LOAD_OCTALIO_DTR(false, 0, NULL, 0),
 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
 
+static SPINAND_CTRL_OPS_VARIANTS(ctrl_ops_variants_w35n01jw,
+		SPINAND_CTRL_OPS(SPINAND_8D,
+				 SPINAND_RESET_OP_OCTAL_DTR,
+				 SPINAND_GET_FEATURE_OP_OCTAL_DTR(0, NULL),
+				 SPINAND_SET_FEATURE_OP_OCTAL_DTR(0, NULL),
+				 SPINAND_WR_EN_DIS_OP_OCTAL_DTR(true),
+				 SPINAND_BLK_ERASE_OP_OCTAL_DTR(0),
+				 SPINAND_PAGE_READ_OP_OCTAL_DTR(0),
+				 SPINAND_PROG_EXEC_OP_OCTAL_DTR(0)),
+		SPINAND_CTRL_OPS(SPINAND_1S,
+				 SPINAND_RESET_OP,
+				 SPINAND_GET_FEATURE_OP(0, NULL),
+				 SPINAND_SET_FEATURE_OP(0, NULL),
+				 SPINAND_WR_EN_DIS_OP(true),
+				 SPINAND_BLK_ERASE_OP(0),
+				 SPINAND_PAGE_READ_OP(0),
+				 SPINAND_PROG_EXEC_OP(0)));
+
 static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
 				  struct mtd_oob_region *region)
 {
@@ -141,9 +176,9 @@ static const struct spinand_info winbond_spinand_table[] = {
 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_w35n01jw,
 					      &write_cache_variants_w35n01jw,
 					      &update_cache_variants_w35n01jw),
-		     0,
-		     SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)),
-
+		     SPINAND_HAS_OCTAL_DTR_BIT | SPINAND_HAS_CR_FEAT_BIT,
+		     SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
+		     SPINAND_INFO_CTRL_OPS_VARIANTS(&ctrl_ops_variants_w35n01jw)),
 };
 
 /**
@@ -189,9 +224,180 @@ static int winbond_spinand_init(struct spinand_device *spinand)
 	return 0;
 }
 
+/**
+ * winbond_write_vcr_op() - write values onto the volatile configuration
+ *			    registers (VCR)
+ * @spinand: the spinand device
+ * @reg: the address of the particular reg in the VCR to be written on
+ * @val: the value to be written on the reg in the VCR
+ *
+ * Volatile configuration registers are a separate set of configuration
+ * registers, i.e. they differ from the status registers SR-1/2/3. A different
+ * SPI instruction is required to write to these registers. Any changes
+ * to the Volatile Configuration Register get transferred directly to
+ * the Internal Configuration Register and instantly reflect on the
+ * device operation.
+ */
+static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val)
+{
+	int ret;
+	struct spi_mem_op op =
+		SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1),
+			   SPI_MEM_OP_ADDR(3, reg, 1),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(1, spinand->scratchbuf, 1));
+
+	*spinand->scratchbuf = val;
+
+	ret = spinand_write_enable_op(spinand);
+	if (ret)
+		return ret;
+
+	ret = spi_mem_exec_op(spinand->slave, &op);
+	if (ret)
+		return ret;
+
+	/*
+	 * Write VCR operation doesn't set the busy bit in SR, so can't perform
+	 * a status poll. Minimum time of 50ns is needed to complete the write.
+	 * So, give thrice the minimum required delay.
+	 */
+	ndelay(150);
+	return 0;
+}
+
+static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand)
+{
+	int ret;
+	struct spi_mem_op op;
+
+	ret = winbond_write_vcr_op(spinand, WINBOND_VCR_DUMMY_CLK_ADDR,
+				   WINBOND_VCR_DUMMY_CLK_COUNT);
+	if (ret)
+		return ret;
+
+	ret = winbond_write_vcr_op(spinand, WINBOND_VCR_IO_MODE_ADDR,
+				   WINBOND_VCR_IO_MODE_OCTAL_DTR);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x9f9f, 8, SPI_MEM_OP_DTR),
+			   SPI_MEM_OP_NO_ADDR,
+			   SPI_MEM_OP_DUMMY(16, 8, SPI_MEM_OP_DTR),
+			   SPI_MEM_OP_DATA_IN(SPINAND_MAX_ID_LEN,
+					      spinand->scratchbuf, 8,
+					      SPI_MEM_OP_DTR));
+
+	ret = spi_mem_exec_op(spinand->slave, &op);
+	if (ret)
+		return ret;
+
+	if (memcmp(spinand->scratchbuf, spinand->id.data + 1, WINBOND_ID_LEN))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int winbond_spinand_octal_dtr_disable(struct spinand_device *spinand)
+{
+	int ret;
+	struct spi_mem_op op =
+		SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x8181, 8, SPI_MEM_OP_DTR),
+			   SPI_MEM_OP_ADDR(4, WINBOND_VCR_IO_MODE_ADDR, 8,
+					   SPI_MEM_OP_DTR),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(2, spinand->scratchbuf, 8,
+					       SPI_MEM_OP_DTR));
+
+	*spinand->scratchbuf = WINBOND_VCR_IO_MODE_SINGLE_STR;
+
+	ret = spinand_write_enable_op(spinand);
+	if (ret)
+		return ret;
+
+	ret = spi_mem_exec_op(spinand->slave, &op);
+	if (ret)
+		return ret;
+
+	ret = winbond_write_vcr_op(spinand, WINBOND_VCR_DUMMY_CLK_ADDR,
+				   WINBOND_VCR_DUMMY_CLK_DEFAULT);
+	if (ret)
+		return ret;
+
+	/* Read flash ID to make sure the switch was successful. */
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),
+			   SPI_MEM_OP_NO_ADDR,
+			   SPI_MEM_OP_DUMMY(1, 1),
+			   SPI_MEM_OP_DATA_IN(SPINAND_MAX_ID_LEN,
+					      spinand->scratchbuf, 1));
+
+	ret = spi_mem_exec_op(spinand->slave, &op);
+	if (ret)
+		return ret;
+
+	if (memcmp(spinand->scratchbuf, spinand->id.data + 1, WINBOND_ID_LEN))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int winbond_change_spi_protocol(struct spinand_device *spinand,
+				       const enum spinand_protocol protocol)
+{
+	if (spinand->protocol == protocol)
+		return 0;
+
+	switch (spinand->protocol) {
+	case SPINAND_1S:
+		if (protocol == SPINAND_8D)
+			return winbond_spinand_octal_dtr_enable(spinand);
+		break;
+
+	case SPINAND_8D:
+		if (protocol == SPINAND_1S)
+			return winbond_spinand_octal_dtr_disable(spinand);
+		break;
+
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return -EOPNOTSUPP;
+}
+
+static void winbond_spinand_cleanup(struct spinand_device *spinand)
+{
+	struct spi_mem_op op;
+
+	/* Perform Power-On-Reset if the device is in Octal-DTR mode */
+	if (spinand->protocol == SPINAND_8D) {
+		op = (struct spi_mem_op)
+			SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x6666, 8, SPI_MEM_OP_DTR),
+				   SPI_MEM_OP_NO_ADDR,
+				   SPI_MEM_OP_NO_DUMMY,
+				   SPI_MEM_OP_NO_DATA);
+		spi_mem_exec_op(spinand->slave, &op);
+
+		op = (struct spi_mem_op)
+			SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x9999, 8, SPI_MEM_OP_DTR),
+				   SPI_MEM_OP_NO_ADDR,
+				   SPI_MEM_OP_NO_DUMMY,
+				   SPI_MEM_OP_NO_DATA);
+		spi_mem_exec_op(spinand->slave, &op);
+
+		/* PoR can take max 500 us to complete, so sleep for 1000 us*/
+		udelay(WINBOND_POR_DELAY_US);
+	}
+}
+
 static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
 	.detect = winbond_spinand_detect,
 	.init = winbond_spinand_init,
+	.change_protocol = winbond_change_spi_protocol,
+	.cleanup = winbond_spinand_cleanup,
 };
 
 const struct spinand_manufacturer winbond_spinand_manufacturer = {
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index d9aa17ab0e..5a42280619 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -72,6 +72,16 @@ config REMOTEPROC_TI_K3_R5F
 	  on various TI K3 family of SoCs through the remote processor
 	  framework.
 
+config REMOTEPROC_TI_K3_M4F
+	bool "TI K3 M4F remoteproc support"
+	select REMOTEPROC
+	depends on ARCH_K3
+	depends on TI_SCI_PROTOCOL
+	help
+	  Say y here to support TI's M4F remote processor subsystems
+	  on various TI K3 family of SoCs through the remote processor
+	  framework.
+
 config REMOTEPROC_TI_POWER
 	bool "Support for TI Power processor"
 	select REMOTEPROC
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index fbe9c172bc..f418298979 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
 obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
+obj-$(CONFIG_REMOTEPROC_TI_K3_M4F) += ti_k3_m4_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
 obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
diff --git a/drivers/remoteproc/ti_k3_m4_rproc.c b/drivers/remoteproc/ti_k3_m4_rproc.c
new file mode 100644
index 0000000000..90f0f7c44a
--- /dev/null
+++ b/drivers/remoteproc/ti_k3_m4_rproc.c
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 M4 Remoteproc driver
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ *	Hari Nagalla <hnagalla@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <dm/device_compat.h>
+#include <linux/err.h>
+#include <linux/sizes.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include "ti_sci_proc.h"
+#include <mach/security.h>
+
+#define KEYSTONE_RPROC_LOCAL_ADDRESS_MASK	(SZ_16M - 1)
+
+/**
+ * struct k3_m4_mem - internal memory structure
+ * @cpu_addr: MPU virtual address of the memory region
+ * @bus_addr: Bus address used to access the memory region
+ * @dev_addr: Device address from remoteproc view
+ * @size: Size of the memory region
+ */
+struct k3_m4_mem {
+	void __iomem *cpu_addr;
+	phys_addr_t bus_addr;
+	phys_addr_t dev_addr;
+	size_t size;
+};
+
+/**
+ * struct k3_m4_mem_data - memory definitions for a DSP
+ * @name: name for this memory entry
+ * @dev_addr: device address for the memory entry
+ */
+struct k3_m4_mem_data {
+	const char *name;
+	const u32 dev_addr;
+};
+
+/**
+ * struct k3_m4_boot_data - internal data structure used for boot
+ * @boot_align_addr: Boot vector address alignment granularity
+ * @uses_lreset: Flag to denote the need for local reset management
+ */
+struct k3_m4_boot_data {
+	u32 boot_align_addr;
+	bool uses_lreset;
+};
+
+/**
+ * struct k3_m4_privdata - Structure representing Remote processor data.
+ * @rproc_rst:		rproc reset control data
+ * @tsp:		Pointer to TISCI proc contrl handle
+ * @data:		Pointer to DSP specific boot data structure
+ * @mem:		Array of available memories
+ * @num_mem:		Number of available memories
+ */
+struct k3_m4_privdata {
+	struct reset_ctl m4_rst;
+	struct ti_sci_proc tsp;
+	struct k3_m4_boot_data *data;
+	struct k3_m4_mem *mem;
+	int num_mems;
+};
+
+/*
+ * The C66x DSP cores have a local reset that affects only the CPU, and a
+ * generic module reset that powers on the device and allows the DSP internal
+ * memories to be accessed while the local reset is asserted. This function is
+ * used to release the global reset on C66x DSPs to allow loading into the DSP
+ * internal RAMs. This helper function is invoked in k3_dsp_load() before any
+ * actual firmware loading and is undone only in k3_dsp_stop(). The local reset
+ * on C71x cores is a no-op and the global reset cannot be released on C71x
+ * cores until after the firmware images are loaded, so this function does
+ * nothing for C71x cores.
+ */
+static int k3_m4_prepare(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	struct k3_m4_boot_data *data = m4->data;
+	int ret;
+
+	/* local reset is no-op on M4 processors */
+	if (!data->uses_lreset)
+		return 0;
+
+	ret = ti_sci_proc_power_domain_on(&m4->tsp);
+	if (ret)
+		dev_err(dev, "cannot enable internal RAM loading, ret = %d\n",
+			ret);
+
+	return ret;
+}
+
+/*
+ * This function is the counterpart to k3_dsp_prepare() and is used to assert
+ * the global reset on C66x DSP cores (no-op for C71x DSP cores). This completes
+ * the second step of powering down the C66x DSP cores. The cores themselves
+ * are halted through the local reset in first step. This function is invoked
+ * in k3_dsp_stop() after the local reset is asserted.
+ */
+static int k3_m4_unprepare(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	struct k3_m4_boot_data *data = m4->data;
+
+	/* local reset is no-op on C71x processors */
+	if (!data->uses_lreset)
+		return 0;
+
+	return ti_sci_proc_power_domain_off(&m4->tsp);
+}
+
+/**
+ * k3_dsp_load() - Load up the Remote processor image
+ * @dev:	rproc device pointer
+ * @addr:	Address at which image is available
+ * @size:	size of the image
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_m4_load(struct udevice *dev, ulong addr, ulong size)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	struct k3_m4_boot_data *data = m4->data;
+	u32 boot_vector;
+	void *image_addr = (void *)addr;
+	int ret;
+
+	dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
+	ret = ti_sci_proc_request(&m4->tsp);
+	if (ret)
+		return ret;
+
+	ret = k3_m4_prepare(dev);
+	if (ret) {
+		dev_err(dev, "DSP prepare failed for core %d\n",
+			m4->tsp.proc_id);
+		goto proc_release;
+	}
+
+	ti_secure_image_post_process(&image_addr, &size);
+
+	ret = rproc_elf_load_image(dev, addr, size);
+	if (ret < 0) {
+		dev_err(dev, "Loading elf failed %d\n", ret);
+		goto unprepare;
+	}
+
+	boot_vector = rproc_elf_get_boot_addr(dev, addr);
+
+	dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector);
+
+unprepare:
+	if (ret)
+		k3_m4_unprepare(dev);
+proc_release:
+	ti_sci_proc_release(&m4->tsp);
+	return ret;
+}
+
+/**
+ * k3_dsp_start() - Start the remote processor
+ * @dev:	rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_m4_start(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	struct k3_m4_boot_data *data = m4->data;
+	int ret;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	ret = ti_sci_proc_request(&m4->tsp);
+	if (ret)
+		return ret;
+
+	if (!data->uses_lreset) {
+		ret = ti_sci_proc_power_domain_on(&m4->tsp);
+		if (ret)
+			goto proc_release;
+	}
+
+	ret = reset_deassert(&m4->m4_rst);
+	if (ret) {
+		if (!data->uses_lreset)
+			ti_sci_proc_power_domain_off(&m4->tsp);
+	}
+
+proc_release:
+	ti_sci_proc_release(&m4->tsp);
+
+	return ret;
+}
+
+static int k3_m4_stop(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	ti_sci_proc_request(&m4->tsp);
+	reset_assert(&m4->m4_rst);
+	ti_sci_proc_power_domain_off(&m4->tsp);
+	ti_sci_proc_release(&m4->tsp);
+
+	return 0;
+}
+
+/**
+ * k3_dsp_init() - Initialize the remote processor
+ * @dev:	rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_m4_init(struct udevice *dev)
+{
+	dev_dbg(dev, "%s\n", __func__);
+
+	return 0;
+}
+
+static int k3_m4_reset(struct udevice *dev)
+{
+	dev_dbg(dev, "%s\n", __func__);
+
+	return 0;
+}
+
+static void *k3_m4_da_to_va(struct udevice *dev, ulong da, ulong len)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	phys_addr_t bus_addr, dev_addr;
+	void __iomem *va = NULL;
+	size_t size;
+	u32 offset;
+	int i;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (len <= 0)
+		return NULL;
+
+	for (i = 0; i < m4->num_mems; i++) {
+		bus_addr = m4->mem[i].bus_addr;
+		dev_addr = m4->mem[i].dev_addr;
+		size = m4->mem[i].size;
+
+		if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
+			offset = da - dev_addr;
+			va = m4->mem[i].cpu_addr + offset;
+			dev_dbg(dev, "%s da=0x%x : va=0x%x \n", __func__, da, va);
+			return (__force void *)va;
+		}
+
+		if (da >= bus_addr && (da + len) <= (bus_addr + size)) {
+			offset = da - bus_addr;
+			va = m4->mem[i].cpu_addr + offset;
+			dev_dbg(dev, "%s da=0x%x : va=0x%x \n", __func__, da, va);
+			return (__force void *)va;
+		}
+	}
+
+	/* Assume it is DDR region and return da */
+	dev_dbg(dev, "%s DDR da=0x%x \n", __func__, da);
+	return map_physmem(da, len, MAP_NOCACHE);
+}
+
+static const struct dm_rproc_ops k3_m4_ops = {
+	.init = k3_m4_init,
+	.load = k3_m4_load,
+	.start = k3_m4_start,
+	.stop = k3_m4_stop,
+	.reset = k3_m4_reset,
+	.device_to_virt = k3_m4_da_to_va,
+};
+
+static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp)
+{
+	u32 ids[2];
+	int ret;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci");
+	if (IS_ERR(tsp->sci)) {
+		dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
+		return PTR_ERR(tsp->sci);
+	}
+
+	ret = dev_read_u32_array(dev, "ti,sci-proc-ids", ids, 2);
+	if (ret) {
+		dev_err(dev, "Proc IDs not populated %d\n", ret);
+		return ret;
+	}
+
+	tsp->ops = &tsp->sci->ops.proc_ops;
+	tsp->proc_id = ids[0];
+	tsp->host_id = ids[1];
+	tsp->dev_id = dev_read_u32_default(dev, "ti,sci-dev-id",
+					   TI_SCI_RESOURCE_NULL);
+	if (tsp->dev_id == TI_SCI_RESOURCE_NULL) {
+		dev_err(dev, "Device ID not populated %d\n", ret);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static const struct k3_m4_mem_data am6_m4_mems[] = {
+	{ .name = "iram", .dev_addr = 0x0 },
+	{ .name = "dram", .dev_addr = 0x30000 },
+};
+
+static int k3_m4_of_get_memories(struct udevice *dev)
+{
+	// static const char * const mem_names[] = {"iram", "dram"};
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	int i;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	// m4->num_mems = ARRAY_SIZE(mem_names);
+	m4->num_mems = ARRAY_SIZE(am6_m4_mems);
+	m4->mem = calloc(m4->num_mems, sizeof(*m4->mem));
+	if (!m4->mem)
+		return -ENOMEM;
+
+	for (i = 0; i < m4->num_mems; i++) {
+		m4->mem[i].bus_addr = dev_read_addr_size_name(dev,
+							      am6_m4_mems[i].name,
+					  (fdt_addr_t *)&m4->mem[i].size);
+		if (m4->mem[i].bus_addr == FDT_ADDR_T_NONE) {
+			dev_err(dev, "%s bus address not found\n",
+				am6_m4_mems[i].name);
+			return -EINVAL;
+		}
+		m4->mem[i].cpu_addr = map_physmem(m4->mem[i].bus_addr,
+						  m4->mem[i].size,
+						  MAP_NOCACHE);
+		m4->mem[i].dev_addr = am6_m4_mems[i].dev_addr;
+
+		dev_dbg(dev, "memory %8s: bus addr %pa size 0x%zx va %p da %pa\n",
+			am6_m4_mems[i].name, &m4->mem[i].bus_addr,
+			m4->mem[i].size, m4->mem[i].cpu_addr,
+			&m4->mem[i].dev_addr);
+	}
+
+	return 0;
+}
+
+/**
+ * k3_of_to_priv() - generate private data from device tree
+ * @dev:	corresponding k3 dsp processor device
+ * @dsp:	pointer to driver specific private data
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_m4_of_to_priv(struct udevice *dev, struct k3_m4_privdata *m4)
+{
+	int ret;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	ret = reset_get_by_index(dev, 0, &m4->m4_rst);
+	if (ret) {
+		dev_err(dev, "reset_get() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ti_sci_proc_of_to_priv(dev, &m4->tsp);
+	if (ret)
+		return ret;
+
+	ret =  k3_m4_of_get_memories(dev);
+	if (ret)
+		return ret;
+
+	m4->data = (struct k3_m4_boot_data *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+/**
+ * k3_dsp_probe() - Basic probe
+ * @dev:	corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_m4_probe(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4;
+	int ret;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	m4 = dev_get_priv(dev);
+
+	ret = k3_m4_of_to_priv(dev, m4);
+	if (ret) {
+		dev_dbg(dev, "%s: Probe failed with error %d\n", __func__, ret);
+		return ret;
+	}
+
+	/*
+	 * The DSP local resets are deasserted by default on Power-On-Reset.
+	 * Assert the local resets to ensure the DSPs don't execute bogus code
+	 * in .load() callback when the module reset is released to support
+	 * internal memory loading. This is needed for C66x DSPs, and is a
+	 * no-op on C71x DSPs.
+	 */
+	reset_assert(&m4->m4_rst);
+
+	dev_dbg(dev, "Remoteproc successfully probed\n");
+
+	return 0;
+}
+
+static int k3_m4_remove(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+
+	free(m4->mem);
+
+	return 0;
+}
+
+static const struct k3_m4_boot_data m4_data = {
+	.boot_align_addr = SZ_1K,
+	.uses_lreset = true,
+};
+
+static const struct udevice_id k3_m4_ids[] = {
+	{ .compatible = "ti,am64-m4fss", .data = (ulong)&m4_data, },
+	{}
+};
+
+U_BOOT_DRIVER(k3_m4) = {
+	.name = "k3_m4",
+	.of_match = k3_m4_ids,
+	.id = UCLASS_REMOTEPROC,
+	.ops = &k3_m4_ops,
+	.probe = k3_m4_probe,
+	.remove = k3_m4_remove,
+	.priv_auto_alloc_size = sizeof(struct k3_m4_privdata),
+};
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 485fe40113..c7b6178a12 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -831,13 +831,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
 	 * which is unsupported on some flash devices during register
 	 * reads, prefer STIG mode for such small reads.
 	 */
-		if (!op->addr.nbytes ||
-		    op->data.nbytes < CQSPI_STIG_DATA_LEN_MAX)
+		if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			mode = CQSPI_STIG_READ;
 		else
 			mode = CQSPI_READ;
 	} else {
-		if (!op->addr.nbytes || !op->data.buf.out)
+		if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 			mode = CQSPI_STIG_WRITE;
 		else
 			mode = CQSPI_WRITE;
@@ -877,8 +876,15 @@ static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
 {
 	bool all_true, all_false;
 
-	all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
-		   op->data.dtr;
+	/*
+	 * op->dummy.dtr is required for converting nbytes into ncycles.
+	 * Also, don't check the dtr field of the op phase having zero nbytes.
+	 */
+	all_true = op->cmd.dtr &&
+		   (!op->addr.nbytes || op->addr.dtr) &&
+		   (!op->dummy.nbytes || op->dummy.dtr) &&
+		   (!op->data.nbytes || op->data.dtr);
+
 	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
 		    !op->data.dtr;
 
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 86cd67ae9c..0f6941ec3f 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -327,7 +327,14 @@ static int cadence_qspi_set_protocol(struct cadence_spi_platdata *plat,
 {
 	int ret;
 
-	plat->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
+	/*
+	 * For an op to be DTR, cmd phase along with every other non-empty
+	 * phase should have dtr field set to 1. If an op phase has zero
+	 * nbytes, ignore its dtr field; otherwise, check its dtr field.
+	 */
+	plat->dtr = op->cmd.dtr &&
+		    (!op->addr.nbytes || op->addr.dtr) &&
+		    (!op->data.nbytes || op->data.dtr);
 
 	ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
 	if (ret < 0)
@@ -632,6 +639,8 @@ static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 	if (!cadence_qspi_wait_idle(reg_base))
 		return -EIO;
 
+	/* Flush the CMDCTRL reg after the execution */
+	writel(0, reg_base + CQSPI_REG_CMDCTRL);
 	return 0;
 }
 
@@ -718,11 +727,6 @@ int cadence_qspi_apb_command_read(struct cadence_spi_platdata *plat,
 	unsigned int dummy_clk;
 	u8 opcode;
 
-	if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
-		printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
-		return -EINVAL;
-	}
-
 	if (plat->dtr)
 		opcode = op->cmd.opcode >> 8;
 	else
@@ -730,6 +734,18 @@ int cadence_qspi_apb_command_read(struct cadence_spi_platdata *plat,
 
 	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 
+	/* setup ADDR BIT field */
+	if (op->addr.nbytes) {
+		writel(op->addr.val, plat->regbase + CQSPI_REG_CMDADDRESS);
+		/*
+		 * address bytes are zero indexed
+		 */
+		reg |= (((op->addr.nbytes - 1) &
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
+		reg |= CQSPI_REG_CMDCTRL_ADDR_EN;
+	}
+
 	/* Set up dummy cycles. */
 	dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr);
 	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
@@ -745,18 +761,6 @@ int cadence_qspi_apb_command_read(struct cadence_spi_platdata *plat,
 	reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 		<< CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 
-	/* setup ADDR BIT field */
-	if (op->addr.nbytes) {
-		writel(op->addr.val, plat->regbase + CQSPI_REG_CMDADDRESS);
-		/*
-		 * address bytes are zero indexed
-		 */
-		reg |= (((op->addr.nbytes - 1) &
-			  CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
-			  CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
-		reg |= CQSPI_REG_CMDCTRL_ADDR_EN;
-	}
-
 	status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 	if (status != 0)
 		return status;
@@ -805,25 +809,12 @@ int cadence_qspi_apb_command_write(struct cadence_spi_platdata *plat,
 	unsigned int reg = 0;
 	unsigned int wr_data;
 	unsigned int wr_len;
+	unsigned int dummy_clk;
 	unsigned int txlen = op->data.nbytes;
 	const void *txbuf = op->data.buf.out;
 	void *reg_base = plat->regbase;
-	u32 addr;
 	u8 opcode;
 
-	/* Reorder address to SPI bus order if only transferring address */
-	if (!txlen) {
-		addr = cpu_to_be32(op->addr.val);
-		if (op->addr.nbytes == 3)
-			addr >>= 8;
-		txbuf = &addr;
-		txlen = op->addr.nbytes;
-	}
-
-	if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
-		printf("QSPI: Invalid input arguments txlen %u\n", txlen);
-		return -EINVAL;
-	}
 
 	if (plat->dtr)
 		opcode = op->cmd.opcode >> 8;
@@ -832,6 +823,27 @@ int cadence_qspi_apb_command_write(struct cadence_spi_platdata *plat,
 
 	reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 
+	/* setup ADDR BIT field */
+	if (op->addr.nbytes) {
+		writel(op->addr.val, plat->regbase + CQSPI_REG_CMDADDRESS);
+		/*
+		 * address bytes are zero indexed
+		 */
+		reg |= (((op->addr.nbytes - 1) &
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
+			  CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
+		reg |= CQSPI_REG_CMDCTRL_ADDR_EN;
+	}
+
+	/* Set up dummy cycles. */
+	dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr);
+	if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
+		return -ENOTSUPP;
+
+	if (dummy_clk)
+		reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
+		     << CQSPI_REG_CMDCTRL_DUMMY_LSB;
+
 	if (txlen) {
 		/* writing data = yes */
 		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h
index 6c3a139cae..3685271d7e 100644
--- a/include/configs/am62ax_evm.h
+++ b/include/configs/am62ax_evm.h
@@ -91,6 +91,28 @@
 		"${bootdir}/${name_fit}\0"				\
 	"partitions=" PARTS_DEFAULT
 
+#define EXTRA_ENV_AM62A7_BOARD_SETTINGS_OSPI_NAND				\
+	"nbootpart=ospi.rootfs\0"					\
+	"nbootvolume=ubi0:rootfs\0"					\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"ubi_init=ubi part ${nbootpart}; ubifsmount ${nbootvolume};\0"	\
+	"args_ospi_nand=setenv bootargs console=${console} "			\
+		"${optargs} ubi.mtd=${nbootpart} "			\
+		"root=${nbootvolume} rootfstype=ubifs\0"			\
+	"init_ospi_nand=run args_all args_ospi_nand ubi_init\0"			\
+	"get_fdt_ospi_nand=ubifsload ${fdtaddr} ${bootdir}/${fdtfile};\0"	\
+	"get_overlay_ospi_nand="						\
+		"fdt address ${fdtaddr};"				\
+		"fdt resize 0x100000;"					\
+		"for overlay in $name_overlays;"			\
+		"do;"							\
+		"ubifsload ${dtboaddr} ${bootdir}/${overlay} && "	\
+		"fdt apply ${dtboaddr};"				\
+		"done;\0"						\
+	"get_kern_ospi_nand=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"	\
+	"get_fit_ospi_nand=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0"
+
 #if defined(CONFIG_TARGET_AM62A7_A53_EVM)
 #if defined(DEFAULT_RPROCS)
 #undef DEFAULT_RPROCS
@@ -104,7 +126,8 @@
 	DFU_ALT_INFO_MMC \
 	DFU_ALT_INFO_EMMC \
 	DFU_ALT_INFO_RAM \
-	DFU_ALT_INFO_OSPI
+	DFU_ALT_INFO_OSPI \
+	DFU_ALT_INFO_OSPI_NAND
 
 /* Incorporate settings into the U-Boot environment */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
@@ -113,6 +136,7 @@
 	DEFAULT_MMC_TI_ARGS						\
 	EXTRA_ENV_AM62A7_BOARD_SETTINGS					\
 	EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC				\
+	EXTRA_ENV_AM62A7_BOARD_SETTINGS_OSPI_NAND			\
 	EXTRA_ENV_RPROC_SETTINGS					\
 	EXTRA_ENV_DFUARGS
 
diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h
index f66e616693..97bd7c1fd7 100644
--- a/include/configs/am62x_evm.h
+++ b/include/configs/am62x_evm.h
@@ -13,11 +13,56 @@
 #include <config_distro_bootcmd.h>
 #include <environment/ti/mmc.h>
 #include <environment/ti/k3_dfu.h>
+#include <environment/ti/k3_rproc.h>
 
 /* DDR Configuration */
 #define CONFIG_SYS_SDRAM_BASE1		0x880000000
 #define CONFIG_SYS_BOOTM_LEN            SZ_64M
 
+/* NAND support */
+
+/* NAND Device Configuration : MT29F8G08ADAFAH4 chip */
+#define CONFIG_SYS_NAND_PAGE_SIZE	4096
+#define CONFIG_SYS_NAND_OOBSIZE		256
+#define CONFIG_SYS_NAND_BLOCK_SIZE      SZ_256K
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+/* NAND Driver config */
+#define CONFIG_SPL_NAND_INIT	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
+
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE         512
+#define CONFIG_SYS_NAND_ECCBYTES        14
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x200000	/* tispl.bin partition */
+#else
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x600000	/* u-boot.img partition */
+#endif
+
+#define CONFIG_SYS_NAND_MAX_CHIPS       1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+
+#define CONFIG_SYS_NAND_BASE            0x51000000
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_SYS_ENV_SECT_SIZE        CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+
+/*-- end NAND config --*/
+
 #ifdef CONFIG_SYS_K3_SPL_ATF
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"tispl.bin"
 #endif
@@ -140,11 +185,70 @@
 		"run get_fdt_usb;"					\
 		"run run_kern\0"
 
+#ifdef CONFIG_TARGET_AM625_A53_EVM
+#define EXTRA_ENV_AM625_BOARD_SETTINGS_MTD				\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#else
+#define EXTRA_ENV_AM625_BOARD_SETTINGS_MTD
+#endif
+
+#define EXTRA_ENV_AM625_BOARD_SETTINGS_OSPI_NAND			\
+	"nbootpart=ospi.rootfs\0"					\
+	"nbootvolume=ubi0:rootfs\0"					\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"ubi_init=ubi part ${nbootpart}; ubifsmount ${nbootvolume};\0"	\
+	"args_ospi_nand=setenv bootargs console=${console} "		\
+		"${optargs} ubi.mtd=${nbootpart} "			\
+		"root=${nbootvolume} rootfstype=ubifs\0"		\
+	"init_ospi_nand=run args_all args_ospi_nand ubi_init\0"		\
+	"get_fdt_ospi_nand=ubifsload ${fdtaddr} ${bootdir}/${fdtfile};\0"	\
+	"get_overlay_ospi_nand="					\
+		"fdt address ${fdtaddr};"				\
+		"fdt resize 0x100000;"					\
+		"for overlay in $name_overlays;"			\
+		"do;"							\
+		"ubifsload ${dtboaddr} ${bootdir}/${overlay} && "	\
+		"fdt apply ${dtboaddr};"				\
+		"done;\0"						\
+	"get_kern_ospi_nand=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"	\
+	"get_fit_ospi_nand=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0"
+
+#define EXTRA_ENV_AM625_BOARD_SETTINGS_NAND				\
+	"nbootpart=NAND.file-system\0"					\
+	"nbootvolume=ubi0:rootfs\0"					\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"ubi_init=ubi part ${nbootpart}; ubifsmount ${nbootvolume};\0"	\
+	"args_nand=setenv bootargs console=${console} "			\
+		"${optargs} ubi.mtd=${nbootpart} "			\
+		"root=${nbootvolume} rootfstype=ubifs\0"			\
+	"init_nand=run args_all args_nand ubi_init\0"			\
+	"get_fdt_nand=ubifsload ${fdtaddr} ${bootdir}/${fdtfile};\0"	\
+	"get_overlay_nand="						\
+		"fdt address ${fdtaddr};"				\
+		"fdt resize 0x100000;"					\
+		"for overlay in $name_overlays;"			\
+		"do;"							\
+		"ubifsload ${dtboaddr} ${bootdir}/${overlay} && "	\
+		"fdt apply ${dtboaddr};"				\
+		"done;\0"						\
+	"get_kern_nand=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"	\
+	"get_fit_nand=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0"
+
+#if defined(CONFIG_TARGET_AM625_A53_EVM)
+#if defined(DEFAULT_RPROCS)
+#undef DEFAULT_RPROCS
+#endif
+#define DEFAULT_RPROCS ""						\
+		"0 /lib/firmware/am62-mcu-m4f0_0-fw "
+#endif
 
 #define BOOTENV_DEV_LINUX(devtypeu, devtypel, instance) \
 	"bootcmd_linux=" \
 		"if test \"${android_boot}\" -eq 0; then;" \
-			"run findfdt; run envboot; run init_${boot};" \
+			"run findfdt; run envboot; run init_${boot}; run boot_rprocs;" \
 			"if test ${boot_fit} -eq 1; then;" \
 				"run get_fit_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit;"\
 			"else;" \
@@ -400,11 +504,17 @@
 
 #endif
 
+#ifdef CONFIG_TARGET_AM625_A53_EVM
 #define EXTRA_ENV_DFUARGS \
 	DFU_ALT_INFO_MMC \
 	DFU_ALT_INFO_EMMC \
 	DFU_ALT_INFO_RAM \
-	DFU_ALT_INFO_OSPI
+	DFU_ALT_INFO_OSPI \
+	DFU_ALT_INFO_OSPI_NAND \
+	DFU_ALT_INFO_GPMC_NAND
+#else
+#define EXTRA_ENV_DFUARGS
+#endif
 
 /* Incorporate settings into the U-Boot environment */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
@@ -414,8 +524,11 @@
 	DEFAULT_MMC_TI_ARGS						\
 	EXTRA_ENV_AM625_BOARD_SETTINGS					\
 	EXTRA_ENV_AM625_BOARD_SETTINGS_MMC				\
+	EXTRA_ENV_AM625_BOARD_SETTINGS_NAND				\
 	EXTRA_ENV_DFUARGS						\
-	EXTRA_ENV_AM625_BOARD_SETTING_USBMSC
+	EXTRA_ENV_AM625_BOARD_SETTING_USBMSC				\
+	EXTRA_ENV_AM625_BOARD_SETTINGS_OSPI_NAND			\
+	EXTRA_ENV_RPROC_SETTINGS
 
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
diff --git a/include/configs/j784s4_evm.h b/include/configs/j784s4_evm.h
index 7502aa72d0..eb609100b0 100644
--- a/include/configs/j784s4_evm.h
+++ b/include/configs/j784s4_evm.h
@@ -66,8 +66,12 @@
 /* U-Boot general configuration */
 #define EXTRA_ENV_J784S4_BOARD_SETTINGS					\
 	"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"	\
-	"findfdt="							\
-		"setenv name_fdt ${default_device_tree};"		\
+	"findfdt="                                                      \
+		"setenv name_fdt ${default_device_tree};"               \
+		"if test $board_name = am69-sk; then "           \
+			"setenv name_fdt k3-am69-sk.dtb; fi;" \
+		"if test $board_name = j784s4; then "                    \
+			"setenv name_fdt k3-j784s4-evm.dtb; fi;" \
 		"setenv fdtfile ${name_fdt}\0"				\
 	"name_kern=Image\0"						\
 	"console=ttyS2,115200n8\0"					\
diff --git a/include/environment/ti/k3_dfu.h b/include/environment/ti/k3_dfu.h
index 0df8baf3c7..15cd8f2621 100644
--- a/include/environment/ti/k3_dfu.h
+++ b/include/environment/ti/k3_dfu.h
@@ -60,4 +60,23 @@
 	"tispl.bin ram 0x80080000 0x200000;" \
 	"u-boot.img ram 0x81000000 0x400000\0" \
 
+#define DFU_ALT_INFO_OSPI_NAND \
+	"dfu_alt_info_ospi_nand=" \
+	"tiboot3.bin raw 0x0 0x080000;" \
+	"tispl.bin raw 0x080000 0x200000;" \
+	"u-boot.img raw 0x280000 0x400000;" \
+	"u-boot-env raw 0x680000 0x040000;" \
+	"rootfs raw 0x2000000 0x5fc0000;" \
+	"phypattern raw 0x7fc0000 0x40000\0"
+
+#define DFU_ALT_INFO_GPMC_NAND \
+       "dfu_alt_info_gpmc_nand=" \
+       "tiboot3.bin raw 0x0 0x00200000;" \
+       "tispl.bin raw 0x00200000 0x00200000;" \
+       "tiboot3.backup raw 0x00400000 0x00200000;"\
+       "u-boot.img raw 0x00600000 0x00400000;" \
+       "u-boot-env raw 0x00a00000 0x00040000;" \
+       "u-boot-env.backup raw 0x00a40000 0x00040000;" \
+       "file-system raw 0x00a80000 0x3f580000\0" \
+
 #endif /* __TI_DFU_H */
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 88bacde91e..5c89bd1dcc 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -33,12 +33,25 @@
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
+#define SPINAND_RESET_OP_OCTAL_DTR					\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0xffff, 8, SPI_MEM_OP_DTR),	\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
 #define SPINAND_WR_EN_DIS_OP(enable)					\
 	SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1),		\
 		   SPI_MEM_OP_NO_ADDR,					\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
+#define SPINAND_WR_EN_DIS_OP_OCTAL_DTR(enable)				\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, (enable) ? 0x0606 : 0x0404, 8,	\
+				      SPI_MEM_OP_DTR),			\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
 #define SPINAND_READID_OP(ndummy, buf, len)				\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
 		   SPI_MEM_OP_NO_ADDR,					\
@@ -51,24 +64,48 @@
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_DATA_OUT(1, valptr, 1))
 
+#define SPINAND_SET_FEATURE_OP_OCTAL_DTR(reg, valptr)			\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x1f1f, 8, SPI_MEM_OP_DTR),	\
+		   SPI_MEM_OP_ADDR(2, reg, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(2, valptr, 8, SPI_MEM_OP_DTR))
+
 #define SPINAND_GET_FEATURE_OP(reg, valptr)				\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1),				\
 		   SPI_MEM_OP_ADDR(1, reg, 1),				\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_DATA_IN(1, valptr, 1))
 
+#define SPINAND_GET_FEATURE_OP_OCTAL_DTR(reg, valptr)			\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x0f0f, 8, SPI_MEM_OP_DTR),	\
+		   SPI_MEM_OP_ADDR(2, reg, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_DUMMY(14, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_DATA_IN(2, valptr, 8, SPI_MEM_OP_DTR))
+
 #define SPINAND_BLK_ERASE_OP(addr)					\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1),				\
 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
+#define SPINAND_BLK_ERASE_OP_OCTAL_DTR(addr)				\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0xd8d8, 8, SPI_MEM_OP_DTR),	\
+		   SPI_MEM_OP_ADDR(2, addr, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
 #define SPINAND_PAGE_READ_OP(addr)					\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1),				\
 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
+#define SPINAND_PAGE_READ_OP_OCTAL_DTR(addr)				\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x1313, 8, SPI_MEM_OP_DTR),	\
+		   SPI_MEM_OP_ADDR(2, addr, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len)	\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),		\
 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
@@ -99,18 +136,37 @@
 		   SPI_MEM_OP_DUMMY(ndummy, 4),				\
 		   SPI_MEM_OP_DATA_IN(len, buf, 4))
 
+#define SPINAND_PAGE_READ_FROM_CACHE_OCTALIO_DTR_OP(addr, ndummy, buf, len) \
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x9d9d, 8, SPI_MEM_OP_DTR),	\
+		   SPI_MEM_OP_ADDR(2, addr, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_DUMMY(ndummy, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_DATA_IN(len, buf, 8, SPI_MEM_OP_DTR))
+
 #define SPINAND_PROG_EXEC_OP(addr)					\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1),				\
 		   SPI_MEM_OP_ADDR(3, addr, 1),				\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
+#define SPINAND_PROG_EXEC_OP_OCTAL_DTR(addr)				\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, 0x1010, 8, SPI_MEM_OP_DTR),	\
+		   SPI_MEM_OP_ADDR(2, addr, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
 #define SPINAND_PROG_LOAD(reset, addr, buf, len)			\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1),		\
 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_DATA_OUT(len, buf, 1))
 
+#define SPINAND_PROG_LOAD_OCTALIO_DTR(reset, addr, buf, len)		\
+	SPI_MEM_OP(SPI_MEM_OP_EXT_CMD(2, reset ? 0x0202 : 0x8484, 8,	\
+				      SPI_MEM_OP_DTR),			\
+		   SPI_MEM_OP_ADDR(2, addr, 8, SPI_MEM_OP_DTR),		\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(len, buf, 8, SPI_MEM_OP_DTR))
+
 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len)			\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1),		\
 		   SPI_MEM_OP_ADDR(2, addr, 1),				\
@@ -118,6 +174,18 @@
 		   SPI_MEM_OP_DATA_OUT(len, buf, 4))
 
 /**
+ * enum spinand_protocol - List of SPI protocols to denote the op protocol and
+ *			   SPI NAND flash IO modes.
+ */
+enum spinand_protocol {
+	SPINAND_1S,
+	SPINAND_2S,
+	SPINAND_4S,
+	SPINAND_8S,
+	SPINAND_8D,
+};
+
+/**
  * Standard SPI NAND flash commands
  */
 #define SPINAND_CMD_PROG_LOAD_X4		0x32
@@ -177,6 +245,7 @@ struct spinand_id {
  *	    that properties of the NAND chip (spinand->base.memorg and
  *	    spinand->base.eccreq) have been filled
  * @init: initialize a SPI NAND device
+ * @change_protocol: switch the SPI NAND flash to a specific SPI protocol
  * @cleanup: cleanup a SPI NAND device
  *
  * Each SPI NAND manufacturer driver should implement this interface so that
@@ -185,6 +254,8 @@ struct spinand_id {
 struct spinand_manufacturer_ops {
 	int (*detect)(struct spinand_device *spinand);
 	int (*init)(struct spinand_device *spinand);
+	int (*change_protocol)(struct spinand_device *spinand,
+			       const enum spinand_protocol protocol);
 	void (*cleanup)(struct spinand_device *spinand);
 };
 
@@ -229,6 +300,46 @@ struct spinand_op_variants {
 		.nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) /	\
 			sizeof(struct spi_mem_op),			\
 	}
+struct spinand_ctrl_ops {
+	const struct {
+		struct spi_mem_op reset;
+		struct spi_mem_op get_feature;
+		struct spi_mem_op set_feature;
+		struct spi_mem_op write_enable;
+		struct spi_mem_op block_erase;
+		struct spi_mem_op page_read;
+		struct spi_mem_op program_execute;
+	} ops;
+	const enum spinand_protocol protocol;
+};
+
+#define SPINAND_CTRL_OPS(__protocol, __reset, __get_feature, __set_feature,	\
+			 __write_enable, __block_erase, __page_read,		\
+			 __program_execute)					\
+	{									\
+		.ops = {							\
+			.reset = __reset,					\
+			.get_feature = __get_feature,				\
+			.set_feature = __set_feature,				\
+			.write_enable = __write_enable,				\
+			.block_erase = __block_erase,				\
+			.page_read = __page_read,				\
+			.program_execute = __program_execute,			\
+		},								\
+		.protocol = __protocol,						\
+	}
+
+struct spinand_ctrl_ops_variants {
+	const struct spinand_ctrl_ops *ctrl_ops_list;
+	unsigned int nvariants;
+};
+
+#define SPINAND_CTRL_OPS_VARIANTS(name, ...)					\
+	const struct spinand_ctrl_ops_variants name = {				\
+		.ctrl_ops_list = (struct spinand_ctrl_ops[]){ __VA_ARGS__ },	\
+		.nvariants = sizeof((struct spinand_ctrl_ops[]){ __VA_ARGS__ })/\
+			     sizeof(struct spinand_ctrl_ops),			\
+	}
 
 /**
  * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
@@ -247,6 +358,7 @@ struct spinand_ecc_info {
 
 #define SPINAND_HAS_QE_BIT		BIT(0)
 #define SPINAND_HAS_CR_FEAT_BIT		BIT(1)
+#define SPINAND_HAS_OCTAL_DTR_BIT	BIT(2)
 
 /**
  * struct spinand_info - Structure used to describe SPI NAND chips
@@ -256,10 +368,10 @@ struct spinand_ecc_info {
  * @memorg: memory organization
  * @eccreq: ECC requirements
  * @eccinfo: on-die ECC info
- * @op_variants: operations variants
- * @op_variants.read_cache: variants of the read-cache operation
- * @op_variants.write_cache: variants of the write-cache operation
- * @op_variants.update_cache: variants of the update-cache operation
+ * @data_ops_variants: operations variants for page read/writes
+ * @data_ops_variants.read_cache: variants of the read-cache operation
+ * @data_ops_variants.write_cache: variants of the write-cache operation
+ * @data_ops_variants.update_cache: variants of the update-cache operation
  * @select_target: function used to select a target/die. Required only for
  *		   multi-die chips
  *
@@ -277,7 +389,9 @@ struct spinand_info {
 		const struct spinand_op_variants *read_cache;
 		const struct spinand_op_variants *write_cache;
 		const struct spinand_op_variants *update_cache;
-	} op_variants;
+	} data_ops_variants;
+
+	const struct spinand_ctrl_ops_variants *ctrl_ops_variants;
 	int (*select_target)(struct spinand_device *spinand,
 			     unsigned int target);
 };
@@ -289,6 +403,9 @@ struct spinand_info {
 		.update_cache = __update,				\
 	}
 
+#define SPINAND_INFO_CTRL_OPS_VARIANTS(__ctrl_ops_variants)		\
+	.ctrl_ops_variants = __ctrl_ops_variants
+
 #define SPINAND_ECCINFO(__ooblayout, __get_status)			\
 	.eccinfo = {							\
 		.ooblayout = __ooblayout,				\
@@ -298,14 +415,14 @@ struct spinand_info {
 #define SPINAND_SELECT_TARGET(__func)					\
 	.select_target = __func,
 
-#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants,	\
-		     __flags, ...)					\
+#define SPINAND_INFO(__model, __id, __memorg, __eccreq,			\
+		     __data_ops_variants, __flags, ...)			\
 	{								\
 		.model = __model,					\
 		.devid = __id,						\
 		.memorg = __memorg,					\
 		.eccreq = __eccreq,					\
-		.op_variants = __op_variants,				\
+		.data_ops_variants = __data_ops_variants,		\
 		.flags = __flags,					\
 		__VA_ARGS__						\
 	}
@@ -317,15 +434,19 @@ struct spinand_info {
  * @lock: lock used to serialize accesses to the NAND
  * @id: NAND ID as returned by READ_ID
  * @flags: NAND flags
- * @op_templates: various SPI mem op templates
- * @op_templates.read_cache: read cache op template
- * @op_templates.write_cache: write cache op template
- * @op_templates.update_cache: update cache op template
+ * @data_ops: various SPI mem op templates for reading and writing on pages
+ * @data_ops.read_cache: read cache op template
+ * @data_ops.write_cache: write cache op template
+ * @data_ops.update_cache: update cache op template
+ * @ctrl_ops: various SPI mem op templates for handling the flash device, i.e.
+ *	      non page-read/write ops.
  * @select_target: select a specific target/die. Usually called before sending
  *		   a command addressing a page or an eraseblock embedded in
  *		   this die. Only required if your chip exposes several dies
  * @cur_target: currently selected target/die
  * @eccinfo: on-die ECC information
+ * @protocol: SPI IO protocol in operation. Update on successful transition into
+ *	      a different SPI IO protocol.
  * @cfg_cache: config register cache. One entry per die
  * @databuf: bounce buffer for data
  * @oobbuf: bounce buffer for OOB data
@@ -334,6 +455,8 @@ struct spinand_info {
  *		passed in spi_mem_op be DMA-able, so we can't based the bufs on
  *		the stack
  * @manufacturer: SPI NAND manufacturer information
+ * @desc_entry: pointer to device description entry in the manufacturer's
+ *		spinand_info tables
  * @priv: manufacturer private data
  */
 struct spinand_device {
@@ -351,7 +474,9 @@ struct spinand_device {
 		const struct spi_mem_op *read_cache;
 		const struct spi_mem_op *write_cache;
 		const struct spi_mem_op *update_cache;
-	} op_templates;
+	} data_ops;
+
+	const struct spinand_ctrl_ops *ctrl_ops;
 
 	int (*select_target)(struct spinand_device *spinand,
 			     unsigned int target);
@@ -359,11 +484,14 @@ struct spinand_device {
 
 	struct spinand_ecc_info eccinfo;
 
+	enum spinand_protocol protocol;
+
 	u8 *cfg_cache;
 	u8 *databuf;
 	u8 *oobbuf;
 	u8 *scratchbuf;
 	const struct spinand_manufacturer *manufacturer;
+	const struct spinand_info *desc_entry;
 	void *priv;
 };
 
@@ -431,5 +559,6 @@ int spinand_match_and_init(struct spinand_device *dev,
 
 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
+int spinand_write_enable_op(struct spinand_device *spinand);
 
 #endif /* __LINUX_MTD_SPINAND_H */
diff --git a/include/mtd.h b/include/mtd.h
index b0f8693386..926ee2075e 100644
--- a/include/mtd.h
+++ b/include/mtd.h
@@ -9,6 +9,7 @@
 #include <linux/mtd/mtd.h>
 
 int mtd_probe(struct udevice *dev);
+int mtd_remove(struct mtd_info *mtd);
 int mtd_probe_devices(void);
 
 void board_mtdparts_default(const char **mtdids, const char **mtdparts);
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 1719fe0820..8255c54c6e 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -13,44 +13,59 @@
 
 struct udevice;
 
-#define SPI_MEM_OP_CMD(__opcode, __buswidth)			\
+#define SPI_MEM_OP_DTR .dtr = 1
+
+#define SPI_MEM_OP_CMD(__opcode, __buswidth, ...)		\
 	{							\
 		.buswidth = __buswidth,				\
 		.opcode = __opcode,				\
 		.nbytes = 1,					\
+		__VA_ARGS__					\
+	}
+
+#define SPI_MEM_OP_EXT_CMD(__nbytes, __opcode, __buswidth, ...)	\
+	{							\
+		.buswidth = __buswidth,				\
+		.opcode = __opcode,				\
+		.nbytes = __nbytes,				\
+		__VA_ARGS__					\
 	}
 
-#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth)		\
+#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth, ...)	\
 	{							\
 		.nbytes = __nbytes,				\
 		.val = __val,					\
 		.buswidth = __buswidth,				\
+		__VA_ARGS__					\
 	}
 
 #define SPI_MEM_OP_NO_ADDR	{ }
 
-#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth)			\
+#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth, ...)		\
 	{							\
 		.nbytes = __nbytes,				\
 		.buswidth = __buswidth,				\
+		__VA_ARGS__					\
 	}
 
 #define SPI_MEM_OP_NO_DUMMY	{ }
 
-#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth)		\
+#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth, ...)	\
 	{							\
 		.dir = SPI_MEM_DATA_IN,				\
 		.nbytes = __nbytes,				\
 		.buf.in = __buf,				\
 		.buswidth = __buswidth,				\
+		__VA_ARGS__					\
 	}
 
-#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth)	\
+#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth, ...)	\
 	{							\
 		.dir = SPI_MEM_DATA_OUT,			\
 		.nbytes = __nbytes,				\
 		.buf.out = __buf,				\
 		.buswidth = __buswidth,				\
+		__VA_ARGS__					\
 	}
 
 #define SPI_MEM_OP_NO_DATA	{ }