diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2023-03-16 17:07:01 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2023-03-20 15:15:39 +0100 |
| commit | 1599df538a93a3848f82b21b4ac6f1f96abd676e (patch) | |
| tree | a2174dff15fb5de8cd6f0d0ae4fa855840f8d169 | |
| parent | 0f4c9db2f5b6b9b9590a57679ece07772d29fa52 (diff) | |
verdin-am62: enable the 32kHz clock input
Set the LFOSC0 mode to bypass. This makes the external provided
32kHz clock available.
A noteable consumer is the AM62x internal RTC.
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | board/toradex/verdin-am62/verdin-am62.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index f1c0614e07..e718eb0030 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -226,6 +226,18 @@ void spl_board_init(void) writel(val, CTRLMMR_USB1_PHY_CTRL); /* We use the 32k FOUT from the Epson RX8130CE RTC chip */ + /* In WKUP_LFOSC0 clear the power down bit and set the bypass bit + * The bypass bit is required as we provide a CMOS clock signal and + * the power down seems to be required also in the bypass case + * despite of the datasheet stating otherwise + */ + /* Compare with the AM62 datasheet, + * Table 7-21. LFXOSC Modes of Operation + */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL; + val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL; + writel(val, MCU_CTRL_LFXOSC_CTRL); /* Make sure to mux up to take the SoC 32k from the LFOSC input */ writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); |