arm: dts: k3-am625-verdin-lpddr4-1600MTs: update to sysconfig v0.09.05

Update LPDDR4 RAM timings to what the online AM62x SysConfig DDR
Subsystem Register Configuration Tool v0.09.05 generates. From its
README:

v9.04:
-changed wrlvl_delay_early_threshold=0x100 to allow write leveling
 to complete successfully for wider array of layouts
-add cmm output
-LPDDR4: phy_rddqs_latency_adjust changed to 0 default
 recommendation (this value gets optimized during training)
-LPDDR4: optimized training loops to support 1 operating frequency
-LPDDR4/DDR4: optimized IO calibration configuration based on
 operating frequency
-LPDDR4/DDR4: optimized internal calibration clock based on
 operating frequency
-LPDDR4: changed default MR22 ODTE-CS=1
-LPDDR4: changed rx_ctle_cs default to No Boost
-AM62x dual rank support
-updated to use sysconfig v1.15
-public release for AM62A LPDDR4 support

v9.05:
-cleaned up supported frequencies

Upstream-Status: Pending

Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

1 files changed, 16 insertions, 20 deletions

diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
index 83aba268e5..fbe9670856 100644
--- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -1,18 +1,20 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.80
- * Fri Jan 20 2023 15:18:33 GMT+0100 (Central European Standard Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.05
+ * Fri Jan 27 2023 15:03:47 GMT+0100 (Central European Standard Time)
  * DDR Type: LPDDR4
- * F0 = 50MHz    F1 = 800MHz    F2 = 800MHz
+ * F0 = 50MHz    F1 = NA     F2 = 800MHz
  * Density (per channel): 16Gb
+ * Write DBI: Enable
  * Number of Ranks: 1
- */
+*/
 
-#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
 
+
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
 #define DDRSS_CTL_2_DATA 0x00000000
@@ -283,10 +285,10 @@
 #define DDRSS_CTL_267_DATA 0x0000000F
 #define DDRSS_CTL_268_DATA 0x0000000F
 #define DDRSS_CTL_269_DATA 0x00000000
-#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00001000
 #define DDRSS_CTL_271_DATA 0x00000015
 #define DDRSS_CTL_272_DATA 0x00000015
-#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000010
 #define DDRSS_CTL_274_DATA 0x00000015
 #define DDRSS_CTL_275_DATA 0x00000015
 #define DDRSS_CTL_276_DATA 0x00000020
@@ -448,7 +450,7 @@
 #define DDRSS_PI_9_DATA 0x00000000
 #define DDRSS_PI_10_DATA 0x00000000
 #define DDRSS_PI_11_DATA 0x00000002
-#define DDRSS_PI_12_DATA 0x00000007
+#define DDRSS_PI_12_DATA 0x00000005
 #define DDRSS_PI_13_DATA 0x00010001
 #define DDRSS_PI_14_DATA 0x08000000
 #define DDRSS_PI_15_DATA 0x00010300
@@ -740,7 +742,7 @@
 #define DDRSS_PI_301_DATA 0x00000000
 #define DDRSS_PI_302_DATA 0x00000000
 #define DDRSS_PI_303_DATA 0x00000000
-#define DDRSS_PI_304_DATA 0x00000F27
+#define DDRSS_PI_304_DATA 0x00100F27
 #define DDRSS_PI_305_DATA 0x00000000
 #define DDRSS_PI_306_DATA 0x00000024
 #define DDRSS_PI_307_DATA 0x00000012
@@ -764,7 +766,7 @@
 #define DDRSS_PI_325_DATA 0x00000000
 #define DDRSS_PI_326_DATA 0x00000000
 #define DDRSS_PI_327_DATA 0x00000000
-#define DDRSS_PI_328_DATA 0x00000F27
+#define DDRSS_PI_328_DATA 0x00100F27
 #define DDRSS_PI_329_DATA 0x00000000
 #define DDRSS_PI_330_DATA 0x00000024
 #define DDRSS_PI_331_DATA 0x00000012
@@ -884,10 +886,7 @@
 #define DDRSS_PHY_100_DATA 0x000001CC
 #define DDRSS_PHY_101_DATA 0x20100200
 #define DDRSS_PHY_102_DATA 0x00000005
-
-//#define DDRSS_PHY_103_DATA 0x76543210
 #define DDRSS_PHY_103_DATA 0x56704132 // [Byte 0 SWIZZLE] PHY_DQ_DM_SWIZZLE0_0
-
 #define DDRSS_PHY_104_DATA 0x00000008
 #define DDRSS_PHY_105_DATA 0x034C034C
 #define DDRSS_PHY_106_DATA 0x034C034C
@@ -904,7 +903,7 @@
 #define DDRSS_PHY_117_DATA 0x00800080
 #define DDRSS_PHY_118_DATA 0x00800080
 #define DDRSS_PHY_119_DATA 0x01800080
-#define DDRSS_PHY_120_DATA 0x01A00001
+#define DDRSS_PHY_120_DATA 0x01000000
 #define DDRSS_PHY_121_DATA 0x00000000
 #define DDRSS_PHY_122_DATA 0x00000000
 #define DDRSS_PHY_123_DATA 0x00080200
@@ -1143,10 +1142,7 @@
 #define DDRSS_PHY_356_DATA 0x000001CC
 #define DDRSS_PHY_357_DATA 0x20100200
 #define DDRSS_PHY_358_DATA 0x00000005
-
-//#define DDRSS_PHY_359_DATA 0x76543210
 #define DDRSS_PHY_359_DATA 0x03415762 // [Byte 1 SWIZZLE] PHY_DQ_DM_SWIZZLE0_1
-
 #define DDRSS_PHY_360_DATA 0x00000008
 #define DDRSS_PHY_361_DATA 0x034C034C
 #define DDRSS_PHY_362_DATA 0x034C034C
@@ -1163,7 +1159,7 @@
 #define DDRSS_PHY_373_DATA 0x00800080
 #define DDRSS_PHY_374_DATA 0x00800080
 #define DDRSS_PHY_375_DATA 0x01800080
-#define DDRSS_PHY_376_DATA 0x01A00001
+#define DDRSS_PHY_376_DATA 0x01000000
 #define DDRSS_PHY_377_DATA 0x00000000
 #define DDRSS_PHY_378_DATA 0x00000000
 #define DDRSS_PHY_379_DATA 0x00080200
@@ -2158,7 +2154,7 @@
 #define DDRSS_PHY_1368_DATA 0x00000002
 #define DDRSS_PHY_1369_DATA 0x00000000
 #define DDRSS_PHY_1370_DATA 0x00000000
-#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1371_DATA 0x00000AC3
 #define DDRSS_PHY_1372_DATA 0x00020002
 #define DDRSS_PHY_1373_DATA 0x00000000
 #define DDRSS_PHY_1374_DATA 0x00001142
@@ -2189,7 +2185,7 @@
 #define DDRSS_PHY_1399_DATA 0x000C3F11
 #define DDRSS_PHY_1400_DATA 0x01990000
 #define DDRSS_PHY_1401_DATA 0x3F0DFF11
-#define DDRSS_PHY_1402_DATA 0x019900E0
+#define DDRSS_PHY_1402_DATA 0x01990000
 #define DDRSS_PHY_1403_DATA 0x00018011
 #define DDRSS_PHY_1404_DATA 0x0089FF00
 #define DDRSS_PHY_1405_DATA 0x20040004