board: toradex: verdin-imx8mp: integrate 8 gb ram configuration

As a first step, integrate the quad die, dual rank aka 8 GB
configuration.

In a later step, the previous dual die, single rank aka 1 GB (untested),
2 GB or 4 GB configuration will be re-added as a fall-back configuration
allowing for dynamic unified memory configuration of all our (current)
SKUs.

Related-to: ELB-3938
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

1 files changed, 11 insertions, 12 deletions

diff --git a/board/toradex/verdin-imx8mp/lpddr4_timing.c b/board/toradex/verdin-imx8mp/lpddr4_timing.c
index cab984c3a0..a543489c6d 100644
--- a/board/toradex/verdin-imx8mp/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mp/lpddr4_timing.c
@@ -18,7 +18,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	/** Initialize DDRC registers **/
 	{ 0x3d400304, 0x1 },
 	{ 0x3d400030, 0x1 },
-	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400000, 0xa3080020 },
 	{ 0x3d400020, 0x1303 },
 	{ 0x3d400024, 0x1e84800 },
 	{ 0x3d400064, 0x7a0118 },
@@ -55,7 +55,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 	{ 0x3d4001c4, 0x1 },
 	{ 0x3d4000f4, 0xc99 },
 	{ 0x3d400108, 0x9121c1c },
-	{ 0x3d400200, 0x1f },
+	{ 0x3d400200, 0x18 },
 	{ 0x3d40020c, 0x0 },
 	{ 0x3d400210, 0x1f1f },
 	{ 0x3d400204, 0x80808 },
@@ -1069,7 +1069,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
 	{ 0x5400f, 0x100 },
-	{ 0x54012, 0x110 },
+	{ 0x54012, 0x310 },
 	{ 0x54019, 0x3ff4 },
 	{ 0x5401a, 0x33 },
 	{ 0x5401b, 0x4866 },
@@ -1081,7 +1081,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0x54022, 0x4800 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
+	{ 0x5402c, 0x3 },
 	{ 0x54032, 0xf400 },
 	{ 0x54033, 0x333f },
 	{ 0x54034, 0x6600 },
@@ -1110,7 +1110,7 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
 	{ 0x5400f, 0x100 },
-	{ 0x54012, 0x110 },
+	{ 0x54012, 0x310 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x33 },
 	{ 0x5401b, 0x4866 },
@@ -1122,7 +1122,7 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0x54022, 0x4800 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
+	{ 0x5402c, 0x3 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3300 },
 	{ 0x54034, 0x6600 },
@@ -1151,7 +1151,7 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
 	{ 0x5400f, 0x100 },
-	{ 0x54012, 0x110 },
+	{ 0x54012, 0x310 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x33 },
 	{ 0x5401b, 0x4866 },
@@ -1163,7 +1163,7 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0x54022, 0x4800 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
+	{ 0x5402c, 0x3 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3300 },
 	{ 0x54034, 0x6600 },
@@ -1190,10 +1190,9 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400d, 0x100 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
-	{ 0x54012, 0x110 },
+	{ 0x54012, 0x310 },
 	{ 0x54019, 0x3ff4 },
 	{ 0x5401a, 0x33 },
 	{ 0x5401b, 0x4866 },
@@ -1205,7 +1204,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0x54022, 0x4800 },
 	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
-	{ 0x5402c, 0x1 },
+	{ 0x5402c, 0x3 },
 	{ 0x54032, 0xf400 },
 	{ 0x54033, 0x333f },
 	{ 0x54034, 0x6600 },
@@ -1837,7 +1836,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 	},
 };
 
-/* ddr timing config params */
+/* quad die, dual rank aka 8 GB DDR timing config params */
 struct dram_timing_info dram_timing = {
 	.ddrc_cfg = ddr_ddrc_cfg,
 	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),